\t (00:00:05) allegro 24.1 P001 (4234998) [9/4/2024] Windows SPB 64-bit Edition
\t (00:00:05)     Journal start - Mon Aug 10 16:28:46 2026
\t (00:00:05)         Host=WIND User=Hydro Pid=35176 CPUs=20
\t (00:00:05) CmdLine= d:\tools\cadence\spb_24.1\tools\bin\allegro.exe D:\polaris\PCB\Library\AllegroPCBFootprint\K922.dra
\t (00:00:05) 
\t (00:00:05) Loading axlcore.cxt 
\t (00:00:08) 正在打开现有设计...
\i (00:00:08) QtSignal SPBFoldDockArea FoldAreaTabWidget currentChanged K922
\d (00:00:08) 设计已打开：D:/polaris/PCB/Library/AllegroPCBFootprint/K922.dra
\i (00:00:08) trapsize 3880
\i (00:00:08) trapsize 4094
\i (00:00:08) trapsize 3880
\i (00:00:08) trapsize 3880
\i (00:00:08) trapsize 3006
\i (00:00:08) generaledit 
\t (00:00:08) [16:28:49.238000] Periodic Lic check successful
[16:28:49.238000] Feature usage summary:

\i (00:00:12) exit 
\t (00:00:15) Lic Summary:
[16:28:55.416000] Cdslmd servers:
[16:28:55.416000] Feature usage summary:

\t (00:00:15)     Journal end - Mon Aug 10 16:28:55 2026