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祈风
2026-02-23 21:13:00 +08:00
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8
Controller/CMakeLists.txt Normal file
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cmake_minimum_required(VERSION 3.22)
# Register library to the system
add_library(Controller INTERFACE)
file(GLOB_RECURSE SOURCES "${CMAKE_CURRENT_LIST_DIR}/*.c")
target_sources(Controller INTERFACE ${SOURCES})
target_include_directories(Controller INTERFACE
include
)

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/*
* Academic License - for use in teaching, academic research, and meeting
* course requirements at degree granting institutions only. Not for
* government, commercial, or other organizational use.
*
* File: Controller.c
*
* Code generated for Simulink model 'Controller'.
*
* Model version : 2.23
* Simulink Coder version : 25.1 (R2025a) 21-Nov-2024
* C/C++ source code generated on : Sat Jun 14 13:33:39 2025
*
* Target selection: ert.tlc
* Embedded hardware selection: ARM Compatible->ARM Cortex-M
* Code generation objectives:
* 1. Execution efficiency
* 2. RAM efficiency
* Validation result: Not run
*/
#include "Controller.h"
#include "rtwtypes.h"
#include <math.h>
#include "arm_math.h"
/* Block signals and states (default storage) */
DW rtDW;
/* External inputs (root inport signals with default storage) */
ExtU rtU;
/* External outputs (root outports fed by signals with default storage) */
ExtY rtY;
/* Real-time model */
static RT_MODEL rtM_;
RT_MODEL *const rtM = &rtM_;
static real32_T IfActionSubsystem(real32_T rtu_In1);
static real32_T IfActionSubsystem1(real32_T rtu_In1);
/*
* Output and update for action system:
* '<S22>/If Action Subsystem'
* '<S193>/If Action Subsystem'
*/
static real32_T IfActionSubsystem(real32_T rtu_In1)
{
/* Sum: '<S25>/Sum' incorporates:
* DataTypeConversion: '<S25>/Convert_back'
* DataTypeConversion: '<S25>/Convert_uint16'
*/
return rtu_In1 - (real32_T)(int16_T)floorf(rtu_In1);
}
/*
* Output and update for action system:
* '<S22>/If Action Subsystem1'
* '<S193>/If Action Subsystem1'
*/
static real32_T IfActionSubsystem1(real32_T rtu_In1)
{
/* Sum: '<S26>/Sum' incorporates:
* DataTypeConversion: '<S26>/Convert_back'
* DataTypeConversion: '<S26>/Convert_uint16'
*/
return rtu_In1 - (real32_T)(int16_T)rtu_In1;
}
/* Model step function */
void Controller_step(void)
{
real32_T T_idx_0;
real32_T T_idx_1;
real32_T T_idx_2;
real32_T T_idx_3;
real32_T d_Temp;
real32_T rtb_Gain1;
real32_T rtb_Sum2;
real32_T rtb_Sum4_f;
real32_T rtb_algDD_o1;
real32_T rtb_algDD_o1_n;
real32_T rtb_algDD_o2_h;
real32_T rtb_convert_pu;
real32_T rtb_sum_alpha;
real32_T u0;
real32_T u0_0;
uint16_T rtb_Get_Integer_e;
/* Gain: '<S22>/convert_pu' incorporates:
* Gain: '<S1>/Gain'
* Inport: '<Root>/theta'
*/
rtb_convert_pu = 7.0F * rtU.Rotoranglethetamrad * 0.159154937F;
/* If: '<S22>/If' incorporates:
* Constant: '<S24>/Constant'
* RelationalOperator: '<S24>/Compare'
*/
if (rtb_convert_pu < 0.0F) {
/* Outputs for IfAction SubSystem: '<S22>/If Action Subsystem' incorporates:
* ActionPort: '<S25>/Action Port'
*/
T_idx_2 = IfActionSubsystem(rtb_convert_pu);
/* End of Outputs for SubSystem: '<S22>/If Action Subsystem' */
} else {
/* Outputs for IfAction SubSystem: '<S22>/If Action Subsystem1' incorporates:
* ActionPort: '<S26>/Action Port'
*/
T_idx_2 = IfActionSubsystem1(rtb_convert_pu);
/* End of Outputs for SubSystem: '<S22>/If Action Subsystem1' */
}
/* End of If: '<S22>/If' */
/* Gain: '<S20>/indexing' */
T_idx_2 *= 800.0F;
/* If: '<S193>/If' incorporates:
* Constant: '<S195>/Constant'
* RelationalOperator: '<S195>/Compare'
*/
if (rtb_convert_pu < 0.0F) {
/* Outputs for IfAction SubSystem: '<S193>/If Action Subsystem' incorporates:
* ActionPort: '<S196>/Action Port'
*/
rtb_Sum2 = IfActionSubsystem(rtb_convert_pu);
/* End of Outputs for SubSystem: '<S193>/If Action Subsystem' */
} else {
/* Outputs for IfAction SubSystem: '<S193>/If Action Subsystem1' incorporates:
* ActionPort: '<S197>/Action Port'
*/
rtb_Sum2 = IfActionSubsystem1(rtb_convert_pu);
/* End of Outputs for SubSystem: '<S193>/If Action Subsystem1' */
}
/* End of If: '<S193>/If' */
/* Gain: '<S191>/indexing' */
rtb_Sum2 *= 800.0F;
/* DataTypeConversion: '<S191>/Get_Integer' */
rtb_Get_Integer_e = (uint16_T)rtb_Sum2;
/* Sum: '<S191>/Sum2' incorporates:
* DataTypeConversion: '<S191>/Data Type Conversion1'
* DataTypeConversion: '<S191>/Get_Integer'
*/
rtb_Sum2 -= (real32_T)(uint16_T)rtb_Sum2;
/* Outputs for Atomic SubSystem: '<S13>/Two phase CRL wrap' */
/* AlgorithmDescriptorDelegate generated from: '<S14>/a16' incorporates:
* Inport: '<Root>/Ia'
* Inport: '<Root>/Ib'
*/
arm_clarke_f32(rtU.Ia, rtU.Ib, &rtb_convert_pu, &rtb_algDD_o2_h);
/* End of Outputs for SubSystem: '<S13>/Two phase CRL wrap' */
/* Outputs for Atomic SubSystem: '<S187>/Two inputs CRL' */
/* AlgorithmDescriptorDelegate generated from: '<S189>/a16' incorporates:
* Constant: '<S191>/offset'
* Constant: '<S191>/sine_table_values'
* Gain: '<S13>/Kalpha'
* Gain: '<S13>/Kbeta'
* Product: '<S192>/Product'
* Product: '<S192>/Product1'
* Selector: '<S191>/Lookup'
* Sum: '<S191>/Sum'
* Sum: '<S192>/Sum3'
* Sum: '<S192>/Sum4'
* Sum: '<S192>/Sum5'
* Sum: '<S192>/Sum6'
*/
arm_park_f32(1.22474492F * rtb_convert_pu, 1.22474492F * rtb_algDD_o2_h,
&rtb_algDD_o1, &T_idx_0, (rtConstP.pooled1[(int32_T)
(rtb_Get_Integer_e + 1U)] - rtConstP.pooled1[rtb_Get_Integer_e]) * rtb_Sum2
+ rtConstP.pooled1[rtb_Get_Integer_e], (rtConstP.pooled1[(int32_T)
(rtb_Get_Integer_e + 201U)] - rtConstP.pooled1[(int32_T)(rtb_Get_Integer_e +
200U)]) * rtb_Sum2 + rtConstP.pooled1[(int32_T)(rtb_Get_Integer_e + 200U)]);
/* End of Outputs for SubSystem: '<S187>/Two inputs CRL' */
/* SampleTimeMath: '<S3>/TSamp' incorporates:
* Inport: '<Root>/theta'
*
* About '<S3>/TSamp':
* y = u * K where K = 1 / ( w * Ts )
* */
rtb_convert_pu = rtU.Rotoranglethetamrad * 10000.0F;
/* Sum: '<S3>/Diff' incorporates:
* UnitDelay: '<S3>/UD'
*
* Block description for '<S3>/Diff':
*
* Add in CPU
*
* Block description for '<S3>/UD':
*
* Store in Global RAM
*/
rtb_Sum2 = rtb_convert_pu - rtDW.UD_DSTATE;
/* Gain: '<S1>/Gain1' */
rtb_Gain1 = 7.0F * rtb_Sum2;
/* Sum: '<S1>/Sum3' incorporates:
* Inport: '<Root>/Id_ref'
*/
rtb_algDD_o2_h = rtU.Id_ref - rtb_algDD_o1;
/* Sum: '<S1>/Sum4' incorporates:
* Gain: '<S1>/Gain2'
* Inport: '<Root>/Speed_ref'
*/
rtb_Sum4_f = rtU.Speed_ref - 9.54929638F * rtb_Sum2;
/* Sum: '<S1>/Sum2' incorporates:
* DiscreteIntegrator: '<S167>/Integrator'
* Gain: '<S172>/Proportional Gain'
* Sum: '<S176>/Sum'
*/
rtb_Sum2 = (0.026F * rtb_Sum4_f + rtDW.Integrator_DSTATE_n) - T_idx_0;
/* Sum: '<S20>/Sum2' incorporates:
* DataTypeConversion: '<S20>/Data Type Conversion1'
* DataTypeConversion: '<S20>/Get_Integer'
*/
rtb_sum_alpha = T_idx_2 - (real32_T)(uint16_T)T_idx_2;
/* Sum: '<S124>/Sum' incorporates:
* DiscreteIntegrator: '<S115>/Integrator'
* Gain: '<S120>/Proportional Gain'
*/
u0 = 0.558F * rtb_algDD_o2_h + rtDW.Integrator_DSTATE;
/* Sum: '<S72>/Sum' incorporates:
* DiscreteIntegrator: '<S63>/Integrator'
* Gain: '<S68>/Proportional Gain'
*/
u0_0 = 0.558F * rtb_Sum2 + rtDW.Integrator_DSTATE_h;
/* Saturate: '<S122>/Saturation' */
if (u0 > 6.92820311F) {
u0 = 6.92820311F;
} else if (u0 < -6.92820311F) {
u0 = -6.92820311F;
}
/* Saturate: '<S70>/Saturation' */
if (u0_0 > 6.92820311F) {
u0_0 = 6.92820311F;
} else if (u0_0 < -6.92820311F) {
u0_0 = -6.92820311F;
}
/* Outputs for Atomic SubSystem: '<S17>/Two inputs CRL' */
/* AlgorithmDescriptorDelegate generated from: '<S19>/a16' incorporates:
* Constant: '<S20>/offset'
* Constant: '<S20>/sine_table_values'
* DataTypeConversion: '<S20>/Get_Integer'
* Fcn: '<S1>/Fcn'
* Fcn: '<S1>/Fcn1'
* Product: '<S21>/Product'
* Product: '<S21>/Product1'
* Saturate: '<S122>/Saturation'
* Saturate: '<S70>/Saturation'
* Selector: '<S20>/Lookup'
* Sum: '<S1>/Sum'
* Sum: '<S1>/Sum1'
* Sum: '<S20>/Sum'
* Sum: '<S21>/Sum3'
* Sum: '<S21>/Sum4'
* Sum: '<S21>/Sum5'
* Sum: '<S21>/Sum6'
*/
arm_inv_park_f32(u0 + -rtb_Gain1 * T_idx_0 * 0.000279F, u0_0 + rtb_Gain1 *
(0.000279F * rtb_algDD_o1 + 0.005753F), &rtb_algDD_o1_n,
&T_idx_2, (rtConstP.pooled1[(int32_T)((uint16_T)T_idx_2 + 1U)]
- rtConstP.pooled1[(uint16_T)T_idx_2]) * rtb_sum_alpha + rtConstP.pooled1
[(uint16_T)T_idx_2], (rtConstP.pooled1[(int32_T)((uint16_T)
T_idx_2 + 201U)] - rtConstP.pooled1[(int32_T)((uint16_T)T_idx_2 + 200U)]) *
rtb_sum_alpha + rtConstP.pooled1[(int32_T)((uint16_T)T_idx_2
+ 200U)]);
/* End of Outputs for SubSystem: '<S17>/Two inputs CRL' */
/* MATLAB Function: '<S9>/MATLAB Function2' */
switch ((((T_idx_2 - rtb_algDD_o1_n * 1.73205078F > 0.0F) << 2) +
((rtb_algDD_o1_n * 1.73205078F + T_idx_2 > 0.0F) << 1)) + (T_idx_2 <=
0.0F)) {
case 1:
T_idx_0 = 5.0F;
break;
case 2:
T_idx_0 = 1.0F;
break;
case 3:
T_idx_0 = 6.0F;
break;
case 4:
T_idx_0 = 3.0F;
break;
case 5:
T_idx_0 = 4.0F;
break;
case 6:
T_idx_0 = 2.0F;
break;
default:
T_idx_0 = -1.0F;
break;
}
/* End of MATLAB Function: '<S9>/MATLAB Function2' */
/* MATLAB Function: '<S9>/MATLAB Function1' incorporates:
* Constant: '<S9>/Constant'
* Constant: '<S9>/Constant1'
*/
switch ((int32_T)T_idx_0) {
case 1:
rtb_algDD_o1 = 2.0F * T_idx_2 * 1800.0F / 1.73205078F / 8.0F;
T_idx_3 = (rtb_algDD_o1_n - T_idx_2 / 1.73205078F) * 1800.0F / 8.0F;
T_idx_1 = rtb_algDD_o1;
d_Temp = T_idx_3 + rtb_algDD_o1;
if (d_Temp > 1800.0F) {
d_Temp = 1800.0F / d_Temp;
T_idx_3 *= d_Temp;
T_idx_1 = rtb_algDD_o1 * d_Temp;
}
d_Temp = ((1800.0F - T_idx_3) - T_idx_1) / 2.0F;
T_idx_3 = (T_idx_3 + T_idx_1) + d_Temp;
T_idx_1 += d_Temp;
break;
case 2:
T_idx_3 = T_idx_2 / 1.73205078F;
T_idx_1 = (T_idx_3 - rtb_algDD_o1_n) * 1800.0F / 8.0F;
rtb_algDD_o1 = (T_idx_3 + rtb_algDD_o1_n) * 1800.0F / 8.0F;
T_idx_2 = rtb_algDD_o1;
d_Temp = T_idx_1 + rtb_algDD_o1;
if (d_Temp > 1800.0F) {
d_Temp = 1800.0F / d_Temp;
T_idx_1 *= d_Temp;
T_idx_2 = rtb_algDD_o1 * d_Temp;
}
d_Temp = ((1800.0F - T_idx_1) - T_idx_2) / 2.0F;
T_idx_3 = T_idx_2 + d_Temp;
T_idx_1 = (T_idx_1 + T_idx_2) + d_Temp;
break;
case 3:
T_idx_1 = 1.73205078F * T_idx_2 * 1800.0F / 12.0F;
T_idx_2 = -((1.5F * rtb_algDD_o1_n + 0.866025388F * T_idx_2) * 150.0F);
d_Temp = T_idx_1 + T_idx_2;
if (d_Temp > 1800.0F) {
d_Temp = 1800.0F / d_Temp;
T_idx_1 *= d_Temp;
T_idx_2 *= d_Temp;
}
d_Temp = ((1800.0F - T_idx_1) - T_idx_2) / 2.0F;
T_idx_3 = d_Temp;
T_idx_1 = (T_idx_1 + T_idx_2) + d_Temp;
d_Temp += T_idx_2;
break;
case 4:
T_idx_0 = -2.0F * T_idx_2 * 1800.0F / 1.73205078F / 8.0F;
T_idx_2 = (T_idx_2 / 1.73205078F - rtb_algDD_o1_n) * 1800.0F / 8.0F;
d_Temp = T_idx_0 + T_idx_2;
if (d_Temp > 1800.0F) {
d_Temp = 1800.0F / d_Temp;
T_idx_0 *= d_Temp;
T_idx_2 *= d_Temp;
}
d_Temp = ((1800.0F - T_idx_0) - T_idx_2) / 2.0F;
T_idx_3 = d_Temp;
T_idx_1 = T_idx_2 + d_Temp;
d_Temp += T_idx_0 + T_idx_2;
break;
case 5:
T_idx_3 = -T_idx_2 / 1.73205078F;
T_idx_0 = (T_idx_3 - rtb_algDD_o1_n) * 1800.0F / 8.0F;
T_idx_1 = (T_idx_3 + rtb_algDD_o1_n) * 1800.0F / 8.0F;
T_idx_2 = T_idx_1;
d_Temp = T_idx_0 + T_idx_1;
if (d_Temp > 1800.0F) {
d_Temp = 1800.0F / d_Temp;
T_idx_0 *= d_Temp;
T_idx_2 = T_idx_1 * d_Temp;
}
d_Temp = ((1800.0F - T_idx_0) - T_idx_2) / 2.0F;
T_idx_3 = T_idx_2 + d_Temp;
T_idx_1 = d_Temp;
d_Temp += T_idx_0 + T_idx_2;
break;
case 6:
T_idx_1 = -2.0F * T_idx_2 * 1800.0F / 1.73205078F / 8.0F;
T_idx_3 = (T_idx_2 / 1.73205078F + rtb_algDD_o1_n) * 1800.0F / 8.0F;
T_idx_2 = T_idx_1;
d_Temp = T_idx_3 + T_idx_1;
if (d_Temp > 1800.0F) {
d_Temp = 1800.0F / d_Temp;
T_idx_3 *= d_Temp;
T_idx_2 = T_idx_1 * d_Temp;
}
d_Temp = ((1800.0F - T_idx_3) - T_idx_2) / 2.0F;
T_idx_3 = (T_idx_3 + T_idx_2) + d_Temp;
T_idx_1 = d_Temp;
d_Temp += T_idx_2;
break;
}
/* Outport: '<Root>/CCR1' incorporates:
* Constant: '<S9>/Constant1'
* MATLAB Function: '<S9>/MATLAB Function1'
*/
rtY.CCR1 = (1800.0F - T_idx_3) / 2.0F;
/* Outport: '<Root>/CCR2' incorporates:
* Constant: '<S9>/Constant1'
* MATLAB Function: '<S9>/MATLAB Function1'
*/
rtY.CCR2 = (1800.0F - T_idx_1) / 2.0F;
/* Outport: '<Root>/CCR3' incorporates:
* Constant: '<S9>/Constant1'
* MATLAB Function: '<S9>/MATLAB Function1'
*/
rtY.CCR3 = (1800.0F - d_Temp) / 2.0F;
/* Update for UnitDelay: '<S3>/UD'
*
* Block description for '<S3>/UD':
*
* Store in Global RAM
*/
rtDW.UD_DSTATE = rtb_convert_pu;
/* Update for DiscreteIntegrator: '<S115>/Integrator' incorporates:
* Gain: '<S112>/Integral Gain'
*/
rtDW.Integrator_DSTATE += 1600.0F * rtb_algDD_o2_h * 0.0001F;
/* Update for DiscreteIntegrator: '<S167>/Integrator' incorporates:
* Gain: '<S164>/Integral Gain'
*/
rtDW.Integrator_DSTATE_n += 2.408F * rtb_Sum4_f * 0.0001F;
/* Update for DiscreteIntegrator: '<S63>/Integrator' incorporates:
* Gain: '<S60>/Integral Gain'
*/
rtDW.Integrator_DSTATE_h += 1600.0F * rtb_Sum2 * 0.0001F;
}
/* Model initialize function */
void Controller_initialize(void)
{
/* (no initialization code required) */
}
/*
* File trailer for generated code.
*
* [EOF]
*/

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/*
* Academic License - for use in teaching, academic research, and meeting
* course requirements at degree granting institutions only. Not for
* government, commercial, or other organizational use.
*
* File: Controller_data.c
*
* Code generated for Simulink model 'Controller'.
*
* Model version : 2.23
* Simulink Coder version : 25.1 (R2025a) 21-Nov-2024
* C/C++ source code generated on : Sat Jun 14 13:33:39 2025
*
* Target selection: ert.tlc
* Embedded hardware selection: ARM Compatible->ARM Cortex-M
* Code generation objectives:
* 1. Execution efficiency
* 2. RAM efficiency
* Validation result: Not run
*/
#include "Controller.h"
/* Constant parameters (default storage) */
const ConstP rtConstP = {
/* Pooled Parameter (Expression: )
* Referenced by:
* '<S20>/sine_table_values'
* '<S191>/sine_table_values'
*/
{ 0.0F, 0.00785390101F, 0.0157073177F, 0.023559764F, 0.0314107575F,
0.0392598175F, 0.0471064523F, 0.0549501814F, 0.0627905205F, 0.070626989F,
0.0784591F, 0.086286366F, 0.0941083133F, 0.101924457F, 0.109734312F,
0.117537394F, 0.125333235F, 0.133121341F, 0.140901238F, 0.148672432F,
0.156434461F, 0.16418685F, 0.171929106F, 0.179660752F, 0.187381312F,
0.195090324F, 0.202787295F, 0.210471764F, 0.21814324F, 0.225801274F,
0.233445361F, 0.241075054F, 0.24868989F, 0.256289363F, 0.263873041F,
0.271440446F, 0.278991103F, 0.286524564F, 0.294040322F, 0.301537961F,
0.309017F, 0.316476971F, 0.323917419F, 0.331337899F, 0.338737935F,
0.346117049F, 0.353474855F, 0.360810816F, 0.368124545F, 0.375415564F,
0.382683426F, 0.389927685F, 0.397147894F, 0.404343605F, 0.411514372F,
0.418659747F, 0.425779283F, 0.432872593F, 0.439939171F, 0.446978629F,
0.453990489F, 0.460974365F, 0.46792981F, 0.474856377F, 0.481753677F,
0.488621235F, 0.495458663F, 0.502265513F, 0.509041429F, 0.515785873F,
0.522498548F, 0.529179F, 0.535826802F, 0.542441547F, 0.549022794F,
0.555570245F, 0.562083364F, 0.568561852F, 0.575005233F, 0.581413209F,
0.587785244F, 0.594121039F, 0.600420237F, 0.60668236F, 0.612907052F,
0.619093955F, 0.625242651F, 0.631352782F, 0.637424F, 0.643455863F,
0.649448037F, 0.655400157F, 0.661311865F, 0.667182744F, 0.673012495F,
0.678800762F, 0.684547126F, 0.690251231F, 0.695912778F, 0.70153141F,
0.707106769F, 0.712638497F, 0.718126297F, 0.723569751F, 0.72896862F,
0.734322488F, 0.739631116F, 0.744894F, 0.750111043F, 0.755281806F,
0.760405958F, 0.765483201F, 0.770513237F, 0.775495768F, 0.780430436F,
0.785316944F, 0.790155F, 0.794944346F, 0.799684644F, 0.804375648F, 0.809017F,
0.813608468F, 0.818149745F, 0.822640538F, 0.827080548F, 0.831469595F,
0.835807383F, 0.840093553F, 0.844327927F, 0.848510206F, 0.852640152F,
0.856717527F, 0.860742033F, 0.86471343F, 0.868631542F, 0.872496F,
0.876306653F, 0.880063295F, 0.883765638F, 0.887413442F, 0.891006529F,
0.894544661F, 0.898027599F, 0.901455104F, 0.904827058F, 0.908143163F,
0.911403298F, 0.914607167F, 0.91775465F, 0.920845509F, 0.923879504F,
0.926856577F, 0.92977649F, 0.932639F, 0.935444057F, 0.938191354F,
0.940880775F, 0.943512142F, 0.946085334F, 0.948600173F, 0.95105654F,
0.953454196F, 0.955793F, 0.958072901F, 0.96029371F, 0.962455213F,
0.964557409F, 0.96660012F, 0.968583167F, 0.970506489F, 0.972369909F,
0.974173367F, 0.975916743F, 0.977599919F, 0.979222834F, 0.980785251F,
0.982287228F, 0.983728647F, 0.985109329F, 0.986429274F, 0.987688363F,
0.988886476F, 0.990023673F, 0.991099775F, 0.992114723F, 0.993068457F,
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0.999722421F, 0.999876618F, 0.999969184F, 1.0F, 0.999969184F }
};
/*
* File trailer for generated code.
*
* [EOF]
*/

361
Controller/include/Controller.h Normal file
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@@ -0,0 +1,361 @@
/*
* Academic License - for use in teaching, academic research, and meeting
* course requirements at degree granting institutions only. Not for
* government, commercial, or other organizational use.
*
* File: Controller.h
*
* Code generated for Simulink model 'Controller'.
*
* Model version : 2.23
* Simulink Coder version : 25.1 (R2025a) 21-Nov-2024
* C/C++ source code generated on : Sat Jun 14 13:33:39 2025
*
* Target selection: ert.tlc
* Embedded hardware selection: ARM Compatible->ARM Cortex-M
* Code generation objectives:
* 1. Execution efficiency
* 2. RAM efficiency
* Validation result: Not run
*/
#ifndef Controller_h_
#define Controller_h_
#ifndef Controller_COMMON_INCLUDES_
#define Controller_COMMON_INCLUDES_
#include "rtwtypes.h"
#include "math.h"
#endif /* Controller_COMMON_INCLUDES_ */
#include <stddef.h>
#include "MW_target_hardware_resources.h"
/* Macros for accessing real-time model data structure */
#ifndef rtmGetErrorStatus
#define rtmGetErrorStatus(rtm) ((rtm)->errorStatus)
#endif
#ifndef rtmSetErrorStatus
#define rtmSetErrorStatus(rtm, val) ((rtm)->errorStatus = (val))
#endif
#define Controller_M (rtM)
/* Forward declaration for rtModel */
typedef struct tag_RTM RT_MODEL;
/* Block signals and states (default storage) for system '<Root>' */
typedef struct {
real32_T UD_DSTATE; /* '<S3>/UD' */
real32_T Integrator_DSTATE; /* '<S115>/Integrator' */
real32_T Integrator_DSTATE_n; /* '<S167>/Integrator' */
real32_T Integrator_DSTATE_h; /* '<S63>/Integrator' */
} DW;
/* Constant parameters (default storage) */
typedef struct {
/* Pooled Parameter (Expression: )
* Referenced by:
* '<S20>/sine_table_values'
* '<S191>/sine_table_values'
*/
real32_T pooled1[1002];
} ConstP;
/* External inputs (root inport signals with default storage) */
typedef struct {
real32_T Speed_ref; /* '<Root>/Speed_ref' */
real32_T Ia; /* '<Root>/Ia' */
real32_T Ib; /* '<Root>/Ib' */
real32_T Rotoranglethetamrad; /* '<Root>/theta' */
real32_T Id_ref; /* '<Root>/Id_ref' */
} ExtU;
/* External outputs (root outports fed by signals with default storage) */
typedef struct {
real32_T CCR1; /* '<Root>/CCR1' */
real32_T CCR2; /* '<Root>/CCR2' */
real32_T CCR3; /* '<Root>/CCR3' */
} ExtY;
/* Real-time Model Data Structure */
struct tag_RTM {
const char_T * volatile errorStatus;
};
/* Block signals and states (default storage) */
extern DW rtDW;
/* External inputs (root inport signals with default storage) */
extern ExtU rtU;
/* External outputs (root outports fed by signals with default storage) */
extern ExtY rtY;
/* Constant parameters (default storage) */
extern const ConstP rtConstP;
/* Model entry point functions */
extern void Controller_initialize(void);
extern void Controller_step(void);
/* Real-time Model object */
extern RT_MODEL *const rtM;
extern volatile boolean_T stopRequested;
extern volatile boolean_T runModel;
/*-
* These blocks were eliminated from the model due to optimizations:
*
* Block '<S14>/Data Type Duplicate' : Unused code path elimination
* Block '<S3>/Data Type Duplicate' : Unused code path elimination
* Block '<S4>/D' : Unused code path elimination
* Block '<S20>/Data Type Duplicate' : Unused code path elimination
* Block '<S20>/Data Type Propagation' : Unused code path elimination
* Block '<S25>/Data Type Duplicate' : Unused code path elimination
* Block '<S26>/Data Type Duplicate' : Unused code path elimination
* Block '<S19>/Data Type Duplicate' : Unused code path elimination
* Block '<S19>/Data Type Duplicate1' : Unused code path elimination
* Block '<S8>/D' : Unused code path elimination
* Block '<S191>/Data Type Duplicate' : Unused code path elimination
* Block '<S191>/Data Type Propagation' : Unused code path elimination
* Block '<S196>/Data Type Duplicate' : Unused code path elimination
* Block '<S197>/Data Type Duplicate' : Unused code path elimination
* Block '<S189>/Data Type Duplicate' : Unused code path elimination
* Block '<S189>/Data Type Duplicate1' : Unused code path elimination
* Block '<S9>/Scope' : Unused code path elimination
* Block '<S20>/Get_FractionVal' : Eliminate redundant data type conversion
* Block '<S191>/Get_FractionVal' : Eliminate redundant data type conversion
* Block '<S28>/Offset' : Unused code path elimination
* Block '<S28>/Unary_Minus' : Unused code path elimination
* Block '<S199>/Offset' : Unused code path elimination
* Block '<S199>/Unary_Minus' : Unused code path elimination
*/
/*-
* The generated code includes comments that allow you to trace directly
* back to the appropriate location in the model. The basic format
* is <system>/block_name, where system is the system number (uniquely
* assigned by Simulink) and block_name is the name of the block.
*
* Note that this particular code originates from a subsystem build,
* and has its own system numbers different from the parent model.
* Refer to the system hierarchy for this subsystem below, and use the
* MATLAB hilite_system command to trace the generated code back
* to the parent model. For example,
*
* hilite_system('foc/Controller') - opens subsystem foc/Controller
* hilite_system('foc/Controller/Kp') - opens and selects block Kp
*
* Here is the system hierarchy for this model
*
* '<Root>' : 'foc'
* '<S1>' : 'foc/Controller'
* '<S2>' : 'foc/Controller/Clarke Transform'
* '<S3>' : 'foc/Controller/Discrete Derivative'
* '<S4>' : 'foc/Controller/Inverse Park Transform'
* '<S5>' : 'foc/Controller/PID Controller'
* '<S6>' : 'foc/Controller/PID Controller1'
* '<S7>' : 'foc/Controller/PID Controller2'
* '<S8>' : 'foc/Controller/Park Transform'
* '<S9>' : 'foc/Controller/Subsystem1'
* '<S10>' : 'foc/Controller/Clarke Transform/Variant'
* '<S11>' : 'foc/Controller/Clarke Transform/Variant/mcb'
* '<S12>' : 'foc/Controller/Clarke Transform/Variant/mcb/Clarke Transform'
* '<S13>' : 'foc/Controller/Clarke Transform/Variant/mcb/Clarke Transform/Two phase input'
* '<S14>' : 'foc/Controller/Clarke Transform/Variant/mcb/Clarke Transform/Two phase input/Two phase CRL wrap'
* '<S15>' : 'foc/Controller/Inverse Park Transform/Variant'
* '<S16>' : 'foc/Controller/Inverse Park Transform/Variant/mcb'
* '<S17>' : 'foc/Controller/Inverse Park Transform/Variant/mcb/Inverse Park Transform'
* '<S18>' : 'foc/Controller/Inverse Park Transform/Variant/mcb/Inverse Park Transform/Sine Cosine'
* '<S19>' : 'foc/Controller/Inverse Park Transform/Variant/mcb/Inverse Park Transform/Two inputs CRL'
* '<S20>' : 'foc/Controller/Inverse Park Transform/Variant/mcb/Inverse Park Transform/Sine Cosine/Sine-Cosine Lookup'
* '<S21>' : 'foc/Controller/Inverse Park Transform/Variant/mcb/Inverse Park Transform/Sine Cosine/Sine-Cosine Lookup/Interpolation'
* '<S22>' : 'foc/Controller/Inverse Park Transform/Variant/mcb/Inverse Park Transform/Sine Cosine/Sine-Cosine Lookup/WrapUp'
* '<S23>' : 'foc/Controller/Inverse Park Transform/Variant/mcb/Inverse Park Transform/Sine Cosine/Sine-Cosine Lookup/datatype'
* '<S24>' : 'foc/Controller/Inverse Park Transform/Variant/mcb/Inverse Park Transform/Sine Cosine/Sine-Cosine Lookup/WrapUp/Compare To Zero'
* '<S25>' : 'foc/Controller/Inverse Park Transform/Variant/mcb/Inverse Park Transform/Sine Cosine/Sine-Cosine Lookup/WrapUp/If Action Subsystem'
* '<S26>' : 'foc/Controller/Inverse Park Transform/Variant/mcb/Inverse Park Transform/Sine Cosine/Sine-Cosine Lookup/WrapUp/If Action Subsystem1'
* '<S27>' : 'foc/Controller/Inverse Park Transform/Variant/mcb/Inverse Park Transform/Sine Cosine/Sine-Cosine Lookup/datatype/datatype no change'
* '<S28>' : 'foc/Controller/Inverse Park Transform/Variant/mcb/Inverse Park Transform/Two inputs CRL/Switch_Axis'
* '<S29>' : 'foc/Controller/PID Controller/Anti-windup'
* '<S30>' : 'foc/Controller/PID Controller/D Gain'
* '<S31>' : 'foc/Controller/PID Controller/External Derivative'
* '<S32>' : 'foc/Controller/PID Controller/Filter'
* '<S33>' : 'foc/Controller/PID Controller/Filter ICs'
* '<S34>' : 'foc/Controller/PID Controller/I Gain'
* '<S35>' : 'foc/Controller/PID Controller/Ideal P Gain'
* '<S36>' : 'foc/Controller/PID Controller/Ideal P Gain Fdbk'
* '<S37>' : 'foc/Controller/PID Controller/Integrator'
* '<S38>' : 'foc/Controller/PID Controller/Integrator ICs'
* '<S39>' : 'foc/Controller/PID Controller/N Copy'
* '<S40>' : 'foc/Controller/PID Controller/N Gain'
* '<S41>' : 'foc/Controller/PID Controller/P Copy'
* '<S42>' : 'foc/Controller/PID Controller/Parallel P Gain'
* '<S43>' : 'foc/Controller/PID Controller/Reset Signal'
* '<S44>' : 'foc/Controller/PID Controller/Saturation'
* '<S45>' : 'foc/Controller/PID Controller/Saturation Fdbk'
* '<S46>' : 'foc/Controller/PID Controller/Sum'
* '<S47>' : 'foc/Controller/PID Controller/Sum Fdbk'
* '<S48>' : 'foc/Controller/PID Controller/Tracking Mode'
* '<S49>' : 'foc/Controller/PID Controller/Tracking Mode Sum'
* '<S50>' : 'foc/Controller/PID Controller/Tsamp - Integral'
* '<S51>' : 'foc/Controller/PID Controller/Tsamp - Ngain'
* '<S52>' : 'foc/Controller/PID Controller/postSat Signal'
* '<S53>' : 'foc/Controller/PID Controller/preInt Signal'
* '<S54>' : 'foc/Controller/PID Controller/preSat Signal'
* '<S55>' : 'foc/Controller/PID Controller/Anti-windup/Passthrough'
* '<S56>' : 'foc/Controller/PID Controller/D Gain/Disabled'
* '<S57>' : 'foc/Controller/PID Controller/External Derivative/Disabled'
* '<S58>' : 'foc/Controller/PID Controller/Filter/Disabled'
* '<S59>' : 'foc/Controller/PID Controller/Filter ICs/Disabled'
* '<S60>' : 'foc/Controller/PID Controller/I Gain/Internal Parameters'
* '<S61>' : 'foc/Controller/PID Controller/Ideal P Gain/Passthrough'
* '<S62>' : 'foc/Controller/PID Controller/Ideal P Gain Fdbk/Disabled'
* '<S63>' : 'foc/Controller/PID Controller/Integrator/Discrete'
* '<S64>' : 'foc/Controller/PID Controller/Integrator ICs/Internal IC'
* '<S65>' : 'foc/Controller/PID Controller/N Copy/Disabled wSignal Specification'
* '<S66>' : 'foc/Controller/PID Controller/N Gain/Disabled'
* '<S67>' : 'foc/Controller/PID Controller/P Copy/Disabled'
* '<S68>' : 'foc/Controller/PID Controller/Parallel P Gain/Internal Parameters'
* '<S69>' : 'foc/Controller/PID Controller/Reset Signal/Disabled'
* '<S70>' : 'foc/Controller/PID Controller/Saturation/Enabled'
* '<S71>' : 'foc/Controller/PID Controller/Saturation Fdbk/Disabled'
* '<S72>' : 'foc/Controller/PID Controller/Sum/Sum_PI'
* '<S73>' : 'foc/Controller/PID Controller/Sum Fdbk/Disabled'
* '<S74>' : 'foc/Controller/PID Controller/Tracking Mode/Disabled'
* '<S75>' : 'foc/Controller/PID Controller/Tracking Mode Sum/Passthrough'
* '<S76>' : 'foc/Controller/PID Controller/Tsamp - Integral/TsSignalSpecification'
* '<S77>' : 'foc/Controller/PID Controller/Tsamp - Ngain/Passthrough'
* '<S78>' : 'foc/Controller/PID Controller/postSat Signal/Forward_Path'
* '<S79>' : 'foc/Controller/PID Controller/preInt Signal/Internal PreInt'
* '<S80>' : 'foc/Controller/PID Controller/preSat Signal/Forward_Path'
* '<S81>' : 'foc/Controller/PID Controller1/Anti-windup'
* '<S82>' : 'foc/Controller/PID Controller1/D Gain'
* '<S83>' : 'foc/Controller/PID Controller1/External Derivative'
* '<S84>' : 'foc/Controller/PID Controller1/Filter'
* '<S85>' : 'foc/Controller/PID Controller1/Filter ICs'
* '<S86>' : 'foc/Controller/PID Controller1/I Gain'
* '<S87>' : 'foc/Controller/PID Controller1/Ideal P Gain'
* '<S88>' : 'foc/Controller/PID Controller1/Ideal P Gain Fdbk'
* '<S89>' : 'foc/Controller/PID Controller1/Integrator'
* '<S90>' : 'foc/Controller/PID Controller1/Integrator ICs'
* '<S91>' : 'foc/Controller/PID Controller1/N Copy'
* '<S92>' : 'foc/Controller/PID Controller1/N Gain'
* '<S93>' : 'foc/Controller/PID Controller1/P Copy'
* '<S94>' : 'foc/Controller/PID Controller1/Parallel P Gain'
* '<S95>' : 'foc/Controller/PID Controller1/Reset Signal'
* '<S96>' : 'foc/Controller/PID Controller1/Saturation'
* '<S97>' : 'foc/Controller/PID Controller1/Saturation Fdbk'
* '<S98>' : 'foc/Controller/PID Controller1/Sum'
* '<S99>' : 'foc/Controller/PID Controller1/Sum Fdbk'
* '<S100>' : 'foc/Controller/PID Controller1/Tracking Mode'
* '<S101>' : 'foc/Controller/PID Controller1/Tracking Mode Sum'
* '<S102>' : 'foc/Controller/PID Controller1/Tsamp - Integral'
* '<S103>' : 'foc/Controller/PID Controller1/Tsamp - Ngain'
* '<S104>' : 'foc/Controller/PID Controller1/postSat Signal'
* '<S105>' : 'foc/Controller/PID Controller1/preInt Signal'
* '<S106>' : 'foc/Controller/PID Controller1/preSat Signal'
* '<S107>' : 'foc/Controller/PID Controller1/Anti-windup/Passthrough'
* '<S108>' : 'foc/Controller/PID Controller1/D Gain/Disabled'
* '<S109>' : 'foc/Controller/PID Controller1/External Derivative/Disabled'
* '<S110>' : 'foc/Controller/PID Controller1/Filter/Disabled'
* '<S111>' : 'foc/Controller/PID Controller1/Filter ICs/Disabled'
* '<S112>' : 'foc/Controller/PID Controller1/I Gain/Internal Parameters'
* '<S113>' : 'foc/Controller/PID Controller1/Ideal P Gain/Passthrough'
* '<S114>' : 'foc/Controller/PID Controller1/Ideal P Gain Fdbk/Disabled'
* '<S115>' : 'foc/Controller/PID Controller1/Integrator/Discrete'
* '<S116>' : 'foc/Controller/PID Controller1/Integrator ICs/Internal IC'
* '<S117>' : 'foc/Controller/PID Controller1/N Copy/Disabled wSignal Specification'
* '<S118>' : 'foc/Controller/PID Controller1/N Gain/Disabled'
* '<S119>' : 'foc/Controller/PID Controller1/P Copy/Disabled'
* '<S120>' : 'foc/Controller/PID Controller1/Parallel P Gain/Internal Parameters'
* '<S121>' : 'foc/Controller/PID Controller1/Reset Signal/Disabled'
* '<S122>' : 'foc/Controller/PID Controller1/Saturation/Enabled'
* '<S123>' : 'foc/Controller/PID Controller1/Saturation Fdbk/Disabled'
* '<S124>' : 'foc/Controller/PID Controller1/Sum/Sum_PI'
* '<S125>' : 'foc/Controller/PID Controller1/Sum Fdbk/Disabled'
* '<S126>' : 'foc/Controller/PID Controller1/Tracking Mode/Disabled'
* '<S127>' : 'foc/Controller/PID Controller1/Tracking Mode Sum/Passthrough'
* '<S128>' : 'foc/Controller/PID Controller1/Tsamp - Integral/TsSignalSpecification'
* '<S129>' : 'foc/Controller/PID Controller1/Tsamp - Ngain/Passthrough'
* '<S130>' : 'foc/Controller/PID Controller1/postSat Signal/Forward_Path'
* '<S131>' : 'foc/Controller/PID Controller1/preInt Signal/Internal PreInt'
* '<S132>' : 'foc/Controller/PID Controller1/preSat Signal/Forward_Path'
* '<S133>' : 'foc/Controller/PID Controller2/Anti-windup'
* '<S134>' : 'foc/Controller/PID Controller2/D Gain'
* '<S135>' : 'foc/Controller/PID Controller2/External Derivative'
* '<S136>' : 'foc/Controller/PID Controller2/Filter'
* '<S137>' : 'foc/Controller/PID Controller2/Filter ICs'
* '<S138>' : 'foc/Controller/PID Controller2/I Gain'
* '<S139>' : 'foc/Controller/PID Controller2/Ideal P Gain'
* '<S140>' : 'foc/Controller/PID Controller2/Ideal P Gain Fdbk'
* '<S141>' : 'foc/Controller/PID Controller2/Integrator'
* '<S142>' : 'foc/Controller/PID Controller2/Integrator ICs'
* '<S143>' : 'foc/Controller/PID Controller2/N Copy'
* '<S144>' : 'foc/Controller/PID Controller2/N Gain'
* '<S145>' : 'foc/Controller/PID Controller2/P Copy'
* '<S146>' : 'foc/Controller/PID Controller2/Parallel P Gain'
* '<S147>' : 'foc/Controller/PID Controller2/Reset Signal'
* '<S148>' : 'foc/Controller/PID Controller2/Saturation'
* '<S149>' : 'foc/Controller/PID Controller2/Saturation Fdbk'
* '<S150>' : 'foc/Controller/PID Controller2/Sum'
* '<S151>' : 'foc/Controller/PID Controller2/Sum Fdbk'
* '<S152>' : 'foc/Controller/PID Controller2/Tracking Mode'
* '<S153>' : 'foc/Controller/PID Controller2/Tracking Mode Sum'
* '<S154>' : 'foc/Controller/PID Controller2/Tsamp - Integral'
* '<S155>' : 'foc/Controller/PID Controller2/Tsamp - Ngain'
* '<S156>' : 'foc/Controller/PID Controller2/postSat Signal'
* '<S157>' : 'foc/Controller/PID Controller2/preInt Signal'
* '<S158>' : 'foc/Controller/PID Controller2/preSat Signal'
* '<S159>' : 'foc/Controller/PID Controller2/Anti-windup/Passthrough'
* '<S160>' : 'foc/Controller/PID Controller2/D Gain/Disabled'
* '<S161>' : 'foc/Controller/PID Controller2/External Derivative/Disabled'
* '<S162>' : 'foc/Controller/PID Controller2/Filter/Disabled'
* '<S163>' : 'foc/Controller/PID Controller2/Filter ICs/Disabled'
* '<S164>' : 'foc/Controller/PID Controller2/I Gain/Internal Parameters'
* '<S165>' : 'foc/Controller/PID Controller2/Ideal P Gain/Passthrough'
* '<S166>' : 'foc/Controller/PID Controller2/Ideal P Gain Fdbk/Disabled'
* '<S167>' : 'foc/Controller/PID Controller2/Integrator/Discrete'
* '<S168>' : 'foc/Controller/PID Controller2/Integrator ICs/Internal IC'
* '<S169>' : 'foc/Controller/PID Controller2/N Copy/Disabled wSignal Specification'
* '<S170>' : 'foc/Controller/PID Controller2/N Gain/Disabled'
* '<S171>' : 'foc/Controller/PID Controller2/P Copy/Disabled'
* '<S172>' : 'foc/Controller/PID Controller2/Parallel P Gain/Internal Parameters'
* '<S173>' : 'foc/Controller/PID Controller2/Reset Signal/Disabled'
* '<S174>' : 'foc/Controller/PID Controller2/Saturation/Passthrough'
* '<S175>' : 'foc/Controller/PID Controller2/Saturation Fdbk/Disabled'
* '<S176>' : 'foc/Controller/PID Controller2/Sum/Sum_PI'
* '<S177>' : 'foc/Controller/PID Controller2/Sum Fdbk/Disabled'
* '<S178>' : 'foc/Controller/PID Controller2/Tracking Mode/Disabled'
* '<S179>' : 'foc/Controller/PID Controller2/Tracking Mode Sum/Passthrough'
* '<S180>' : 'foc/Controller/PID Controller2/Tsamp - Integral/TsSignalSpecification'
* '<S181>' : 'foc/Controller/PID Controller2/Tsamp - Ngain/Passthrough'
* '<S182>' : 'foc/Controller/PID Controller2/postSat Signal/Forward_Path'
* '<S183>' : 'foc/Controller/PID Controller2/preInt Signal/Internal PreInt'
* '<S184>' : 'foc/Controller/PID Controller2/preSat Signal/Forward_Path'
* '<S185>' : 'foc/Controller/Park Transform/Variant'
* '<S186>' : 'foc/Controller/Park Transform/Variant/mcb'
* '<S187>' : 'foc/Controller/Park Transform/Variant/mcb/Park Transform'
* '<S188>' : 'foc/Controller/Park Transform/Variant/mcb/Park Transform/Sine Cosine'
* '<S189>' : 'foc/Controller/Park Transform/Variant/mcb/Park Transform/Two inputs CRL'
* '<S190>' : 'foc/Controller/Park Transform/Variant/mcb/Park Transform/Sine Cosine/Sine-Cosine Lookup'
* '<S191>' : 'foc/Controller/Park Transform/Variant/mcb/Park Transform/Sine Cosine/Sine-Cosine Lookup/Sine-Cosine Lookup'
* '<S192>' : 'foc/Controller/Park Transform/Variant/mcb/Park Transform/Sine Cosine/Sine-Cosine Lookup/Sine-Cosine Lookup/Interpolation'
* '<S193>' : 'foc/Controller/Park Transform/Variant/mcb/Park Transform/Sine Cosine/Sine-Cosine Lookup/Sine-Cosine Lookup/WrapUp'
* '<S194>' : 'foc/Controller/Park Transform/Variant/mcb/Park Transform/Sine Cosine/Sine-Cosine Lookup/Sine-Cosine Lookup/datatype'
* '<S195>' : 'foc/Controller/Park Transform/Variant/mcb/Park Transform/Sine Cosine/Sine-Cosine Lookup/Sine-Cosine Lookup/WrapUp/Compare To Zero'
* '<S196>' : 'foc/Controller/Park Transform/Variant/mcb/Park Transform/Sine Cosine/Sine-Cosine Lookup/Sine-Cosine Lookup/WrapUp/If Action Subsystem'
* '<S197>' : 'foc/Controller/Park Transform/Variant/mcb/Park Transform/Sine Cosine/Sine-Cosine Lookup/Sine-Cosine Lookup/WrapUp/If Action Subsystem1'
* '<S198>' : 'foc/Controller/Park Transform/Variant/mcb/Park Transform/Sine Cosine/Sine-Cosine Lookup/Sine-Cosine Lookup/datatype/datatype no change'
* '<S199>' : 'foc/Controller/Park Transform/Variant/mcb/Park Transform/Two inputs CRL/Switch_Axis'
* '<S200>' : 'foc/Controller/Subsystem1/MATLAB Function1'
* '<S201>' : 'foc/Controller/Subsystem1/MATLAB Function2'
*/
#endif /* Controller_h_ */
/*
* File trailer for generated code.
*
* [EOF]
*/

588
Controller/include/MW_target_hardware_resources.h Normal file
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@@ -0,0 +1,588 @@
#ifndef PORTABLE_WORDSIZES
#ifdef __MW_TARGET_USE_HARDWARE_RESOURCES_H__
#ifndef __MW_TARGET_HARDWARE_RESOURCES_H__
#define __MW_TARGET_HARDWARE_RESOURCES_H__
#define MW_MULTI_TASKING_MODE 1
#include "mw_stm32_board_header.h"
#include "SysTickScheduler.h"
#include "arm_cortex_m_multitasking.h"
#define MW_USECODERTARGET 1
#define MW_TARGETHARDWARE STM32F3xx Based
#define MW_EXTMODEPROTOCOLINFO_CAN_HOSTINTERFACE Simulink
#define MW_EXTMODEPROTOCOLINFO_CAN_LOGGINGBUFFERAUTO 1
#define MW_EXTMODEPROTOCOLINFO_CAN_LOGGINGBUFFERSIZE 1000
#define MW_EXTMODEPROTOCOLINFO_CAN_LOGGINGBUFFERNUM 3
#define MW_EXTMODEPROTOCOLINFO_CAN_MAXCONTIGSAMPLES 10
#define MW_CONNECTIONINFO_SERIAL_BAUDRATE stm32cube.codegen.getConnectivityBaudrate
#define MW_CONNECTIONINFO_SERIAL_COMPORT stm32cube.codegen.getConnectivityCOMPort
#define MW_CONNECTIONINFO_SERIAL_VERBOSE 1
#define MW_CONNECTIONINFO_CAN_CANVENDOR matlab:stm32cube.codegen.getXCPonCANConnectivity(hCS,'Vendor')
#define MW_CONNECTIONINFO_CAN_CANDEVICE matlab:stm32cube.codegen.getXCPonCANConnectivity(hCS,'Device')
#define MW_CONNECTIONINFO_CAN_CANCHANNEL stm32cube.codegen.getXCPonCANConnectivity(hCS,'Channel')
#define MW_CONNECTIONINFO_CAN_BUSSPEED stm32cube.codegen.getXCPonCANConnectivity(hCS,'Baudrate')
#define MW_CONNECTIONINFO_CAN_CANIDCOMMAND stm32cube.codegen.getXCPonCANConnectivity(hCS,'CANIDCommand')
#define MW_CONNECTIONINFO_CAN_CANIDRESPONSE stm32cube.codegen.getXCPonCANConnectivity(hCS,'CANIDResponse')
#define MW_CONNECTIONINFO_CAN_ISCANIDEXTENDED stm32cube.codegen.getXCPonCANConnectivity(hCS,'IsCANIDExtended')
#define MW_CONNECTIONINFO_CAN_VERBOSE 1
#define MW_EXTMODE_CONFIGURATION Serial
#define MW_EXTMODE_SIGNALBUFFERSIZE 2048.000000
#define MW_EXTMODE_USEREALTIMESTAMPLOGGING 1
#define MW_RTOS Baremetal
#define MW_RTOSBASERATETASKPRIORITY 40
#define MW_SCHEDULER_INTERRUPT_SOURCE 0
#define MW_RUNTIME_BUILDACTION 1
#define MW_RUNTIME_RUNTIMELIBRARY 1
#define MW_RUNTIME_FFPCONTRACTION 1
#define MW_RUNTIME_DISABLEPARALLELBUILD 0
#define MW_STM32CUBEMX_PROJECTFILEBUTTON
#define MW_STM32CUBEMX_CREATEPROJECTFILEBUTTON
#define MW_STM32CUBEMX_LAUNCHPROJECTFILEBUTTON
#define MW_STM32CUBEMX_PROJECTFILE D:/SUX/Simulink/Simulink.ioc
#define MW_STM32CUBEMX_DEVICEID STM32F303C(B-C)Tx
#define MW_STM32CUBEMX_FAMILY STM32F3
#define MW_STM32CUBEMX_CONNECTIVITYMODE 0
#define MW_STM32CUBEMX_CONNECTIONPORT 0
#define MW_STM32CUBEMX_MODE 0
#define MW_STM32CUBEMX_ACCESSPORT 0
#define MW_STM32CUBEMX_RESETMODE 0
#define MW_STM32CUBEMX_AUTODETECTBOARD 1
#define MW_STM32CUBEMX_DEVICELIST -1
#define MW_STM32CUBEMX_DEVICELISTREFRESH
#define MW_CLOCKING_CPUCLOCKRATEMHZ 64.000000
#define MW_CONNECTION_SERIALCONFIGUREMODULE 1
#define MW_CONNECTION_SERIALMODULE 0
#define MW_CONNECTION_SERIALPORT COM4
#define MW_CONNECTION_ETHERNETCONFIGUREMODULE 48
#define MW_CONNECTION_ETHERNETPORT 17725.000000
#define MW_CONNECTION_CANCONFIGUREMODULE 48
#define MW_CONNECTION_CANMODULE 0
#define MW_CONNECTION_BAUDRATE 1000000
#define MW_CONNECTION_CANREADSOURCE 0
#define MW_CONNECTION_CANVENDOR -1
#define MW_CONNECTION_CANDEVICE -1
#define MW_CONNECTION_CANCHANNEL -1
#define MW_CONNECTION_ISCANIDEXTENDED 48
#define MW_CONNECTION_CANIDCOMMAND 2
#define MW_CONNECTION_CANIDRESPONSE 3
#define MW_CONNECTIVITY_REFRESH
#define MW_SIMULINKIO_MODELTRANSPORTDATAFCN stm32cube.connectedIO.getConfigSetInfo
#define MW_SIMULINKIO_SERVERDEPLOYFCN stm32cube.connectedIO.updateServer
#define MW_SIMULINKIO_VALIDATESERVERFCN stm32cube.connectedIO.validateIoServer
#define MW_SIMULINKIO_INTERFACE 0
#define MW_SIMULINKIO_VALIDATEBEFORECONNECTFCN stm32cube.connectedIO.connectedIOModelValidation
#define MW_SIMULINKIO_CONNECTEDIOSUPPORTEDBLOCKS DigitalPortRead,DigitalPortWrite,PWMOutput,AnalogInput,I2CControllerRead,I2CControllerWrite,LSM6DS3Block,LSM6DS3HBlock,LSM6DSLBlock,LSM6DSMBlock,LSM6DSRBlock,LSM6DSOBlock,LSM303CBlock,LIS3MDLBlock,LPS22HBBlock,HTS221Block,BMI160Block,ADXL34xBlock,CCS811Block,ICM20948Block,LIS3DHBlock
#define MW_CONNECTEDIO_CONNECTEDIOMODE 0
#define MW_CONNECTEDIO_ACTIONONOVERRUN 0
#define MW_USART_USART1CONFIGUREMODULE 0
#define MW_USART_USART1TRANSMITMODE 0
#define MW_USART_USART1RECEIVEMODE 0
#define MW_USART_USART1TRANSMITBUFFERLENGTH 128
#define MW_USART_USART1RECEIVEBUFFERLENGTH 128
#define MW_USART_USART1DISABLEDMAINTERRUPTONERROR 48
#define MW_USART_USART2CONFIGUREMODULE 48
#define MW_USART_USART2TRANSMITMODE 0
#define MW_USART_USART2RECEIVEMODE 0
#define MW_USART_USART2TRANSMITBUFFERLENGTH 128
#define MW_USART_USART2RECEIVEBUFFERLENGTH 128
#define MW_USART_USART2DISABLEDMAINTERRUPTONERROR 48
#define MW_USART_USART3CONFIGUREMODULE 0
#define MW_USART_USART3TRANSMITMODE 0
#define MW_USART_USART3RECEIVEMODE 0
#define MW_USART_USART3TRANSMITBUFFERLENGTH 128
#define MW_USART_USART3RECEIVEBUFFERLENGTH 128
#define MW_USART_USART3DISABLEDMAINTERRUPTONERROR 48
#define MW_USART_UART4CONFIGUREMODULE 48
#define MW_USART_UART4TRANSMITMODE 0
#define MW_USART_UART4RECEIVEMODE 0
#define MW_USART_UART4TRANSMITBUFFERLENGTH 128
#define MW_USART_UART4RECEIVEBUFFERLENGTH 128
#define MW_USART_UART4DISABLEDMAINTERRUPTONERROR 48
#define MW_USART_UART5CONFIGUREMODULE 48
#define MW_USART_UART5TRANSMITMODE 0
#define MW_USART_UART5RECEIVEMODE 0
#define MW_USART_UART5TRANSMITBUFFERLENGTH 128
#define MW_USART_UART5RECEIVEBUFFERLENGTH 128
#define MW_USART_UART5DISABLEDMAINTERRUPTONERROR 48
#define MW_ADC1_USEDMA 1
#define MW_ADC1_USEWATCHDOG 0
#define MW_ADC1_EOCENABLEINTERRUPT 1
#define MW_ADC1_JEOCENABLEINTERRUPT 48
#define MW_ADC1_OVRENABLEINTERRUPT 48
#define MW_ADC1_CALIBRATE 1
#define MW_ADC1_CALIBRATIONMETHOD 0
#define MW_ADC1_ADCCONVERSIONMODE 0
#define MW_ADC1_OFFSETCALIBRATIONFACTORSINGLEENDED 0
#define MW_ADC1_OFFSETCALIBRATIONFACTORDIFFENDED 0
#define MW_ADC1_PROJECTFILEBUTTON
#define MW_ADC2_USEDMA 0
#define MW_ADC2_USEWATCHDOG 0
#define MW_ADC2_EOCENABLEINTERRUPT 0
#define MW_ADC2_JEOCENABLEINTERRUPT 48
#define MW_ADC2_OVRENABLEINTERRUPT 48
#define MW_ADC2_CALIBRATE 1
#define MW_ADC2_CALIBRATIONMETHOD 0
#define MW_ADC2_ADCCONVERSIONMODE 0
#define MW_ADC2_OFFSETCALIBRATIONFACTORSINGLEENDED 0
#define MW_ADC2_OFFSETCALIBRATIONFACTORDIFFENDED 0
#define MW_ADC2_PROJECTFILEBUTTON
#define MW_ADC3_USEDMA 0
#define MW_ADC3_USEWATCHDOG 0
#define MW_ADC3_EOCENABLEINTERRUPT 0
#define MW_ADC3_JEOCENABLEINTERRUPT 48
#define MW_ADC3_OVRENABLEINTERRUPT 48
#define MW_ADC3_CALIBRATE 1
#define MW_ADC3_CALIBRATIONMETHOD 0
#define MW_ADC3_ADCCONVERSIONMODE 0
#define MW_ADC3_OFFSETCALIBRATIONFACTORSINGLEENDED 0
#define MW_ADC3_OFFSETCALIBRATIONFACTORDIFFENDED 0
#define MW_ADC3_PROJECTFILEBUTTON
#define MW_ADC4_USEDMA 0
#define MW_ADC4_USEWATCHDOG 0
#define MW_ADC4_EOCENABLEINTERRUPT 0
#define MW_ADC4_JEOCENABLEINTERRUPT 48
#define MW_ADC4_OVRENABLEINTERRUPT 48
#define MW_ADC4_CALIBRATE 1
#define MW_ADC4_CALIBRATIONMETHOD 0
#define MW_ADC4_ADCCONVERSIONMODE 0
#define MW_ADC4_OFFSETCALIBRATIONFACTORSINGLEENDED 0
#define MW_ADC4_OFFSETCALIBRATIONFACTORDIFFENDED 0
#define MW_ADC4_PROJECTFILEBUTTON
#define MW_SPI_SPIMODULESELECT 2
#define MW_SPI_SPI1TRANSMITMODE 2
#define MW_SPI_SPI1TRANSMITBUFFERLENGTH 128
#define MW_SPI_SPI1RECEIVEMODE 2
#define MW_SPI_SPI1RECEIVEBUFFERLENGTH 128
#define MW_SPI_SPI1RXFIFOINTERRUPT 0
#define MW_SPI_SPI1ERRORINTERRUPT 0
#define MW_SPI_SPI2TRANSMITMODE 2
#define MW_SPI_SPI2TRANSMITBUFFERLENGTH 128
#define MW_SPI_SPI2RECEIVEMODE 2
#define MW_SPI_SPI2RECEIVEBUFFERLENGTH 128
#define MW_SPI_SPI2RXFIFOINTERRUPT 0
#define MW_SPI_SPI2ERRORINTERRUPT 0
#define MW_SPI_SPI3TRANSMITMODE 2
#define MW_SPI_SPI3TRANSMITBUFFERLENGTH 128
#define MW_SPI_SPI3RECEIVEMODE 2
#define MW_SPI_SPI3RECEIVEBUFFERLENGTH 128
#define MW_SPI_SPI3RXFIFOINTERRUPT 1
#define MW_SPI_SPI3ERRORINTERRUPT 1
#define MW_SPI_SPI4TRANSMITMODE 2
#define MW_SPI_SPI4TRANSMITBUFFERLENGTH 128
#define MW_SPI_SPI4RECEIVEMODE 2
#define MW_SPI_SPI4RECEIVEBUFFERLENGTH 128
#define MW_SPI_SPI4RXFIFOINTERRUPT 0
#define MW_SPI_SPI4ERRORINTERRUPT 0
#define MW_HRTIM_UPDATEEVENTSUSPENDED 48
#define MW_HRTIM_SELECTTIMERAFORUPDATEEVENTSUSPENDED 48
#define MW_HRTIM_SELECTTIMERBFORUPDATEEVENTSUSPENDED 48
#define MW_HRTIM_SELECTTIMERCFORUPDATEEVENTSUSPENDED 48
#define MW_HRTIM_SELECTTIMERDFORUPDATEEVENTSUSPENDED 48
#define MW_HRTIM_SELECTTIMEREFORUPDATEEVENTSUSPENDED 48
#define MW_HRTIM_SELECTTIMERFFORUPDATEEVENTSUSPENDED 48
#define MW_HRTIM_SELECTMAINTIMERFORUPDATEEVENTSUSPENDED 48
#define MW_HRTIM_SELECTTIMERSFORSYNCCOUNTERSTART 0
#define MW_HRTIM_SELECTTIMERAFORSYNCCOUNTERSTART 0
#define MW_HRTIM_SELECTTIMERBFORSYNCCOUNTERSTART 0
#define MW_HRTIM_SELECTTIMERCFORSYNCCOUNTERSTART 0
#define MW_HRTIM_SELECTTIMERDFORSYNCCOUNTERSTART 0
#define MW_HRTIM_SELECTTIMEREFORSYNCCOUNTERSTART 0
#define MW_HRTIM_SELECTTIMERFFORSYNCCOUNTERSTART 0
#define MW_HRTIM_SELECTMAINTIMERFORSYNCCOUNTERSTART 0
#define MW_HRTIM_TIMERINTERRUPTSELECT 0
#define MW_HRTIM_TIMERADELAYEDPROTECTIONINTERRUPT 0
#define MW_HRTIM_TIMERARESETROLLOVERINTERRUPT 0
#define MW_HRTIM_TIMERAOUTPUT1RESETINTERRUPT 0
#define MW_HRTIM_TIMERAOUTPUT2RESETINTERRUPT 0
#define MW_HRTIM_TIMERAOUTPUT1SETINTERRUPT 0
#define MW_HRTIM_TIMERAOUTPUT2SETINTERRUPT 0
#define MW_HRTIM_TIMERACAPTURE1EVENTINTERRUPT 0
#define MW_HRTIM_TIMERACAPTURE2EVENTINTERRUPT 0
#define MW_HRTIM_TIMERAUPDATEEVENTINTERRUPT 0
#define MW_HRTIM_TIMERAREPETITIONEVENTINTERRUPT 0
#define MW_HRTIM_TIMERACOMPARE1EVENTINTERRUPT 0
#define MW_HRTIM_TIMERACOMPARE2EVENTINTERRUPT 0
#define MW_HRTIM_TIMERACOMPARE3EVENTINTERRUPT 0
#define MW_HRTIM_TIMERACOMPARE4EVENTINTERRUPT 0
#define MW_HRTIM_TIMERBDELAYEDPROTECTIONINTERRUPT 0
#define MW_HRTIM_TIMERBRESETROLLOVERINTERRUPT 0
#define MW_HRTIM_TIMERBOUTPUT1RESETINTERRUPT 0
#define MW_HRTIM_TIMERBOUTPUT2RESETINTERRUPT 0
#define MW_HRTIM_TIMERBOUTPUT1SETINTERRUPT 0
#define MW_HRTIM_TIMERBOUTPUT2SETINTERRUPT 0
#define MW_HRTIM_TIMERBCAPTURE1EVENTINTERRUPT 0
#define MW_HRTIM_TIMERBCAPTURE2EVENTINTERRUPT 0
#define MW_HRTIM_TIMERBUPDATEEVENTINTERRUPT 0
#define MW_HRTIM_TIMERBREPETITIONEVENTINTERRUPT 0
#define MW_HRTIM_TIMERBCOMPARE1EVENTINTERRUPT 0
#define MW_HRTIM_TIMERBCOMPARE2EVENTINTERRUPT 0
#define MW_HRTIM_TIMERBCOMPARE3EVENTINTERRUPT 0
#define MW_HRTIM_TIMERBCOMPARE4EVENTINTERRUPT 0
#define MW_HRTIM_TIMERCDELAYEDPROTECTIONINTERRUPT 0
#define MW_HRTIM_TIMERCRESETROLLOVERINTERRUPT 0
#define MW_HRTIM_TIMERCOUTPUT1RESETINTERRUPT 0
#define MW_HRTIM_TIMERCOUTPUT2RESETINTERRUPT 0
#define MW_HRTIM_TIMERCOUTPUT1SETINTERRUPT 0
#define MW_HRTIM_TIMERCOUTPUT2SETINTERRUPT 0
#define MW_HRTIM_TIMERCCAPTURE1EVENTINTERRUPT 0
#define MW_HRTIM_TIMERCCAPTURE2EVENTINTERRUPT 0
#define MW_HRTIM_TIMERCUPDATEEVENTINTERRUPT 0
#define MW_HRTIM_TIMERCREPETITIONEVENTINTERRUPT 0
#define MW_HRTIM_TIMERCCOMPARE1EVENTINTERRUPT 0
#define MW_HRTIM_TIMERCCOMPARE2EVENTINTERRUPT 0
#define MW_HRTIM_TIMERCCOMPARE3EVENTINTERRUPT 0
#define MW_HRTIM_TIMERCCOMPARE4EVENTINTERRUPT 0
#define MW_HRTIM_TIMERDDELAYEDPROTECTIONINTERRUPT 0
#define MW_HRTIM_TIMERDRESETROLLOVERINTERRUPT 0
#define MW_HRTIM_TIMERDOUTPUT1RESETINTERRUPT 0
#define MW_HRTIM_TIMERDOUTPUT2RESETINTERRUPT 0
#define MW_HRTIM_TIMERDOUTPUT1SETINTERRUPT 0
#define MW_HRTIM_TIMERDOUTPUT2SETINTERRUPT 0
#define MW_HRTIM_TIMERDCAPTURE1EVENTINTERRUPT 0
#define MW_HRTIM_TIMERDCAPTURE2EVENTINTERRUPT 0
#define MW_HRTIM_TIMERDUPDATEEVENTINTERRUPT 0
#define MW_HRTIM_TIMERDREPETITIONEVENTINTERRUPT 0
#define MW_HRTIM_TIMERDCOMPARE1EVENTINTERRUPT 0
#define MW_HRTIM_TIMERDCOMPARE2EVENTINTERRUPT 0
#define MW_HRTIM_TIMERDCOMPARE3EVENTINTERRUPT 0
#define MW_HRTIM_TIMERDCOMPARE4EVENTINTERRUPT 0
#define MW_HRTIM_TIMEREDELAYEDPROTECTIONINTERRUPT 0
#define MW_HRTIM_TIMERERESETROLLOVERINTERRUPT 0
#define MW_HRTIM_TIMEREOUTPUT1RESETINTERRUPT 0
#define MW_HRTIM_TIMEREOUTPUT2RESETINTERRUPT 0
#define MW_HRTIM_TIMEREOUTPUT1SETINTERRUPT 0
#define MW_HRTIM_TIMEREOUTPUT2SETINTERRUPT 0
#define MW_HRTIM_TIMERECAPTURE1EVENTINTERRUPT 0
#define MW_HRTIM_TIMERECAPTURE2EVENTINTERRUPT 0
#define MW_HRTIM_TIMEREUPDATEEVENTINTERRUPT 0
#define MW_HRTIM_TIMEREREPETITIONEVENTINTERRUPT 0
#define MW_HRTIM_TIMERECOMPARE1EVENTINTERRUPT 0
#define MW_HRTIM_TIMERECOMPARE2EVENTINTERRUPT 0
#define MW_HRTIM_TIMERECOMPARE3EVENTINTERRUPT 0
#define MW_HRTIM_TIMERECOMPARE4EVENTINTERRUPT 0
#define MW_HRTIM_TIMERFDELAYEDPROTECTIONINTERRUPT 0
#define MW_HRTIM_TIMERFRESETROLLOVERINTERRUPT 0
#define MW_HRTIM_TIMERFOUTPUT1RESETINTERRUPT 0
#define MW_HRTIM_TIMERFOUTPUT2RESETINTERRUPT 0
#define MW_HRTIM_TIMERFOUTPUT1SETINTERRUPT 0
#define MW_HRTIM_TIMERFOUTPUT2SETINTERRUPT 0
#define MW_HRTIM_TIMERFCAPTURE1EVENTINTERRUPT 0
#define MW_HRTIM_TIMERFCAPTURE2EVENTINTERRUPT 0
#define MW_HRTIM_TIMERFUPDATEEVENTINTERRUPT 0
#define MW_HRTIM_TIMERFREPETITIONEVENTINTERRUPT 0
#define MW_HRTIM_TIMERFCOMPARE1EVENTINTERRUPT 0
#define MW_HRTIM_TIMERFCOMPARE2EVENTINTERRUPT 0
#define MW_HRTIM_TIMERFCOMPARE3EVENTINTERRUPT 0
#define MW_HRTIM_TIMERFCOMPARE4EVENTINTERRUPT 0
#define MW_HRTIM_MAINTIMERRREGISTERUPDATEINTERRUPT 0
#define MW_HRTIM_MAINTIMERSYNCEVENTINTERRUPT 0
#define MW_HRTIM_MAINTIMERREPETITIONEVENTINTERRUPT 0
#define MW_HRTIM_MAINTIMERCOMPARE1EVENTINTERRUPT 0
#define MW_HRTIM_MAINTIMERCOMPARE2EVENTINTERRUPT 0
#define MW_HRTIM_MAINTIMERCOMPARE3EVENTINTERRUPT 0
#define MW_HRTIM_MAINTIMERCOMPARE4EVENTINTERRUPT 0
#define MW_HRTIM_DLLCALDONEINTERRUPT 0
#define MW_HRTIM_BURSTPRDDONETINTERRUPT 0
#define MW_HRTIM_SYSFAULTEVENTINTERRUPT 0
#define MW_HRTIM_FAULT1EVENTINTERRUPT 0
#define MW_HRTIM_FAULT2EVENTINTERRUPT 0
#define MW_HRTIM_FAULT3EVENTINTERRUPT 0
#define MW_HRTIM_FAULT4EVENTINTERRUPT 0
#define MW_HRTIM_FAULT5EVENTINTERRUPT 0
#define MW_TIMER_TIMERGROUP 0
#define MW_TIMER_TIM1CONFIGUREMODULE 1
#define MW_TIMER_TIM8CONFIGUREMODULE 48
#define MW_TIMER_TIM20CONFIGUREMODULE 48
#define MW_TIMER_TIM2CONFIGUREMODULE 48
#define MW_TIMER_TIM3CONFIGUREMODULE 48
#define MW_TIMER_TIM4CONFIGUREMODULE 48
#define MW_TIMER_TIM5CONFIGUREMODULE 48
#define MW_TIMER_TIM19CONFIGUREMODULE 48
#define MW_TIMER_TIM6CONFIGUREMODULE 48
#define MW_TIMER_TIM7CONFIGUREMODULE 48
#define MW_TIMER_TIM18CONFIGUREMODULE 48
#define MW_TIMER_TIM12CONFIGUREMODULE 48
#define MW_TIMER_TIM13CONFIGUREMODULE 48
#define MW_TIMER_TIM14CONFIGUREMODULE 48
#define MW_TIMER_TIM15CONFIGUREMODULE 48
#define MW_TIMER_TIM16CONFIGUREMODULE 48
#define MW_TIMER_TIM17CONFIGUREMODULE 48
#define MW_TIM1_STARTTIMER 49
#define MW_TIM1_TRIGGERINTERRUPT 48
#define MW_TIM1_CAPTURECOMPARE1INTERRUPT 48
#define MW_TIM1_CAPTURECOMPARE2INTERRUPT 48
#define MW_TIM1_CAPTURECOMPARE3INTERRUPT 48
#define MW_TIM1_CAPTURECOMPARE4INTERRUPT 48
#define MW_TIM1_UPDATEINTERRUPT 48
#define MW_TIM1_BREAKINTERRUPT 48
#define MW_TIM1_COMINTERRUPT 48
#define MW_TIM8_STARTTIMER 49
#define MW_TIM8_TRIGGERINTERRUPT 48
#define MW_TIM8_CAPTURECOMPARE1INTERRUPT 48
#define MW_TIM8_CAPTURECOMPARE2INTERRUPT 48
#define MW_TIM8_CAPTURECOMPARE3INTERRUPT 48
#define MW_TIM8_CAPTURECOMPARE4INTERRUPT 48
#define MW_TIM8_UPDATEINTERRUPT 48
#define MW_TIM8_BREAKINTERRUPT 48
#define MW_TIM8_COMINTERRUPT 48
#define MW_TIM20_STARTTIMER 49
#define MW_TIM20_TRIGGERINTERRUPT 48
#define MW_TIM20_CAPTURECOMPARE1INTERRUPT 48
#define MW_TIM20_CAPTURECOMPARE2INTERRUPT 48
#define MW_TIM20_CAPTURECOMPARE3INTERRUPT 48
#define MW_TIM20_CAPTURECOMPARE4INTERRUPT 48
#define MW_TIM20_UPDATEINTERRUPT 48
#define MW_TIM20_BREAKINTERRUPT 48
#define MW_TIM20_COMINTERRUPT 48
#define MW_TIM2_STARTTIMER 49
#define MW_TIM2_TRIGGERINTERRUPT 48
#define MW_TIM2_CAPTURECOMPARE1INTERRUPT 48
#define MW_TIM2_CAPTURECOMPARE2INTERRUPT 48
#define MW_TIM2_CAPTURECOMPARE3INTERRUPT 48
#define MW_TIM2_CAPTURECOMPARE4INTERRUPT 48
#define MW_TIM2_UPDATEINTERRUPT 48
#define MW_TIM3_STARTTIMER 49
#define MW_TIM3_TRIGGERINTERRUPT 48
#define MW_TIM3_CAPTURECOMPARE1INTERRUPT 48
#define MW_TIM3_CAPTURECOMPARE2INTERRUPT 48
#define MW_TIM3_CAPTURECOMPARE3INTERRUPT 48
#define MW_TIM3_CAPTURECOMPARE4INTERRUPT 48
#define MW_TIM3_UPDATEINTERRUPT 48
#define MW_TIM4_STARTTIMER 49
#define MW_TIM4_TRIGGERINTERRUPT 48
#define MW_TIM4_CAPTURECOMPARE1INTERRUPT 48
#define MW_TIM4_CAPTURECOMPARE2INTERRUPT 48
#define MW_TIM4_CAPTURECOMPARE3INTERRUPT 48
#define MW_TIM4_CAPTURECOMPARE4INTERRUPT 48
#define MW_TIM4_UPDATEINTERRUPT 48
#define MW_TIM5_STARTTIMER 49
#define MW_TIM5_TRIGGERINTERRUPT 48
#define MW_TIM5_CAPTURECOMPARE1INTERRUPT 48
#define MW_TIM5_CAPTURECOMPARE2INTERRUPT 48
#define MW_TIM5_CAPTURECOMPARE3INTERRUPT 48
#define MW_TIM5_CAPTURECOMPARE4INTERRUPT 48
#define MW_TIM5_UPDATEINTERRUPT 48
#define MW_TIM19_STARTTIMER 49
#define MW_TIM19_TRIGGERINTERRUPT 48
#define MW_TIM19_CAPTURECOMPARE1INTERRUPT 48
#define MW_TIM19_CAPTURECOMPARE2INTERRUPT 48
#define MW_TIM19_CAPTURECOMPARE3INTERRUPT 48
#define MW_TIM19_CAPTURECOMPARE4INTERRUPT 48
#define MW_TIM19_UPDATEINTERRUPT 48
#define MW_TIM6_STARTTIMER 49
#define MW_TIM6_UPDATEINTERRUPT 48
#define MW_TIM7_STARTTIMER 49
#define MW_TIM7_UPDATEINTERRUPT 48
#define MW_TIM18_STARTTIMER 49
#define MW_TIM18_UPDATEINTERRUPT 48
#define MW_TIM12_STARTTIMER 49
#define MW_TIM12_CAPTURECOMPARE1INTERRUPT 48
#define MW_TIM12_CAPTURECOMPARE2INTERRUPT 48
#define MW_TIM12_UPDATEINTERRUPT 48
#define MW_TIM13_STARTTIMER 49
#define MW_TIM13_CAPTURECOMPARE1INTERRUPT 48
#define MW_TIM13_UPDATEINTERRUPT 48
#define MW_TIM14_STARTTIMER 49
#define MW_TIM14_CAPTURECOMPARE1INTERRUPT 48
#define MW_TIM14_UPDATEINTERRUPT 48
#define MW_TIM15_STARTTIMER 49
#define MW_TIM15_TRIGGERINTERRUPT 48
#define MW_TIM15_CAPTURECOMPARE1INTERRUPT 48
#define MW_TIM15_CAPTURECOMPARE2INTERRUPT 48
#define MW_TIM15_CAPTURECOMPARE3INTERRUPT 48
#define MW_TIM15_CAPTURECOMPARE4INTERRUPT 48
#define MW_TIM15_UPDATEINTERRUPT 48
#define MW_TIM15_BREAKINTERRUPT 48
#define MW_TIM15_COMINTERRUPT 48
#define MW_TIM16_STARTTIMER 49
#define MW_TIM16_CAPTURECOMPARE1INTERRUPT 48
#define MW_TIM16_UPDATEINTERRUPT 48
#define MW_TIM17_STARTTIMER 49
#define MW_TIM17_CAPTURECOMPARE1INTERRUPT 48
#define MW_TIM17_UPDATEINTERRUPT 48
#define MW_CAN_MODULE 0
#define MW_CAN1_BAUDRATE 1000000
#define MW_CAN1_CONFIGUREINTENRX 0
#define MW_CAN1_CONFIGUREINTFIFO0RX 0
#define MW_CAN1_ENABLEFIFO0MSGPENDINGINTR 0
#define MW_CAN1_ENABLEFIFO0FULLINTR 0
#define MW_CAN1_ENABLEFIFO0OVRINTR 0
#define MW_CAN1_CONFIGUREINTFIFO1RX 0
#define MW_CAN1_ENABLEFIFO1MSGPENDINGINTR 0
#define MW_CAN1_ENABLEFIFO1FULLINTR 0
#define MW_CAN1_ENABLEFIFO1OVRINTR 0
#define MW_CAN1_CONFIGUREINTENTX 0
#define MW_CAN1_ENABLETXMAILBOXEMPTYINTR 0
#define MW_CAN1_CONFIGUREINTENOTHER 0
#define MW_CAN1_ENABLEERRWARNINTR 0
#define MW_CAN1_ENABLEERRPASSIVEINTR 0
#define MW_CAN1_ENABLEBUSOFFINTR 0
#define MW_CAN1_ENABLELASTERRCODEINTR 0
#define MW_CAN1_ENABLEWAKEUPINTR 0
#define MW_CAN1_ENABLESLEEPACKINTR 0
#define MW_CAN1_ACCEPTALLMESSAGES 1
#define MW_CAN1_FILTERBANKNUMBER 0
#define MW_CAN1_ENABLEFILTERBANK00 0
#define MW_CAN1_SCALE00 0
#define MW_CAN1_MODE00 0
#define MW_CAN1_FIFOASSIGNMENT00 0
#define MW_CAN1_IDTYPE00 0
#define MW_CAN1_ID1_00 0
#define MW_CAN1_MASK1_00 0
#define MW_CAN1_ID2_00 0
#define MW_CAN1_MASK2_00 0
#define MW_CAN1_ID3_00 0
#define MW_CAN1_ID4_00 0
#define MW_CAN1_ENABLEFILTERBANK01 0
#define MW_CAN1_SCALE01 0
#define MW_CAN1_MODE01 0
#define MW_CAN1_FIFOASSIGNMENT01 0
#define MW_CAN1_IDTYPE01 0
#define MW_CAN1_ID1_01 0
#define MW_CAN1_MASK1_01 0
#define MW_CAN1_ID2_01 0
#define MW_CAN1_MASK2_01 0
#define MW_CAN1_ID3_01 0
#define MW_CAN1_ID4_01 0
#define MW_CAN1_ENABLEFILTERBANK02 0
#define MW_CAN1_SCALE02 0
#define MW_CAN1_MODE02 0
#define MW_CAN1_FIFOASSIGNMENT02 0
#define MW_CAN1_IDTYPE02 0
#define MW_CAN1_ID1_02 0
#define MW_CAN1_MASK1_02 0
#define MW_CAN1_ID2_02 0
#define MW_CAN1_MASK2_02 0
#define MW_CAN1_ID3_02 0
#define MW_CAN1_ID4_02 0
#define MW_CAN1_ENABLEFILTERBANK03 0
#define MW_CAN1_SCALE03 0
#define MW_CAN1_MODE03 0
#define MW_CAN1_FIFOASSIGNMENT03 0
#define MW_CAN1_IDTYPE03 0
#define MW_CAN1_ID1_03 0
#define MW_CAN1_MASK1_03 0
#define MW_CAN1_ID2_03 0
#define MW_CAN1_MASK2_03 0
#define MW_CAN1_ID3_03 0
#define MW_CAN1_ID4_03 0
#define MW_CAN1_ENABLEFILTERBANK04 0
#define MW_CAN1_SCALE04 0
#define MW_CAN1_MODE04 0
#define MW_CAN1_FIFOASSIGNMENT04 0
#define MW_CAN1_IDTYPE04 0
#define MW_CAN1_ID1_04 0
#define MW_CAN1_MASK1_04 0
#define MW_CAN1_ID2_04 0
#define MW_CAN1_MASK2_04 0
#define MW_CAN1_ID3_04 0
#define MW_CAN1_ID4_04 0
#define MW_CAN1_ENABLEFILTERBANK05 0
#define MW_CAN1_SCALE05 0
#define MW_CAN1_MODE05 0
#define MW_CAN1_FIFOASSIGNMENT05 0
#define MW_CAN1_IDTYPE05 0
#define MW_CAN1_ID1_05 0
#define MW_CAN1_MASK1_05 0
#define MW_CAN1_ID2_05 0
#define MW_CAN1_MASK2_05 0
#define MW_CAN1_ID3_05 0
#define MW_CAN1_ID4_05 0
#define MW_CAN1_ENABLEFILTERBANK06 0
#define MW_CAN1_SCALE06 0
#define MW_CAN1_MODE06 0
#define MW_CAN1_FIFOASSIGNMENT06 0
#define MW_CAN1_IDTYPE06 0
#define MW_CAN1_ID1_06 0
#define MW_CAN1_MASK1_06 0
#define MW_CAN1_ID2_06 0
#define MW_CAN1_MASK2_06 0
#define MW_CAN1_ID3_06 0
#define MW_CAN1_ID4_06 0
#define MW_CAN1_ENABLEFILTERBANK07 0
#define MW_CAN1_SCALE07 0
#define MW_CAN1_MODE07 0
#define MW_CAN1_FIFOASSIGNMENT07 0
#define MW_CAN1_IDTYPE07 0
#define MW_CAN1_ID1_07 0
#define MW_CAN1_MASK1_07 0
#define MW_CAN1_ID2_07 0
#define MW_CAN1_MASK2_07 0
#define MW_CAN1_ID3_07 0
#define MW_CAN1_ID4_07 0
#define MW_CAN1_ENABLEFILTERBANK08 0
#define MW_CAN1_SCALE08 0
#define MW_CAN1_MODE08 0
#define MW_CAN1_FIFOASSIGNMENT08 0
#define MW_CAN1_IDTYPE08 0
#define MW_CAN1_ID1_08 0
#define MW_CAN1_MASK1_08 0
#define MW_CAN1_ID2_08 0
#define MW_CAN1_MASK2_08 0
#define MW_CAN1_ID3_08 0
#define MW_CAN1_ID4_08 0
#define MW_CAN1_ENABLEFILTERBANK09 0
#define MW_CAN1_SCALE09 0
#define MW_CAN1_MODE09 0
#define MW_CAN1_FIFOASSIGNMENT09 0
#define MW_CAN1_IDTYPE09 0
#define MW_CAN1_ID1_09 0
#define MW_CAN1_MASK1_09 0
#define MW_CAN1_ID2_09 0
#define MW_CAN1_MASK2_09 0
#define MW_CAN1_ID3_09 0
#define MW_CAN1_ID4_09 0
#define MW_CAN1_ENABLEFILTERBANK10 0
#define MW_CAN1_SCALE10 0
#define MW_CAN1_MODE10 0
#define MW_CAN1_FIFOASSIGNMENT10 0
#define MW_CAN1_IDTYPE10 0
#define MW_CAN1_ID1_10 0
#define MW_CAN1_MASK1_10 0
#define MW_CAN1_ID2_10 0
#define MW_CAN1_MASK2_10 0
#define MW_CAN1_ID3_10 0
#define MW_CAN1_ID4_10 0
#define MW_CAN1_ENABLEFILTERBANK11 0
#define MW_CAN1_SCALE11 0
#define MW_CAN1_MODE11 0
#define MW_CAN1_FIFOASSIGNMENT11 0
#define MW_CAN1_IDTYPE11 0
#define MW_CAN1_ID1_11 0
#define MW_CAN1_MASK1_11 0
#define MW_CAN1_ID2_11 0
#define MW_CAN1_MASK2_11 0
#define MW_CAN1_ID3_11 0
#define MW_CAN1_ID4_11 0
#define MW_CAN1_ENABLEFILTERBANK12 0
#define MW_CAN1_SCALE12 0
#define MW_CAN1_MODE12 0
#define MW_CAN1_FIFOASSIGNMENT12 0
#define MW_CAN1_IDTYPE12 0
#define MW_CAN1_ID1_12 0
#define MW_CAN1_MASK1_12 0
#define MW_CAN1_ID2_12 0
#define MW_CAN1_MASK2_12 0
#define MW_CAN1_ID3_12 0
#define MW_CAN1_ID4_12 0
#define MW_CAN1_ENABLEFILTERBANK13 0
#define MW_CAN1_SCALE13 0
#define MW_CAN1_MODE13 0
#define MW_CAN1_FIFOASSIGNMENT13 0
#define MW_CAN1_IDTYPE13 0
#define MW_CAN1_ID1_13 0
#define MW_CAN1_MASK1_13 0
#define MW_CAN1_ID2_13 0
#define MW_CAN1_MASK2_13 0
#define MW_CAN1_ID3_13 0
#define MW_CAN1_ID4_13 0
#define MW_SENSOR_FILELOCATION stm32cube.sensors
#define MW_IOBLOCKSMODE deployed
#define MW_DATAVERSION 2016.02
#endif /* __MW_TARGET_HARDWARE_RESOURCES_H__ */
#endif
#endif

36
Controller/include/rtmodel.h Normal file
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/*
* Academic License - for use in teaching, academic research, and meeting
* course requirements at degree granting institutions only. Not for
* government, commercial, or other organizational use.
*
* File: rtmodel.h
*
* Code generated for Simulink model 'Controller'.
*
* Model version : 2.23
* Simulink Coder version : 25.1 (R2025a) 21-Nov-2024
* C/C++ source code generated on : Sat Jun 14 13:33:39 2025
*
* Target selection: ert.tlc
* Embedded hardware selection: ARM Compatible->ARM Cortex-M
* Code generation objectives:
* 1. Execution efficiency
* 2. RAM efficiency
* Validation result: Not run
*/
#ifndef rtmodel_h_
#define rtmodel_h_
#include "Controller.h"
/* Macros generated for backwards compatibility */
#ifndef rtmGetStopRequested
#define rtmGetStopRequested(rtm) ((void*) 0)
#endif
#endif /* rtmodel_h_ */
/*
* File trailer for generated code.
*
* [EOF]
*/

106
Controller/include/rtwtypes.h Normal file
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/*
* Academic License - for use in teaching, academic research, and meeting
* course requirements at degree granting institutions only. Not for
* government, commercial, or other organizational use.
*
* File: rtwtypes.h
*
* Code generated for Simulink model 'Controller'.
*
* Model version : 2.23
* Simulink Coder version : 25.1 (R2025a) 21-Nov-2024
* C/C++ source code generated on : Sat Jun 14 13:33:39 2025
*
* Target selection: ert.tlc
* Embedded hardware selection: ARM Compatible->ARM Cortex-M
* Code generation objectives:
* 1. Execution efficiency
* 2. RAM efficiency
* Validation result: Not run
*/
#ifndef RTWTYPES_H
#define RTWTYPES_H
/* Logical type definitions */
#if (!defined(__cplusplus))
#ifndef false
#define false (0U)
#endif
#ifndef true
#define true (1U)
#endif
#endif
/*=======================================================================*
* Target hardware information
* Device type: ARM Compatible->ARM Cortex-M
* Number of bits: char: 8 short: 16 int: 32
* long: 32 long long: 64
* native word size: 32
* Byte ordering: LittleEndian
* Signed integer division rounds to: Zero
* Shift right on a signed integer as arithmetic shift: on
*=======================================================================*/
/*=======================================================================*
* Fixed width word size data types: *
* int8_T, int16_T, int32_T - signed 8, 16, or 32 bit integers *
* uint8_T, uint16_T, uint32_T - unsigned 8, 16, or 32 bit integers *
* real32_T, real64_T - 32 and 64 bit floating point numbers *
*=======================================================================*/
typedef signed char int8_T;
typedef unsigned char uint8_T;
typedef short int16_T;
typedef unsigned short uint16_T;
typedef int int32_T;
typedef unsigned int uint32_T;
typedef long long int64_T;
typedef unsigned long long uint64_T;
typedef float real32_T;
typedef double real64_T;
/*===========================================================================*
* Generic type definitions: boolean_T, char_T, byte_T, int_T, uint_T, *
* real_T, time_T, ulong_T, ulonglong_T. *
*===========================================================================*/
typedef double real_T;
typedef double time_T;
typedef unsigned char boolean_T;
typedef int int_T;
typedef unsigned int uint_T;
typedef unsigned long ulong_T;
typedef unsigned long long ulonglong_T;
typedef char char_T;
typedef unsigned char uchar_T;
typedef char_T byte_T;
/*=======================================================================*
* Min and Max: *
* int8_T, int16_T, int32_T - signed 8, 16, or 32 bit integers *
* uint8_T, uint16_T, uint32_T - unsigned 8, 16, or 32 bit integers *
*=======================================================================*/
#define MAX_int8_T ((int8_T)(127))
#define MIN_int8_T ((int8_T)(-128))
#define MAX_uint8_T ((uint8_T)(255U))
#define MAX_int16_T ((int16_T)(32767))
#define MIN_int16_T ((int16_T)(-32768))
#define MAX_uint16_T ((uint16_T)(65535U))
#define MAX_int32_T ((int32_T)(2147483647))
#define MIN_int32_T ((int32_T)(-2147483647-1))
#define MAX_uint32_T ((uint32_T)(0xFFFFFFFFU))
#define MAX_int64_T ((int64_T)(9223372036854775807LL))
#define MIN_int64_T ((int64_T)(-9223372036854775807LL-1LL))
#define MAX_uint64_T ((uint64_T)(0xFFFFFFFFFFFFFFFFULL))
/* Block D-Work pointer type */
typedef void * pointer_T;
#endif /* RTWTYPES_H */
/*
* File trailer for generated code.
*
* [EOF]
*/