diff --git a/.gitignore b/.gitignore index 205337f..4dd382c 100644 --- a/.gitignore +++ b/.gitignore @@ -37,3 +37,6 @@ Desktop.ini *.lst *.xml *.log* +*.rpt +*.rpt* +*.tag \ No newline at end of file diff --git a/RK3506_NAV.DSN b/RK3506_NAV.DSN index 7d552f2..468a787 100644 Binary files a/RK3506_NAV.DSN and b/RK3506_NAV.DSN differ diff --git a/allegro/chipsview.dat b/allegro/chipsview.dat index c34d14f..b0e0bcf 100644 --- a/allegro/chipsview.dat +++ b/allegro/chipsview.dat @@ -1,4 +1,2049 @@ FILE_TYPE=LIBRARY_PARTS; +primitive 'TLV62569DBVR_SOT_23_5_TLV62569DBV'; + pin + '\VIN\': + PIN_NUMBER='(4)'; + PINUSE='POWER'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\SW\': + PIN_NUMBER='(3)'; + PINUSE='POWER'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\GND\': + PIN_NUMBER='(2)'; + PINUSE='POWER'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\FB\': + PIN_NUMBER='(5)'; + INPUT_LOAD='(-0.01,0.01)'; + '\EN\': + PIN_NUMBER='(1)'; + INPUT_LOAD='(-0.01,0.01)'; + end_pin; + body + PART_NAME='TLV62569DBVR'; + VALUE='TLV62569DBV'; + BODY_NAME='TLV62569DBVR_SOT_23_5_TLV62569DBV'; + JEDEC_TYPE='SOT_23_5'; + PHYS_DES_PREFIX='U'; + CLASS='IC'; + end_body; +end_primitive; + +primitive 'INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L'; + pin + '\RFU9\': + PIN_NUMBER='(0,P10)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\RFU8\': + PIN_NUMBER='(0,P7)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\RFU7\': + PIN_NUMBER='(0,K7)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\RFU6\': + PIN_NUMBER='(0,K6)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\RFU5\': + PIN_NUMBER='(0,G10)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\RFU4\': + PIN_NUMBER='(0,G3)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\RFU3\': + PIN_NUMBER='(0,E8)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\RFU2\': + PIN_NUMBER='(0,E5)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\RFU1\': + PIN_NUMBER='(0,A7)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\NC9\': + PIN_NUMBER='(0,A9)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\NC99\': + PIN_NUMBER='(0,H1)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\NC98\': + PIN_NUMBER='(0,G14)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\NC97\': + PIN_NUMBER='(0,G13)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\NC96\': + PIN_NUMBER='(0,G12)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\NC8\': + PIN_NUMBER='(0,A8)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\NC86\': + PIN_NUMBER='(0,G2)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\NC85\': + PIN_NUMBER='(0,G1)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\NC84\': + PIN_NUMBER='(0,F14)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\NC83\': + PIN_NUMBER='(0,F13)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\NC82\': + PIN_NUMBER='(0,F12)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\NC73\': + PIN_NUMBER='(0,F3)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\NC72\': + PIN_NUMBER='(0,F2)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\NC71\': + PIN_NUMBER='(0,F1)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\NC70\': + PIN_NUMBER='(0,E14)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\NC69\': + PIN_NUMBER='(0,E13)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\NC68\': + PIN_NUMBER='(0,E12)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\NC59\': + PIN_NUMBER='(0,E3)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\NC58\': + PIN_NUMBER='(0,E2)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\NC57\': + PIN_NUMBER='(0,E1)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\NC56\': + PIN_NUMBER='(0,D14)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\NC55\': + PIN_NUMBER='(0,D13)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\NC54\': + PIN_NUMBER='(0,D12)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\NC46\': + PIN_NUMBER='(0,D4)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\NC45\': + PIN_NUMBER='(0,D3)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\NC44\': + PIN_NUMBER='(0,D2)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\NC43\': + PIN_NUMBER='(0,D1)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\NC42\': + PIN_NUMBER='(0,C14)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\NC41\': + PIN_NUMBER='(0,C13)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\NC40\': + PIN_NUMBER='(0,C12)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\NC39\': + PIN_NUMBER='(0,C11)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\NC38\': + PIN_NUMBER='(0,C10)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\NC37\': + PIN_NUMBER='(0,C9)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\NC36\': + PIN_NUMBER='(0,C8)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\NC35\': + PIN_NUMBER='(0,C7)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\NC31\': + PIN_NUMBER='(0,C3)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\NC2\': + PIN_NUMBER='(0,A2)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\NC29\': + PIN_NUMBER='(0,C1)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\NC28\': + PIN_NUMBER='(0,B14)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\NC27\': + PIN_NUMBER='(0,B13)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\NC26\': + PIN_NUMBER='(0,B12)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\NC25\': + PIN_NUMBER='(0,B11)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\NC24\': + PIN_NUMBER='(0,B10)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\NC23\': + PIN_NUMBER='(0,B9)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\NC22\': + PIN_NUMBER='(0,B8)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\NC21\': + PIN_NUMBER='(0,B7)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\NC196\': + PIN_NUMBER='(0,P14)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\NC195\': + PIN_NUMBER='(0,P13)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\NC194\': + PIN_NUMBER='(0,P12)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\NC193\': + PIN_NUMBER='(0,P11)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\NC191\': + PIN_NUMBER='(0,P9)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\NC190\': + PIN_NUMBER='(0,P8)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\NC184\': + PIN_NUMBER='(0,P2)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\NC183\': + PIN_NUMBER='(0,P1)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\NC182\': + PIN_NUMBER='(0,N14)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\NC181\': + PIN_NUMBER='(0,N13)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\NC180\': + PIN_NUMBER='(0,N12)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\NC179\': + PIN_NUMBER='(0,N11)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\NC178\': + PIN_NUMBER='(0,N10)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\NC177\': + PIN_NUMBER='(0,N9)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\NC176\': + PIN_NUMBER='(0,N8)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\NC175\': + PIN_NUMBER='(0,N7)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\NC174\': + PIN_NUMBER='(0,N6)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\NC171\': + PIN_NUMBER='(0,N3)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\NC169\': + PIN_NUMBER='(0,N1)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\NC168\': + PIN_NUMBER='(0,M14)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\NC167\': + PIN_NUMBER='(0,M13)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\NC166\': + PIN_NUMBER='(0,M12)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\NC165\': + PIN_NUMBER='(0,M11)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\NC164\': + PIN_NUMBER='(0,M10)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\NC163\': + PIN_NUMBER='(0,M9)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\NC162\': + PIN_NUMBER='(0,M8)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\NC161\': + PIN_NUMBER='(0,M7)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\NC15\': + PIN_NUMBER='(0,B1)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\NC157\': + PIN_NUMBER='(0,M3)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\NC156\': + PIN_NUMBER='(0,M2)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\NC155\': + PIN_NUMBER='(0,M1)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\NC154\': + PIN_NUMBER='(0,L14)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\NC153\': + PIN_NUMBER='(0,L13)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\NC152\': + PIN_NUMBER='(0,L12)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\NC14\': + PIN_NUMBER='(0,A14)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\NC143\': + PIN_NUMBER='(0,L3)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\NC142\': + PIN_NUMBER='(0,L2)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\NC141\': + PIN_NUMBER='(0,L1)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\NC140\': + PIN_NUMBER='(0,K14)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\NC13\': + PIN_NUMBER='(0,A13)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\NC139\': + PIN_NUMBER='(0,K13)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\NC138\': + PIN_NUMBER='(0,K12)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\NC12\': + PIN_NUMBER='(0,A12)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\NC129\': + PIN_NUMBER='(0,K3)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\NC128\': + PIN_NUMBER='(0,K2)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\NC127\': + PIN_NUMBER='(0,K1)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\NC126\': + PIN_NUMBER='(0,J14)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\NC125\': + PIN_NUMBER='(0,J13)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\NC124\': + PIN_NUMBER='(0,J12)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\NC11\': + PIN_NUMBER='(0,A11)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\NC115\': + PIN_NUMBER='(0,J3)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\NC114\': + PIN_NUMBER='(0,J2)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\NC113\': + PIN_NUMBER='(0,J1)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\NC112\': + PIN_NUMBER='(0,H14)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\NC111\': + PIN_NUMBER='(0,H13)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\NC110\': + PIN_NUMBER='(0,H12)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\NC10\': + PIN_NUMBER='(0,A10)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\NC101\': + PIN_NUMBER='(0,H3)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\NC100\': + PIN_NUMBER='(0,H2)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSSQ5\': + PIN_NUMBER='(P6,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSSQ4\': + PIN_NUMBER='(P4,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSSQ3\': + PIN_NUMBER='(N5,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSSQ2\': + PIN_NUMBER='(N2,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSSQ1\': + PIN_NUMBER='(K8,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS6\': + PIN_NUMBER='(H10,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS5\': + PIN_NUMBER='(G5,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS4\': + PIN_NUMBER='(E7,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS3\': + PIN_NUMBER='(C4,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS2\': + PIN_NUMBER='(A6,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS1\': + PIN_NUMBER='(J5,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSF4\': + PIN_NUMBER='(K10,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSF3\': + PIN_NUMBER='(F10,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSF2\': + PIN_NUMBER='(E10,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSF1\': + PIN_NUMBER='(E9,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VDDI\': + PIN_NUMBER='(C2,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VCCQ5\': + PIN_NUMBER='(P5,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VCCQ4\': + PIN_NUMBER='(P3,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VCCQ3\': + PIN_NUMBER='(N4,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VCCQ2\': + PIN_NUMBER='(M4,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VCCQ1\': + PIN_NUMBER='(C6,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VCC4\': + PIN_NUMBER='(K9,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VCC3\': + PIN_NUMBER='(J10,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VCC2\': + PIN_NUMBER='(F5,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VCC1\': + PIN_NUMBER='(E6,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\RST_N\': + PIN_NUMBER='(K5,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\DATA7\': + PIN_NUMBER='(B6,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\DATA6\': + PIN_NUMBER='(B5,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\DATA5\': + PIN_NUMBER='(B4,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\DATA4\': + PIN_NUMBER='(B3,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\DATA3\': + PIN_NUMBER='(B2,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\DATA2\': + PIN_NUMBER='(A5,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\DATA1\': + PIN_NUMBER='(A4,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\DATA0\': + PIN_NUMBER='(A3,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\DATA STROBE\': + PIN_NUMBER='(H5,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\CMD\': + PIN_NUMBER='(M5,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\CLK\': + PIN_NUMBER='(M6,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + end_pin; + body + PART_NAME='INAND_EMMC_153_2L'; + VALUE='INAND_EMMC_153_2L'; + BODY_NAME='INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L'; + JEDEC_TYPE='BGA153_050_1150X1300'; + PHYS_DES_PREFIX='U'; + CLASS='IC'; + end_body; +end_primitive; + +primitive 'DDR3_16BIT_FBGA96_14R00X11R00X1R20_DDR3_16BIT'; + pin + '\ZQ1\': + PIN_NUMBER='(L9)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\ZQ0\': + PIN_NUMBER='(L8)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\WE#\': + PIN_NUMBER='(L3)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSSQ9\': + PIN_NUMBER='(G9)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSSQ8\': + PIN_NUMBER='(G1)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSSQ7\': + PIN_NUMBER='(F9)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSSQ6\': + PIN_NUMBER='(E8)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSSQ5\': + PIN_NUMBER='(E2)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSSQ4\': + PIN_NUMBER='(D8)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSSQ3\': + PIN_NUMBER='(D1)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSSQ2\': + PIN_NUMBER='(B9)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSSQ1\': + PIN_NUMBER='(B1)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS9\': + PIN_NUMBER='(P1)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS8\': + PIN_NUMBER='(M9)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS7\': + PIN_NUMBER='(M1)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS6\': + PIN_NUMBER='(J8)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS5\': + PIN_NUMBER='(J2)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS4\': + PIN_NUMBER='(G8)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS3\': + PIN_NUMBER='(E1)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS2\': + PIN_NUMBER='(B3)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS1\': + PIN_NUMBER='(A9)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS12\': + PIN_NUMBER='(T9)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS11\': + PIN_NUMBER='(T1)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS10\': + PIN_NUMBER='(P9)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VREFDQ\': + PIN_NUMBER='(H1)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VREFCA\': + PIN_NUMBER='(M8)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VDDQ9\': + PIN_NUMBER='(H9)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VDDQ8\': + PIN_NUMBER='(H2)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VDDQ7\': + PIN_NUMBER='(F1)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VDDQ6\': + PIN_NUMBER='(E9)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VDDQ5\': + PIN_NUMBER='(D2)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VDDQ4\': + PIN_NUMBER='(C9)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VDDQ3\': + PIN_NUMBER='(C1)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VDDQ2\': + PIN_NUMBER='(A8)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VDDQ1\': + PIN_NUMBER='(A1)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VDD9\': + PIN_NUMBER='(R9)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VDD8\': + PIN_NUMBER='(R1)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VDD7\': + PIN_NUMBER='(N9)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VDD6\': + PIN_NUMBER='(N1)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VDD5\': + PIN_NUMBER='(K8)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VDD4\': + PIN_NUMBER='(K2)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VDD3\': + PIN_NUMBER='(G7)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VDD2\': + PIN_NUMBER='(D9)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VDD1\': + PIN_NUMBER='(B2)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\UDQS\': + PIN_NUMBER='(C7)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\UDQS#\': + PIN_NUMBER='(B7)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\UDM\': + PIN_NUMBER='(D3)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\RESET#\': + PIN_NUMBER='(T2)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\RAS#\': + PIN_NUMBER='(J3)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\ODT1\': + PIN_NUMBER='(J1)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\ODT0\': + PIN_NUMBER='(K1)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\LDQS\': + PIN_NUMBER='(F3)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\LDQS#\': + PIN_NUMBER='(G3)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\LDM\': + PIN_NUMBER='(E7)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\DQ9\': + PIN_NUMBER='(C3)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\DQ8\': + PIN_NUMBER='(D7)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\DQ7\': + PIN_NUMBER='(H7)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\DQ6\': + PIN_NUMBER='(G2)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\DQ5\': + PIN_NUMBER='(H8)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\DQ4\': + PIN_NUMBER='(H3)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\DQ3\': + PIN_NUMBER='(F8)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\DQ2\': + PIN_NUMBER='(F2)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\DQ1\': + PIN_NUMBER='(F7)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\DQ15\': + PIN_NUMBER='(A3)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\DQ14\': + PIN_NUMBER='(B8)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\DQ13\': + PIN_NUMBER='(A2)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\DQ12\': + PIN_NUMBER='(A7)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\DQ11\': + PIN_NUMBER='(C2)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\DQ10\': + PIN_NUMBER='(C8)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\DQ0\': + PIN_NUMBER='(E3)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\CS#1\': + PIN_NUMBER='(L1)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\CS#0\': + PIN_NUMBER='(L2)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\CK\': + PIN_NUMBER='(J7)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\CKE1\': + PIN_NUMBER='(J9)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\CKE0\': + PIN_NUMBER='(K9)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\CK#\': + PIN_NUMBER='(K7)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\CAS#\': + PIN_NUMBER='(K3)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\BA2\': + PIN_NUMBER='(M3)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\BA1\': + PIN_NUMBER='(N8)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\BA0\': + PIN_NUMBER='(M2)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\A9\': + PIN_NUMBER='(R3)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\A8\': + PIN_NUMBER='(T8)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\A7\': + PIN_NUMBER='(R2)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\A6\': + PIN_NUMBER='(R8)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\A5\': + PIN_NUMBER='(P2)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\A4\': + PIN_NUMBER='(P8)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\A3\': + PIN_NUMBER='(N2)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\A2\': + PIN_NUMBER='(P3)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\A1\': + PIN_NUMBER='(P7)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\A15\': + PIN_NUMBER='(M7)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\A14\': + PIN_NUMBER='(T7)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\A13\': + PIN_NUMBER='(T3)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\A12/BC#\': + PIN_NUMBER='(N7)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\A11\': + PIN_NUMBER='(R7)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\A10/AP\': + PIN_NUMBER='(L7)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\A0\': + PIN_NUMBER='(N3)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + end_pin; + body + PART_NAME='DDR3_16bit'; + VALUE='DDR3_16bit'; + BODY_NAME='DDR3_16BIT_FBGA96_14R00X11R00X1R20_DDR3_16BIT'; + JEDEC_TYPE='FBGA96_14R00X11R00X1R20'; + PHYS_DES_PREFIX='U'; + CLASS='IC'; + end_body; +end_primitive; + primitive 'CAP NP_C0402_DISCRETE_18PF'; pin '2': @@ -3835,49 +5880,6 @@ primitive 'LAN8720A-CP-ABC_QFN24-6X6_MC_MCH_LAN8720A-CP-ABC'; end_body; end_primitive; -primitive 'TLV62569DBVR_DBV0005A_N_TLV62569DBV'; - pin - '\VIN\': - PIN_NUMBER='(4)'; - PINUSE='POWER'; - NO_LOAD_CHECK='Both'; - NO_IO_CHECK='Both'; - NO_ASSERT_CHECK='TRUE'; - NO_DIR_CHECK='TRUE'; - ALLOW_CONNECT='TRUE'; - '\SW\': - PIN_NUMBER='(3)'; - PINUSE='POWER'; - NO_LOAD_CHECK='Both'; - NO_IO_CHECK='Both'; - NO_ASSERT_CHECK='TRUE'; - NO_DIR_CHECK='TRUE'; - ALLOW_CONNECT='TRUE'; - '\GND\': - PIN_NUMBER='(2)'; - PINUSE='POWER'; - NO_LOAD_CHECK='Both'; - NO_IO_CHECK='Both'; - NO_ASSERT_CHECK='TRUE'; - NO_DIR_CHECK='TRUE'; - ALLOW_CONNECT='TRUE'; - '\FB\': - PIN_NUMBER='(5)'; - INPUT_LOAD='(-0.01,0.01)'; - '\EN\': - PIN_NUMBER='(1)'; - INPUT_LOAD='(-0.01,0.01)'; - end_pin; - body - PART_NAME='TLV62569DBVR'; - VALUE='TLV62569DBV'; - BODY_NAME='TLV62569DBVR_DBV0005A_N_TLV62569DBV'; - JEDEC_TYPE='DBV0005A_N'; - PHYS_DES_PREFIX='U'; - CLASS='IC'; - end_body; -end_primitive; - primitive 'K922_K922_K922'; pin '\RSV9\': diff --git a/allegro/cmbcview.dat b/allegro/cmbcview.dat index 2db830e..fe6dfaa 100644 Binary files a/allegro/cmbcview.dat and b/allegro/cmbcview.dat differ diff --git a/allegro/cmdbview.dat b/allegro/cmdbview.dat index 6df964b..eb557f0 100644 Binary files a/allegro/cmdbview.dat and b/allegro/cmdbview.dat differ diff --git a/allegro/compview.dat b/allegro/compview.dat index 2b4cc1c..a155709 100644 --- a/allegro/compview.dat +++ b/allegro/compview.dat @@ -1,5 +1,12 @@ A!REFDES!COMP_REUSE_ID!COMP_SIGNAL_MODEL!COMP_NO_XNET_CONNECTION!COMP_PARENT_PPT!COMP_SYMBOL_EDITED!COMP_PARENT_PPT_PART!COMP_EMBEDDED_PLACEMENT!COMP_RKO_NUM_LAYERS!COMP_RKO_SHORT_SIDE_OVERSIZE!COMP_RKO_LONG_SIDE_OVERSIZE!COMP_RKO_REF_LAYER!COMP_ASI_MODEL! -J!w:/rk3506_nav/rk3506_nav.brd!Thu Aug 13 02:28:08 2026!-0.9400!-0.9400!6.6800!6.6800!0.0001!millimeters!RK3506_NAV!10.400000 mil!2!UP TO DATE! +J!D:/POLARIS/RK3506_NAV/rk3506_nav.brd!Thu Aug 13 15:48:14 2026!-100.0000!-100.0000!100.0000!100.0000!0.0001!millimeters!RK3506_NAV!28.800000 mil!4!UP TO DATE! +S!U11!!!!!!!!!!!!! +S!U12!!!!!!!!!!!!! +S!U13!!!!!!!!!!!!! +S!U14!!!!!!!!!!!!! +S!U15!!!!!!!!!!!!! +S!U16!!!!!!!!!!!!! +S!U10!!!!!!!!!!!!! S!C1!!!!!!!!!!!!! S!C2!!!!!!!!!!!!! S!C10!!!!!!!!!!!!! @@ -15,10 +22,5 @@ S!R1!!!!!!!!!!!!! S!U1!!!!!!!!!!!!! S!U2!!!!!!!!!!!!! S!U3!!!!!!!!!!!!! -S!U4!!!!!!!!!!!!! -S!U5!!!!!!!!!!!!! -S!U6!!!!!!!!!!!!! -S!U7!!!!!!!!!!!!! -S!U8!!!!!!!!!!!!! S!U9!!!!!!!!!!!!! S!X1!!!!!!!!!!!!! diff --git a/allegro/feedbackview.cdsz b/allegro/feedbackview.cdsz index d972b46..b4c3c52 100644 Binary files a/allegro/feedbackview.cdsz and b/allegro/feedbackview.cdsz differ diff --git a/allegro/funcView.dat b/allegro/funcView.dat index 2fed905..b226784 100644 --- a/allegro/funcView.dat +++ b/allegro/funcView.dat @@ -1,5 +1,13 @@ A!FUNC_LOGICAL_PATH!COMP_DEVICE_TYPE!REFDES!FUNC_PRIM_FILE!COMP_PARENT_PPT!COMP_PARENT_PPT_PART!COMP_PARENT_PART_TYPE!FUNC_SCH_SIZE!FUNC_HAS_FIXED_SIZE!FUNC_DES!FUNC_GROUP!FUNC_ROOM!FUNC_TERM_IDENT!FUNC_CDS_FSP_INSTANCE_ID!FUNC_CDS_FSP_IS_FPGA!FUNC_CDS_FSP_UID! -J!w:/rk3506_nav/rk3506_nav.brd!Thu Aug 13 02:28:08 2026!-0.9400!-0.9400!6.6800!6.6800!0.0001!millimeters!RK3506_NAV!10.400000 mil!2!UP TO DATE! +J!D:/POLARIS/RK3506_NAV/rk3506_nav.brd!Thu Aug 13 15:48:14 2026!-100.0000!-100.0000!100.0000!100.0000!0.0001!millimeters!RK3506_NAV!28.800000 mil!4!UP TO DATE! +S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS55441\@d.s(v)!TLV62569DBVR_SOT_23_5_TLV62569DBV!U11!.\chipsView.dat!!!!!!F8!!!!!!! +S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS55469\@d.s(v)!TLV62569DBVR_SOT_23_5_TLV62569DBV!U12!.\chipsView.dat!!!!!!F7!!!!!!! +S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS55497\@d.s(v)!TLV62569DBVR_SOT_23_5_TLV62569DBV!U13!.\chipsView.dat!!!!!!F6!!!!!!! +S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS55525\@d.s(v)!TLV62569DBVR_SOT_23_5_TLV62569DBV!U14!.\chipsView.dat!!!!!!F5!!!!!!! +S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS55553\@d.s(v)!TLV62569DBVR_SOT_23_5_TLV62569DBV!U15!.\chipsView.dat!!!!!!F4!!!!!!! +S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS57948\@\QF_IC\.\INAND_EMMC_153_2LA.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!U16!.\chipsView.dat!!!!!!TF-40!!!!!!! +S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS58273\@\QF_IC\.\INAND_EMMC_153_2LB.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!U16!.\chipsView.dat!!!!!!TF-39!!!!!!! +S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS55212\@\QF_IC\.\DDR3_16bit.Normal\(chips)!DDR3_16BIT_FBGA96_14R00X11R00X1R20_DDR3_16BIT!U10!.\chipsView.dat!!!!!!TF-38!!!!!!! S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS19387\@\DISCRETE\.\CAP NP.Normal\(chips)!CAP NP_C0402_DISCRETE_18PF!C1!.\chipsView.dat!!!!!!F23!!!!!!! S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS19709\@\DISCRETE\.\CAP NP.Normal\(chips)!CAP NP_C0402_DISCRETE_18PF!C2!.\chipsView.dat!!!!!!F22!!!!!!! S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS41270\@\QF_DISCRETE\.\CAP NP.Normal\(chips)!CAP NP_C0402_BGA_DISCRETE_10UF!C10!.\chipsView.dat!!!!!!F21!!!!!!! @@ -23,14 +31,9 @@ S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS15564\@\LIBRARY\.\SOC_RK3506BH.Normal\(c S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS14255\@\LIBRARY\.\SOC_RK3506BI.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!U1!.\chipsView.dat!!!!!!F10!!!!!!! S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS14712\@\LIBRARY\.\SOC_RK3506BJ.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!U1!.\chipsView.dat!!!!!!F9!!!!!!! S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS20987\@d.s(v)!LAN8720A-CP-ABC_QFN24-6X6_MC_MCH_LAN8720A-CP-ABC!U2!.\chipsView.dat!!!!!!TF-15!!!!!!! -S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS21054\@d.s(v)!LAN8720A-CP-ABC_QFN24-6X6_MC_MCH_LAN8720A-CP-ABC!U2!.\chipsView.dat!!!!!!F8!!!!!!! +S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS21054\@d.s(v)!LAN8720A-CP-ABC_QFN24-6X6_MC_MCH_LAN8720A-CP-ABC!U2!.\chipsView.dat!!!!!!F3!!!!!!! S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS21176\@d.s(v)!LAN8720A-CP-ABC_QFN24-6X6_MC_MCH_LAN8720A-CP-ABC!U3!.\chipsView.dat!!!!!!TF-13!!!!!!! -S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS21243\@d.s(v)!LAN8720A-CP-ABC_QFN24-6X6_MC_MCH_LAN8720A-CP-ABC!U3!.\chipsView.dat!!!!!!F7!!!!!!! -S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS22426\@d.s(v)!TLV62569DBVR_DBV0005A_N_TLV62569DBV!U4!.\chipsView.dat!!!!!!F6!!!!!!! -S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS22454\@d.s(v)!TLV62569DBVR_DBV0005A_N_TLV62569DBV!U5!.\chipsView.dat!!!!!!F5!!!!!!! -S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS22482\@d.s(v)!TLV62569DBVR_DBV0005A_N_TLV62569DBV!U6!.\chipsView.dat!!!!!!F4!!!!!!! -S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS22510\@d.s(v)!TLV62569DBVR_DBV0005A_N_TLV62569DBV!U7!.\chipsView.dat!!!!!!F3!!!!!!! -S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS22538\@d.s(v)!TLV62569DBVR_DBV0005A_N_TLV62569DBV!U8!.\chipsView.dat!!!!!!F2!!!!!!! +S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS21243\@d.s(v)!LAN8720A-CP-ABC_QFN24-6X6_MC_MCH_LAN8720A-CP-ABC!U3!.\chipsView.dat!!!!!!F2!!!!!!! S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS52680\@\QF_IC\.\K922A.Normal\(chips)!K922_K922_K922!U9!.\chipsView.dat!!!!!!F1!!!!!!! S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS52780\@\QF_IC\.\K922B.Normal\(chips)!K922_K922_K922!U9!.\chipsView.dat!!!!!!TF-5!!!!!!! S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS52850\@\QF_IC\.\K922C.Normal\(chips)!K922_K922_K922!U9!.\chipsView.dat!!!!!!TF-4!!!!!!! diff --git a/allegro/netview.dat b/allegro/netview.dat index 2afba59..9a8266d 100644 --- a/allegro/netview.dat +++ b/allegro/netview.dat @@ -1,7 +1,7 @@ A!NET_NAME!NET_LOGICAL_PATH!NET_VOLTAGE! -J!w:/rk3506_nav/rk3506_nav.brd!Thu Aug 13 02:28:08 2026!-0.9400!-0.9400!6.6800!6.6800!0.0001!millimeters!RK3506_NAV!10.400000 mil!2!UP TO DATE! -S!VIN!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\VIN\!1.5V! -S!SW!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\SW\!1.5V! +J!D:/POLARIS/RK3506_NAV/rk3506_nav.brd!Thu Aug 13 15:48:14 2026!-100.0000!-100.0000!100.0000!100.0000!0.0001!millimeters!RK3506_NAV!28.800000 mil!4!UP TO DATE! +S!VIN!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\VIN\!5V! +S!SW!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\SW\!3.3V! S!VDDCR!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\VDDCR\!1.5V! S!VDD2A!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\VDD2A\!1.5V! S!VDDIO!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\VDDIO\!3.3! diff --git a/allegro/pinview.dat b/allegro/pinview.dat index dd3c9fe..2852c53 100644 --- a/allegro/pinview.dat +++ b/allegro/pinview.dat @@ -1,5 +1,277 @@ A!NET_NAME!REFDES!PIN_NUMBER!FUNC_LOGICAL_PATH!COMP_DEVICE_TYPE!FUNC_SCH_SIZE!FUNC_HAS_FIXED_SIZE!FUNC_DES!PIN_CDS_PINID!PIN_TERMINATION!PIN_TERM_IDENT!PIN_NET_SHORT!PIN_XNET_PINS!PIN_RKO_NUM_LAYERS!PIN_RKO_SHORT_SIDE_OVERSIZE!PIN_RKO_LONG_SIDE_OVERSIZE! -J!w:/rk3506_nav/rk3506_nav.brd!Thu Aug 13 02:28:08 2026!-0.9400!-0.9400!6.6800!6.6800!0.0001!millimeters!RK3506_NAV!10.400000 mil!2!UP TO DATE! +J!D:/POLARIS/RK3506_NAV/rk3506_nav.brd!Thu Aug 13 15:48:14 2026!-100.0000!-100.0000!100.0000!100.0000!0.0001!millimeters!RK3506_NAV!28.800000 mil!4!UP TO DATE! +S!!U11!1!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS55441\@d.s(v)!TLV62569DBVR_SOT_23_5_TLV62569DBV!!!F8!\EN\!!!!!!!! +S!!U11!5!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS55441\@d.s(v)!TLV62569DBVR_SOT_23_5_TLV62569DBV!!!F8!\FB\!!!!!!!! +S!GND!U11!2!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS55441\@d.s(v)!TLV62569DBVR_SOT_23_5_TLV62569DBV!!!F8!\GND\!!!!!!!! +S!SW!U11!3!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS55441\@d.s(v)!TLV62569DBVR_SOT_23_5_TLV62569DBV!!!F8!\SW\!!!!!!!! +S!VIN!U11!4!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS55441\@d.s(v)!TLV62569DBVR_SOT_23_5_TLV62569DBV!!!F8!\VIN\!!!!!!!! +S!!U12!1!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS55469\@d.s(v)!TLV62569DBVR_SOT_23_5_TLV62569DBV!!!F7!\EN\!!!!!!!! +S!!U12!5!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS55469\@d.s(v)!TLV62569DBVR_SOT_23_5_TLV62569DBV!!!F7!\FB\!!!!!!!! +S!GND!U12!2!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS55469\@d.s(v)!TLV62569DBVR_SOT_23_5_TLV62569DBV!!!F7!\GND\!!!!!!!! +S!SW!U12!3!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS55469\@d.s(v)!TLV62569DBVR_SOT_23_5_TLV62569DBV!!!F7!\SW\!!!!!!!! +S!VIN!U12!4!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS55469\@d.s(v)!TLV62569DBVR_SOT_23_5_TLV62569DBV!!!F7!\VIN\!!!!!!!! +S!!U13!1!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS55497\@d.s(v)!TLV62569DBVR_SOT_23_5_TLV62569DBV!!!F6!\EN\!!!!!!!! +S!!U13!5!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS55497\@d.s(v)!TLV62569DBVR_SOT_23_5_TLV62569DBV!!!F6!\FB\!!!!!!!! +S!GND!U13!2!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS55497\@d.s(v)!TLV62569DBVR_SOT_23_5_TLV62569DBV!!!F6!\GND\!!!!!!!! +S!SW!U13!3!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS55497\@d.s(v)!TLV62569DBVR_SOT_23_5_TLV62569DBV!!!F6!\SW\!!!!!!!! +S!VIN!U13!4!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS55497\@d.s(v)!TLV62569DBVR_SOT_23_5_TLV62569DBV!!!F6!\VIN\!!!!!!!! +S!!U14!1!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS55525\@d.s(v)!TLV62569DBVR_SOT_23_5_TLV62569DBV!!!F5!\EN\!!!!!!!! +S!!U14!5!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS55525\@d.s(v)!TLV62569DBVR_SOT_23_5_TLV62569DBV!!!F5!\FB\!!!!!!!! +S!GND!U14!2!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS55525\@d.s(v)!TLV62569DBVR_SOT_23_5_TLV62569DBV!!!F5!\GND\!!!!!!!! +S!SW!U14!3!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS55525\@d.s(v)!TLV62569DBVR_SOT_23_5_TLV62569DBV!!!F5!\SW\!!!!!!!! +S!VIN!U14!4!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS55525\@d.s(v)!TLV62569DBVR_SOT_23_5_TLV62569DBV!!!F5!\VIN\!!!!!!!! +S!!U15!1!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS55553\@d.s(v)!TLV62569DBVR_SOT_23_5_TLV62569DBV!!!F4!\EN\!!!!!!!! +S!!U15!5!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS55553\@d.s(v)!TLV62569DBVR_SOT_23_5_TLV62569DBV!!!F4!\FB\!!!!!!!! +S!GND!U15!2!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS55553\@d.s(v)!TLV62569DBVR_SOT_23_5_TLV62569DBV!!!F4!\GND\!!!!!!!! +S!SW!U15!3!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS55553\@d.s(v)!TLV62569DBVR_SOT_23_5_TLV62569DBV!!!F4!\SW\!!!!!!!! +S!VIN!U15!4!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS55553\@d.s(v)!TLV62569DBVR_SOT_23_5_TLV62569DBV!!!F4!\VIN\!!!!!!!! +S!!U16!M6!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS57948\@\QF_IC\.\INAND_EMMC_153_2LA.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!!!TF-40!\CLK\!!!!!!!! +S!!U16!M5!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS57948\@\QF_IC\.\INAND_EMMC_153_2LA.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!!!TF-40!\CMD\!!!!!!!! +S!!U16!H5!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS57948\@\QF_IC\.\INAND_EMMC_153_2LA.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!!!TF-40!\DATA STROBE\!!!!!!!! +S!!U16!A3!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS57948\@\QF_IC\.\INAND_EMMC_153_2LA.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!!!TF-40!\DATA0\!!!!!!!! +S!!U16!A4!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS57948\@\QF_IC\.\INAND_EMMC_153_2LA.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!!!TF-40!\DATA1\!!!!!!!! +S!!U16!A5!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS57948\@\QF_IC\.\INAND_EMMC_153_2LA.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!!!TF-40!\DATA2\!!!!!!!! +S!!U16!B2!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS57948\@\QF_IC\.\INAND_EMMC_153_2LA.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!!!TF-40!\DATA3\!!!!!!!! +S!!U16!B3!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS57948\@\QF_IC\.\INAND_EMMC_153_2LA.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!!!TF-40!\DATA4\!!!!!!!! +S!!U16!B4!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS57948\@\QF_IC\.\INAND_EMMC_153_2LA.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!!!TF-40!\DATA5\!!!!!!!! +S!!U16!B5!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS57948\@\QF_IC\.\INAND_EMMC_153_2LA.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!!!TF-40!\DATA6\!!!!!!!! +S!!U16!B6!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS57948\@\QF_IC\.\INAND_EMMC_153_2LA.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!!!TF-40!\DATA7\!!!!!!!! +S!!U16!K5!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS57948\@\QF_IC\.\INAND_EMMC_153_2LA.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!!!TF-40!\RST_N\!!!!!!!! +S!!U16!E6!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS57948\@\QF_IC\.\INAND_EMMC_153_2LA.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!!!TF-40!\VCC1\!!!!!!!! +S!!U16!F5!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS57948\@\QF_IC\.\INAND_EMMC_153_2LA.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!!!TF-40!\VCC2\!!!!!!!! +S!!U16!J10!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS57948\@\QF_IC\.\INAND_EMMC_153_2LA.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!!!TF-40!\VCC3\!!!!!!!! +S!!U16!K9!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS57948\@\QF_IC\.\INAND_EMMC_153_2LA.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!!!TF-40!\VCC4\!!!!!!!! +S!!U16!C6!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS57948\@\QF_IC\.\INAND_EMMC_153_2LA.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!!!TF-40!\VCCQ1\!!!!!!!! +S!!U16!M4!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS57948\@\QF_IC\.\INAND_EMMC_153_2LA.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!!!TF-40!\VCCQ2\!!!!!!!! +S!!U16!N4!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS57948\@\QF_IC\.\INAND_EMMC_153_2LA.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!!!TF-40!\VCCQ3\!!!!!!!! +S!!U16!P3!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS57948\@\QF_IC\.\INAND_EMMC_153_2LA.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!!!TF-40!\VCCQ4\!!!!!!!! +S!!U16!P5!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS57948\@\QF_IC\.\INAND_EMMC_153_2LA.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!!!TF-40!\VCCQ5\!!!!!!!! +S!!U16!C2!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS57948\@\QF_IC\.\INAND_EMMC_153_2LA.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!!!TF-40!\VDDI\!!!!!!!! +S!!U16!E9!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS57948\@\QF_IC\.\INAND_EMMC_153_2LA.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!!!TF-40!\VSF1\!!!!!!!! +S!!U16!E10!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS57948\@\QF_IC\.\INAND_EMMC_153_2LA.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!!!TF-40!\VSF2\!!!!!!!! +S!!U16!F10!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS57948\@\QF_IC\.\INAND_EMMC_153_2LA.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!!!TF-40!\VSF3\!!!!!!!! +S!!U16!K10!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS57948\@\QF_IC\.\INAND_EMMC_153_2LA.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!!!TF-40!\VSF4\!!!!!!!! +S!!U16!J5!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS57948\@\QF_IC\.\INAND_EMMC_153_2LA.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!!!TF-40!\VSS1\!!!!!!!! +S!!U16!A6!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS57948\@\QF_IC\.\INAND_EMMC_153_2LA.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!!!TF-40!\VSS2\!!!!!!!! +S!!U16!C4!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS57948\@\QF_IC\.\INAND_EMMC_153_2LA.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!!!TF-40!\VSS3\!!!!!!!! +S!!U16!E7!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS57948\@\QF_IC\.\INAND_EMMC_153_2LA.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!!!TF-40!\VSS4\!!!!!!!! +S!!U16!G5!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS57948\@\QF_IC\.\INAND_EMMC_153_2LA.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!!!TF-40!\VSS5\!!!!!!!! +S!!U16!H10!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS57948\@\QF_IC\.\INAND_EMMC_153_2LA.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!!!TF-40!\VSS6\!!!!!!!! +S!!U16!K8!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS57948\@\QF_IC\.\INAND_EMMC_153_2LA.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!!!TF-40!\VSSQ1\!!!!!!!! +S!!U16!N2!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS57948\@\QF_IC\.\INAND_EMMC_153_2LA.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!!!TF-40!\VSSQ2\!!!!!!!! +S!!U16!N5!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS57948\@\QF_IC\.\INAND_EMMC_153_2LA.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!!!TF-40!\VSSQ3\!!!!!!!! +S!!U16!P4!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS57948\@\QF_IC\.\INAND_EMMC_153_2LA.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!!!TF-40!\VSSQ4\!!!!!!!! +S!!U16!P6!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS57948\@\QF_IC\.\INAND_EMMC_153_2LA.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!!!TF-40!\VSSQ5\!!!!!!!! +S!!U16!H2!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS58273\@\QF_IC\.\INAND_EMMC_153_2LB.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!!!TF-39!\NC100\!!!!!!!! +S!!U16!H3!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS58273\@\QF_IC\.\INAND_EMMC_153_2LB.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!!!TF-39!\NC101\!!!!!!!! +S!!U16!A10!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS58273\@\QF_IC\.\INAND_EMMC_153_2LB.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!!!TF-39!\NC10\!!!!!!!! +S!!U16!H12!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS58273\@\QF_IC\.\INAND_EMMC_153_2LB.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!!!TF-39!\NC110\!!!!!!!! +S!!U16!H13!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS58273\@\QF_IC\.\INAND_EMMC_153_2LB.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!!!TF-39!\NC111\!!!!!!!! +S!!U16!H14!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS58273\@\QF_IC\.\INAND_EMMC_153_2LB.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!!!TF-39!\NC112\!!!!!!!! +S!!U16!J1!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS58273\@\QF_IC\.\INAND_EMMC_153_2LB.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!!!TF-39!\NC113\!!!!!!!! +S!!U16!J2!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS58273\@\QF_IC\.\INAND_EMMC_153_2LB.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!!!TF-39!\NC114\!!!!!!!! +S!!U16!J3!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS58273\@\QF_IC\.\INAND_EMMC_153_2LB.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!!!TF-39!\NC115\!!!!!!!! +S!!U16!A11!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS58273\@\QF_IC\.\INAND_EMMC_153_2LB.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!!!TF-39!\NC11\!!!!!!!! +S!!U16!J12!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS58273\@\QF_IC\.\INAND_EMMC_153_2LB.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!!!TF-39!\NC124\!!!!!!!! +S!!U16!J13!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS58273\@\QF_IC\.\INAND_EMMC_153_2LB.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!!!TF-39!\NC125\!!!!!!!! +S!!U16!J14!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS58273\@\QF_IC\.\INAND_EMMC_153_2LB.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!!!TF-39!\NC126\!!!!!!!! +S!!U16!K1!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS58273\@\QF_IC\.\INAND_EMMC_153_2LB.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!!!TF-39!\NC127\!!!!!!!! +S!!U16!K2!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS58273\@\QF_IC\.\INAND_EMMC_153_2LB.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!!!TF-39!\NC128\!!!!!!!! +S!!U16!K3!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS58273\@\QF_IC\.\INAND_EMMC_153_2LB.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!!!TF-39!\NC129\!!!!!!!! +S!!U16!A12!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS58273\@\QF_IC\.\INAND_EMMC_153_2LB.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!!!TF-39!\NC12\!!!!!!!! +S!!U16!K12!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS58273\@\QF_IC\.\INAND_EMMC_153_2LB.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!!!TF-39!\NC138\!!!!!!!! +S!!U16!K13!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS58273\@\QF_IC\.\INAND_EMMC_153_2LB.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!!!TF-39!\NC139\!!!!!!!! +S!!U16!A13!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS58273\@\QF_IC\.\INAND_EMMC_153_2LB.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!!!TF-39!\NC13\!!!!!!!! +S!!U16!K14!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS58273\@\QF_IC\.\INAND_EMMC_153_2LB.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!!!TF-39!\NC140\!!!!!!!! +S!!U16!L1!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS58273\@\QF_IC\.\INAND_EMMC_153_2LB.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!!!TF-39!\NC141\!!!!!!!! +S!!U16!L2!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS58273\@\QF_IC\.\INAND_EMMC_153_2LB.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!!!TF-39!\NC142\!!!!!!!! +S!!U16!L3!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS58273\@\QF_IC\.\INAND_EMMC_153_2LB.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!!!TF-39!\NC143\!!!!!!!! +S!!U16!A14!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS58273\@\QF_IC\.\INAND_EMMC_153_2LB.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!!!TF-39!\NC14\!!!!!!!! +S!!U16!L12!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS58273\@\QF_IC\.\INAND_EMMC_153_2LB.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!!!TF-39!\NC152\!!!!!!!! +S!!U16!L13!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS58273\@\QF_IC\.\INAND_EMMC_153_2LB.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!!!TF-39!\NC153\!!!!!!!! +S!!U16!L14!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS58273\@\QF_IC\.\INAND_EMMC_153_2LB.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!!!TF-39!\NC154\!!!!!!!! +S!!U16!M1!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS58273\@\QF_IC\.\INAND_EMMC_153_2LB.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!!!TF-39!\NC155\!!!!!!!! +S!!U16!M2!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS58273\@\QF_IC\.\INAND_EMMC_153_2LB.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!!!TF-39!\NC156\!!!!!!!! +S!!U16!M3!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS58273\@\QF_IC\.\INAND_EMMC_153_2LB.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!!!TF-39!\NC157\!!!!!!!! +S!!U16!B1!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS58273\@\QF_IC\.\INAND_EMMC_153_2LB.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!!!TF-39!\NC15\!!!!!!!! +S!!U16!M7!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS58273\@\QF_IC\.\INAND_EMMC_153_2LB.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!!!TF-39!\NC161\!!!!!!!! +S!!U16!M8!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS58273\@\QF_IC\.\INAND_EMMC_153_2LB.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!!!TF-39!\NC162\!!!!!!!! +S!!U16!M9!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS58273\@\QF_IC\.\INAND_EMMC_153_2LB.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!!!TF-39!\NC163\!!!!!!!! +S!!U16!M10!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS58273\@\QF_IC\.\INAND_EMMC_153_2LB.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!!!TF-39!\NC164\!!!!!!!! +S!!U16!M11!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS58273\@\QF_IC\.\INAND_EMMC_153_2LB.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!!!TF-39!\NC165\!!!!!!!! +S!!U16!M12!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS58273\@\QF_IC\.\INAND_EMMC_153_2LB.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!!!TF-39!\NC166\!!!!!!!! +S!!U16!M13!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS58273\@\QF_IC\.\INAND_EMMC_153_2LB.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!!!TF-39!\NC167\!!!!!!!! +S!!U16!M14!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS58273\@\QF_IC\.\INAND_EMMC_153_2LB.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!!!TF-39!\NC168\!!!!!!!! +S!!U16!N1!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS58273\@\QF_IC\.\INAND_EMMC_153_2LB.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!!!TF-39!\NC169\!!!!!!!! +S!!U16!N3!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS58273\@\QF_IC\.\INAND_EMMC_153_2LB.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!!!TF-39!\NC171\!!!!!!!! +S!!U16!N6!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS58273\@\QF_IC\.\INAND_EMMC_153_2LB.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!!!TF-39!\NC174\!!!!!!!! +S!!U16!N7!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS58273\@\QF_IC\.\INAND_EMMC_153_2LB.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!!!TF-39!\NC175\!!!!!!!! +S!!U16!N8!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS58273\@\QF_IC\.\INAND_EMMC_153_2LB.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!!!TF-39!\NC176\!!!!!!!! +S!!U16!N9!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS58273\@\QF_IC\.\INAND_EMMC_153_2LB.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!!!TF-39!\NC177\!!!!!!!! +S!!U16!N10!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS58273\@\QF_IC\.\INAND_EMMC_153_2LB.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!!!TF-39!\NC178\!!!!!!!! +S!!U16!N11!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS58273\@\QF_IC\.\INAND_EMMC_153_2LB.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!!!TF-39!\NC179\!!!!!!!! +S!!U16!N12!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS58273\@\QF_IC\.\INAND_EMMC_153_2LB.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!!!TF-39!\NC180\!!!!!!!! +S!!U16!N13!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS58273\@\QF_IC\.\INAND_EMMC_153_2LB.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!!!TF-39!\NC181\!!!!!!!! +S!!U16!N14!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS58273\@\QF_IC\.\INAND_EMMC_153_2LB.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!!!TF-39!\NC182\!!!!!!!! +S!!U16!P1!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS58273\@\QF_IC\.\INAND_EMMC_153_2LB.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!!!TF-39!\NC183\!!!!!!!! +S!!U16!P2!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS58273\@\QF_IC\.\INAND_EMMC_153_2LB.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!!!TF-39!\NC184\!!!!!!!! +S!!U16!P8!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS58273\@\QF_IC\.\INAND_EMMC_153_2LB.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!!!TF-39!\NC190\!!!!!!!! +S!!U16!P9!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS58273\@\QF_IC\.\INAND_EMMC_153_2LB.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!!!TF-39!\NC191\!!!!!!!! +S!!U16!P11!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS58273\@\QF_IC\.\INAND_EMMC_153_2LB.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!!!TF-39!\NC193\!!!!!!!! +S!!U16!P12!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS58273\@\QF_IC\.\INAND_EMMC_153_2LB.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!!!TF-39!\NC194\!!!!!!!! +S!!U16!P13!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS58273\@\QF_IC\.\INAND_EMMC_153_2LB.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!!!TF-39!\NC195\!!!!!!!! +S!!U16!P14!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS58273\@\QF_IC\.\INAND_EMMC_153_2LB.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!!!TF-39!\NC196\!!!!!!!! +S!!U16!B7!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS58273\@\QF_IC\.\INAND_EMMC_153_2LB.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!!!TF-39!\NC21\!!!!!!!! +S!!U16!B8!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS58273\@\QF_IC\.\INAND_EMMC_153_2LB.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!!!TF-39!\NC22\!!!!!!!! +S!!U16!B9!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS58273\@\QF_IC\.\INAND_EMMC_153_2LB.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!!!TF-39!\NC23\!!!!!!!! +S!!U16!B10!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS58273\@\QF_IC\.\INAND_EMMC_153_2LB.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!!!TF-39!\NC24\!!!!!!!! +S!!U16!B11!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS58273\@\QF_IC\.\INAND_EMMC_153_2LB.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!!!TF-39!\NC25\!!!!!!!! +S!!U16!B12!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS58273\@\QF_IC\.\INAND_EMMC_153_2LB.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!!!TF-39!\NC26\!!!!!!!! +S!!U16!B13!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS58273\@\QF_IC\.\INAND_EMMC_153_2LB.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!!!TF-39!\NC27\!!!!!!!! +S!!U16!B14!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS58273\@\QF_IC\.\INAND_EMMC_153_2LB.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!!!TF-39!\NC28\!!!!!!!! +S!!U16!C1!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS58273\@\QF_IC\.\INAND_EMMC_153_2LB.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!!!TF-39!\NC29\!!!!!!!! +S!!U16!A2!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS58273\@\QF_IC\.\INAND_EMMC_153_2LB.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!!!TF-39!\NC2\!!!!!!!! +S!!U16!C3!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS58273\@\QF_IC\.\INAND_EMMC_153_2LB.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!!!TF-39!\NC31\!!!!!!!! +S!!U16!C7!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS58273\@\QF_IC\.\INAND_EMMC_153_2LB.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!!!TF-39!\NC35\!!!!!!!! +S!!U16!C8!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS58273\@\QF_IC\.\INAND_EMMC_153_2LB.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!!!TF-39!\NC36\!!!!!!!! +S!!U16!C9!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS58273\@\QF_IC\.\INAND_EMMC_153_2LB.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!!!TF-39!\NC37\!!!!!!!! +S!!U16!C10!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS58273\@\QF_IC\.\INAND_EMMC_153_2LB.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!!!TF-39!\NC38\!!!!!!!! +S!!U16!C11!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS58273\@\QF_IC\.\INAND_EMMC_153_2LB.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!!!TF-39!\NC39\!!!!!!!! +S!!U16!C12!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS58273\@\QF_IC\.\INAND_EMMC_153_2LB.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!!!TF-39!\NC40\!!!!!!!! +S!!U16!C13!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS58273\@\QF_IC\.\INAND_EMMC_153_2LB.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!!!TF-39!\NC41\!!!!!!!! +S!!U16!C14!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS58273\@\QF_IC\.\INAND_EMMC_153_2LB.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!!!TF-39!\NC42\!!!!!!!! +S!!U16!D1!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS58273\@\QF_IC\.\INAND_EMMC_153_2LB.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!!!TF-39!\NC43\!!!!!!!! +S!!U16!D2!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS58273\@\QF_IC\.\INAND_EMMC_153_2LB.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!!!TF-39!\NC44\!!!!!!!! +S!!U16!D3!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS58273\@\QF_IC\.\INAND_EMMC_153_2LB.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!!!TF-39!\NC45\!!!!!!!! +S!!U16!D4!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS58273\@\QF_IC\.\INAND_EMMC_153_2LB.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!!!TF-39!\NC46\!!!!!!!! +S!!U16!D12!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS58273\@\QF_IC\.\INAND_EMMC_153_2LB.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!!!TF-39!\NC54\!!!!!!!! +S!!U16!D13!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS58273\@\QF_IC\.\INAND_EMMC_153_2LB.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!!!TF-39!\NC55\!!!!!!!! +S!!U16!D14!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS58273\@\QF_IC\.\INAND_EMMC_153_2LB.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!!!TF-39!\NC56\!!!!!!!! +S!!U16!E1!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS58273\@\QF_IC\.\INAND_EMMC_153_2LB.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!!!TF-39!\NC57\!!!!!!!! +S!!U16!E2!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS58273\@\QF_IC\.\INAND_EMMC_153_2LB.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!!!TF-39!\NC58\!!!!!!!! +S!!U16!E3!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS58273\@\QF_IC\.\INAND_EMMC_153_2LB.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!!!TF-39!\NC59\!!!!!!!! +S!!U16!E12!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS58273\@\QF_IC\.\INAND_EMMC_153_2LB.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!!!TF-39!\NC68\!!!!!!!! +S!!U16!E13!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS58273\@\QF_IC\.\INAND_EMMC_153_2LB.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!!!TF-39!\NC69\!!!!!!!! +S!!U16!E14!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS58273\@\QF_IC\.\INAND_EMMC_153_2LB.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!!!TF-39!\NC70\!!!!!!!! +S!!U16!F1!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS58273\@\QF_IC\.\INAND_EMMC_153_2LB.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!!!TF-39!\NC71\!!!!!!!! +S!!U16!F2!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS58273\@\QF_IC\.\INAND_EMMC_153_2LB.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!!!TF-39!\NC72\!!!!!!!! +S!!U16!F3!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS58273\@\QF_IC\.\INAND_EMMC_153_2LB.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!!!TF-39!\NC73\!!!!!!!! +S!!U16!F12!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS58273\@\QF_IC\.\INAND_EMMC_153_2LB.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!!!TF-39!\NC82\!!!!!!!! +S!!U16!F13!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS58273\@\QF_IC\.\INAND_EMMC_153_2LB.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!!!TF-39!\NC83\!!!!!!!! +S!!U16!F14!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS58273\@\QF_IC\.\INAND_EMMC_153_2LB.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!!!TF-39!\NC84\!!!!!!!! +S!!U16!G1!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS58273\@\QF_IC\.\INAND_EMMC_153_2LB.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!!!TF-39!\NC85\!!!!!!!! +S!!U16!G2!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS58273\@\QF_IC\.\INAND_EMMC_153_2LB.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!!!TF-39!\NC86\!!!!!!!! +S!!U16!A8!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS58273\@\QF_IC\.\INAND_EMMC_153_2LB.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!!!TF-39!\NC8\!!!!!!!! +S!!U16!G12!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS58273\@\QF_IC\.\INAND_EMMC_153_2LB.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!!!TF-39!\NC96\!!!!!!!! +S!!U16!G13!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS58273\@\QF_IC\.\INAND_EMMC_153_2LB.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!!!TF-39!\NC97\!!!!!!!! +S!!U16!G14!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS58273\@\QF_IC\.\INAND_EMMC_153_2LB.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!!!TF-39!\NC98\!!!!!!!! +S!!U16!H1!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS58273\@\QF_IC\.\INAND_EMMC_153_2LB.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!!!TF-39!\NC99\!!!!!!!! +S!!U16!A9!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS58273\@\QF_IC\.\INAND_EMMC_153_2LB.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!!!TF-39!\NC9\!!!!!!!! +S!!U16!A7!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS58273\@\QF_IC\.\INAND_EMMC_153_2LB.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!!!TF-39!\RFU1\!!!!!!!! +S!!U16!E5!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS58273\@\QF_IC\.\INAND_EMMC_153_2LB.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!!!TF-39!\RFU2\!!!!!!!! +S!!U16!E8!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS58273\@\QF_IC\.\INAND_EMMC_153_2LB.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!!!TF-39!\RFU3\!!!!!!!! +S!!U16!G3!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS58273\@\QF_IC\.\INAND_EMMC_153_2LB.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!!!TF-39!\RFU4\!!!!!!!! +S!!U16!G10!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS58273\@\QF_IC\.\INAND_EMMC_153_2LB.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!!!TF-39!\RFU5\!!!!!!!! +S!!U16!K6!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS58273\@\QF_IC\.\INAND_EMMC_153_2LB.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!!!TF-39!\RFU6\!!!!!!!! +S!!U16!K7!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS58273\@\QF_IC\.\INAND_EMMC_153_2LB.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!!!TF-39!\RFU7\!!!!!!!! +S!!U16!P7!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS58273\@\QF_IC\.\INAND_EMMC_153_2LB.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!!!TF-39!\RFU8\!!!!!!!! +S!!U16!P10!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS58273\@\QF_IC\.\INAND_EMMC_153_2LB.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!!!TF-39!\RFU9\!!!!!!!! +S!!U10!N3!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS55212\@\QF_IC\.\DDR3_16bit.Normal\(chips)!DDR3_16BIT_FBGA96_14R00X11R00X1R20_DDR3_16BIT!!!TF-38!\A0\!!!!!!!! +S!!U10!L7!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS55212\@\QF_IC\.\DDR3_16bit.Normal\(chips)!DDR3_16BIT_FBGA96_14R00X11R00X1R20_DDR3_16BIT!!!TF-38!\A10/AP\!!!!!!!! +S!!U10!R7!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS55212\@\QF_IC\.\DDR3_16bit.Normal\(chips)!DDR3_16BIT_FBGA96_14R00X11R00X1R20_DDR3_16BIT!!!TF-38!\A11\!!!!!!!! +S!!U10!N7!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS55212\@\QF_IC\.\DDR3_16bit.Normal\(chips)!DDR3_16BIT_FBGA96_14R00X11R00X1R20_DDR3_16BIT!!!TF-38!\A12/BC#\!!!!!!!! +S!!U10!T3!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS55212\@\QF_IC\.\DDR3_16bit.Normal\(chips)!DDR3_16BIT_FBGA96_14R00X11R00X1R20_DDR3_16BIT!!!TF-38!\A13\!!!!!!!! +S!!U10!T7!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS55212\@\QF_IC\.\DDR3_16bit.Normal\(chips)!DDR3_16BIT_FBGA96_14R00X11R00X1R20_DDR3_16BIT!!!TF-38!\A14\!!!!!!!! +S!!U10!M7!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS55212\@\QF_IC\.\DDR3_16bit.Normal\(chips)!DDR3_16BIT_FBGA96_14R00X11R00X1R20_DDR3_16BIT!!!TF-38!\A15\!!!!!!!! +S!!U10!P7!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS55212\@\QF_IC\.\DDR3_16bit.Normal\(chips)!DDR3_16BIT_FBGA96_14R00X11R00X1R20_DDR3_16BIT!!!TF-38!\A1\!!!!!!!! +S!!U10!P3!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS55212\@\QF_IC\.\DDR3_16bit.Normal\(chips)!DDR3_16BIT_FBGA96_14R00X11R00X1R20_DDR3_16BIT!!!TF-38!\A2\!!!!!!!! +S!!U10!N2!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS55212\@\QF_IC\.\DDR3_16bit.Normal\(chips)!DDR3_16BIT_FBGA96_14R00X11R00X1R20_DDR3_16BIT!!!TF-38!\A3\!!!!!!!! +S!!U10!P8!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS55212\@\QF_IC\.\DDR3_16bit.Normal\(chips)!DDR3_16BIT_FBGA96_14R00X11R00X1R20_DDR3_16BIT!!!TF-38!\A4\!!!!!!!! +S!!U10!P2!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS55212\@\QF_IC\.\DDR3_16bit.Normal\(chips)!DDR3_16BIT_FBGA96_14R00X11R00X1R20_DDR3_16BIT!!!TF-38!\A5\!!!!!!!! +S!!U10!R8!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS55212\@\QF_IC\.\DDR3_16bit.Normal\(chips)!DDR3_16BIT_FBGA96_14R00X11R00X1R20_DDR3_16BIT!!!TF-38!\A6\!!!!!!!! +S!!U10!R2!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS55212\@\QF_IC\.\DDR3_16bit.Normal\(chips)!DDR3_16BIT_FBGA96_14R00X11R00X1R20_DDR3_16BIT!!!TF-38!\A7\!!!!!!!! +S!!U10!T8!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS55212\@\QF_IC\.\DDR3_16bit.Normal\(chips)!DDR3_16BIT_FBGA96_14R00X11R00X1R20_DDR3_16BIT!!!TF-38!\A8\!!!!!!!! +S!!U10!R3!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS55212\@\QF_IC\.\DDR3_16bit.Normal\(chips)!DDR3_16BIT_FBGA96_14R00X11R00X1R20_DDR3_16BIT!!!TF-38!\A9\!!!!!!!! +S!!U10!M2!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS55212\@\QF_IC\.\DDR3_16bit.Normal\(chips)!DDR3_16BIT_FBGA96_14R00X11R00X1R20_DDR3_16BIT!!!TF-38!\BA0\!!!!!!!! +S!!U10!N8!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS55212\@\QF_IC\.\DDR3_16bit.Normal\(chips)!DDR3_16BIT_FBGA96_14R00X11R00X1R20_DDR3_16BIT!!!TF-38!\BA1\!!!!!!!! +S!!U10!M3!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS55212\@\QF_IC\.\DDR3_16bit.Normal\(chips)!DDR3_16BIT_FBGA96_14R00X11R00X1R20_DDR3_16BIT!!!TF-38!\BA2\!!!!!!!! +S!!U10!K3!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS55212\@\QF_IC\.\DDR3_16bit.Normal\(chips)!DDR3_16BIT_FBGA96_14R00X11R00X1R20_DDR3_16BIT!!!TF-38!\CAS#\!!!!!!!! +S!!U10!K7!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS55212\@\QF_IC\.\DDR3_16bit.Normal\(chips)!DDR3_16BIT_FBGA96_14R00X11R00X1R20_DDR3_16BIT!!!TF-38!\CK#\!!!!!!!! +S!!U10!K9!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS55212\@\QF_IC\.\DDR3_16bit.Normal\(chips)!DDR3_16BIT_FBGA96_14R00X11R00X1R20_DDR3_16BIT!!!TF-38!\CKE0\!!!!!!!! +S!!U10!J9!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS55212\@\QF_IC\.\DDR3_16bit.Normal\(chips)!DDR3_16BIT_FBGA96_14R00X11R00X1R20_DDR3_16BIT!!!TF-38!\CKE1\!!!!!!!! +S!!U10!J7!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS55212\@\QF_IC\.\DDR3_16bit.Normal\(chips)!DDR3_16BIT_FBGA96_14R00X11R00X1R20_DDR3_16BIT!!!TF-38!\CK\!!!!!!!! +S!!U10!L2!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS55212\@\QF_IC\.\DDR3_16bit.Normal\(chips)!DDR3_16BIT_FBGA96_14R00X11R00X1R20_DDR3_16BIT!!!TF-38!\CS#0\!!!!!!!! +S!!U10!L1!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS55212\@\QF_IC\.\DDR3_16bit.Normal\(chips)!DDR3_16BIT_FBGA96_14R00X11R00X1R20_DDR3_16BIT!!!TF-38!\CS#1\!!!!!!!! +S!!U10!E3!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS55212\@\QF_IC\.\DDR3_16bit.Normal\(chips)!DDR3_16BIT_FBGA96_14R00X11R00X1R20_DDR3_16BIT!!!TF-38!\DQ0\!!!!!!!! +S!!U10!C8!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS55212\@\QF_IC\.\DDR3_16bit.Normal\(chips)!DDR3_16BIT_FBGA96_14R00X11R00X1R20_DDR3_16BIT!!!TF-38!\DQ10\!!!!!!!! +S!!U10!C2!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS55212\@\QF_IC\.\DDR3_16bit.Normal\(chips)!DDR3_16BIT_FBGA96_14R00X11R00X1R20_DDR3_16BIT!!!TF-38!\DQ11\!!!!!!!! +S!!U10!A7!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS55212\@\QF_IC\.\DDR3_16bit.Normal\(chips)!DDR3_16BIT_FBGA96_14R00X11R00X1R20_DDR3_16BIT!!!TF-38!\DQ12\!!!!!!!! +S!!U10!A2!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS55212\@\QF_IC\.\DDR3_16bit.Normal\(chips)!DDR3_16BIT_FBGA96_14R00X11R00X1R20_DDR3_16BIT!!!TF-38!\DQ13\!!!!!!!! +S!!U10!B8!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS55212\@\QF_IC\.\DDR3_16bit.Normal\(chips)!DDR3_16BIT_FBGA96_14R00X11R00X1R20_DDR3_16BIT!!!TF-38!\DQ14\!!!!!!!! +S!!U10!A3!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS55212\@\QF_IC\.\DDR3_16bit.Normal\(chips)!DDR3_16BIT_FBGA96_14R00X11R00X1R20_DDR3_16BIT!!!TF-38!\DQ15\!!!!!!!! +S!!U10!F7!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS55212\@\QF_IC\.\DDR3_16bit.Normal\(chips)!DDR3_16BIT_FBGA96_14R00X11R00X1R20_DDR3_16BIT!!!TF-38!\DQ1\!!!!!!!! +S!!U10!F2!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS55212\@\QF_IC\.\DDR3_16bit.Normal\(chips)!DDR3_16BIT_FBGA96_14R00X11R00X1R20_DDR3_16BIT!!!TF-38!\DQ2\!!!!!!!! +S!!U10!F8!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS55212\@\QF_IC\.\DDR3_16bit.Normal\(chips)!DDR3_16BIT_FBGA96_14R00X11R00X1R20_DDR3_16BIT!!!TF-38!\DQ3\!!!!!!!! +S!!U10!H3!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS55212\@\QF_IC\.\DDR3_16bit.Normal\(chips)!DDR3_16BIT_FBGA96_14R00X11R00X1R20_DDR3_16BIT!!!TF-38!\DQ4\!!!!!!!! +S!!U10!H8!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS55212\@\QF_IC\.\DDR3_16bit.Normal\(chips)!DDR3_16BIT_FBGA96_14R00X11R00X1R20_DDR3_16BIT!!!TF-38!\DQ5\!!!!!!!! +S!!U10!G2!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS55212\@\QF_IC\.\DDR3_16bit.Normal\(chips)!DDR3_16BIT_FBGA96_14R00X11R00X1R20_DDR3_16BIT!!!TF-38!\DQ6\!!!!!!!! +S!!U10!H7!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS55212\@\QF_IC\.\DDR3_16bit.Normal\(chips)!DDR3_16BIT_FBGA96_14R00X11R00X1R20_DDR3_16BIT!!!TF-38!\DQ7\!!!!!!!! +S!!U10!D7!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS55212\@\QF_IC\.\DDR3_16bit.Normal\(chips)!DDR3_16BIT_FBGA96_14R00X11R00X1R20_DDR3_16BIT!!!TF-38!\DQ8\!!!!!!!! +S!!U10!C3!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS55212\@\QF_IC\.\DDR3_16bit.Normal\(chips)!DDR3_16BIT_FBGA96_14R00X11R00X1R20_DDR3_16BIT!!!TF-38!\DQ9\!!!!!!!! +S!!U10!E7!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS55212\@\QF_IC\.\DDR3_16bit.Normal\(chips)!DDR3_16BIT_FBGA96_14R00X11R00X1R20_DDR3_16BIT!!!TF-38!\LDM\!!!!!!!! +S!!U10!G3!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS55212\@\QF_IC\.\DDR3_16bit.Normal\(chips)!DDR3_16BIT_FBGA96_14R00X11R00X1R20_DDR3_16BIT!!!TF-38!\LDQS#\!!!!!!!! +S!!U10!F3!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS55212\@\QF_IC\.\DDR3_16bit.Normal\(chips)!DDR3_16BIT_FBGA96_14R00X11R00X1R20_DDR3_16BIT!!!TF-38!\LDQS\!!!!!!!! +S!!U10!K1!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS55212\@\QF_IC\.\DDR3_16bit.Normal\(chips)!DDR3_16BIT_FBGA96_14R00X11R00X1R20_DDR3_16BIT!!!TF-38!\ODT0\!!!!!!!! +S!!U10!J1!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS55212\@\QF_IC\.\DDR3_16bit.Normal\(chips)!DDR3_16BIT_FBGA96_14R00X11R00X1R20_DDR3_16BIT!!!TF-38!\ODT1\!!!!!!!! +S!!U10!J3!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS55212\@\QF_IC\.\DDR3_16bit.Normal\(chips)!DDR3_16BIT_FBGA96_14R00X11R00X1R20_DDR3_16BIT!!!TF-38!\RAS#\!!!!!!!! +S!!U10!T2!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS55212\@\QF_IC\.\DDR3_16bit.Normal\(chips)!DDR3_16BIT_FBGA96_14R00X11R00X1R20_DDR3_16BIT!!!TF-38!\RESET#\!!!!!!!! +S!!U10!D3!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS55212\@\QF_IC\.\DDR3_16bit.Normal\(chips)!DDR3_16BIT_FBGA96_14R00X11R00X1R20_DDR3_16BIT!!!TF-38!\UDM\!!!!!!!! +S!!U10!B7!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS55212\@\QF_IC\.\DDR3_16bit.Normal\(chips)!DDR3_16BIT_FBGA96_14R00X11R00X1R20_DDR3_16BIT!!!TF-38!\UDQS#\!!!!!!!! +S!!U10!C7!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS55212\@\QF_IC\.\DDR3_16bit.Normal\(chips)!DDR3_16BIT_FBGA96_14R00X11R00X1R20_DDR3_16BIT!!!TF-38!\UDQS\!!!!!!!! +S!!U10!B2!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS55212\@\QF_IC\.\DDR3_16bit.Normal\(chips)!DDR3_16BIT_FBGA96_14R00X11R00X1R20_DDR3_16BIT!!!TF-38!\VDD1\!!!!!!!! +S!!U10!D9!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS55212\@\QF_IC\.\DDR3_16bit.Normal\(chips)!DDR3_16BIT_FBGA96_14R00X11R00X1R20_DDR3_16BIT!!!TF-38!\VDD2\!!!!!!!! +S!!U10!G7!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS55212\@\QF_IC\.\DDR3_16bit.Normal\(chips)!DDR3_16BIT_FBGA96_14R00X11R00X1R20_DDR3_16BIT!!!TF-38!\VDD3\!!!!!!!! +S!!U10!K2!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS55212\@\QF_IC\.\DDR3_16bit.Normal\(chips)!DDR3_16BIT_FBGA96_14R00X11R00X1R20_DDR3_16BIT!!!TF-38!\VDD4\!!!!!!!! +S!!U10!K8!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS55212\@\QF_IC\.\DDR3_16bit.Normal\(chips)!DDR3_16BIT_FBGA96_14R00X11R00X1R20_DDR3_16BIT!!!TF-38!\VDD5\!!!!!!!! +S!!U10!N1!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS55212\@\QF_IC\.\DDR3_16bit.Normal\(chips)!DDR3_16BIT_FBGA96_14R00X11R00X1R20_DDR3_16BIT!!!TF-38!\VDD6\!!!!!!!! +S!!U10!N9!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS55212\@\QF_IC\.\DDR3_16bit.Normal\(chips)!DDR3_16BIT_FBGA96_14R00X11R00X1R20_DDR3_16BIT!!!TF-38!\VDD7\!!!!!!!! +S!!U10!R1!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS55212\@\QF_IC\.\DDR3_16bit.Normal\(chips)!DDR3_16BIT_FBGA96_14R00X11R00X1R20_DDR3_16BIT!!!TF-38!\VDD8\!!!!!!!! +S!!U10!R9!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS55212\@\QF_IC\.\DDR3_16bit.Normal\(chips)!DDR3_16BIT_FBGA96_14R00X11R00X1R20_DDR3_16BIT!!!TF-38!\VDD9\!!!!!!!! +S!!U10!A1!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS55212\@\QF_IC\.\DDR3_16bit.Normal\(chips)!DDR3_16BIT_FBGA96_14R00X11R00X1R20_DDR3_16BIT!!!TF-38!\VDDQ1\!!!!!!!! +S!!U10!A8!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS55212\@\QF_IC\.\DDR3_16bit.Normal\(chips)!DDR3_16BIT_FBGA96_14R00X11R00X1R20_DDR3_16BIT!!!TF-38!\VDDQ2\!!!!!!!! +S!!U10!C1!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS55212\@\QF_IC\.\DDR3_16bit.Normal\(chips)!DDR3_16BIT_FBGA96_14R00X11R00X1R20_DDR3_16BIT!!!TF-38!\VDDQ3\!!!!!!!! +S!!U10!C9!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS55212\@\QF_IC\.\DDR3_16bit.Normal\(chips)!DDR3_16BIT_FBGA96_14R00X11R00X1R20_DDR3_16BIT!!!TF-38!\VDDQ4\!!!!!!!! +S!!U10!D2!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS55212\@\QF_IC\.\DDR3_16bit.Normal\(chips)!DDR3_16BIT_FBGA96_14R00X11R00X1R20_DDR3_16BIT!!!TF-38!\VDDQ5\!!!!!!!! +S!!U10!E9!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS55212\@\QF_IC\.\DDR3_16bit.Normal\(chips)!DDR3_16BIT_FBGA96_14R00X11R00X1R20_DDR3_16BIT!!!TF-38!\VDDQ6\!!!!!!!! +S!!U10!F1!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS55212\@\QF_IC\.\DDR3_16bit.Normal\(chips)!DDR3_16BIT_FBGA96_14R00X11R00X1R20_DDR3_16BIT!!!TF-38!\VDDQ7\!!!!!!!! +S!!U10!H2!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS55212\@\QF_IC\.\DDR3_16bit.Normal\(chips)!DDR3_16BIT_FBGA96_14R00X11R00X1R20_DDR3_16BIT!!!TF-38!\VDDQ8\!!!!!!!! +S!!U10!H9!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS55212\@\QF_IC\.\DDR3_16bit.Normal\(chips)!DDR3_16BIT_FBGA96_14R00X11R00X1R20_DDR3_16BIT!!!TF-38!\VDDQ9\!!!!!!!! +S!!U10!M8!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS55212\@\QF_IC\.\DDR3_16bit.Normal\(chips)!DDR3_16BIT_FBGA96_14R00X11R00X1R20_DDR3_16BIT!!!TF-38!\VREFCA\!!!!!!!! +S!!U10!H1!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS55212\@\QF_IC\.\DDR3_16bit.Normal\(chips)!DDR3_16BIT_FBGA96_14R00X11R00X1R20_DDR3_16BIT!!!TF-38!\VREFDQ\!!!!!!!! +S!!U10!P9!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS55212\@\QF_IC\.\DDR3_16bit.Normal\(chips)!DDR3_16BIT_FBGA96_14R00X11R00X1R20_DDR3_16BIT!!!TF-38!\VSS10\!!!!!!!! +S!!U10!T1!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS55212\@\QF_IC\.\DDR3_16bit.Normal\(chips)!DDR3_16BIT_FBGA96_14R00X11R00X1R20_DDR3_16BIT!!!TF-38!\VSS11\!!!!!!!! +S!!U10!T9!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS55212\@\QF_IC\.\DDR3_16bit.Normal\(chips)!DDR3_16BIT_FBGA96_14R00X11R00X1R20_DDR3_16BIT!!!TF-38!\VSS12\!!!!!!!! +S!!U10!A9!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS55212\@\QF_IC\.\DDR3_16bit.Normal\(chips)!DDR3_16BIT_FBGA96_14R00X11R00X1R20_DDR3_16BIT!!!TF-38!\VSS1\!!!!!!!! +S!!U10!B3!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS55212\@\QF_IC\.\DDR3_16bit.Normal\(chips)!DDR3_16BIT_FBGA96_14R00X11R00X1R20_DDR3_16BIT!!!TF-38!\VSS2\!!!!!!!! +S!!U10!E1!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS55212\@\QF_IC\.\DDR3_16bit.Normal\(chips)!DDR3_16BIT_FBGA96_14R00X11R00X1R20_DDR3_16BIT!!!TF-38!\VSS3\!!!!!!!! +S!!U10!G8!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS55212\@\QF_IC\.\DDR3_16bit.Normal\(chips)!DDR3_16BIT_FBGA96_14R00X11R00X1R20_DDR3_16BIT!!!TF-38!\VSS4\!!!!!!!! +S!!U10!J2!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS55212\@\QF_IC\.\DDR3_16bit.Normal\(chips)!DDR3_16BIT_FBGA96_14R00X11R00X1R20_DDR3_16BIT!!!TF-38!\VSS5\!!!!!!!! +S!!U10!J8!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS55212\@\QF_IC\.\DDR3_16bit.Normal\(chips)!DDR3_16BIT_FBGA96_14R00X11R00X1R20_DDR3_16BIT!!!TF-38!\VSS6\!!!!!!!! +S!!U10!M1!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS55212\@\QF_IC\.\DDR3_16bit.Normal\(chips)!DDR3_16BIT_FBGA96_14R00X11R00X1R20_DDR3_16BIT!!!TF-38!\VSS7\!!!!!!!! +S!!U10!M9!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS55212\@\QF_IC\.\DDR3_16bit.Normal\(chips)!DDR3_16BIT_FBGA96_14R00X11R00X1R20_DDR3_16BIT!!!TF-38!\VSS8\!!!!!!!! +S!!U10!P1!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS55212\@\QF_IC\.\DDR3_16bit.Normal\(chips)!DDR3_16BIT_FBGA96_14R00X11R00X1R20_DDR3_16BIT!!!TF-38!\VSS9\!!!!!!!! +S!!U10!B1!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS55212\@\QF_IC\.\DDR3_16bit.Normal\(chips)!DDR3_16BIT_FBGA96_14R00X11R00X1R20_DDR3_16BIT!!!TF-38!\VSSQ1\!!!!!!!! +S!!U10!B9!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS55212\@\QF_IC\.\DDR3_16bit.Normal\(chips)!DDR3_16BIT_FBGA96_14R00X11R00X1R20_DDR3_16BIT!!!TF-38!\VSSQ2\!!!!!!!! +S!!U10!D1!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS55212\@\QF_IC\.\DDR3_16bit.Normal\(chips)!DDR3_16BIT_FBGA96_14R00X11R00X1R20_DDR3_16BIT!!!TF-38!\VSSQ3\!!!!!!!! +S!!U10!D8!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS55212\@\QF_IC\.\DDR3_16bit.Normal\(chips)!DDR3_16BIT_FBGA96_14R00X11R00X1R20_DDR3_16BIT!!!TF-38!\VSSQ4\!!!!!!!! +S!!U10!E2!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS55212\@\QF_IC\.\DDR3_16bit.Normal\(chips)!DDR3_16BIT_FBGA96_14R00X11R00X1R20_DDR3_16BIT!!!TF-38!\VSSQ5\!!!!!!!! +S!!U10!E8!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS55212\@\QF_IC\.\DDR3_16bit.Normal\(chips)!DDR3_16BIT_FBGA96_14R00X11R00X1R20_DDR3_16BIT!!!TF-38!\VSSQ6\!!!!!!!! +S!!U10!F9!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS55212\@\QF_IC\.\DDR3_16bit.Normal\(chips)!DDR3_16BIT_FBGA96_14R00X11R00X1R20_DDR3_16BIT!!!TF-38!\VSSQ7\!!!!!!!! +S!!U10!G1!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS55212\@\QF_IC\.\DDR3_16bit.Normal\(chips)!DDR3_16BIT_FBGA96_14R00X11R00X1R20_DDR3_16BIT!!!TF-38!\VSSQ8\!!!!!!!! +S!!U10!G9!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS55212\@\QF_IC\.\DDR3_16bit.Normal\(chips)!DDR3_16BIT_FBGA96_14R00X11R00X1R20_DDR3_16BIT!!!TF-38!\VSSQ9\!!!!!!!! +S!!U10!L3!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS55212\@\QF_IC\.\DDR3_16bit.Normal\(chips)!DDR3_16BIT_FBGA96_14R00X11R00X1R20_DDR3_16BIT!!!TF-38!\WE#\!!!!!!!! +S!!U10!L8!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS55212\@\QF_IC\.\DDR3_16bit.Normal\(chips)!DDR3_16BIT_FBGA96_14R00X11R00X1R20_DDR3_16BIT!!!TF-38!\ZQ0\!!!!!!!! +S!!U10!L9!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS55212\@\QF_IC\.\DDR3_16bit.Normal\(chips)!DDR3_16BIT_FBGA96_14R00X11R00X1R20_DDR3_16BIT!!!TF-38!\ZQ1\!!!!!!!! S!N19188!C1!1!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS19387\@\DISCRETE\.\CAP NP.Normal\(chips)!CAP NP_C0402_DISCRETE_18PF!!!F23!\1\!!!!!!!! S!GND!C1!2!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS19387\@\DISCRETE\.\CAP NP.Normal\(chips)!CAP NP_C0402_DISCRETE_18PF!!!F23!\2\!!!!!!!! S!N19203!C2!1!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS19709\@\DISCRETE\.\CAP NP.Normal\(chips)!CAP NP_C0402_DISCRETE_18PF!!!F22!\1\!!!!!!!! @@ -456,10 +728,10 @@ S!!U2!20!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS20987\@d.s(v)!LAN8720A-CP-ABC_QFN S!!U2!21!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS20987\@d.s(v)!LAN8720A-CP-ABC_QFN24-6X6_MC_MCH_LAN8720A-CP-ABC!!!TF-15!\TXP\!!!!!!!! S!!U2!5!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS20987\@d.s(v)!LAN8720A-CP-ABC_QFN24-6X6_MC_MCH_LAN8720A-CP-ABC!!!TF-15!\XTAL1/CLKIN\!!!!!!!! S!!U2!4!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS20987\@d.s(v)!LAN8720A-CP-ABC_QFN24-6X6_MC_MCH_LAN8720A-CP-ABC!!!TF-15!\XTAL2\!!!!!!!! -S!VDD1A!U2!19!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS21054\@d.s(v)!LAN8720A-CP-ABC_QFN24-6X6_MC_MCH_LAN8720A-CP-ABC!!!F8!\VDD1A\!!!!!!!! -S!VDD2A!U2!1!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS21054\@d.s(v)!LAN8720A-CP-ABC_QFN24-6X6_MC_MCH_LAN8720A-CP-ABC!!!F8!\VDD2A\!!!!!!!! -S!VDDCR!U2!6!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS21054\@d.s(v)!LAN8720A-CP-ABC_QFN24-6X6_MC_MCH_LAN8720A-CP-ABC!!!F8!\VDDCR\!!!!!!!! -S!VDDIO!U2!9!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS21054\@d.s(v)!LAN8720A-CP-ABC_QFN24-6X6_MC_MCH_LAN8720A-CP-ABC!!!F8!\VDDIO\!!!!!!!! +S!VDD1A!U2!19!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS21054\@d.s(v)!LAN8720A-CP-ABC_QFN24-6X6_MC_MCH_LAN8720A-CP-ABC!!!F3!\VDD1A\!!!!!!!! +S!VDD2A!U2!1!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS21054\@d.s(v)!LAN8720A-CP-ABC_QFN24-6X6_MC_MCH_LAN8720A-CP-ABC!!!F3!\VDD2A\!!!!!!!! +S!VDDCR!U2!6!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS21054\@d.s(v)!LAN8720A-CP-ABC_QFN24-6X6_MC_MCH_LAN8720A-CP-ABC!!!F3!\VDDCR\!!!!!!!! +S!VDDIO!U2!9!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS21054\@d.s(v)!LAN8720A-CP-ABC_QFN24-6X6_MC_MCH_LAN8720A-CP-ABC!!!F3!\VDDIO\!!!!!!!! S!!U3!11!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS21176\@d.s(v)!LAN8720A-CP-ABC_QFN24-6X6_MC_MCH_LAN8720A-CP-ABC!!!TF-13!\CRS_DV/*MODE2\!!!!!!!! S!!U3!25!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS21176\@d.s(v)!LAN8720A-CP-ABC_QFN24-6X6_MC_MCH_LAN8720A-CP-ABC!!!TF-13!\EPAD\!!!!!!!! S!!U3!3!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS21176\@d.s(v)!LAN8720A-CP-ABC_QFN24-6X6_MC_MCH_LAN8720A-CP-ABC!!!TF-13!\LED1/*REGOFF\!!!!!!!! @@ -481,35 +753,10 @@ S!!U3!20!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS21176\@d.s(v)!LAN8720A-CP-ABC_QFN S!!U3!21!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS21176\@d.s(v)!LAN8720A-CP-ABC_QFN24-6X6_MC_MCH_LAN8720A-CP-ABC!!!TF-13!\TXP\!!!!!!!! S!!U3!5!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS21176\@d.s(v)!LAN8720A-CP-ABC_QFN24-6X6_MC_MCH_LAN8720A-CP-ABC!!!TF-13!\XTAL1/CLKIN\!!!!!!!! S!!U3!4!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS21176\@d.s(v)!LAN8720A-CP-ABC_QFN24-6X6_MC_MCH_LAN8720A-CP-ABC!!!TF-13!\XTAL2\!!!!!!!! -S!VDD1A!U3!19!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS21243\@d.s(v)!LAN8720A-CP-ABC_QFN24-6X6_MC_MCH_LAN8720A-CP-ABC!!!F7!\VDD1A\!!!!!!!! -S!VDD2A!U3!1!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS21243\@d.s(v)!LAN8720A-CP-ABC_QFN24-6X6_MC_MCH_LAN8720A-CP-ABC!!!F7!\VDD2A\!!!!!!!! -S!VDDCR!U3!6!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS21243\@d.s(v)!LAN8720A-CP-ABC_QFN24-6X6_MC_MCH_LAN8720A-CP-ABC!!!F7!\VDDCR\!!!!!!!! -S!VDDIO!U3!9!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS21243\@d.s(v)!LAN8720A-CP-ABC_QFN24-6X6_MC_MCH_LAN8720A-CP-ABC!!!F7!\VDDIO\!!!!!!!! -S!!U4!1!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS22426\@d.s(v)!TLV62569DBVR_DBV0005A_N_TLV62569DBV!!!F6!\EN\!!!!!!!! -S!!U4!5!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS22426\@d.s(v)!TLV62569DBVR_DBV0005A_N_TLV62569DBV!!!F6!\FB\!!!!!!!! -S!GND!U4!2!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS22426\@d.s(v)!TLV62569DBVR_DBV0005A_N_TLV62569DBV!!!F6!\GND\!!!!!!!! -S!SW!U4!3!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS22426\@d.s(v)!TLV62569DBVR_DBV0005A_N_TLV62569DBV!!!F6!\SW\!!!!!!!! -S!VIN!U4!4!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS22426\@d.s(v)!TLV62569DBVR_DBV0005A_N_TLV62569DBV!!!F6!\VIN\!!!!!!!! -S!!U5!1!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS22454\@d.s(v)!TLV62569DBVR_DBV0005A_N_TLV62569DBV!!!F5!\EN\!!!!!!!! -S!!U5!5!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS22454\@d.s(v)!TLV62569DBVR_DBV0005A_N_TLV62569DBV!!!F5!\FB\!!!!!!!! -S!GND!U5!2!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS22454\@d.s(v)!TLV62569DBVR_DBV0005A_N_TLV62569DBV!!!F5!\GND\!!!!!!!! -S!SW!U5!3!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS22454\@d.s(v)!TLV62569DBVR_DBV0005A_N_TLV62569DBV!!!F5!\SW\!!!!!!!! -S!VIN!U5!4!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS22454\@d.s(v)!TLV62569DBVR_DBV0005A_N_TLV62569DBV!!!F5!\VIN\!!!!!!!! -S!!U6!1!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS22482\@d.s(v)!TLV62569DBVR_DBV0005A_N_TLV62569DBV!!!F4!\EN\!!!!!!!! -S!!U6!5!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS22482\@d.s(v)!TLV62569DBVR_DBV0005A_N_TLV62569DBV!!!F4!\FB\!!!!!!!! -S!GND!U6!2!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS22482\@d.s(v)!TLV62569DBVR_DBV0005A_N_TLV62569DBV!!!F4!\GND\!!!!!!!! -S!SW!U6!3!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS22482\@d.s(v)!TLV62569DBVR_DBV0005A_N_TLV62569DBV!!!F4!\SW\!!!!!!!! -S!VIN!U6!4!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS22482\@d.s(v)!TLV62569DBVR_DBV0005A_N_TLV62569DBV!!!F4!\VIN\!!!!!!!! -S!!U7!1!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS22510\@d.s(v)!TLV62569DBVR_DBV0005A_N_TLV62569DBV!!!F3!\EN\!!!!!!!! -S!!U7!5!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS22510\@d.s(v)!TLV62569DBVR_DBV0005A_N_TLV62569DBV!!!F3!\FB\!!!!!!!! -S!GND!U7!2!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS22510\@d.s(v)!TLV62569DBVR_DBV0005A_N_TLV62569DBV!!!F3!\GND\!!!!!!!! -S!SW!U7!3!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS22510\@d.s(v)!TLV62569DBVR_DBV0005A_N_TLV62569DBV!!!F3!\SW\!!!!!!!! -S!VIN!U7!4!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS22510\@d.s(v)!TLV62569DBVR_DBV0005A_N_TLV62569DBV!!!F3!\VIN\!!!!!!!! -S!!U8!1!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS22538\@d.s(v)!TLV62569DBVR_DBV0005A_N_TLV62569DBV!!!F2!\EN\!!!!!!!! -S!!U8!5!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS22538\@d.s(v)!TLV62569DBVR_DBV0005A_N_TLV62569DBV!!!F2!\FB\!!!!!!!! -S!GND!U8!2!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS22538\@d.s(v)!TLV62569DBVR_DBV0005A_N_TLV62569DBV!!!F2!\GND\!!!!!!!! -S!SW!U8!3!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS22538\@d.s(v)!TLV62569DBVR_DBV0005A_N_TLV62569DBV!!!F2!\SW\!!!!!!!! -S!VIN!U8!4!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS22538\@d.s(v)!TLV62569DBVR_DBV0005A_N_TLV62569DBV!!!F2!\VIN\!!!!!!!! +S!VDD1A!U3!19!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS21243\@d.s(v)!LAN8720A-CP-ABC_QFN24-6X6_MC_MCH_LAN8720A-CP-ABC!!!F2!\VDD1A\!!!!!!!! +S!VDD2A!U3!1!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS21243\@d.s(v)!LAN8720A-CP-ABC_QFN24-6X6_MC_MCH_LAN8720A-CP-ABC!!!F2!\VDD2A\!!!!!!!! +S!VDDCR!U3!6!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS21243\@d.s(v)!LAN8720A-CP-ABC_QFN24-6X6_MC_MCH_LAN8720A-CP-ABC!!!F2!\VDDCR\!!!!!!!! +S!VDDIO!U3!9!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS21243\@d.s(v)!LAN8720A-CP-ABC_QFN24-6X6_MC_MCH_LAN8720A-CP-ABC!!!F2!\VDDIO\!!!!!!!! S!GND!U9!1!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS52680\@\QF_IC\.\K922A.Normal\(chips)!K922_K922_K922!!!F1!\GND#1\!!!!!!!! S!GND!U9!34!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS52680\@\QF_IC\.\K922A.Normal\(chips)!K922_K922_K922!!!F1!\GND#34\!!!!!!!! S!GND!U9!35!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS52680\@\QF_IC\.\K922A.Normal\(chips)!K922_K922_K922!!!F1!\GND#35\!!!!!!!! diff --git a/allegro/pstdedb.cdsz b/allegro/pstdedb.cdsz index 6c1a8c2..e1d9fbf 100644 Binary files a/allegro/pstdedb.cdsz and b/allegro/pstdedb.cdsz differ diff --git a/allegro/rk3506_nav_rk3506_nav.json b/allegro/rk3506_nav_rk3506_nav.json index fa91227..6ab8060 100644 --- a/allegro/rk3506_nav_rk3506_nav.json +++ b/allegro/rk3506_nav_rk3506_nav.json @@ -5,7 +5,69 @@ "Component Property" : [], "Net Property" : [], "Pin Property" : [], - "Component" : [], + "Component" : [ + { + "Name" : "J2", + "C_PATH" : "@\\RK3506_NAV\\.\\SCHEMATIC1\\(sch_1):\\INS60593\\@\\QF_ANT\\.\\MMCX-180.Normal\\(chips)", + "Logical" : "J2", + "Physical" : null + }, + { + "Name" : "J3", + "C_PATH" : "@\\RK3506_NAV\\.\\SCHEMATIC1\\(sch_1):\\INS60619\\@\\QF_ANT\\.\\MMCX-180.Normal\\(chips)", + "Logical" : "J3", + "Physical" : null + } + ], "Net" : [], - "Connection" : [] + "Connection" : [ + { + "Name" : "J2.3", + "C_PATH" : "@\\RK3506_NAV\\.\\SCHEMATIC1\\(sch_1):\\INS60593\\@\\QF_ANT\\.\\MMCX-180.Normal\\(chips):\\GND#3\\", + "Logical" : "GND", + "Physical" : null + }, + { + "Name" : "J2.4", + "C_PATH" : "@\\RK3506_NAV\\.\\SCHEMATIC1\\(sch_1):\\INS60593\\@\\QF_ANT\\.\\MMCX-180.Normal\\(chips):\\GND#4\\", + "Logical" : "GND", + "Physical" : null + }, + { + "Name" : "J2.2", + "C_PATH" : "@\\RK3506_NAV\\.\\SCHEMATIC1\\(sch_1):\\INS60593\\@\\QF_ANT\\.\\MMCX-180.Normal\\(chips):\\GND#2\\", + "Logical" : "GND", + "Physical" : null + }, + { + "Name" : "J2.5", + "C_PATH" : "@\\RK3506_NAV\\.\\SCHEMATIC1\\(sch_1):\\INS60593\\@\\QF_ANT\\.\\MMCX-180.Normal\\(chips):\\GND#5\\", + "Logical" : "GND", + "Physical" : null + }, + { + "Name" : "J3.2", + "C_PATH" : "@\\RK3506_NAV\\.\\SCHEMATIC1\\(sch_1):\\INS60619\\@\\QF_ANT\\.\\MMCX-180.Normal\\(chips):\\GND#2\\", + "Logical" : "GND", + "Physical" : null + }, + { + "Name" : "J3.3", + "C_PATH" : "@\\RK3506_NAV\\.\\SCHEMATIC1\\(sch_1):\\INS60619\\@\\QF_ANT\\.\\MMCX-180.Normal\\(chips):\\GND#3\\", + "Logical" : "GND", + "Physical" : null + }, + { + "Name" : "J3.4", + "C_PATH" : "@\\RK3506_NAV\\.\\SCHEMATIC1\\(sch_1):\\INS60619\\@\\QF_ANT\\.\\MMCX-180.Normal\\(chips):\\GND#4\\", + "Logical" : "GND", + "Physical" : null + }, + { + "Name" : "J3.5", + "C_PATH" : "@\\RK3506_NAV\\.\\SCHEMATIC1\\(sch_1):\\INS60619\\@\\QF_ANT\\.\\MMCX-180.Normal\\(chips):\\GND#5\\", + "Logical" : "GND", + "Physical" : null + } + ] } diff --git a/rk3506_nav.brd b/rk3506_nav.brd index 7895ba1..d4822b3 100644 Binary files a/rk3506_nav.brd and b/rk3506_nav.brd differ