diff --git a/.gitignore b/.gitignore index 94372be..205337f 100644 --- a/.gitignore +++ b/.gitignore @@ -17,6 +17,9 @@ CAPTURE_DESIGN_DCF/ *.log devices.dml +# ---- Allegro 网表目录（只跟踪 pst* 网表数据等关键文件）---- +allegro/*,1 + # ---- SigXplorer ---- signoise.log signoise.run/ @@ -28,4 +31,9 @@ Desktop.ini *.lck -*.DSNlck \ No newline at end of file +*.DSNlck + +*.txt* +*.lst +*.xml +*.log* diff --git a/RK3506_NAV.DSN b/RK3506_NAV.DSN index 83d63cc..7d552f2 100644 Binary files a/RK3506_NAV.DSN and b/RK3506_NAV.DSN differ diff --git a/allegro/chipsview.dat b/allegro/chipsview.dat new file mode 100644 index 0000000..c34d14f --- /dev/null +++ b/allegro/chipsview.dat @@ -0,0 +1,4603 @@ +FILE_TYPE=LIBRARY_PARTS; +primitive 'CAP NP_C0402_DISCRETE_18PF'; + pin + '2': + PIN_NUMBER='(2)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '1': + PIN_NUMBER='(1)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + end_pin; + body + PART_NAME='CAP NP'; + VALUE='18pF'; + BODY_NAME='CAP NP_C0402_DISCRETE_18PF'; + JEDEC_TYPE='C0402'; + PHYS_DES_PREFIX='C'; + CLASS='DISCRETE'; + end_body; +end_primitive; + +primitive 'CAP NP_C0402_BGA_DISCRETE_10UF'; + pin + '2': + PIN_NUMBER='(2)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '1': + PIN_NUMBER='(1)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + end_pin; + body + PART_NAME='CAP NP'; + VALUE='10uF'; + BODY_NAME='CAP NP_C0402_BGA_DISCRETE_10UF'; + JEDEC_TYPE='C0402_BGA'; + PHYS_DES_PREFIX='C'; + CLASS='DISCRETE'; + end_body; +end_primitive; + +primitive 'CAP NP_C0402_DISCRETE_100NF'; + pin + '2': + PIN_NUMBER='(2)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '1': + PIN_NUMBER='(1)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + end_pin; + body + PART_NAME='CAP NP'; + VALUE='100nF'; + BODY_NAME='CAP NP_C0402_DISCRETE_100NF'; + JEDEC_TYPE='C0402'; + PHYS_DES_PREFIX='C'; + CLASS='DISCRETE'; + end_body; +end_primitive; + +primitive 'CAP NP_C0402_DISCRETE_10UF'; + pin + '2': + PIN_NUMBER='(2)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '1': + PIN_NUMBER='(1)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + end_pin; + body + PART_NAME='CAP NP'; + VALUE='10uF'; + BODY_NAME='CAP NP_C0402_DISCRETE_10UF'; + JEDEC_TYPE='C0402'; + PHYS_DES_PREFIX='C'; + CLASS='DISCRETE'; + end_body; +end_primitive; + +primitive 'CAP NP_C0603_DISCRETE_22UF'; + pin + '2': + PIN_NUMBER='(2)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '1': + PIN_NUMBER='(1)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + end_pin; + body + PART_NAME='CAP NP'; + VALUE='22uF'; + BODY_NAME='CAP NP_C0603_DISCRETE_22UF'; + JEDEC_TYPE='C0603'; + PHYS_DES_PREFIX='C'; + CLASS='DISCRETE'; + end_body; +end_primitive; + +primitive 'CAP NP_C0402_BGA_DISCRETE_100NF'; + pin + '2': + PIN_NUMBER='(2)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '1': + PIN_NUMBER='(1)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + end_pin; + body + PART_NAME='CAP NP'; + VALUE='100nF'; + BODY_NAME='CAP NP_C0402_BGA_DISCRETE_100NF'; + JEDEC_TYPE='C0402_BGA'; + PHYS_DES_PREFIX='C'; + CLASS='DISCRETE'; + end_body; +end_primitive; + +primitive 'LSHM-140-030-L-DV-A-N-TR_SAMTEC_LSHM-140-030-L-DV-A-N-TR_LSHM-140-030-L-DV-A-N-TR'; + pin + '80': + PIN_NUMBER='(80)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '79': + PIN_NUMBER='(79)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '78': + PIN_NUMBER='(78)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '77': + PIN_NUMBER='(77)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '76': + PIN_NUMBER='(76)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '75': + PIN_NUMBER='(75)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '74': + PIN_NUMBER='(74)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '73': + PIN_NUMBER='(73)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '72': + PIN_NUMBER='(72)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '71': + PIN_NUMBER='(71)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '70': + PIN_NUMBER='(70)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '69': + PIN_NUMBER='(69)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '68': + PIN_NUMBER='(68)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '67': + PIN_NUMBER='(67)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '66': + PIN_NUMBER='(66)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '65': + PIN_NUMBER='(65)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '64': + PIN_NUMBER='(64)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '63': + PIN_NUMBER='(63)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '62': + PIN_NUMBER='(62)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '61': + PIN_NUMBER='(61)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '60': + PIN_NUMBER='(60)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '59': + PIN_NUMBER='(59)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '58': + PIN_NUMBER='(58)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '57': + PIN_NUMBER='(57)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '56': + PIN_NUMBER='(56)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '55': + PIN_NUMBER='(55)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '54': + PIN_NUMBER='(54)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '53': + PIN_NUMBER='(53)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '52': + PIN_NUMBER='(52)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '51': + PIN_NUMBER='(51)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '50': + PIN_NUMBER='(50)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '49': + PIN_NUMBER='(49)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '48': + PIN_NUMBER='(48)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '47': + PIN_NUMBER='(47)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '46': + PIN_NUMBER='(46)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '45': + PIN_NUMBER='(45)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '44': + PIN_NUMBER='(44)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '43': + PIN_NUMBER='(43)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '42': + PIN_NUMBER='(42)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '41': + PIN_NUMBER='(41)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '40': + PIN_NUMBER='(40)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '39': + PIN_NUMBER='(39)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '38': + PIN_NUMBER='(38)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '37': + PIN_NUMBER='(37)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '36': + PIN_NUMBER='(36)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '35': + PIN_NUMBER='(35)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '34': + PIN_NUMBER='(34)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '33': + PIN_NUMBER='(33)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '32': + PIN_NUMBER='(32)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '31': + PIN_NUMBER='(31)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '30': + PIN_NUMBER='(30)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '29': + PIN_NUMBER='(29)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '28': + PIN_NUMBER='(28)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '27': + PIN_NUMBER='(27)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '26': + PIN_NUMBER='(26)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '25': + PIN_NUMBER='(25)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '24': + PIN_NUMBER='(24)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '23': + PIN_NUMBER='(23)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '22': + PIN_NUMBER='(22)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '21': + PIN_NUMBER='(21)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '20': + PIN_NUMBER='(20)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '19': + PIN_NUMBER='(19)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '18': + PIN_NUMBER='(18)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '17': + PIN_NUMBER='(17)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '16': + PIN_NUMBER='(16)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '15': + PIN_NUMBER='(15)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '14': + PIN_NUMBER='(14)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '13': + PIN_NUMBER='(13)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '12': + PIN_NUMBER='(12)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '11': + PIN_NUMBER='(11)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '10': + PIN_NUMBER='(10)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '09': + PIN_NUMBER='(09)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '08': + PIN_NUMBER='(08)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '07': + PIN_NUMBER='(07)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '06': + PIN_NUMBER='(06)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '05': + PIN_NUMBER='(05)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '04': + PIN_NUMBER='(04)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '03': + PIN_NUMBER='(03)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '02': + PIN_NUMBER='(02)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '01': + PIN_NUMBER='(01)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + end_pin; + body + PART_NAME='LSHM-140-030-L-DV-A-N-TR'; + VALUE='LSHM-140-030-L-DV-A-N-TR'; + BODY_NAME='LSHM-140-030-L-DV-A-N-TR_SAMTEC_LSHM-140-030-L-DV-A-N-TR_LSHM-140-030-L-DV-A-N-TR'; + JEDEC_TYPE='SAMTEC_LSHM-140-030-L-DV-A-N-TR'; + PHYS_DES_PREFIX='J'; + CLASS='IC'; + end_body; +end_primitive; + +primitive 'R_R0402_DISCRETE_1M'; + pin + '2': + PIN_NUMBER='(2)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '1': + PIN_NUMBER='(1)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + end_pin; + body + PART_NAME='R'; + VALUE='1M'; + BODY_NAME='R_R0402_DISCRETE_1M'; + JEDEC_TYPE='R0402'; + PHYS_DES_PREFIX='R'; + CLASS='DISCRETE'; + end_body; +end_primitive; + +primitive 'SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B'; + pin + '\VSS_99\': + PIN_NUMBER='(0,0,0,0,0,0,0,0,0,1H5)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS_98\': + PIN_NUMBER='(0,0,0,0,0,0,0,0,0,1H4)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS_97\': + PIN_NUMBER='(0,0,0,0,0,0,0,0,0,1H3)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS_96\': + PIN_NUMBER='(0,0,0,0,0,0,0,0,0,1H2)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS_95\': + PIN_NUMBER='(0,0,0,0,0,0,0,0,0,1G13)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS_94\': + PIN_NUMBER='(0,0,0,0,0,0,0,0,0,1G12)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS_93\': + PIN_NUMBER='(0,0,0,0,0,0,0,0,0,1G10)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS_92\': + PIN_NUMBER='(0,0,0,0,0,0,0,0,0,1G9)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS_91\': + PIN_NUMBER='(0,0,0,0,0,0,0,0,0,1G8)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS_90\': + PIN_NUMBER='(0,0,0,0,0,0,0,0,0,1G7)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS_89\': + PIN_NUMBER='(0,0,0,0,0,0,0,0,0,1G6)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS_88\': + PIN_NUMBER='(0,0,0,0,0,0,0,0,0,1G5)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS_87\': + PIN_NUMBER='(0,0,0,0,0,0,0,0,0,1G4)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS_86\': + PIN_NUMBER='(0,0,0,0,0,0,0,0,0,1G3)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS_85\': + PIN_NUMBER='(0,0,0,0,0,0,0,0,0,1G1)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS_84\': + PIN_NUMBER='(0,0,0,0,0,0,0,0,0,1F13)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS_83\': + PIN_NUMBER='(0,0,0,0,0,0,0,0,0,1F12)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS_82\': + PIN_NUMBER='(0,0,0,0,0,0,0,0,0,1F10)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS_81\': + PIN_NUMBER='(0,0,0,0,0,0,0,0,0,1F9)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS_80\': + PIN_NUMBER='(0,0,0,0,0,0,0,0,0,1F8)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS_79\': + PIN_NUMBER='(0,0,0,0,0,0,0,0,0,1F7)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS_78\': + PIN_NUMBER='(0,0,0,0,0,0,0,0,0,1F6)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS_77\': + PIN_NUMBER='(0,0,0,0,0,0,0,0,0,1F5)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS_76\': + PIN_NUMBER='(0,0,0,0,0,0,0,0,0,1F4)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS_75\': + PIN_NUMBER='(0,0,0,0,0,0,0,0,0,1F2)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS_74\': + PIN_NUMBER='(0,0,0,0,0,0,0,0,0,1F1)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS_73\': + PIN_NUMBER='(0,0,0,0,0,0,0,0,0,1E14)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS_72\': + PIN_NUMBER='(0,0,0,0,0,0,0,0,0,1E13)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS_71\': + PIN_NUMBER='(0,0,0,0,0,0,0,0,0,1E12)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS_70\': + PIN_NUMBER='(0,0,0,0,0,0,0,0,0,1E2)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS_138\': + PIN_NUMBER='(0,0,0,0,0,0,0,0,0,1N11)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS_137\': + PIN_NUMBER='(0,0,0,0,0,0,0,0,0,1N7)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS_136\': + PIN_NUMBER='(0,0,0,0,0,0,0,0,0,1N3)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS_135\': + PIN_NUMBER='(0,0,0,0,0,0,0,0,0,1M14)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS_134\': + PIN_NUMBER='(0,0,0,0,0,0,0,0,0,1M12)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS_133\': + PIN_NUMBER='(0,0,0,0,0,0,0,0,0,1M10)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS_132\': + PIN_NUMBER='(0,0,0,0,0,0,0,0,0,1M7)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS_131\': + PIN_NUMBER='(0,0,0,0,0,0,0,0,0,1M3)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS_130\': + PIN_NUMBER='(0,0,0,0,0,0,0,0,0,1M2)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS_129\': + PIN_NUMBER='(0,0,0,0,0,0,0,0,0,1M1)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS_128\': + PIN_NUMBER='(0,0,0,0,0,0,0,0,0,1L14)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS_127\': + PIN_NUMBER='(0,0,0,0,0,0,0,0,0,1L9)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS_126\': + PIN_NUMBER='(0,0,0,0,0,0,0,0,0,1L7)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS_125\': + PIN_NUMBER='(0,0,0,0,0,0,0,0,0,1L5)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS_124\': + PIN_NUMBER='(0,0,0,0,0,0,0,0,0,1L4)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS_123\': + PIN_NUMBER='(0,0,0,0,0,0,0,0,0,1L3)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS_122\': + PIN_NUMBER='(0,0,0,0,0,0,0,0,0,1L2)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS_121\': + PIN_NUMBER='(0,0,0,0,0,0,0,0,0,1K14)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS_120\': + PIN_NUMBER='(0,0,0,0,0,0,0,0,0,1K4)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS_119\': + PIN_NUMBER='(0,0,0,0,0,0,0,0,0,1K1)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS_118\': + PIN_NUMBER='(0,0,0,0,0,0,0,0,0,1J14)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS_117\': + PIN_NUMBER='(0,0,0,0,0,0,0,0,0,1J13)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS_116\': + PIN_NUMBER='(0,0,0,0,0,0,0,0,0,1J11)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS_115\': + PIN_NUMBER='(0,0,0,0,0,0,0,0,0,1J9)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS_114\': + PIN_NUMBER='(0,0,0,0,0,0,0,0,0,1J8)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS_113\': + PIN_NUMBER='(0,0,0,0,0,0,0,0,0,1J7)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS_112\': + PIN_NUMBER='(0,0,0,0,0,0,0,0,0,1J6)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS_111\': + PIN_NUMBER='(0,0,0,0,0,0,0,0,0,1J5)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS_110\': + PIN_NUMBER='(0,0,0,0,0,0,0,0,0,1J4)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS_109\': + PIN_NUMBER='(0,0,0,0,0,0,0,0,0,1J3)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS_108\': + PIN_NUMBER='(0,0,0,0,0,0,0,0,0,1J2)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS_107\': + PIN_NUMBER='(0,0,0,0,0,0,0,0,0,1J1)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS_106\': + PIN_NUMBER='(0,0,0,0,0,0,0,0,0,1H13)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS_105\': + PIN_NUMBER='(0,0,0,0,0,0,0,0,0,1H12)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS_104\': + PIN_NUMBER='(0,0,0,0,0,0,0,0,0,1H10)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS_103\': + PIN_NUMBER='(0,0,0,0,0,0,0,0,0,1H9)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS_102\': + PIN_NUMBER='(0,0,0,0,0,0,0,0,0,1H8)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS_101\': + PIN_NUMBER='(0,0,0,0,0,0,0,0,0,1H7)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS_100\': + PIN_NUMBER='(0,0,0,0,0,0,0,0,0,1H6)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS_9\': + PIN_NUMBER='(0,0,0,0,0,0,0,0,H21,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS_8\': + PIN_NUMBER='(0,0,0,0,0,0,0,0,G2,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS_7\': + PIN_NUMBER='(0,0,0,0,0,0,0,0,D22,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS_6\': + PIN_NUMBER='(0,0,0,0,0,0,0,0,D2,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS_69\': + PIN_NUMBER='(0,0,0,0,0,0,0,0,1E1,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS_68\': + PIN_NUMBER='(0,0,0,0,0,0,0,0,1D14,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS_67\': + PIN_NUMBER='(0,0,0,0,0,0,0,0,1D13,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS_66\': + PIN_NUMBER='(0,0,0,0,0,0,0,0,1D12,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS_65\': + PIN_NUMBER='(0,0,0,0,0,0,0,0,1D11,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS_64\': + PIN_NUMBER='(0,0,0,0,0,0,0,0,1D10,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS_63\': + PIN_NUMBER='(0,0,0,0,0,0,0,0,1D9,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS_62\': + PIN_NUMBER='(0,0,0,0,0,0,0,0,1D8,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS_61\': + PIN_NUMBER='(0,0,0,0,0,0,0,0,1D7,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS_60\': + PIN_NUMBER='(0,0,0,0,0,0,0,0,1D6,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS_5\': + PIN_NUMBER='(0,0,0,0,0,0,0,0,B6,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS_59\': + PIN_NUMBER='(0,0,0,0,0,0,0,0,1D5,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS_58\': + PIN_NUMBER='(0,0,0,0,0,0,0,0,1D4,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS_57\': + PIN_NUMBER='(0,0,0,0,0,0,0,0,1D3,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS_56\': + PIN_NUMBER='(0,0,0,0,0,0,0,0,1D2,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS_55\': + PIN_NUMBER='(0,0,0,0,0,0,0,0,1D1,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS_54\': + PIN_NUMBER='(0,0,0,0,0,0,0,0,1C14,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS_53\': + PIN_NUMBER='(0,0,0,0,0,0,0,0,1C13,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS_52\': + PIN_NUMBER='(0,0,0,0,0,0,0,0,1C12,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS_51\': + PIN_NUMBER='(0,0,0,0,0,0,0,0,1C11,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS_50\': + PIN_NUMBER='(0,0,0,0,0,0,0,0,1C10,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS_4\': + PIN_NUMBER='(0,0,0,0,0,0,0,0,B4,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS_49\': + PIN_NUMBER='(0,0,0,0,0,0,0,0,1C9,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS_48\': + PIN_NUMBER='(0,0,0,0,0,0,0,0,1C6,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS_47\': + PIN_NUMBER='(0,0,0,0,0,0,0,0,1C5,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS_46\': + PIN_NUMBER='(0,0,0,0,0,0,0,0,1C1,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS_45\': + PIN_NUMBER='(0,0,0,0,0,0,0,0,1B8,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS_44\': + PIN_NUMBER='(0,0,0,0,0,0,0,0,1B5,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS_43\': + PIN_NUMBER='(0,0,0,0,0,0,0,0,1B4,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS_42\': + PIN_NUMBER='(0,0,0,0,0,0,0,0,1B3,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS_41\': + PIN_NUMBER='(0,0,0,0,0,0,0,0,1B2,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS_40\': + PIN_NUMBER='(0,0,0,0,0,0,0,0,1B1,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS_3\': + PIN_NUMBER='(0,0,0,0,0,0,0,0,A23,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS_39\': + PIN_NUMBER='(0,0,0,0,0,0,0,0,1A14,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS_38\': + PIN_NUMBER='(0,0,0,0,0,0,0,0,1A12,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS_37\': + PIN_NUMBER='(0,0,0,0,0,0,0,0,1A11,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS_36\': + PIN_NUMBER='(0,0,0,0,0,0,0,0,1A10,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS_35\': + PIN_NUMBER='(0,0,0,0,0,0,0,0,1A9,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS_34\': + PIN_NUMBER='(0,0,0,0,0,0,0,0,1A8,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS_33\': + PIN_NUMBER='(0,0,0,0,0,0,0,0,1A7,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS_32\': + PIN_NUMBER='(0,0,0,0,0,0,0,0,1A6,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS_31\': + PIN_NUMBER='(0,0,0,0,0,0,0,0,Y23,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS_30\': + PIN_NUMBER='(0,0,0,0,0,0,0,0,Y15,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS_2\': + PIN_NUMBER='(0,0,0,0,0,0,0,0,A17,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS_29\': + PIN_NUMBER='(0,0,0,0,0,0,0,0,Y9,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS_28\': + PIN_NUMBER='(0,0,0,0,0,0,0,0,Y1,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS_27\': + PIN_NUMBER='(0,0,0,0,0,0,0,0,W21,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS_26\': + PIN_NUMBER='(0,0,0,0,0,0,0,0,W19,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS_25\': + PIN_NUMBER='(0,0,0,0,0,0,0,0,W16,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS_24\': + PIN_NUMBER='(0,0,0,0,0,0,0,0,W13,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS_23\': + PIN_NUMBER='(0,0,0,0,0,0,0,0,W12,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS_22\': + PIN_NUMBER='(0,0,0,0,0,0,0,0,W11,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS_21\': + PIN_NUMBER='(0,0,0,0,0,0,0,0,W8,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS_20\': + PIN_NUMBER='(0,0,0,0,0,0,0,0,W5,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS_1\': + PIN_NUMBER='(0,0,0,0,0,0,0,0,A13,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS_19\': + PIN_NUMBER='(0,0,0,0,0,0,0,0,W3,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS_18\': + PIN_NUMBER='(0,0,0,0,0,0,0,0,V21,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS_17\': + PIN_NUMBER='(0,0,0,0,0,0,0,0,U21,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS_16\': + PIN_NUMBER='(0,0,0,0,0,0,0,0,T21,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS_15\': + PIN_NUMBER='(0,0,0,0,0,0,0,0,R21,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS_14\': + PIN_NUMBER='(0,0,0,0,0,0,0,0,N22,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS_13\': + PIN_NUMBER='(0,0,0,0,0,0,0,0,L21,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS_12\': + PIN_NUMBER='(0,0,0,0,0,0,0,0,L3,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS_11\': + PIN_NUMBER='(0,0,0,0,0,0,0,0,J22,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS_10\': + PIN_NUMBER='(0,0,0,0,0,0,0,0,J3,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VSS_0\': + PIN_NUMBER='(0,0,0,0,0,0,0,0,A1,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\DDR_VREF_DQ\': + PIN_NUMBER='(0,0,0,0,0,0,0,1L11,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\DDR_VREF_CA\': + PIN_NUMBER='(0,0,0,0,0,0,0,1L10,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\DDR_VDDQ_4\': + PIN_NUMBER='(0,0,0,0,0,0,0,1K10,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\DDR_VDDQ_3\': + PIN_NUMBER='(0,0,0,0,0,0,0,1K9,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\DDR_VDDQ_2\': + PIN_NUMBER='(0,0,0,0,0,0,0,1K8,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\DDR_VDDQ_1\': + PIN_NUMBER='(0,0,0,0,0,0,0,1K7,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\DDR_VDDQ_0\': + PIN_NUMBER='(0,0,0,0,0,0,0,1K6,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\DDR_RZQ\': + PIN_NUMBER='(0,0,0,0,0,0,0,1L8,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\DDR_OPEN1\': + PIN_NUMBER='(0,0,0,0,0,0,0,1K5,0,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\DDR_OPEN0\': + PIN_NUMBER='(0,0,0,0,0,0,0,1L6,0,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\DDR_ODT\': + PIN_NUMBER='(0,0,0,0,0,0,0,1N10,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\DDR_DQS1P\': + PIN_NUMBER='(0,0,0,0,0,0,0,Y4,0,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\DDR_DQS1N\': + PIN_NUMBER='(0,0,0,0,0,0,0,W4,0,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\DDR_DQS0P\': + PIN_NUMBER='(0,0,0,0,0,0,0,Y10,0,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\DDR_DQS0N\': + PIN_NUMBER='(0,0,0,0,0,0,0,W10,0,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\DDR_DQ9\': + PIN_NUMBER='(0,0,0,0,0,0,0,W7,0,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\DDR_DQ8\': + PIN_NUMBER='(0,0,0,0,0,0,0,Y7,0,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\DDR_DQ7\': + PIN_NUMBER='(0,0,0,0,0,0,0,1N5,0,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\DDR_DQ6\': + PIN_NUMBER='(0,0,0,0,0,0,0,W9,0,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\DDR_DQ5\': + PIN_NUMBER='(0,0,0,0,0,0,0,1N6,0,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\DDR_DQ4\': + PIN_NUMBER='(0,0,0,0,0,0,0,1M5,0,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\DDR_DQ3\': + PIN_NUMBER='(0,0,0,0,0,0,0,1M6,0,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\DDR_DQ2\': + PIN_NUMBER='(0,0,0,0,0,0,0,Y11,0,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\DDR_DQ1\': + PIN_NUMBER='(0,0,0,0,0,0,0,Y12,0,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\DDR_DQ15\': + PIN_NUMBER='(0,0,0,0,0,0,0,1N2,0,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\DDR_DQ14\': + PIN_NUMBER='(0,0,0,0,0,0,0,1N1,0,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\DDR_DQ13\': + PIN_NUMBER='(0,0,0,0,0,0,0,Y2,0,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\DDR_DQ12\': + PIN_NUMBER='(0,0,0,0,0,0,0,W6,0,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\DDR_DQ11\': + PIN_NUMBER='(0,0,0,0,0,0,0,Y3,0,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\DDR_DQ10\': + PIN_NUMBER='(0,0,0,0,0,0,0,Y6,0,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\DDR_DQ0\': + PIN_NUMBER='(0,0,0,0,0,0,0,Y13,0,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\DDR_DM1\': + PIN_NUMBER='(0,0,0,0,0,0,0,1M4,0,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\DDR_DM0\': + PIN_NUMBER='(0,0,0,0,0,0,0,1N4,0,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\DDR_CSN\': + PIN_NUMBER='(0,0,0,0,0,0,0,1M11,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\DDR_CLKP\': + PIN_NUMBER='(0,0,0,0,0,0,0,Y14,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\DDR_CLKN\': + PIN_NUMBER='(0,0,0,0,0,0,0,W14,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\DDR_CKE\': + PIN_NUMBER='(0,0,0,0,0,0,0,W15,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\DDR3_RESET\': + PIN_NUMBER='(0,0,0,0,0,0,0,1M13,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\DDR2_WEN | DDR3_RASN\': + PIN_NUMBER='(0,0,0,0,0,0,0,1M8,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\DDR2_RASN | DDR3_A10\': + PIN_NUMBER='(0,0,0,0,0,0,0,W17,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\DDR2_CASN | DDR3_BA1\': + PIN_NUMBER='(0,0,0,0,0,0,0,Y18,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\DDR2_BA2 | DDR3_BA2\': + PIN_NUMBER='(0,0,0,0,0,0,0,1N9,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\DDR2_BA1 | DDR3_WEN\': + PIN_NUMBER='(0,0,0,0,0,0,0,1M9,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\DDR2_BA0 | DDR3_CASN\': + PIN_NUMBER='(0,0,0,0,0,0,0,1N8,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\DDR2_A9 | DDR3_A7\': + PIN_NUMBER='(0,0,0,0,0,0,0,T22,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\DDR2_A8 | DDR3_A8\': + PIN_NUMBER='(0,0,0,0,0,0,0,Y21,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\DDR2_A7 | DDR3_A2\': + PIN_NUMBER='(0,0,0,0,0,0,0,V22,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\DDR2_A6 | DDR3_A6\': + PIN_NUMBER='(0,0,0,0,0,0,0,Y20,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\DDR2_A5 | DDR3_A5\': + PIN_NUMBER='(0,0,0,0,0,0,0,1N14,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\DDR2_A4 | DDR3_A1\': + PIN_NUMBER='(0,0,0,0,0,0,0,W20,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\DDR2_A3 | DDR3_A0\': + PIN_NUMBER='(0,0,0,0,0,0,0,V23,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\DDR2_A2 | DDR3_A4\': + PIN_NUMBER='(0,0,0,0,0,0,0,W18,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\DDR2_A15 | DDR3_A15\': + PIN_NUMBER='(0,0,0,0,0,0,0,Y17,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\DDR2_A14 | DDR3_A14\': + PIN_NUMBER='(0,0,0,0,0,0,0,Y22,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\DDR2_A13 | DDR3_A13\': + PIN_NUMBER='(0,0,0,0,0,0,0,T23,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\DDR2_A12 | DDR3_A9\': + PIN_NUMBER='(0,0,0,0,0,0,0,U22,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\DDR2_A11 | DDR3_A11\': + PIN_NUMBER='(0,0,0,0,0,0,0,W22,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\DDR2_A10 | DDR3_BA0\': + PIN_NUMBER='(0,0,0,0,0,0,0,1N12,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\DDR2_A1 | DDR3_A3\': + PIN_NUMBER='(0,0,0,0,0,0,0,1N13,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\DDR2_A0 | DDR3_A12\': + PIN_NUMBER='(0,0,0,0,0,0,0,W23,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\LOGIC_DVDD_6\': + PIN_NUMBER='(0,0,0,0,0,0,1J10,0,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\LOGIC_DVDD_5\': + PIN_NUMBER='(0,0,0,0,0,0,1H11,0,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\LOGIC_DVDD_4\': + PIN_NUMBER='(0,0,0,0,0,0,1G11,0,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\LOGIC_DVDD_3\': + PIN_NUMBER='(0,0,0,0,0,0,1F11,0,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\LOGIC_DVDD_2\': + PIN_NUMBER='(0,0,0,0,0,0,1E6,0,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\LOGIC_DVDD_1\': + PIN_NUMBER='(0,0,0,0,0,0,1E5,0,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\LOGIC_DVDD_0\': + PIN_NUMBER='(0,0,0,0,0,0,1E4,0,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\CPU_DVDD_2\': + PIN_NUMBER='(0,0,0,0,0,0,1C4,0,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\CPU_DVDD_1\': + PIN_NUMBER='(0,0,0,0,0,0,1C3,0,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\CPU_DVDD_0\': + PIN_NUMBER='(0,0,0,0,0,0,1C2,0,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\USB20_OTG_AVDD3V3\': + PIN_NUMBER='(0,0,0,0,0,1B10,0,0,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\USB20_OTG_AVDD1V8\': + PIN_NUMBER='(0,0,0,0,0,1B9,0,0,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\USB20_OTG_AVDD0V9\': + PIN_NUMBER='(0,0,0,0,0,1C8,0,0,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\USB20_OTG1_DP\': + PIN_NUMBER='(0,0,0,0,0,B15,0,0,0,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\USB20_OTG1_DM\': + PIN_NUMBER='(0,0,0,0,0,A15,0,0,0,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\USB20_OTG0_VBUSDET\': + PIN_NUMBER='(0,0,0,0,0,B18,0,0,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\USB20_OTG0_ID\': + PIN_NUMBER='(0,0,0,0,0,B17,0,0,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\USB20_OTG0_DP\': + PIN_NUMBER='(0,0,0,0,0,A16,0,0,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\USB20_OTG0_DM\': + PIN_NUMBER='(0,0,0,0,0,B16,0,0,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\TSADC_VCC1V8\': + PIN_NUMBER='(0,0,0,0,0,1B6,0,0,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\SARADC_IN3 | GPIO4_B3_Z\': + PIN_NUMBER='(0,0,0,0,0,B21,0,0,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\SARADC_IN2 | GPIO4_B2_Z\': + PIN_NUMBER='(0,0,0,0,0,A21,0,0,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\SARADC_IN1 | GPIO4_B1_Z\': + PIN_NUMBER='(0,0,0,0,0,B20,0,0,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\SARADC_IN0 | GPIO4_B0_Z\': + PIN_NUMBER='(0,0,0,0,0,A20,0,0,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\OTP_AVDD1V8 | SARADC_AVDD1V8\': + PIN_NUMBER='(0,0,0,0,0,1B14,0,0,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\MIPI_DPHY_DSI_TX_D1P | GPO4_A3_Z\': + PIN_NUMBER='(0,0,0,0,0,A12,0,0,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\MIPI_DPHY_DSI_TX_D1N | GPO4_A2_Z\': + PIN_NUMBER='(0,0,0,0,0,B12,0,0,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\MIPI_DPHY_DSI_TX_D0P | GPO4_A1_Z\': + PIN_NUMBER='(0,0,0,0,0,B11,0,0,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\MIPI_DPHY_DSI_TX_D0N | GPO4_A0_Z\': + PIN_NUMBER='(0,0,0,0,0,A11,0,0,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\MIPI_DPHY_DSI_TX_CLKP | GPO4_A5_Z\': + PIN_NUMBER='(0,0,0,0,0,B13,0,0,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\MIPI_DPHY_DSI_TX_CLKN | GPO4_A4_Z\': + PIN_NUMBER='(0,0,0,0,0,B14,0,0,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\MIPI_DPHY_AVDD1V8\': + PIN_NUMBER='(0,0,0,0,0,1B7,0,0,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\MIPI_DPHY_AVDD0V9\': + PIN_NUMBER='(0,0,0,0,0,1C7,0,0,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\ACODEC_ADC_VCM\': + PIN_NUMBER='(0,0,0,0,0,1B11,0,0,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\ACODEC_ADC_INP\': + PIN_NUMBER='(0,0,0,0,0,A19,0,0,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\ACODEC_ADC_INN\': + PIN_NUMBER='(0,0,0,0,0,B19,0,0,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\ACODEC_ADC_AVSS\': + PIN_NUMBER='(0,0,0,0,0,1A13,0,0,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\ACODEC_ADC_AVDD1V8\': + PIN_NUMBER='(0,0,0,0,0,1B13,0,0,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\ACODEC_ADC_AVDD1V6\': + PIN_NUMBER='(0,0,0,0,0,1B12,0,0,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VCCIO4_VCC\': + PIN_NUMBER='(0,0,0,0,1H14,0,0,0,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\TEST_CLK_OUT | SDMMC_D1 | GPIO3_A3_D\': + PIN_NUMBER='(0,0,0,0,K22,0,0,0,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\JTAG_TMS_M0 | SDMMC_D3 | GPIO3_A5_D\': + PIN_NUMBER='(0,0,0,0,H22,0,0,0,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\JTAG_TCK_M0 | SDMMC_D2 | GPIO3_A4_D\': + PIN_NUMBER='(0,0,0,0,H23,0,0,0,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\ETH_RMII1_TXEN | UART5_RX_M0 | GPIO3_B3_D\': + PIN_NUMBER='(0,0,0,0,P22,0,0,0,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\ETH_RMII1_TXD1 | UART5_CTSN_M0 | GPIO3_B2_D\': + PIN_NUMBER='(0,0,0,0,N21,0,0,0,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\ETH_RMII1_TXD0 | SAI2_LRCK_M0 | GPIO3_B1_D\': + PIN_NUMBER='(0,0,0,0,M21,0,0,0,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\ETH_RMII1_RXDVCRS | SAI2_MCLK_M0 | GPIO3_B6_D\': + PIN_NUMBER='(0,0,0,0,R22,0,0,0,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\ETH_RMII1_RXD1 | SAI2_SCLK_M0 | GPIO3_A7_D\': + PIN_NUMBER='(0,0,0,0,M22,0,0,0,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\ETH_RMII1_RXD0 | SAI2_SDI_M0 | GPIO3_A6_D\': + PIN_NUMBER='(0,0,0,0,L22,0,0,0,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\ETH_RMII1_MDIO | UART5_RTSN_M0 | GPIO3_B5_D\': + PIN_NUMBER='(0,0,0,0,P21,0,0,0,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\ETH_RMII1_MDC | UART5_TX_M0 | GPIO3_B4_D\': + PIN_NUMBER='(0,0,0,0,P23,0,0,0,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\ETH_RMII1_CLK | SAI2_SDO_M0 | GPIO3_B0_D\': + PIN_NUMBER='(0,0,0,0,M23,0,0,0,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\-- | SDMMC_D0 | GPIO3_A2_D\': + PIN_NUMBER='(0,0,0,0,K23,0,0,0,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\-- | SDMMC_CMD | GPIO3_A1_D\': + PIN_NUMBER='(0,0,0,0,J21,0,0,0,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\-- | SDMMC_CLK | GPIO3_A0_D\': + PIN_NUMBER='(0,0,0,0,K21,0,0,0,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VCCIO3_VCC\': + PIN_NUMBER='(0,0,0,1G14,0,0,0,0,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\SAI3_SDO | DSM_AUD_LP_M1 | ETH_RMII0_MDIO | GPIO2_B7_D\': + PIN_NUMBER='(0,0,0,G21,0,0,0,0,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\SAI3_SDI | DSM_AUD_LN_M1 | ETH_RMII0_MDC | GPIO2_B6_D\': + PIN_NUMBER='(0,0,0,F22,0,0,0,0,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\SAI3_SCLK | DSM_AUD_RN_M1 | ETH_RMII0_TXD1 | GPIO2_B4_D\': + PIN_NUMBER='(0,0,0,F21,0,0,0,0,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\SAI3_MCLK | -- | ETH_RMII0_RXDVCRS | GPIO2_C0_D\': + PIN_NUMBER='(0,0,0,G22,0,0,0,0,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\SAI3_LRCK | DSM_AUD_RP_M1 | ETH_RMII0_TXEN | GPIO2_B5_D\': + PIN_NUMBER='(0,0,0,F23,0,0,0,0,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\-- | SPI2_MOSI | ETH_RMII0_CLK | GPIO2_B2_D\': + PIN_NUMBER='(0,0,0,E21,0,0,0,0,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\-- | SPI2_MISO | ETH_RMII0_TXD0 | GPIO2_B3_D\': + PIN_NUMBER='(0,0,0,E22,0,0,0,0,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\-- | SPI2_CSN | ETH_RMII0_RXD1 | GPIO2_B1_D\': + PIN_NUMBER='(0,0,0,D23,0,0,0,0,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\-- | SPI2_CLK | ETH_RMII0_RXD0 | GPIO2_B0_D\': + PIN_NUMBER='(0,0,0,D21,0,0,0,0,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VCCIO2_VCC\': + PIN_NUMBER='(0,0,1F14,0,0,0,0,0,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\FSPI_D3 | GPIO2_A5_U\': + PIN_NUMBER='(0,0,C23,0,0,0,0,0,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\FSPI_D2 | GPIO2_A4_U\': + PIN_NUMBER='(0,0,C21,0,0,0,0,0,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\FSPI_D1 | GPIO2_A3_U\': + PIN_NUMBER='(0,0,B22,0,0,0,0,0,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\FSPI_D0 | GPIO2_A2_U\': + PIN_NUMBER='(0,0,B23,0,0,0,0,0,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\FSPI_CSN | GPIO2_A0_U\': + PIN_NUMBER='(0,0,A22,0,0,0,0,0,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\FSPI_CLK | GPIO2_A1_D\': + PIN_NUMBER='(0,0,C22,0,0,0,0,0,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VCCIO1_VCC_1\': + PIN_NUMBER='(0,1F3,0,0,0,0,0,0,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VCCIO1_VCC_0\': + PIN_NUMBER='(0,1E3,0,0,0,0,0,0,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\DSMC_SLV_RDYN | RM_IO31 | UART5_RX_M1 | -- | -- | FLEXBUS0_D0 | DSMC_CSN3 | VO_LCDC_D0 | GPIO1_D3_D\': + PIN_NUMBER='(0,G3,0,0,0,0,0,0,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\DSMC_SLV_INT | -- | -- | -- | DSMC_INT0 | FLEXBUS1_D1 | DSMC_CLKN | VO_LCDC_VSYNC | GPIO1_A1_D\': + PIN_NUMBER='(0,1A5,0,0,0,0,0,0,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\DSMC_SLV_DQS0 | -- | SAI2_MCLK_M1 | FLEXBUS1_CSN_M4 | DSM_AUD_RN_M0 | FLEXBUS0_CLK | DSMC_D8 | VO_LCDC_D10 | GPIO1_C1_D\': + PIN_NUMBER='(0,B2,0,0,0,0,0,0,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\DSMC_SLV_D7 | RM_IO29 | UART5_RTSN_M1 | -- | DSM_AUD_LP_M0 | FLEXBUS0_D2 | DSMC_DQS1 | VO_LCDC_D2 | GPIO1_D1_D\': + PIN_NUMBER='(0,F3,0,0,0,0,0,0,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\DSMC_SLV_D6 | -- | -- | -- | DSM_AUD_LN_M0 | FLEXBUS0_D3 | DSMC_D15 | VO_LCDC_D3 | GPIO1_D0_D\': + PIN_NUMBER='(0,E1,0,0,0,0,0,0,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\DSMC_SLV_D5 | -- | -- | -- | -- | FLEXBUS0_D4 | DSMC_D14 | VO_LCDC_D4 | GPIO1_C7_D\': + PIN_NUMBER='(0,E2,0,0,0,0,0,0,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\DSMC_SLV_D4 | -- | -- | -- | -- | FLEXBUS0_D5 | DSMC_D13 | VO_LCDC_D5 | GPIO1_C6_D\': + PIN_NUMBER='(0,E3,0,0,0,0,0,0,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\DSMC_SLV_D3 | -- | -- | -- | -- | FLEXBUS0_D6 | DSMC_D12 | VO_LCDC_D6 | GPIO1_C5_D\': + PIN_NUMBER='(0,D3,0,0,0,0,0,0,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\DSMC_SLV_D2 | -- | -- | -- | -- | FLEXBUS0_D7 | DSMC_D11 | VO_LCDC_D7 | GPIO1_C4_D\': + PIN_NUMBER='(0,C1,0,0,0,0,0,0,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\DSMC_SLV_D1 | RM_IO28 | SAI2_SDO_M1 | FLEXBUS1_CSN_M5 | -- | FLEXBUS0_D8 | DSMC_D10 | VO_LCDC_D8 | GPIO1_C3_D\': + PIN_NUMBER='(0,C2,0,0,0,0,0,0,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\DSMC_SLV_D0 | RM_IO27 | SAI2_SDI_M1 | FLEXBUS0_CSN_M5 | DSM_AUD_RP_M0 | FLEXBUS0_D9 | DSMC_D9 | VO_LCDC_D9 | GPIO1_C2_D\': + PIN_NUMBER='(0,B1,0,0,0,0,0,0,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\DSMC_SLV_CSN0 | RM_IO30 | UART5_TX_M1 | -- | -- | FLEXBUS0_D1 | DSMC_CSN2 | VO_LCDC_D1 | GPIO1_D2_D\': + PIN_NUMBER='(0,F2,0,0,0,0,0,0,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\DSMC_SLV_CLK | -- | -- | FLEXBUS0_CSN_M4 | DSMC_INT1 | FLEXBUS1_CLK | DSMC_RESETN | VO_LCDC_D11 | GPIO1_C0_D\': + PIN_NUMBER='(0,A2,0,0,0,0,0,0,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\-- | RM_IO26 | SAI2_LRCK_M1 | FLEXBUS1_CSN_M1 | FLEXBUS0_D14 | FLEXBUS1_D11 | DSMC_INT3 | VO_LCDC_D16 | GPIO1_B3_D\': + PIN_NUMBER='(0,B5,0,0,0,0,0,0,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\-- | RM_IO25 | SAI2_SCLK_M1 | FLEXBUS0_CSN_M1 | FLEXBUS0_D15 | FLEXBUS1_D10 | DSMC_INT2 | VO_LCDC_D17 | GPIO1_B2_D\': + PIN_NUMBER='(0,A5,0,0,0,0,0,0,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\-- | RM_IO24 | UART5_CTSN_M1 | FLEXBUS1_CSN_M0 | -- | FLEXBUS1_D9 | DSMC_CSN1 | VO_LCDC_D18 | GPIO1_B1_D\': + PIN_NUMBER='(0,1A2,0,0,0,0,0,0,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\-- | -- | -- | FLEXBUS1_CSN_M3 | FLEXBUS0_D10 | FLEXBUS1_D15 | DSMC_RDYN | VO_LCDC_D12 | GPIO1_B7_D\': + PIN_NUMBER='(0,B3,0,0,0,0,0,0,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\-- | -- | -- | FLEXBUS1_CSN_M2 | FLEXBUS0_D12 | FLEXBUS1_D13 | DSMC_D7 | VO_LCDC_D14 | GPIO1_B5_D\': + PIN_NUMBER='(0,C3,0,0,0,0,0,0,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\-- | -- | -- | FLEXBUS0_CSN_M3 | FLEXBUS0_D11 | FLEXBUS1_D14 | DSMC_CSN0 | VO_LCDC_D13 | GPIO1_B6_D\': + PIN_NUMBER='(0,A3,0,0,0,0,0,0,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\-- | -- | -- | FLEXBUS0_CSN_M2 | FLEXBUS0_D13 | FLEXBUS1_D12 | DSMC_D6 | VO_LCDC_D15 | GPIO1_B4_D\': + PIN_NUMBER='(0,1A1,0,0,0,0,0,0,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\-- | -- | -- | FLEXBUS0_CSN_M0 | -- | FLEXBUS1_D8 | DSMC_D5 | VO_LCDC_D19 | GPIO1_B0_D\': + PIN_NUMBER='(0,1A3,0,0,0,0,0,0,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\-- | -- | -- | -- | -- | FLEXBUS1_D7 | DSMC_D4 | VO_LCDC_D20 | GPIO1_A7_D\': + PIN_NUMBER='(0,B7,0,0,0,0,0,0,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\-- | -- | -- | -- | -- | FLEXBUS1_D6 | DSMC_D3 | VO_LCDC_D21 | GPIO1_A6_D\': + PIN_NUMBER='(0,A7,0,0,0,0,0,0,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\-- | -- | -- | -- | -- | FLEXBUS1_D5 | DSMC_D2 | VO_LCDC_D22 | GPIO1_A5_D\': + PIN_NUMBER='(0,1A4,0,0,0,0,0,0,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\-- | -- | -- | -- | -- | FLEXBUS1_D4 | DSMC_D1 | VO_LCDC_D23 | GPIO1_A4_D\': + PIN_NUMBER='(0,B8,0,0,0,0,0,0,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\-- | -- | -- | -- | -- | FLEXBUS1_D3 | DSMC_D0 | VO_LCDC_CLK | GPIO1_A3_D\': + PIN_NUMBER='(0,B9,0,0,0,0,0,0,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\-- | -- | -- | -- | -- | FLEXBUS1_D2 | DSMC_DQS0 | VO_LCDC_HSYNC | GPIO1_A2_D\': + PIN_NUMBER='(0,A9,0,0,0,0,0,0,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\-- | -- | -- | -- | -- | FLEXBUS1_D0 | DSMC_CLKP | VO_LCDC_DEN | GPIO1_A0_D\': + PIN_NUMBER='(0,B10,0,0,0,0,0,0,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\SYS_PLL_AVDD1V8\': + PIN_NUMBER='(1H1,0,0,0,0,0,0,0,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\RM_IO9 | SPI1_MOSI | SAI1_SCLK | GPIO0_B1_D\': + PIN_NUMBER='(R1,0,0,0,0,0,0,0,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\RM_IO8 | SPI1_CLK | SAI1_MCLK | GPIO0_B0_D\': + PIN_NUMBER='(R2,0,0,0,0,0,0,0,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\RM_IO7 | SPI1_CSN1 | SAI0_SDI3 | GPIO0_A7_D\': + PIN_NUMBER='(T2,0,0,0,0,0,0,0,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\RM_IO6 | -- | SAI0_SDI2 | GPIO0_A6_D\': + PIN_NUMBER='(U3,0,0,0,0,0,0,0,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\RM_IO5 | -- | SAI0_SDI1 | GPIO0_A5_D\': + PIN_NUMBER='(U1,0,0,0,0,0,0,0,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\RM_IO4 | -- | SAI0_SDI0 | GPIO0_A4_D\': + PIN_NUMBER='(U2,0,0,0,0,0,0,0,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\RM_IO3 | -- | SAI0_SDO | GPIO0_A3_D\': + PIN_NUMBER='(V2,0,0,0,0,0,0,0,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\RM_IO23 | JTAG_TMS_M1 | UART0_RX | GPIO0_C7_U\': + PIN_NUMBER='(J1,0,0,0,0,0,0,0,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\RM_IO22 | JTAG_TCK_M1 | UART0_TX | GPIO0_C6_U\': + PIN_NUMBER='(J2,0,0,0,0,0,0,0,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\RM_IO21 | -- | CPU_AVS | GPIO0_C5_Z\': + PIN_NUMBER='(K3,0,0,0,0,0,0,0,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\RM_IO20 | AUPLL_CLK_IN | ETH_CLK0_25M_OUT | GPIO0_C4_D\': + PIN_NUMBER='(K2,0,0,0,0,0,0,0,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\RM_IO2 | -- | SAI0_MCLK | GPIO0_A2_U\': + PIN_NUMBER='(W2,0,0,0,0,0,0,0,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\RM_IO19 | SPI0_CSN0 | ETH_CLK1_25M_OUT | GPIO0_C3_D\': + PIN_NUMBER='(L2,0,0,0,0,0,0,0,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\RM_IO18 | SPI0_MISO | REF_CLK1_OUT | GPIO0_C2_D\': + PIN_NUMBER='(L1,0,0,0,0,0,0,0,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\RM_IO17 | SPI0_MOSI | -- | GPIO0_C1_D\': + PIN_NUMBER='(M3,0,0,0,0,0,0,0,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\RM_IO16 | SPI0_CLK | -- | GPIO0_C0_D\': + PIN_NUMBER='(M2,0,0,0,0,0,0,0,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\RM_IO15 | SPI0_CSN1 | SAI1_SDO3 | GPIO0_B7_D\': + PIN_NUMBER='(N2,0,0,0,0,0,0,0,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\RM_IO14 | SPI1_CSN0 | SAI1_SDO2 | GPIO0_B6_D\': + PIN_NUMBER='(N3,0,0,0,0,0,0,0,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\RM_IO13 | -- | SAI1_SDO1 | GPIO0_B5_D\': + PIN_NUMBER='(N1,0,0,0,0,0,0,0,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\RM_IO12 | -- | SAI1_SDO0 | GPIO0_B4_D\': + PIN_NUMBER='(P3,0,0,0,0,0,0,0,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\RM_IO11 | -- | SAI1_SDI | GPIO0_B3_D\': + PIN_NUMBER='(P2,0,0,0,0,0,0,0,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\RM_IO10 | SPI1_MISO | SAI1_LRCK | GPIO0_B2_D\': + PIN_NUMBER='(R3,0,0,0,0,0,0,0,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\RM_IO1 | -- | SAI0_SCLK | GPIO0_A1_D\': + PIN_NUMBER='(W1,0,0,0,0,0,0,0,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\RM_IO0 | -- | SAI0_LRCK | GPIO0_A0_U\': + PIN_NUMBER='(V3,0,0,0,0,0,0,0,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\RFU\': + PIN_NUMBER='(1G2,0,0,0,0,0,0,0,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\REF_CLK0_OUT | OSC_CLK_OUT | GPIO0_D0_D\': + PIN_NUMBER='(G1,0,0,0,0,0,0,0,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\PMU_LOGIC_DVDD0V9\': + PIN_NUMBER='(1K2,0,0,0,0,0,0,0,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\PMUIO_VCC3V3\': + PIN_NUMBER='(1L1,0,0,0,0,0,0,0,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\OSC_XOUT\': + PIN_NUMBER='(H2,0,0,0,0,0,0,0,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\OSC_XIN\': + PIN_NUMBER='(H3,0,0,0,0,0,0,0,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\NPOR\': + PIN_NUMBER='(T3,0,0,0,0,0,0,0,0,0)'; + PIN_GROUP='1'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + end_pin; + body + PART_NAME='SOC_RK3506B'; + VALUE='SOC_RK3506B'; + BODY_NAME='SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B'; + JEDEC_TYPE='BGA333_13R30X11R30X1R25'; + PHYS_DES_PREFIX='U'; + CLASS='IC'; + end_body; +end_primitive; + +primitive 'LAN8720A-CP-ABC_QFN24-6X6_MC_MCH_LAN8720A-CP-ABC'; + pin + '\VDDIO\': + PIN_NUMBER='(0,9)'; + PINUSE='POWER'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VDDCR\': + PIN_NUMBER='(0,6)'; + PINUSE='POWER'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VDD2A\': + PIN_NUMBER='(0,1)'; + PINUSE='POWER'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VDD1A\': + PIN_NUMBER='(0,19)'; + PINUSE='POWER'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\XTAL2\': + PIN_NUMBER='(4,0)'; + OUTPUT_LOAD='(1.0,-1.0)'; + '\XTAL1/CLKIN\': + PIN_NUMBER='(5,0)'; + INPUT_LOAD='(-0.01,0.01)'; + '\TXP\': + PIN_NUMBER='(21,0)'; + BIDIRECTIONAL='TRUE'; + INPUT_LOAD='(-0.01,0.01)'; + OUTPUT_LOAD='(1.0,-1.0)'; + '\TXN\': + PIN_NUMBER='(20,0)'; + BIDIRECTIONAL='TRUE'; + INPUT_LOAD='(-0.01,0.01)'; + OUTPUT_LOAD='(1.0,-1.0)'; + '\TXEN\': + PIN_NUMBER='(16,0)'; + INPUT_LOAD='(-0.01,0.01)'; + '\TXD1\': + PIN_NUMBER='(18,0)'; + INPUT_LOAD='(-0.01,0.01)'; + '\TXD0\': + PIN_NUMBER='(17,0)'; + INPUT_LOAD='(-0.01,0.01)'; + '\RXP\': + PIN_NUMBER='(23,0)'; + BIDIRECTIONAL='TRUE'; + INPUT_LOAD='(-0.01,0.01)'; + OUTPUT_LOAD='(1.0,-1.0)'; + '\RXN\': + PIN_NUMBER='(22,0)'; + BIDIRECTIONAL='TRUE'; + INPUT_LOAD='(-0.01,0.01)'; + OUTPUT_LOAD='(1.0,-1.0)'; + '\RXER/*PHYAD0\': + PIN_NUMBER='(10,0)'; + BIDIRECTIONAL='TRUE'; + INPUT_LOAD='(-0.01,0.01)'; + OUTPUT_LOAD='(1.0,-1.0)'; + '\RXD1/*MODE1\': + PIN_NUMBER='(7,0)'; + BIDIRECTIONAL='TRUE'; + INPUT_LOAD='(-0.01,0.01)'; + OUTPUT_LOAD='(1.0,-1.0)'; + '\RXD0/*MODE0\': + PIN_NUMBER='(8,0)'; + BIDIRECTIONAL='TRUE'; + INPUT_LOAD='(-0.01,0.01)'; + OUTPUT_LOAD='(1.0,-1.0)'; + '\RBIAS\': + PIN_NUMBER='(24,0)'; + INPUT_LOAD='(-0.01,0.01)'; + '\NRST\': + PIN_NUMBER='(15,0)'; + INPUT_LOAD='(-0.01,0.01)'; + '\NINT/REFCLKO\': + PIN_NUMBER='(14,0)'; + OUTPUT_LOAD='(1.0,-1.0)'; + '\MDIO\': + PIN_NUMBER='(12,0)'; + BIDIRECTIONAL='TRUE'; + INPUT_LOAD='(-0.01,0.01)'; + OUTPUT_LOAD='(1.0,-1.0)'; + '\MDC\': + PIN_NUMBER='(13,0)'; + INPUT_LOAD='(-0.01,0.01)'; + '\LED2/*NINTSEL\': + PIN_NUMBER='(2,0)'; + BIDIRECTIONAL='TRUE'; + INPUT_LOAD='(-0.01,0.01)'; + OUTPUT_LOAD='(1.0,-1.0)'; + '\LED1/*REGOFF\': + PIN_NUMBER='(3,0)'; + BIDIRECTIONAL='TRUE'; + INPUT_LOAD='(-0.01,0.01)'; + OUTPUT_LOAD='(1.0,-1.0)'; + '\EPAD\': + PIN_NUMBER='(25,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\CRS_DV/*MODE2\': + PIN_NUMBER='(11,0)'; + BIDIRECTIONAL='TRUE'; + INPUT_LOAD='(-0.01,0.01)'; + OUTPUT_LOAD='(1.0,-1.0)'; + end_pin; + body + PART_NAME='LAN8720A-CP-ABC'; + VALUE='LAN8720A-CP-ABC'; + BODY_NAME='LAN8720A-CP-ABC_QFN24-6X6_MC_MCH_LAN8720A-CP-ABC'; + JEDEC_TYPE='QFN24-6X6_MC_MCH'; + PHYS_DES_PREFIX='U'; + CLASS='IC'; + end_body; +end_primitive; + +primitive 'TLV62569DBVR_DBV0005A_N_TLV62569DBV'; + pin + '\VIN\': + PIN_NUMBER='(4)'; + PINUSE='POWER'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\SW\': + PIN_NUMBER='(3)'; + PINUSE='POWER'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\GND\': + PIN_NUMBER='(2)'; + PINUSE='POWER'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\FB\': + PIN_NUMBER='(5)'; + INPUT_LOAD='(-0.01,0.01)'; + '\EN\': + PIN_NUMBER='(1)'; + INPUT_LOAD='(-0.01,0.01)'; + end_pin; + body + PART_NAME='TLV62569DBVR'; + VALUE='TLV62569DBV'; + BODY_NAME='TLV62569DBVR_DBV0005A_N_TLV62569DBV'; + JEDEC_TYPE='DBV0005A_N'; + PHYS_DES_PREFIX='U'; + CLASS='IC'; + end_body; +end_primitive; + +primitive 'K922_K922_K922'; + pin + '\RSV9\': + PIN_NUMBER='(0,0,0,0,39)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\RSV8\': + PIN_NUMBER='(0,0,0,0,38)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\RSV7\': + PIN_NUMBER='(0,0,0,0,29)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\RSV6\': + PIN_NUMBER='(0,0,0,0,26)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\RSV5\': + PIN_NUMBER='(0,0,0,0,25)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\RSV4\': + PIN_NUMBER='(0,0,0,0,13)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\RSV3\': + PIN_NUMBER='(0,0,0,0,12)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\RSV2\': + PIN_NUMBER='(0,0,0,0,11)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\RSV1\': + PIN_NUMBER='(0,0,0,0,10)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\RSV16\': + PIN_NUMBER='(0,0,0,0,31)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\RSV15\': + PIN_NUMBER='(0,0,0,0,48)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\RSV14\': + PIN_NUMBER='(0,0,0,0,47)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\RSV13\': + PIN_NUMBER='(0,0,0,0,46)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\RSV12\': + PIN_NUMBER='(0,0,0,0,44)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\RSV11\': + PIN_NUMBER='(0,0,0,0,42)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\RSV10\': + PIN_NUMBER='(0,0,0,0,40)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\EP9\': + PIN_NUMBER='(0,0,0,0,57)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\EP8\': + PIN_NUMBER='(0,0,0,0,56)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\EP7\': + PIN_NUMBER='(0,0,0,0,55)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\EP6\': + PIN_NUMBER='(0,0,0,0,54)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\EP5\': + PIN_NUMBER='(0,0,0,0,53)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\EP4\': + PIN_NUMBER='(0,0,0,0,52)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\EP3\': + PIN_NUMBER='(0,0,0,0,51)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\EP35\': + PIN_NUMBER='(0,0,0,0,83)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\EP34\': + PIN_NUMBER='(0,0,0,0,82)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\EP33\': + PIN_NUMBER='(0,0,0,0,81)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\EP32\': + PIN_NUMBER='(0,0,0,0,80)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\EP31\': + PIN_NUMBER='(0,0,0,0,79)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\EP30\': + PIN_NUMBER='(0,0,0,0,78)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\EP2\': + PIN_NUMBER='(0,0,0,0,50)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\EP29\': + PIN_NUMBER='(0,0,0,0,77)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\EP28\': + PIN_NUMBER='(0,0,0,0,76)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\EP27\': + PIN_NUMBER='(0,0,0,0,75)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\EP26\': + PIN_NUMBER='(0,0,0,0,74)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\EP25\': + PIN_NUMBER='(0,0,0,0,73)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\EP24\': + PIN_NUMBER='(0,0,0,0,72)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\EP23\': + PIN_NUMBER='(0,0,0,0,71)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\EP22\': + PIN_NUMBER='(0,0,0,0,70)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\EP21\': + PIN_NUMBER='(0,0,0,0,69)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\EP20\': + PIN_NUMBER='(0,0,0,0,68)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\EP1\': + PIN_NUMBER='(0,0,0,0,49)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\EP19\': + PIN_NUMBER='(0,0,0,0,67)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\EP18\': + PIN_NUMBER='(0,0,0,0,66)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\EP17\': + PIN_NUMBER='(0,0,0,0,65)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\EP16\': + PIN_NUMBER='(0,0,0,0,64)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\EP15\': + PIN_NUMBER='(0,0,0,0,63)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\EP14\': + PIN_NUMBER='(0,0,0,0,62)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\EP13\': + PIN_NUMBER='(0,0,0,0,61)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\EP12\': + PIN_NUMBER='(0,0,0,0,60)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\EP11\': + PIN_NUMBER='(0,0,0,0,59)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\EP10\': + PIN_NUMBER='(0,0,0,0,58)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\ANT_IN_POS\': + PIN_NUMBER='(0,0,0,2,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\ANT_IN_HEAD\': + PIN_NUMBER='(0,0,0,36,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\SYS_RSTN\': + PIN_NUMBER='(0,0,33,0,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\RTK_STAT\': + PIN_NUMBER='(0,0,16,0,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\PVT_STAT\': + PIN_NUMBER='(0,0,15,0,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\PPS\': + PIN_NUMBER='(0,0,30,0,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\EVENT\': + PIN_NUMBER='(0,0,32,0,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\ERR_STAT\': + PIN_NUMBER='(0,0,14,0,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\SPI_MOSI\': + PIN_NUMBER='(0,7,0,0,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\SPI_MISO\': + PIN_NUMBER='(0,9,0,0,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\SPI_CS\': + PIN_NUMBER='(0,6,0,0,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\SPI_CLK\': + PIN_NUMBER='(0,8,0,0,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\I2C_SDA\': + PIN_NUMBER='(0,22,0,0,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\I2C_SCL\': + PIN_NUMBER='(0,21,0,0,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\COM3_TXD/CAN_TXD\': + PIN_NUMBER='(0,27,0,0,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\COM3_RXD/CAN_RXD\': + PIN_NUMBER='(0,28,0,0,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\COM2_TXD\': + PIN_NUMBER='(0,20,0,0,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\COM2_RXD\': + PIN_NUMBER='(0,19,0,0,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\COM1_TXD\': + PIN_NUMBER='(0,18,0,0,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\COM1_RXD\': + PIN_NUMBER='(0,17,0,0,0)'; + PINUSE='UNSPEC'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\V_BCKP\': + PIN_NUMBER='(5,0,0,0,0)'; + PINUSE='POWER'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VCC#24\': + PIN_NUMBER='(24,0,0,0,0)'; + PINUSE='POWER'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\VCC#23\': + PIN_NUMBER='(23,0,0,0,0)'; + PINUSE='POWER'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\GND#4\': + PIN_NUMBER='(4,0,0,0,0)'; + PINUSE='POWER'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\GND#45\': + PIN_NUMBER='(45,0,0,0,0)'; + PINUSE='POWER'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\GND#43\': + PIN_NUMBER='(43,0,0,0,0)'; + PINUSE='POWER'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\GND#41\': + PIN_NUMBER='(41,0,0,0,0)'; + PINUSE='POWER'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\GND#3\': + PIN_NUMBER='(3,0,0,0,0)'; + PINUSE='POWER'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\GND#37\': + PIN_NUMBER='(37,0,0,0,0)'; + PINUSE='POWER'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\GND#35\': + PIN_NUMBER='(35,0,0,0,0)'; + PINUSE='POWER'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\GND#34\': + PIN_NUMBER='(34,0,0,0,0)'; + PINUSE='POWER'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\GND#1\': + PIN_NUMBER='(1,0,0,0,0)'; + PINUSE='POWER'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + end_pin; + body + PART_NAME='K922'; + VALUE='K922'; + BODY_NAME='K922_K922_K922'; + JEDEC_TYPE='K922'; + PHYS_DES_PREFIX='U'; + CLASS='IC'; + end_body; +end_primitive; + +primitive 'CRYSTAL 1-3_4PIN_XTAL3225_CRYSTAL 1-3_4PIN'; + pin + '\X3\': + PIN_NUMBER='(3)'; + PINUSE='POWER'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\X1\': + PIN_NUMBER='(1)'; + PINUSE='POWER'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\GND#4\': + PIN_NUMBER='(4)'; + PINUSE='POWER'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + '\GND#2\': + PIN_NUMBER='(2)'; + PINUSE='POWER'; + NO_LOAD_CHECK='Both'; + NO_IO_CHECK='Both'; + NO_ASSERT_CHECK='TRUE'; + NO_DIR_CHECK='TRUE'; + ALLOW_CONNECT='TRUE'; + end_pin; + body + PART_NAME='CRYSTAL 1-3_4Pin'; + VALUE='CRYSTAL 1-3_4Pin'; + BODY_NAME='CRYSTAL 1-3_4PIN_XTAL3225_CRYSTAL 1-3_4PIN'; + JEDEC_TYPE='XTAL3225'; + PHYS_DES_PREFIX='X'; + CLASS='IC'; + end_body; +end_primitive; + +END. \ No newline at end of file diff --git a/allegro/cmbcview.dat b/allegro/cmbcview.dat new file mode 100644 index 0000000..2db830e Binary files /dev/null and b/allegro/cmbcview.dat differ diff --git a/allegro/cmdbview.dat b/allegro/cmdbview.dat new file mode 100644 index 0000000..6df964b Binary files /dev/null and b/allegro/cmdbview.dat differ diff --git a/allegro/compview.dat b/allegro/compview.dat new file mode 100644 index 0000000..2b4cc1c --- /dev/null +++ b/allegro/compview.dat @@ -0,0 +1,24 @@ +A!REFDES!COMP_REUSE_ID!COMP_SIGNAL_MODEL!COMP_NO_XNET_CONNECTION!COMP_PARENT_PPT!COMP_SYMBOL_EDITED!COMP_PARENT_PPT_PART!COMP_EMBEDDED_PLACEMENT!COMP_RKO_NUM_LAYERS!COMP_RKO_SHORT_SIDE_OVERSIZE!COMP_RKO_LONG_SIDE_OVERSIZE!COMP_RKO_REF_LAYER!COMP_ASI_MODEL! +J!w:/rk3506_nav/rk3506_nav.brd!Thu Aug 13 02:28:08 2026!-0.9400!-0.9400!6.6800!6.6800!0.0001!millimeters!RK3506_NAV!10.400000 mil!2!UP TO DATE! +S!C1!!!!!!!!!!!!! +S!C2!!!!!!!!!!!!! +S!C10!!!!!!!!!!!!! +S!C9!!!!!!!!!!!!! +S!C3!!!!!!!!!!!!! +S!C4!!!!!!!!!!!!! +S!C5!!!!!!!!!!!!! +S!C6!!!!!!!!!!!!! +S!C7!!!!!!!!!!!!! +S!C8!!!!!!!!!!!!! +S!J1!!!!!!!!!!!!! +S!R1!!!!!!!!!!!!! +S!U1!!!!!!!!!!!!! +S!U2!!!!!!!!!!!!! +S!U3!!!!!!!!!!!!! +S!U4!!!!!!!!!!!!! +S!U5!!!!!!!!!!!!! +S!U6!!!!!!!!!!!!! +S!U7!!!!!!!!!!!!! +S!U8!!!!!!!!!!!!! +S!U9!!!!!!!!!!!!! +S!X1!!!!!!!!!!!!! diff --git a/allegro/feedbackview.cdsz b/allegro/feedbackview.cdsz new file mode 100644 index 0000000..d972b46 Binary files /dev/null and b/allegro/feedbackview.cdsz differ diff --git a/allegro/funcView.dat b/allegro/funcView.dat new file mode 100644 index 0000000..2fed905 --- /dev/null +++ b/allegro/funcView.dat @@ -0,0 +1,39 @@ +A!FUNC_LOGICAL_PATH!COMP_DEVICE_TYPE!REFDES!FUNC_PRIM_FILE!COMP_PARENT_PPT!COMP_PARENT_PPT_PART!COMP_PARENT_PART_TYPE!FUNC_SCH_SIZE!FUNC_HAS_FIXED_SIZE!FUNC_DES!FUNC_GROUP!FUNC_ROOM!FUNC_TERM_IDENT!FUNC_CDS_FSP_INSTANCE_ID!FUNC_CDS_FSP_IS_FPGA!FUNC_CDS_FSP_UID! +J!w:/rk3506_nav/rk3506_nav.brd!Thu Aug 13 02:28:08 2026!-0.9400!-0.9400!6.6800!6.6800!0.0001!millimeters!RK3506_NAV!10.400000 mil!2!UP TO DATE! +S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS19387\@\DISCRETE\.\CAP NP.Normal\(chips)!CAP NP_C0402_DISCRETE_18PF!C1!.\chipsView.dat!!!!!!F23!!!!!!! +S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS19709\@\DISCRETE\.\CAP NP.Normal\(chips)!CAP NP_C0402_DISCRETE_18PF!C2!.\chipsView.dat!!!!!!F22!!!!!!! +S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS41270\@\QF_DISCRETE\.\CAP NP.Normal\(chips)!CAP NP_C0402_BGA_DISCRETE_10UF!C10!.\chipsView.dat!!!!!!F21!!!!!!! +S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS40428\@\QF_DISCRETE\.\CAP NP.Normal\(chips)!CAP NP_C0402_BGA_DISCRETE_10UF!C9!.\chipsView.dat!!!!!!F20!!!!!!! +S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS19878\@\DISCRETE\.\CAP NP.Normal\(chips)!CAP NP_C0402_DISCRETE_100NF!C3!.\chipsView.dat!!!!!!F19!!!!!!! +S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS35873\@\QF_DISCRETE\.\CAP NP.Normal\(chips)!CAP NP_C0402_DISCRETE_100NF!C4!.\chipsView.dat!!!!!!F18!!!!!!! +S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS35933\@\QF_DISCRETE\.\CAP NP.Normal\(chips)!CAP NP_C0402_DISCRETE_10UF!C5!.\chipsView.dat!!!!!!F17!!!!!!! +S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS35977\@\QF_DISCRETE\.\CAP NP.Normal\(chips)!CAP NP_C0603_DISCRETE_22UF!C6!.\chipsView.dat!!!!!!F16!!!!!!! +S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS40356\@\QF_DISCRETE\.\CAP NP.Normal\(chips)!CAP NP_C0402_BGA_DISCRETE_100NF!C7!.\chipsView.dat!!!!!!F15!!!!!!! +S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS40392\@\QF_DISCRETE\.\CAP NP.Normal\(chips)!CAP NP_C0402_BGA_DISCRETE_100NF!C8!.\chipsView.dat!!!!!!F14!!!!!!! +S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS33975\@\B2BCONNECTOR\.\LSHM-140-030-L-DV-A-N-TR.Normal\(chips)!LSHM-140-030-L-DV-A-N-TR_SAMTEC_LSHM-140-030-L-DV-A-N-TR_LSHM-140-030-L-DV-A-N-TR!J1!.\chipsView.dat!!!!!!TF-27!!!!!!! +S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS19332\@\DISCRETE\.\R.Normal\(chips)!R_R0402_DISCRETE_1M!R1!.\chipsView.dat!!!!!!F13!!!!!!! +S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS13961\@\LIBRARY\.\SOC_RK3506BA.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!U1!.\chipsView.dat!!!!!!F12!!!!!!! +S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS16006\@\LIBRARY\.\SOC_RK3506BB.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!U1!.\chipsView.dat!!!!!!TF-24!!!!!!! +S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS16199\@\LIBRARY\.\SOC_RK3506BC.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!U1!.\chipsView.dat!!!!!!TF-23!!!!!!! +S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS15385\@\LIBRARY\.\SOC_RK3506BD.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!U1!.\chipsView.dat!!!!!!TF-22!!!!!!! +S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS15310\@\LIBRARY\.\SOC_RK3506BE.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!U1!.\chipsView.dat!!!!!!TF-21!!!!!!! +S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS15781\@\LIBRARY\.\SOC_RK3506BF.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!U1!.\chipsView.dat!!!!!!TF-20!!!!!!! +S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS15156\@\LIBRARY\.\SOC_RK3506BG.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!U1!.\chipsView.dat!!!!!!F11!!!!!!! +S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS15564\@\LIBRARY\.\SOC_RK3506BH.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!U1!.\chipsView.dat!!!!!!TF-18!!!!!!! +S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS14255\@\LIBRARY\.\SOC_RK3506BI.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!U1!.\chipsView.dat!!!!!!F10!!!!!!! +S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS14712\@\LIBRARY\.\SOC_RK3506BJ.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!U1!.\chipsView.dat!!!!!!F9!!!!!!! +S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS20987\@d.s(v)!LAN8720A-CP-ABC_QFN24-6X6_MC_MCH_LAN8720A-CP-ABC!U2!.\chipsView.dat!!!!!!TF-15!!!!!!! +S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS21054\@d.s(v)!LAN8720A-CP-ABC_QFN24-6X6_MC_MCH_LAN8720A-CP-ABC!U2!.\chipsView.dat!!!!!!F8!!!!!!! +S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS21176\@d.s(v)!LAN8720A-CP-ABC_QFN24-6X6_MC_MCH_LAN8720A-CP-ABC!U3!.\chipsView.dat!!!!!!TF-13!!!!!!! +S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS21243\@d.s(v)!LAN8720A-CP-ABC_QFN24-6X6_MC_MCH_LAN8720A-CP-ABC!U3!.\chipsView.dat!!!!!!F7!!!!!!! +S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS22426\@d.s(v)!TLV62569DBVR_DBV0005A_N_TLV62569DBV!U4!.\chipsView.dat!!!!!!F6!!!!!!! +S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS22454\@d.s(v)!TLV62569DBVR_DBV0005A_N_TLV62569DBV!U5!.\chipsView.dat!!!!!!F5!!!!!!! +S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS22482\@d.s(v)!TLV62569DBVR_DBV0005A_N_TLV62569DBV!U6!.\chipsView.dat!!!!!!F4!!!!!!! +S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS22510\@d.s(v)!TLV62569DBVR_DBV0005A_N_TLV62569DBV!U7!.\chipsView.dat!!!!!!F3!!!!!!! +S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS22538\@d.s(v)!TLV62569DBVR_DBV0005A_N_TLV62569DBV!U8!.\chipsView.dat!!!!!!F2!!!!!!! +S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS52680\@\QF_IC\.\K922A.Normal\(chips)!K922_K922_K922!U9!.\chipsView.dat!!!!!!F1!!!!!!! +S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS52780\@\QF_IC\.\K922B.Normal\(chips)!K922_K922_K922!U9!.\chipsView.dat!!!!!!TF-5!!!!!!! +S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS52850\@\QF_IC\.\K922C.Normal\(chips)!K922_K922_K922!U9!.\chipsView.dat!!!!!!TF-4!!!!!!! +S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS52892\@\QF_IC\.\K922D.Normal\(chips)!K922_K922_K922!U9!.\chipsView.dat!!!!!!TF-3!!!!!!! +S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS53122\@\QF_IC\.\K922E.Normal\(chips)!K922_K922_K922!U9!.\chipsView.dat!!!!!!TF-2!!!!!!! +S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS19052\@\OTHER\.\CRYSTAL 1-3_4Pin.Normal\(chips)!CRYSTAL 1-3_4PIN_XTAL3225_CRYSTAL 1-3_4PIN!X1!.\chipsView.dat!!!!!!F0!!!!!!! diff --git a/allegro/netview.dat b/allegro/netview.dat new file mode 100644 index 0000000..2afba59 --- /dev/null +++ b/allegro/netview.dat @@ -0,0 +1,16 @@ +A!NET_NAME!NET_LOGICAL_PATH!NET_VOLTAGE! +J!w:/rk3506_nav/rk3506_nav.brd!Thu Aug 13 02:28:08 2026!-0.9400!-0.9400!6.6800!6.6800!0.0001!millimeters!RK3506_NAV!10.400000 mil!2!UP TO DATE! +S!VIN!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\VIN\!1.5V! +S!SW!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\SW\!1.5V! +S!VDDCR!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\VDDCR\!1.5V! +S!VDD2A!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\VDD2A\!1.5V! +S!VDDIO!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\VDDIO\!3.3! +S!VDD1A!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\VDD1A\!3.3V! +S!VCC!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\VCC\!3.3V! +S!V_BCKP!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\V_BCKP\!3.3V! +S!VCC_1V8!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\VCC_1V8\!1.5V! +S!VDD_0V9!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\VDD_0V9\!0.9V! +S!N19203!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\N19203\!1.5V! +S!N19188!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\N19188\!1.5V! +S!VDD_CPU!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\VDD_CPU\!0.95V! +S!GND!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\GND\!0.0V! diff --git a/allegro/pinview.dat b/allegro/pinview.dat new file mode 100644 index 0000000..dd3c9fe --- /dev/null +++ b/allegro/pinview.dat @@ -0,0 +1,599 @@ +A!NET_NAME!REFDES!PIN_NUMBER!FUNC_LOGICAL_PATH!COMP_DEVICE_TYPE!FUNC_SCH_SIZE!FUNC_HAS_FIXED_SIZE!FUNC_DES!PIN_CDS_PINID!PIN_TERMINATION!PIN_TERM_IDENT!PIN_NET_SHORT!PIN_XNET_PINS!PIN_RKO_NUM_LAYERS!PIN_RKO_SHORT_SIDE_OVERSIZE!PIN_RKO_LONG_SIDE_OVERSIZE! +J!w:/rk3506_nav/rk3506_nav.brd!Thu Aug 13 02:28:08 2026!-0.9400!-0.9400!6.6800!6.6800!0.0001!millimeters!RK3506_NAV!10.400000 mil!2!UP TO DATE! +S!N19188!C1!1!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS19387\@\DISCRETE\.\CAP NP.Normal\(chips)!CAP NP_C0402_DISCRETE_18PF!!!F23!\1\!!!!!!!! +S!GND!C1!2!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS19387\@\DISCRETE\.\CAP NP.Normal\(chips)!CAP NP_C0402_DISCRETE_18PF!!!F23!\2\!!!!!!!! +S!N19203!C2!1!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS19709\@\DISCRETE\.\CAP NP.Normal\(chips)!CAP NP_C0402_DISCRETE_18PF!!!F22!\1\!!!!!!!! +S!GND!C2!2!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS19709\@\DISCRETE\.\CAP NP.Normal\(chips)!CAP NP_C0402_DISCRETE_18PF!!!F22!\2\!!!!!!!! +S!VDD_0V9!C10!1!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS41270\@\QF_DISCRETE\.\CAP NP.Normal\(chips)!CAP NP_C0402_BGA_DISCRETE_10UF!!!F21!\1\!!!!!!!! +S!GND!C10!2!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS41270\@\QF_DISCRETE\.\CAP NP.Normal\(chips)!CAP NP_C0402_BGA_DISCRETE_10UF!!!F21!\2\!!!!!!!! +S!VDD_0V9!C9!1!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS40428\@\QF_DISCRETE\.\CAP NP.Normal\(chips)!CAP NP_C0402_BGA_DISCRETE_10UF!!!F20!\1\!!!!!!!! +S!GND!C9!2!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS40428\@\QF_DISCRETE\.\CAP NP.Normal\(chips)!CAP NP_C0402_BGA_DISCRETE_10UF!!!F20!\2\!!!!!!!! +S!VCC_1V8!C3!1!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS19878\@\DISCRETE\.\CAP NP.Normal\(chips)!CAP NP_C0402_DISCRETE_100NF!!!F19!\1\!!!!!!!! +S!GND!C3!2!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS19878\@\DISCRETE\.\CAP NP.Normal\(chips)!CAP NP_C0402_DISCRETE_100NF!!!F19!\2\!!!!!!!! +S!VDD_CPU!C4!1!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS35873\@\QF_DISCRETE\.\CAP NP.Normal\(chips)!CAP NP_C0402_DISCRETE_100NF!!!F18!\1\!!!!!!!! +S!GND!C4!2!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS35873\@\QF_DISCRETE\.\CAP NP.Normal\(chips)!CAP NP_C0402_DISCRETE_100NF!!!F18!\2\!!!!!!!! +S!VDD_CPU!C5!1!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS35933\@\QF_DISCRETE\.\CAP NP.Normal\(chips)!CAP NP_C0402_DISCRETE_10UF!!!F17!\1\!!!!!!!! +S!GND!C5!2!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS35933\@\QF_DISCRETE\.\CAP NP.Normal\(chips)!CAP NP_C0402_DISCRETE_10UF!!!F17!\2\!!!!!!!! +S!VDD_CPU!C6!1!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS35977\@\QF_DISCRETE\.\CAP NP.Normal\(chips)!CAP NP_C0603_DISCRETE_22UF!!!F16!\1\!!!!!!!! +S!GND!C6!2!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS35977\@\QF_DISCRETE\.\CAP NP.Normal\(chips)!CAP NP_C0603_DISCRETE_22UF!!!F16!\2\!!!!!!!! +S!VDD_0V9!C7!1!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS40356\@\QF_DISCRETE\.\CAP NP.Normal\(chips)!CAP NP_C0402_BGA_DISCRETE_100NF!!!F15!\1\!!!!!!!! +S!GND!C7!2!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS40356\@\QF_DISCRETE\.\CAP NP.Normal\(chips)!CAP NP_C0402_BGA_DISCRETE_100NF!!!F15!\2\!!!!!!!! +S!VDD_0V9!C8!1!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS40392\@\QF_DISCRETE\.\CAP NP.Normal\(chips)!CAP NP_C0402_BGA_DISCRETE_100NF!!!F14!\1\!!!!!!!! +S!GND!C8!2!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS40392\@\QF_DISCRETE\.\CAP NP.Normal\(chips)!CAP NP_C0402_BGA_DISCRETE_100NF!!!F14!\2\!!!!!!!! +S!!J1!01!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS33975\@\B2BCONNECTOR\.\LSHM-140-030-L-DV-A-N-TR.Normal\(chips)!LSHM-140-030-L-DV-A-N-TR_SAMTEC_LSHM-140-030-L-DV-A-N-TR_LSHM-140-030-L-DV-A-N-TR!!!TF-27!\01\!!!!!!!! +S!!J1!02!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS33975\@\B2BCONNECTOR\.\LSHM-140-030-L-DV-A-N-TR.Normal\(chips)!LSHM-140-030-L-DV-A-N-TR_SAMTEC_LSHM-140-030-L-DV-A-N-TR_LSHM-140-030-L-DV-A-N-TR!!!TF-27!\02\!!!!!!!! +S!!J1!03!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS33975\@\B2BCONNECTOR\.\LSHM-140-030-L-DV-A-N-TR.Normal\(chips)!LSHM-140-030-L-DV-A-N-TR_SAMTEC_LSHM-140-030-L-DV-A-N-TR_LSHM-140-030-L-DV-A-N-TR!!!TF-27!\03\!!!!!!!! +S!!J1!04!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS33975\@\B2BCONNECTOR\.\LSHM-140-030-L-DV-A-N-TR.Normal\(chips)!LSHM-140-030-L-DV-A-N-TR_SAMTEC_LSHM-140-030-L-DV-A-N-TR_LSHM-140-030-L-DV-A-N-TR!!!TF-27!\04\!!!!!!!! +S!!J1!05!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS33975\@\B2BCONNECTOR\.\LSHM-140-030-L-DV-A-N-TR.Normal\(chips)!LSHM-140-030-L-DV-A-N-TR_SAMTEC_LSHM-140-030-L-DV-A-N-TR_LSHM-140-030-L-DV-A-N-TR!!!TF-27!\05\!!!!!!!! +S!!J1!06!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS33975\@\B2BCONNECTOR\.\LSHM-140-030-L-DV-A-N-TR.Normal\(chips)!LSHM-140-030-L-DV-A-N-TR_SAMTEC_LSHM-140-030-L-DV-A-N-TR_LSHM-140-030-L-DV-A-N-TR!!!TF-27!\06\!!!!!!!! +S!!J1!07!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS33975\@\B2BCONNECTOR\.\LSHM-140-030-L-DV-A-N-TR.Normal\(chips)!LSHM-140-030-L-DV-A-N-TR_SAMTEC_LSHM-140-030-L-DV-A-N-TR_LSHM-140-030-L-DV-A-N-TR!!!TF-27!\07\!!!!!!!! +S!!J1!08!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS33975\@\B2BCONNECTOR\.\LSHM-140-030-L-DV-A-N-TR.Normal\(chips)!LSHM-140-030-L-DV-A-N-TR_SAMTEC_LSHM-140-030-L-DV-A-N-TR_LSHM-140-030-L-DV-A-N-TR!!!TF-27!\08\!!!!!!!! +S!!J1!09!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS33975\@\B2BCONNECTOR\.\LSHM-140-030-L-DV-A-N-TR.Normal\(chips)!LSHM-140-030-L-DV-A-N-TR_SAMTEC_LSHM-140-030-L-DV-A-N-TR_LSHM-140-030-L-DV-A-N-TR!!!TF-27!\09\!!!!!!!! +S!!J1!10!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS33975\@\B2BCONNECTOR\.\LSHM-140-030-L-DV-A-N-TR.Normal\(chips)!LSHM-140-030-L-DV-A-N-TR_SAMTEC_LSHM-140-030-L-DV-A-N-TR_LSHM-140-030-L-DV-A-N-TR!!!TF-27!\10\!!!!!!!! +S!!J1!11!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS33975\@\B2BCONNECTOR\.\LSHM-140-030-L-DV-A-N-TR.Normal\(chips)!LSHM-140-030-L-DV-A-N-TR_SAMTEC_LSHM-140-030-L-DV-A-N-TR_LSHM-140-030-L-DV-A-N-TR!!!TF-27!\11\!!!!!!!! +S!!J1!12!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS33975\@\B2BCONNECTOR\.\LSHM-140-030-L-DV-A-N-TR.Normal\(chips)!LSHM-140-030-L-DV-A-N-TR_SAMTEC_LSHM-140-030-L-DV-A-N-TR_LSHM-140-030-L-DV-A-N-TR!!!TF-27!\12\!!!!!!!! +S!!J1!13!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS33975\@\B2BCONNECTOR\.\LSHM-140-030-L-DV-A-N-TR.Normal\(chips)!LSHM-140-030-L-DV-A-N-TR_SAMTEC_LSHM-140-030-L-DV-A-N-TR_LSHM-140-030-L-DV-A-N-TR!!!TF-27!\13\!!!!!!!! +S!!J1!14!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS33975\@\B2BCONNECTOR\.\LSHM-140-030-L-DV-A-N-TR.Normal\(chips)!LSHM-140-030-L-DV-A-N-TR_SAMTEC_LSHM-140-030-L-DV-A-N-TR_LSHM-140-030-L-DV-A-N-TR!!!TF-27!\14\!!!!!!!! +S!!J1!15!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS33975\@\B2BCONNECTOR\.\LSHM-140-030-L-DV-A-N-TR.Normal\(chips)!LSHM-140-030-L-DV-A-N-TR_SAMTEC_LSHM-140-030-L-DV-A-N-TR_LSHM-140-030-L-DV-A-N-TR!!!TF-27!\15\!!!!!!!! +S!!J1!16!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS33975\@\B2BCONNECTOR\.\LSHM-140-030-L-DV-A-N-TR.Normal\(chips)!LSHM-140-030-L-DV-A-N-TR_SAMTEC_LSHM-140-030-L-DV-A-N-TR_LSHM-140-030-L-DV-A-N-TR!!!TF-27!\16\!!!!!!!! +S!!J1!17!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS33975\@\B2BCONNECTOR\.\LSHM-140-030-L-DV-A-N-TR.Normal\(chips)!LSHM-140-030-L-DV-A-N-TR_SAMTEC_LSHM-140-030-L-DV-A-N-TR_LSHM-140-030-L-DV-A-N-TR!!!TF-27!\17\!!!!!!!! +S!!J1!18!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS33975\@\B2BCONNECTOR\.\LSHM-140-030-L-DV-A-N-TR.Normal\(chips)!LSHM-140-030-L-DV-A-N-TR_SAMTEC_LSHM-140-030-L-DV-A-N-TR_LSHM-140-030-L-DV-A-N-TR!!!TF-27!\18\!!!!!!!! +S!!J1!19!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS33975\@\B2BCONNECTOR\.\LSHM-140-030-L-DV-A-N-TR.Normal\(chips)!LSHM-140-030-L-DV-A-N-TR_SAMTEC_LSHM-140-030-L-DV-A-N-TR_LSHM-140-030-L-DV-A-N-TR!!!TF-27!\19\!!!!!!!! +S!!J1!20!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS33975\@\B2BCONNECTOR\.\LSHM-140-030-L-DV-A-N-TR.Normal\(chips)!LSHM-140-030-L-DV-A-N-TR_SAMTEC_LSHM-140-030-L-DV-A-N-TR_LSHM-140-030-L-DV-A-N-TR!!!TF-27!\20\!!!!!!!! +S!!J1!21!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS33975\@\B2BCONNECTOR\.\LSHM-140-030-L-DV-A-N-TR.Normal\(chips)!LSHM-140-030-L-DV-A-N-TR_SAMTEC_LSHM-140-030-L-DV-A-N-TR_LSHM-140-030-L-DV-A-N-TR!!!TF-27!\21\!!!!!!!! +S!!J1!22!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS33975\@\B2BCONNECTOR\.\LSHM-140-030-L-DV-A-N-TR.Normal\(chips)!LSHM-140-030-L-DV-A-N-TR_SAMTEC_LSHM-140-030-L-DV-A-N-TR_LSHM-140-030-L-DV-A-N-TR!!!TF-27!\22\!!!!!!!! +S!!J1!23!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS33975\@\B2BCONNECTOR\.\LSHM-140-030-L-DV-A-N-TR.Normal\(chips)!LSHM-140-030-L-DV-A-N-TR_SAMTEC_LSHM-140-030-L-DV-A-N-TR_LSHM-140-030-L-DV-A-N-TR!!!TF-27!\23\!!!!!!!! +S!!J1!24!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS33975\@\B2BCONNECTOR\.\LSHM-140-030-L-DV-A-N-TR.Normal\(chips)!LSHM-140-030-L-DV-A-N-TR_SAMTEC_LSHM-140-030-L-DV-A-N-TR_LSHM-140-030-L-DV-A-N-TR!!!TF-27!\24\!!!!!!!! +S!!J1!25!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS33975\@\B2BCONNECTOR\.\LSHM-140-030-L-DV-A-N-TR.Normal\(chips)!LSHM-140-030-L-DV-A-N-TR_SAMTEC_LSHM-140-030-L-DV-A-N-TR_LSHM-140-030-L-DV-A-N-TR!!!TF-27!\25\!!!!!!!! +S!!J1!26!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS33975\@\B2BCONNECTOR\.\LSHM-140-030-L-DV-A-N-TR.Normal\(chips)!LSHM-140-030-L-DV-A-N-TR_SAMTEC_LSHM-140-030-L-DV-A-N-TR_LSHM-140-030-L-DV-A-N-TR!!!TF-27!\26\!!!!!!!! +S!!J1!27!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS33975\@\B2BCONNECTOR\.\LSHM-140-030-L-DV-A-N-TR.Normal\(chips)!LSHM-140-030-L-DV-A-N-TR_SAMTEC_LSHM-140-030-L-DV-A-N-TR_LSHM-140-030-L-DV-A-N-TR!!!TF-27!\27\!!!!!!!! +S!!J1!28!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS33975\@\B2BCONNECTOR\.\LSHM-140-030-L-DV-A-N-TR.Normal\(chips)!LSHM-140-030-L-DV-A-N-TR_SAMTEC_LSHM-140-030-L-DV-A-N-TR_LSHM-140-030-L-DV-A-N-TR!!!TF-27!\28\!!!!!!!! +S!!J1!29!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS33975\@\B2BCONNECTOR\.\LSHM-140-030-L-DV-A-N-TR.Normal\(chips)!LSHM-140-030-L-DV-A-N-TR_SAMTEC_LSHM-140-030-L-DV-A-N-TR_LSHM-140-030-L-DV-A-N-TR!!!TF-27!\29\!!!!!!!! +S!!J1!30!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS33975\@\B2BCONNECTOR\.\LSHM-140-030-L-DV-A-N-TR.Normal\(chips)!LSHM-140-030-L-DV-A-N-TR_SAMTEC_LSHM-140-030-L-DV-A-N-TR_LSHM-140-030-L-DV-A-N-TR!!!TF-27!\30\!!!!!!!! +S!!J1!31!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS33975\@\B2BCONNECTOR\.\LSHM-140-030-L-DV-A-N-TR.Normal\(chips)!LSHM-140-030-L-DV-A-N-TR_SAMTEC_LSHM-140-030-L-DV-A-N-TR_LSHM-140-030-L-DV-A-N-TR!!!TF-27!\31\!!!!!!!! +S!!J1!32!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS33975\@\B2BCONNECTOR\.\LSHM-140-030-L-DV-A-N-TR.Normal\(chips)!LSHM-140-030-L-DV-A-N-TR_SAMTEC_LSHM-140-030-L-DV-A-N-TR_LSHM-140-030-L-DV-A-N-TR!!!TF-27!\32\!!!!!!!! +S!!J1!33!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS33975\@\B2BCONNECTOR\.\LSHM-140-030-L-DV-A-N-TR.Normal\(chips)!LSHM-140-030-L-DV-A-N-TR_SAMTEC_LSHM-140-030-L-DV-A-N-TR_LSHM-140-030-L-DV-A-N-TR!!!TF-27!\33\!!!!!!!! +S!!J1!34!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS33975\@\B2BCONNECTOR\.\LSHM-140-030-L-DV-A-N-TR.Normal\(chips)!LSHM-140-030-L-DV-A-N-TR_SAMTEC_LSHM-140-030-L-DV-A-N-TR_LSHM-140-030-L-DV-A-N-TR!!!TF-27!\34\!!!!!!!! +S!!J1!35!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS33975\@\B2BCONNECTOR\.\LSHM-140-030-L-DV-A-N-TR.Normal\(chips)!LSHM-140-030-L-DV-A-N-TR_SAMTEC_LSHM-140-030-L-DV-A-N-TR_LSHM-140-030-L-DV-A-N-TR!!!TF-27!\35\!!!!!!!! +S!!J1!36!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS33975\@\B2BCONNECTOR\.\LSHM-140-030-L-DV-A-N-TR.Normal\(chips)!LSHM-140-030-L-DV-A-N-TR_SAMTEC_LSHM-140-030-L-DV-A-N-TR_LSHM-140-030-L-DV-A-N-TR!!!TF-27!\36\!!!!!!!! +S!!J1!37!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS33975\@\B2BCONNECTOR\.\LSHM-140-030-L-DV-A-N-TR.Normal\(chips)!LSHM-140-030-L-DV-A-N-TR_SAMTEC_LSHM-140-030-L-DV-A-N-TR_LSHM-140-030-L-DV-A-N-TR!!!TF-27!\37\!!!!!!!! +S!!J1!38!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS33975\@\B2BCONNECTOR\.\LSHM-140-030-L-DV-A-N-TR.Normal\(chips)!LSHM-140-030-L-DV-A-N-TR_SAMTEC_LSHM-140-030-L-DV-A-N-TR_LSHM-140-030-L-DV-A-N-TR!!!TF-27!\38\!!!!!!!! +S!!J1!39!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS33975\@\B2BCONNECTOR\.\LSHM-140-030-L-DV-A-N-TR.Normal\(chips)!LSHM-140-030-L-DV-A-N-TR_SAMTEC_LSHM-140-030-L-DV-A-N-TR_LSHM-140-030-L-DV-A-N-TR!!!TF-27!\39\!!!!!!!! +S!!J1!40!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS33975\@\B2BCONNECTOR\.\LSHM-140-030-L-DV-A-N-TR.Normal\(chips)!LSHM-140-030-L-DV-A-N-TR_SAMTEC_LSHM-140-030-L-DV-A-N-TR_LSHM-140-030-L-DV-A-N-TR!!!TF-27!\40\!!!!!!!! +S!!J1!41!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS33975\@\B2BCONNECTOR\.\LSHM-140-030-L-DV-A-N-TR.Normal\(chips)!LSHM-140-030-L-DV-A-N-TR_SAMTEC_LSHM-140-030-L-DV-A-N-TR_LSHM-140-030-L-DV-A-N-TR!!!TF-27!\41\!!!!!!!! +S!!J1!42!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS33975\@\B2BCONNECTOR\.\LSHM-140-030-L-DV-A-N-TR.Normal\(chips)!LSHM-140-030-L-DV-A-N-TR_SAMTEC_LSHM-140-030-L-DV-A-N-TR_LSHM-140-030-L-DV-A-N-TR!!!TF-27!\42\!!!!!!!! +S!!J1!43!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS33975\@\B2BCONNECTOR\.\LSHM-140-030-L-DV-A-N-TR.Normal\(chips)!LSHM-140-030-L-DV-A-N-TR_SAMTEC_LSHM-140-030-L-DV-A-N-TR_LSHM-140-030-L-DV-A-N-TR!!!TF-27!\43\!!!!!!!! +S!!J1!44!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS33975\@\B2BCONNECTOR\.\LSHM-140-030-L-DV-A-N-TR.Normal\(chips)!LSHM-140-030-L-DV-A-N-TR_SAMTEC_LSHM-140-030-L-DV-A-N-TR_LSHM-140-030-L-DV-A-N-TR!!!TF-27!\44\!!!!!!!! +S!!J1!45!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS33975\@\B2BCONNECTOR\.\LSHM-140-030-L-DV-A-N-TR.Normal\(chips)!LSHM-140-030-L-DV-A-N-TR_SAMTEC_LSHM-140-030-L-DV-A-N-TR_LSHM-140-030-L-DV-A-N-TR!!!TF-27!\45\!!!!!!!! +S!!J1!46!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS33975\@\B2BCONNECTOR\.\LSHM-140-030-L-DV-A-N-TR.Normal\(chips)!LSHM-140-030-L-DV-A-N-TR_SAMTEC_LSHM-140-030-L-DV-A-N-TR_LSHM-140-030-L-DV-A-N-TR!!!TF-27!\46\!!!!!!!! +S!!J1!47!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS33975\@\B2BCONNECTOR\.\LSHM-140-030-L-DV-A-N-TR.Normal\(chips)!LSHM-140-030-L-DV-A-N-TR_SAMTEC_LSHM-140-030-L-DV-A-N-TR_LSHM-140-030-L-DV-A-N-TR!!!TF-27!\47\!!!!!!!! +S!!J1!48!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS33975\@\B2BCONNECTOR\.\LSHM-140-030-L-DV-A-N-TR.Normal\(chips)!LSHM-140-030-L-DV-A-N-TR_SAMTEC_LSHM-140-030-L-DV-A-N-TR_LSHM-140-030-L-DV-A-N-TR!!!TF-27!\48\!!!!!!!! +S!!J1!49!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS33975\@\B2BCONNECTOR\.\LSHM-140-030-L-DV-A-N-TR.Normal\(chips)!LSHM-140-030-L-DV-A-N-TR_SAMTEC_LSHM-140-030-L-DV-A-N-TR_LSHM-140-030-L-DV-A-N-TR!!!TF-27!\49\!!!!!!!! +S!!J1!50!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS33975\@\B2BCONNECTOR\.\LSHM-140-030-L-DV-A-N-TR.Normal\(chips)!LSHM-140-030-L-DV-A-N-TR_SAMTEC_LSHM-140-030-L-DV-A-N-TR_LSHM-140-030-L-DV-A-N-TR!!!TF-27!\50\!!!!!!!! +S!!J1!51!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS33975\@\B2BCONNECTOR\.\LSHM-140-030-L-DV-A-N-TR.Normal\(chips)!LSHM-140-030-L-DV-A-N-TR_SAMTEC_LSHM-140-030-L-DV-A-N-TR_LSHM-140-030-L-DV-A-N-TR!!!TF-27!\51\!!!!!!!! +S!!J1!52!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS33975\@\B2BCONNECTOR\.\LSHM-140-030-L-DV-A-N-TR.Normal\(chips)!LSHM-140-030-L-DV-A-N-TR_SAMTEC_LSHM-140-030-L-DV-A-N-TR_LSHM-140-030-L-DV-A-N-TR!!!TF-27!\52\!!!!!!!! +S!!J1!53!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS33975\@\B2BCONNECTOR\.\LSHM-140-030-L-DV-A-N-TR.Normal\(chips)!LSHM-140-030-L-DV-A-N-TR_SAMTEC_LSHM-140-030-L-DV-A-N-TR_LSHM-140-030-L-DV-A-N-TR!!!TF-27!\53\!!!!!!!! +S!!J1!54!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS33975\@\B2BCONNECTOR\.\LSHM-140-030-L-DV-A-N-TR.Normal\(chips)!LSHM-140-030-L-DV-A-N-TR_SAMTEC_LSHM-140-030-L-DV-A-N-TR_LSHM-140-030-L-DV-A-N-TR!!!TF-27!\54\!!!!!!!! +S!!J1!55!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS33975\@\B2BCONNECTOR\.\LSHM-140-030-L-DV-A-N-TR.Normal\(chips)!LSHM-140-030-L-DV-A-N-TR_SAMTEC_LSHM-140-030-L-DV-A-N-TR_LSHM-140-030-L-DV-A-N-TR!!!TF-27!\55\!!!!!!!! +S!!J1!56!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS33975\@\B2BCONNECTOR\.\LSHM-140-030-L-DV-A-N-TR.Normal\(chips)!LSHM-140-030-L-DV-A-N-TR_SAMTEC_LSHM-140-030-L-DV-A-N-TR_LSHM-140-030-L-DV-A-N-TR!!!TF-27!\56\!!!!!!!! +S!!J1!57!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS33975\@\B2BCONNECTOR\.\LSHM-140-030-L-DV-A-N-TR.Normal\(chips)!LSHM-140-030-L-DV-A-N-TR_SAMTEC_LSHM-140-030-L-DV-A-N-TR_LSHM-140-030-L-DV-A-N-TR!!!TF-27!\57\!!!!!!!! +S!!J1!58!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS33975\@\B2BCONNECTOR\.\LSHM-140-030-L-DV-A-N-TR.Normal\(chips)!LSHM-140-030-L-DV-A-N-TR_SAMTEC_LSHM-140-030-L-DV-A-N-TR_LSHM-140-030-L-DV-A-N-TR!!!TF-27!\58\!!!!!!!! +S!!J1!59!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS33975\@\B2BCONNECTOR\.\LSHM-140-030-L-DV-A-N-TR.Normal\(chips)!LSHM-140-030-L-DV-A-N-TR_SAMTEC_LSHM-140-030-L-DV-A-N-TR_LSHM-140-030-L-DV-A-N-TR!!!TF-27!\59\!!!!!!!! +S!!J1!60!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS33975\@\B2BCONNECTOR\.\LSHM-140-030-L-DV-A-N-TR.Normal\(chips)!LSHM-140-030-L-DV-A-N-TR_SAMTEC_LSHM-140-030-L-DV-A-N-TR_LSHM-140-030-L-DV-A-N-TR!!!TF-27!\60\!!!!!!!! +S!!J1!61!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS33975\@\B2BCONNECTOR\.\LSHM-140-030-L-DV-A-N-TR.Normal\(chips)!LSHM-140-030-L-DV-A-N-TR_SAMTEC_LSHM-140-030-L-DV-A-N-TR_LSHM-140-030-L-DV-A-N-TR!!!TF-27!\61\!!!!!!!! +S!!J1!62!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS33975\@\B2BCONNECTOR\.\LSHM-140-030-L-DV-A-N-TR.Normal\(chips)!LSHM-140-030-L-DV-A-N-TR_SAMTEC_LSHM-140-030-L-DV-A-N-TR_LSHM-140-030-L-DV-A-N-TR!!!TF-27!\62\!!!!!!!! +S!!J1!63!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS33975\@\B2BCONNECTOR\.\LSHM-140-030-L-DV-A-N-TR.Normal\(chips)!LSHM-140-030-L-DV-A-N-TR_SAMTEC_LSHM-140-030-L-DV-A-N-TR_LSHM-140-030-L-DV-A-N-TR!!!TF-27!\63\!!!!!!!! +S!!J1!64!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS33975\@\B2BCONNECTOR\.\LSHM-140-030-L-DV-A-N-TR.Normal\(chips)!LSHM-140-030-L-DV-A-N-TR_SAMTEC_LSHM-140-030-L-DV-A-N-TR_LSHM-140-030-L-DV-A-N-TR!!!TF-27!\64\!!!!!!!! +S!!J1!65!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS33975\@\B2BCONNECTOR\.\LSHM-140-030-L-DV-A-N-TR.Normal\(chips)!LSHM-140-030-L-DV-A-N-TR_SAMTEC_LSHM-140-030-L-DV-A-N-TR_LSHM-140-030-L-DV-A-N-TR!!!TF-27!\65\!!!!!!!! +S!!J1!66!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS33975\@\B2BCONNECTOR\.\LSHM-140-030-L-DV-A-N-TR.Normal\(chips)!LSHM-140-030-L-DV-A-N-TR_SAMTEC_LSHM-140-030-L-DV-A-N-TR_LSHM-140-030-L-DV-A-N-TR!!!TF-27!\66\!!!!!!!! +S!!J1!67!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS33975\@\B2BCONNECTOR\.\LSHM-140-030-L-DV-A-N-TR.Normal\(chips)!LSHM-140-030-L-DV-A-N-TR_SAMTEC_LSHM-140-030-L-DV-A-N-TR_LSHM-140-030-L-DV-A-N-TR!!!TF-27!\67\!!!!!!!! +S!!J1!68!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS33975\@\B2BCONNECTOR\.\LSHM-140-030-L-DV-A-N-TR.Normal\(chips)!LSHM-140-030-L-DV-A-N-TR_SAMTEC_LSHM-140-030-L-DV-A-N-TR_LSHM-140-030-L-DV-A-N-TR!!!TF-27!\68\!!!!!!!! +S!!J1!69!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS33975\@\B2BCONNECTOR\.\LSHM-140-030-L-DV-A-N-TR.Normal\(chips)!LSHM-140-030-L-DV-A-N-TR_SAMTEC_LSHM-140-030-L-DV-A-N-TR_LSHM-140-030-L-DV-A-N-TR!!!TF-27!\69\!!!!!!!! +S!!J1!70!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS33975\@\B2BCONNECTOR\.\LSHM-140-030-L-DV-A-N-TR.Normal\(chips)!LSHM-140-030-L-DV-A-N-TR_SAMTEC_LSHM-140-030-L-DV-A-N-TR_LSHM-140-030-L-DV-A-N-TR!!!TF-27!\70\!!!!!!!! +S!!J1!71!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS33975\@\B2BCONNECTOR\.\LSHM-140-030-L-DV-A-N-TR.Normal\(chips)!LSHM-140-030-L-DV-A-N-TR_SAMTEC_LSHM-140-030-L-DV-A-N-TR_LSHM-140-030-L-DV-A-N-TR!!!TF-27!\71\!!!!!!!! +S!!J1!72!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS33975\@\B2BCONNECTOR\.\LSHM-140-030-L-DV-A-N-TR.Normal\(chips)!LSHM-140-030-L-DV-A-N-TR_SAMTEC_LSHM-140-030-L-DV-A-N-TR_LSHM-140-030-L-DV-A-N-TR!!!TF-27!\72\!!!!!!!! +S!!J1!73!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS33975\@\B2BCONNECTOR\.\LSHM-140-030-L-DV-A-N-TR.Normal\(chips)!LSHM-140-030-L-DV-A-N-TR_SAMTEC_LSHM-140-030-L-DV-A-N-TR_LSHM-140-030-L-DV-A-N-TR!!!TF-27!\73\!!!!!!!! +S!!J1!74!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS33975\@\B2BCONNECTOR\.\LSHM-140-030-L-DV-A-N-TR.Normal\(chips)!LSHM-140-030-L-DV-A-N-TR_SAMTEC_LSHM-140-030-L-DV-A-N-TR_LSHM-140-030-L-DV-A-N-TR!!!TF-27!\74\!!!!!!!! +S!!J1!75!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS33975\@\B2BCONNECTOR\.\LSHM-140-030-L-DV-A-N-TR.Normal\(chips)!LSHM-140-030-L-DV-A-N-TR_SAMTEC_LSHM-140-030-L-DV-A-N-TR_LSHM-140-030-L-DV-A-N-TR!!!TF-27!\75\!!!!!!!! +S!!J1!76!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS33975\@\B2BCONNECTOR\.\LSHM-140-030-L-DV-A-N-TR.Normal\(chips)!LSHM-140-030-L-DV-A-N-TR_SAMTEC_LSHM-140-030-L-DV-A-N-TR_LSHM-140-030-L-DV-A-N-TR!!!TF-27!\76\!!!!!!!! +S!!J1!77!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS33975\@\B2BCONNECTOR\.\LSHM-140-030-L-DV-A-N-TR.Normal\(chips)!LSHM-140-030-L-DV-A-N-TR_SAMTEC_LSHM-140-030-L-DV-A-N-TR_LSHM-140-030-L-DV-A-N-TR!!!TF-27!\77\!!!!!!!! +S!!J1!78!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS33975\@\B2BCONNECTOR\.\LSHM-140-030-L-DV-A-N-TR.Normal\(chips)!LSHM-140-030-L-DV-A-N-TR_SAMTEC_LSHM-140-030-L-DV-A-N-TR_LSHM-140-030-L-DV-A-N-TR!!!TF-27!\78\!!!!!!!! +S!!J1!79!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS33975\@\B2BCONNECTOR\.\LSHM-140-030-L-DV-A-N-TR.Normal\(chips)!LSHM-140-030-L-DV-A-N-TR_SAMTEC_LSHM-140-030-L-DV-A-N-TR_LSHM-140-030-L-DV-A-N-TR!!!TF-27!\79\!!!!!!!! +S!!J1!80!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS33975\@\B2BCONNECTOR\.\LSHM-140-030-L-DV-A-N-TR.Normal\(chips)!LSHM-140-030-L-DV-A-N-TR_SAMTEC_LSHM-140-030-L-DV-A-N-TR_LSHM-140-030-L-DV-A-N-TR!!!TF-27!\80\!!!!!!!! +S!N19203!R1!1!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS19332\@\DISCRETE\.\R.Normal\(chips)!R_R0402_DISCRETE_1M!!!F13!\1\!!!!!!!! +S!N19188!R1!2!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS19332\@\DISCRETE\.\R.Normal\(chips)!R_R0402_DISCRETE_1M!!!F13!\2\!!!!!!!! +S!!U1!T3!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS13961\@\LIBRARY\.\SOC_RK3506BA.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F12!\NPOR\!!!!!!!! +S!N19188!U1!H3!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS13961\@\LIBRARY\.\SOC_RK3506BA.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F12!\OSC_XIN\!!!!!!!! +S!N19203!U1!H2!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS13961\@\LIBRARY\.\SOC_RK3506BA.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F12!\OSC_XOUT\!!!!!!!! +S!!U1!1L1!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS13961\@\LIBRARY\.\SOC_RK3506BA.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F12!\PMUIO_VCC3V3\!!!!!!!! +S!!U1!1K2!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS13961\@\LIBRARY\.\SOC_RK3506BA.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F12!\PMU_LOGIC_DVDD0V9\!!!!!!!! +S!!U1!G1!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS13961\@\LIBRARY\.\SOC_RK3506BA.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F12!\REF_CLK0_OUT | OSC_CLK_OUT | GPIO0_D0_D\!!!!!!!! +S!!U1!1G2!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS13961\@\LIBRARY\.\SOC_RK3506BA.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F12!\RFU\!!!!!!!! +S!!U1!V3!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS13961\@\LIBRARY\.\SOC_RK3506BA.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F12!\RM_IO0 | -- | SAI0_LRCK | GPIO0_A0_U\!!!!!!!! +S!!U1!W1!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS13961\@\LIBRARY\.\SOC_RK3506BA.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F12!\RM_IO1 | -- | SAI0_SCLK | GPIO0_A1_D\!!!!!!!! +S!!U1!R3!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS13961\@\LIBRARY\.\SOC_RK3506BA.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F12!\RM_IO10 | SPI1_MISO | SAI1_LRCK | GPIO0_B2_D\!!!!!!!! +S!!U1!P2!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS13961\@\LIBRARY\.\SOC_RK3506BA.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F12!\RM_IO11 | -- | SAI1_SDI | GPIO0_B3_D\!!!!!!!! +S!!U1!P3!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS13961\@\LIBRARY\.\SOC_RK3506BA.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F12!\RM_IO12 | -- | SAI1_SDO0 | GPIO0_B4_D\!!!!!!!! +S!!U1!N1!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS13961\@\LIBRARY\.\SOC_RK3506BA.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F12!\RM_IO13 | -- | SAI1_SDO1 | GPIO0_B5_D\!!!!!!!! +S!!U1!N3!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS13961\@\LIBRARY\.\SOC_RK3506BA.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F12!\RM_IO14 | SPI1_CSN0 | SAI1_SDO2 | GPIO0_B6_D\!!!!!!!! +S!!U1!N2!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS13961\@\LIBRARY\.\SOC_RK3506BA.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F12!\RM_IO15 | SPI0_CSN1 | SAI1_SDO3 | GPIO0_B7_D\!!!!!!!! +S!!U1!M2!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS13961\@\LIBRARY\.\SOC_RK3506BA.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F12!\RM_IO16 | SPI0_CLK | -- | GPIO0_C0_D\!!!!!!!! +S!!U1!M3!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS13961\@\LIBRARY\.\SOC_RK3506BA.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F12!\RM_IO17 | SPI0_MOSI | -- | GPIO0_C1_D\!!!!!!!! +S!!U1!L1!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS13961\@\LIBRARY\.\SOC_RK3506BA.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F12!\RM_IO18 | SPI0_MISO | REF_CLK1_OUT | GPIO0_C2_D\!!!!!!!! +S!!U1!L2!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS13961\@\LIBRARY\.\SOC_RK3506BA.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F12!\RM_IO19 | SPI0_CSN0 | ETH_CLK1_25M_OUT | GPIO0_C3_D\!!!!!!!! +S!!U1!W2!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS13961\@\LIBRARY\.\SOC_RK3506BA.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F12!\RM_IO2 | -- | SAI0_MCLK | GPIO0_A2_U\!!!!!!!! +S!!U1!K2!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS13961\@\LIBRARY\.\SOC_RK3506BA.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F12!\RM_IO20 | AUPLL_CLK_IN | ETH_CLK0_25M_OUT | GPIO0_C4_D\!!!!!!!! +S!!U1!K3!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS13961\@\LIBRARY\.\SOC_RK3506BA.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F12!\RM_IO21 | -- | CPU_AVS | GPIO0_C5_Z\!!!!!!!! +S!!U1!J2!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS13961\@\LIBRARY\.\SOC_RK3506BA.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F12!\RM_IO22 | JTAG_TCK_M1 | UART0_TX | GPIO0_C6_U\!!!!!!!! +S!!U1!J1!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS13961\@\LIBRARY\.\SOC_RK3506BA.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F12!\RM_IO23 | JTAG_TMS_M1 | UART0_RX | GPIO0_C7_U\!!!!!!!! +S!!U1!V2!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS13961\@\LIBRARY\.\SOC_RK3506BA.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F12!\RM_IO3 | -- | SAI0_SDO | GPIO0_A3_D\!!!!!!!! +S!!U1!U2!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS13961\@\LIBRARY\.\SOC_RK3506BA.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F12!\RM_IO4 | -- | SAI0_SDI0 | GPIO0_A4_D\!!!!!!!! +S!!U1!U1!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS13961\@\LIBRARY\.\SOC_RK3506BA.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F12!\RM_IO5 | -- | SAI0_SDI1 | GPIO0_A5_D\!!!!!!!! +S!!U1!U3!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS13961\@\LIBRARY\.\SOC_RK3506BA.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F12!\RM_IO6 | -- | SAI0_SDI2 | GPIO0_A6_D\!!!!!!!! +S!!U1!T2!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS13961\@\LIBRARY\.\SOC_RK3506BA.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F12!\RM_IO7 | SPI1_CSN1 | SAI0_SDI3 | GPIO0_A7_D\!!!!!!!! +S!!U1!R2!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS13961\@\LIBRARY\.\SOC_RK3506BA.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F12!\RM_IO8 | SPI1_CLK | SAI1_MCLK | GPIO0_B0_D\!!!!!!!! +S!!U1!R1!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS13961\@\LIBRARY\.\SOC_RK3506BA.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F12!\RM_IO9 | SPI1_MOSI | SAI1_SCLK | GPIO0_B1_D\!!!!!!!! +S!VCC_1V8!U1!1H1!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS13961\@\LIBRARY\.\SOC_RK3506BA.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F12!\SYS_PLL_AVDD1V8\!!!!!!!! +S!!U1!B10!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS16006\@\LIBRARY\.\SOC_RK3506BB.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!TF-24!\-- | -- | -- | -- | -- | FLEXBUS1_D0 | DSMC_CLKP | VO_LCDC_DEN | GPIO1_A0_D\!!!!!!!! +S!!U1!A9!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS16006\@\LIBRARY\.\SOC_RK3506BB.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!TF-24!\-- | -- | -- | -- | -- | FLEXBUS1_D2 | DSMC_DQS0 | VO_LCDC_HSYNC | GPIO1_A2_D\!!!!!!!! +S!!U1!B9!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS16006\@\LIBRARY\.\SOC_RK3506BB.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!TF-24!\-- | -- | -- | -- | -- | FLEXBUS1_D3 | DSMC_D0 | VO_LCDC_CLK | GPIO1_A3_D\!!!!!!!! +S!!U1!B8!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS16006\@\LIBRARY\.\SOC_RK3506BB.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!TF-24!\-- | -- | -- | -- | -- | FLEXBUS1_D4 | DSMC_D1 | VO_LCDC_D23 | GPIO1_A4_D\!!!!!!!! +S!!U1!1A4!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS16006\@\LIBRARY\.\SOC_RK3506BB.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!TF-24!\-- | -- | -- | -- | -- | FLEXBUS1_D5 | DSMC_D2 | VO_LCDC_D22 | GPIO1_A5_D\!!!!!!!! +S!!U1!A7!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS16006\@\LIBRARY\.\SOC_RK3506BB.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!TF-24!\-- | -- | -- | -- | -- | FLEXBUS1_D6 | DSMC_D3 | VO_LCDC_D21 | GPIO1_A6_D\!!!!!!!! +S!!U1!B7!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS16006\@\LIBRARY\.\SOC_RK3506BB.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!TF-24!\-- | -- | -- | -- | -- | FLEXBUS1_D7 | DSMC_D4 | VO_LCDC_D20 | GPIO1_A7_D\!!!!!!!! +S!!U1!1A3!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS16006\@\LIBRARY\.\SOC_RK3506BB.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!TF-24!\-- | -- | -- | FLEXBUS0_CSN_M0 | -- | FLEXBUS1_D8 | DSMC_D5 | VO_LCDC_D19 | GPIO1_B0_D\!!!!!!!! +S!!U1!1A1!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS16006\@\LIBRARY\.\SOC_RK3506BB.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!TF-24!\-- | -- | -- | FLEXBUS0_CSN_M2 | FLEXBUS0_D13 | FLEXBUS1_D12 | DSMC_D6 | VO_LCDC_D15 | GPIO1_B4_D\!!!!!!!! +S!!U1!A3!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS16006\@\LIBRARY\.\SOC_RK3506BB.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!TF-24!\-- | -- | -- | FLEXBUS0_CSN_M3 | FLEXBUS0_D11 | FLEXBUS1_D14 | DSMC_CSN0 | VO_LCDC_D13 | GPIO1_B6_D\!!!!!!!! +S!!U1!C3!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS16006\@\LIBRARY\.\SOC_RK3506BB.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!TF-24!\-- | -- | -- | FLEXBUS1_CSN_M2 | FLEXBUS0_D12 | FLEXBUS1_D13 | DSMC_D7 | VO_LCDC_D14 | GPIO1_B5_D\!!!!!!!! +S!!U1!B3!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS16006\@\LIBRARY\.\SOC_RK3506BB.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!TF-24!\-- | -- | -- | FLEXBUS1_CSN_M3 | FLEXBUS0_D10 | FLEXBUS1_D15 | DSMC_RDYN | VO_LCDC_D12 | GPIO1_B7_D\!!!!!!!! +S!!U1!1A2!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS16006\@\LIBRARY\.\SOC_RK3506BB.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!TF-24!\-- | RM_IO24 | UART5_CTSN_M1 | FLEXBUS1_CSN_M0 | -- | FLEXBUS1_D9 | DSMC_CSN1 | VO_LCDC_D18 | GPIO1_B1_D\!!!!!!!! +S!!U1!A5!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS16006\@\LIBRARY\.\SOC_RK3506BB.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!TF-24!\-- | RM_IO25 | SAI2_SCLK_M1 | FLEXBUS0_CSN_M1 | FLEXBUS0_D15 | FLEXBUS1_D10 | DSMC_INT2 | VO_LCDC_D17 | GPIO1_B2_D\!!!!!!!! +S!!U1!B5!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS16006\@\LIBRARY\.\SOC_RK3506BB.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!TF-24!\-- | RM_IO26 | SAI2_LRCK_M1 | FLEXBUS1_CSN_M1 | FLEXBUS0_D14 | FLEXBUS1_D11 | DSMC_INT3 | VO_LCDC_D16 | GPIO1_B3_D\!!!!!!!! +S!!U1!A2!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS16006\@\LIBRARY\.\SOC_RK3506BB.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!TF-24!\DSMC_SLV_CLK | -- | -- | FLEXBUS0_CSN_M4 | DSMC_INT1 | FLEXBUS1_CLK | DSMC_RESETN | VO_LCDC_D11 | GPIO1_C0_D\!!!!!!!! +S!!U1!F2!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS16006\@\LIBRARY\.\SOC_RK3506BB.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!TF-24!\DSMC_SLV_CSN0 | RM_IO30 | UART5_TX_M1 | -- | -- | FLEXBUS0_D1 | DSMC_CSN2 | VO_LCDC_D1 | GPIO1_D2_D\!!!!!!!! +S!!U1!B1!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS16006\@\LIBRARY\.\SOC_RK3506BB.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!TF-24!\DSMC_SLV_D0 | RM_IO27 | SAI2_SDI_M1 | FLEXBUS0_CSN_M5 | DSM_AUD_RP_M0 | FLEXBUS0_D9 | DSMC_D9 | VO_LCDC_D9 | GPIO1_C2_D\!!!!!!!! +S!!U1!C2!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS16006\@\LIBRARY\.\SOC_RK3506BB.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!TF-24!\DSMC_SLV_D1 | RM_IO28 | SAI2_SDO_M1 | FLEXBUS1_CSN_M5 | -- | FLEXBUS0_D8 | DSMC_D10 | VO_LCDC_D8 | GPIO1_C3_D\!!!!!!!! +S!!U1!C1!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS16006\@\LIBRARY\.\SOC_RK3506BB.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!TF-24!\DSMC_SLV_D2 | -- | -- | -- | -- | FLEXBUS0_D7 | DSMC_D11 | VO_LCDC_D7 | GPIO1_C4_D\!!!!!!!! +S!!U1!D3!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS16006\@\LIBRARY\.\SOC_RK3506BB.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!TF-24!\DSMC_SLV_D3 | -- | -- | -- | -- | FLEXBUS0_D6 | DSMC_D12 | VO_LCDC_D6 | GPIO1_C5_D\!!!!!!!! +S!!U1!E3!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS16006\@\LIBRARY\.\SOC_RK3506BB.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!TF-24!\DSMC_SLV_D4 | -- | -- | -- | -- | FLEXBUS0_D5 | DSMC_D13 | VO_LCDC_D5 | GPIO1_C6_D\!!!!!!!! +S!!U1!E2!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS16006\@\LIBRARY\.\SOC_RK3506BB.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!TF-24!\DSMC_SLV_D5 | -- | -- | -- | -- | FLEXBUS0_D4 | DSMC_D14 | VO_LCDC_D4 | GPIO1_C7_D\!!!!!!!! +S!!U1!E1!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS16006\@\LIBRARY\.\SOC_RK3506BB.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!TF-24!\DSMC_SLV_D6 | -- | -- | -- | DSM_AUD_LN_M0 | FLEXBUS0_D3 | DSMC_D15 | VO_LCDC_D3 | GPIO1_D0_D\!!!!!!!! +S!!U1!F3!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS16006\@\LIBRARY\.\SOC_RK3506BB.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!TF-24!\DSMC_SLV_D7 | RM_IO29 | UART5_RTSN_M1 | -- | DSM_AUD_LP_M0 | FLEXBUS0_D2 | DSMC_DQS1 | VO_LCDC_D2 | GPIO1_D1_D\!!!!!!!! +S!!U1!B2!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS16006\@\LIBRARY\.\SOC_RK3506BB.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!TF-24!\DSMC_SLV_DQS0 | -- | SAI2_MCLK_M1 | FLEXBUS1_CSN_M4 | DSM_AUD_RN_M0 | FLEXBUS0_CLK | DSMC_D8 | VO_LCDC_D10 | GPIO1_C1_D\!!!!!!!! +S!!U1!1A5!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS16006\@\LIBRARY\.\SOC_RK3506BB.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!TF-24!\DSMC_SLV_INT | -- | -- | -- | DSMC_INT0 | FLEXBUS1_D1 | DSMC_CLKN | VO_LCDC_VSYNC | GPIO1_A1_D\!!!!!!!! +S!!U1!G3!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS16006\@\LIBRARY\.\SOC_RK3506BB.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!TF-24!\DSMC_SLV_RDYN | RM_IO31 | UART5_RX_M1 | -- | -- | FLEXBUS0_D0 | DSMC_CSN3 | VO_LCDC_D0 | GPIO1_D3_D\!!!!!!!! +S!!U1!1E3!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS16006\@\LIBRARY\.\SOC_RK3506BB.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!TF-24!\VCCIO1_VCC_0\!!!!!!!! +S!!U1!1F3!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS16006\@\LIBRARY\.\SOC_RK3506BB.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!TF-24!\VCCIO1_VCC_1\!!!!!!!! +S!!U1!C22!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS16199\@\LIBRARY\.\SOC_RK3506BC.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!TF-23!\FSPI_CLK | GPIO2_A1_D\!!!!!!!! +S!!U1!A22!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS16199\@\LIBRARY\.\SOC_RK3506BC.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!TF-23!\FSPI_CSN | GPIO2_A0_U\!!!!!!!! +S!!U1!B23!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS16199\@\LIBRARY\.\SOC_RK3506BC.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!TF-23!\FSPI_D0 | GPIO2_A2_U\!!!!!!!! +S!!U1!B22!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS16199\@\LIBRARY\.\SOC_RK3506BC.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!TF-23!\FSPI_D1 | GPIO2_A3_U\!!!!!!!! +S!!U1!C21!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS16199\@\LIBRARY\.\SOC_RK3506BC.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!TF-23!\FSPI_D2 | GPIO2_A4_U\!!!!!!!! +S!!U1!C23!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS16199\@\LIBRARY\.\SOC_RK3506BC.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!TF-23!\FSPI_D3 | GPIO2_A5_U\!!!!!!!! +S!!U1!1F14!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS16199\@\LIBRARY\.\SOC_RK3506BC.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!TF-23!\VCCIO2_VCC\!!!!!!!! +S!!U1!D21!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS15385\@\LIBRARY\.\SOC_RK3506BD.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!TF-22!\-- | SPI2_CLK | ETH_RMII0_RXD0 | GPIO2_B0_D\!!!!!!!! +S!!U1!D23!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS15385\@\LIBRARY\.\SOC_RK3506BD.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!TF-22!\-- | SPI2_CSN | ETH_RMII0_RXD1 | GPIO2_B1_D\!!!!!!!! +S!!U1!E22!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS15385\@\LIBRARY\.\SOC_RK3506BD.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!TF-22!\-- | SPI2_MISO | ETH_RMII0_TXD0 | GPIO2_B3_D\!!!!!!!! +S!!U1!E21!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS15385\@\LIBRARY\.\SOC_RK3506BD.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!TF-22!\-- | SPI2_MOSI | ETH_RMII0_CLK | GPIO2_B2_D\!!!!!!!! +S!!U1!F23!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS15385\@\LIBRARY\.\SOC_RK3506BD.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!TF-22!\SAI3_LRCK | DSM_AUD_RP_M1 | ETH_RMII0_TXEN | GPIO2_B5_D\!!!!!!!! +S!!U1!G22!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS15385\@\LIBRARY\.\SOC_RK3506BD.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!TF-22!\SAI3_MCLK | -- | ETH_RMII0_RXDVCRS | GPIO2_C0_D\!!!!!!!! +S!!U1!F21!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS15385\@\LIBRARY\.\SOC_RK3506BD.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!TF-22!\SAI3_SCLK | DSM_AUD_RN_M1 | ETH_RMII0_TXD1 | GPIO2_B4_D\!!!!!!!! +S!!U1!F22!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS15385\@\LIBRARY\.\SOC_RK3506BD.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!TF-22!\SAI3_SDI | DSM_AUD_LN_M1 | ETH_RMII0_MDC | GPIO2_B6_D\!!!!!!!! +S!!U1!G21!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS15385\@\LIBRARY\.\SOC_RK3506BD.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!TF-22!\SAI3_SDO | DSM_AUD_LP_M1 | ETH_RMII0_MDIO | GPIO2_B7_D\!!!!!!!! +S!!U1!1G14!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS15385\@\LIBRARY\.\SOC_RK3506BD.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!TF-22!\VCCIO3_VCC\!!!!!!!! +S!!U1!K21!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS15310\@\LIBRARY\.\SOC_RK3506BE.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!TF-21!\-- | SDMMC_CLK | GPIO3_A0_D\!!!!!!!! +S!!U1!J21!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS15310\@\LIBRARY\.\SOC_RK3506BE.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!TF-21!\-- | SDMMC_CMD | GPIO3_A1_D\!!!!!!!! +S!!U1!K23!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS15310\@\LIBRARY\.\SOC_RK3506BE.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!TF-21!\-- | SDMMC_D0 | GPIO3_A2_D\!!!!!!!! +S!!U1!M23!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS15310\@\LIBRARY\.\SOC_RK3506BE.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!TF-21!\ETH_RMII1_CLK | SAI2_SDO_M0 | GPIO3_B0_D\!!!!!!!! +S!!U1!P23!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS15310\@\LIBRARY\.\SOC_RK3506BE.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!TF-21!\ETH_RMII1_MDC | UART5_TX_M0 | GPIO3_B4_D\!!!!!!!! +S!!U1!P21!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS15310\@\LIBRARY\.\SOC_RK3506BE.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!TF-21!\ETH_RMII1_MDIO | UART5_RTSN_M0 | GPIO3_B5_D\!!!!!!!! +S!!U1!L22!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS15310\@\LIBRARY\.\SOC_RK3506BE.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!TF-21!\ETH_RMII1_RXD0 | SAI2_SDI_M0 | GPIO3_A6_D\!!!!!!!! +S!!U1!M22!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS15310\@\LIBRARY\.\SOC_RK3506BE.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!TF-21!\ETH_RMII1_RXD1 | SAI2_SCLK_M0 | GPIO3_A7_D\!!!!!!!! +S!!U1!R22!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS15310\@\LIBRARY\.\SOC_RK3506BE.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!TF-21!\ETH_RMII1_RXDVCRS | SAI2_MCLK_M0 | GPIO3_B6_D\!!!!!!!! +S!!U1!M21!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS15310\@\LIBRARY\.\SOC_RK3506BE.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!TF-21!\ETH_RMII1_TXD0 | SAI2_LRCK_M0 | GPIO3_B1_D\!!!!!!!! +S!!U1!N21!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS15310\@\LIBRARY\.\SOC_RK3506BE.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!TF-21!\ETH_RMII1_TXD1 | UART5_CTSN_M0 | GPIO3_B2_D\!!!!!!!! +S!!U1!P22!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS15310\@\LIBRARY\.\SOC_RK3506BE.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!TF-21!\ETH_RMII1_TXEN | UART5_RX_M0 | GPIO3_B3_D\!!!!!!!! +S!!U1!H23!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS15310\@\LIBRARY\.\SOC_RK3506BE.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!TF-21!\JTAG_TCK_M0 | SDMMC_D2 | GPIO3_A4_D\!!!!!!!! +S!!U1!H22!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS15310\@\LIBRARY\.\SOC_RK3506BE.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!TF-21!\JTAG_TMS_M0 | SDMMC_D3 | GPIO3_A5_D\!!!!!!!! +S!!U1!K22!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS15310\@\LIBRARY\.\SOC_RK3506BE.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!TF-21!\TEST_CLK_OUT | SDMMC_D1 | GPIO3_A3_D\!!!!!!!! +S!!U1!1H14!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS15310\@\LIBRARY\.\SOC_RK3506BE.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!TF-21!\VCCIO4_VCC\!!!!!!!! +S!!U1!1B12!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS15781\@\LIBRARY\.\SOC_RK3506BF.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!TF-20!\ACODEC_ADC_AVDD1V6\!!!!!!!! +S!!U1!1B13!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS15781\@\LIBRARY\.\SOC_RK3506BF.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!TF-20!\ACODEC_ADC_AVDD1V8\!!!!!!!! +S!!U1!1A13!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS15781\@\LIBRARY\.\SOC_RK3506BF.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!TF-20!\ACODEC_ADC_AVSS\!!!!!!!! +S!!U1!B19!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS15781\@\LIBRARY\.\SOC_RK3506BF.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!TF-20!\ACODEC_ADC_INN\!!!!!!!! +S!!U1!A19!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS15781\@\LIBRARY\.\SOC_RK3506BF.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!TF-20!\ACODEC_ADC_INP\!!!!!!!! +S!!U1!1B11!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS15781\@\LIBRARY\.\SOC_RK3506BF.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!TF-20!\ACODEC_ADC_VCM\!!!!!!!! +S!!U1!1C7!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS15781\@\LIBRARY\.\SOC_RK3506BF.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!TF-20!\MIPI_DPHY_AVDD0V9\!!!!!!!! +S!!U1!1B7!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS15781\@\LIBRARY\.\SOC_RK3506BF.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!TF-20!\MIPI_DPHY_AVDD1V8\!!!!!!!! +S!!U1!B14!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS15781\@\LIBRARY\.\SOC_RK3506BF.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!TF-20!\MIPI_DPHY_DSI_TX_CLKN | GPO4_A4_Z\!!!!!!!! +S!!U1!B13!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS15781\@\LIBRARY\.\SOC_RK3506BF.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!TF-20!\MIPI_DPHY_DSI_TX_CLKP | GPO4_A5_Z\!!!!!!!! +S!!U1!A11!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS15781\@\LIBRARY\.\SOC_RK3506BF.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!TF-20!\MIPI_DPHY_DSI_TX_D0N | GPO4_A0_Z\!!!!!!!! +S!!U1!B11!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS15781\@\LIBRARY\.\SOC_RK3506BF.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!TF-20!\MIPI_DPHY_DSI_TX_D0P | GPO4_A1_Z\!!!!!!!! +S!!U1!B12!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS15781\@\LIBRARY\.\SOC_RK3506BF.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!TF-20!\MIPI_DPHY_DSI_TX_D1N | GPO4_A2_Z\!!!!!!!! +S!!U1!A12!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS15781\@\LIBRARY\.\SOC_RK3506BF.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!TF-20!\MIPI_DPHY_DSI_TX_D1P | GPO4_A3_Z\!!!!!!!! +S!!U1!1B14!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS15781\@\LIBRARY\.\SOC_RK3506BF.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!TF-20!\OTP_AVDD1V8 | SARADC_AVDD1V8\!!!!!!!! +S!!U1!A20!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS15781\@\LIBRARY\.\SOC_RK3506BF.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!TF-20!\SARADC_IN0 | GPIO4_B0_Z\!!!!!!!! +S!!U1!B20!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS15781\@\LIBRARY\.\SOC_RK3506BF.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!TF-20!\SARADC_IN1 | GPIO4_B1_Z\!!!!!!!! +S!!U1!A21!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS15781\@\LIBRARY\.\SOC_RK3506BF.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!TF-20!\SARADC_IN2 | GPIO4_B2_Z\!!!!!!!! +S!!U1!B21!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS15781\@\LIBRARY\.\SOC_RK3506BF.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!TF-20!\SARADC_IN3 | GPIO4_B3_Z\!!!!!!!! +S!!U1!1B6!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS15781\@\LIBRARY\.\SOC_RK3506BF.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!TF-20!\TSADC_VCC1V8\!!!!!!!! +S!!U1!B16!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS15781\@\LIBRARY\.\SOC_RK3506BF.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!TF-20!\USB20_OTG0_DM\!!!!!!!! +S!!U1!A16!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS15781\@\LIBRARY\.\SOC_RK3506BF.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!TF-20!\USB20_OTG0_DP\!!!!!!!! +S!!U1!B17!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS15781\@\LIBRARY\.\SOC_RK3506BF.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!TF-20!\USB20_OTG0_ID\!!!!!!!! +S!!U1!B18!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS15781\@\LIBRARY\.\SOC_RK3506BF.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!TF-20!\USB20_OTG0_VBUSDET\!!!!!!!! +S!!U1!A15!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS15781\@\LIBRARY\.\SOC_RK3506BF.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!TF-20!\USB20_OTG1_DM\!!!!!!!! +S!!U1!B15!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS15781\@\LIBRARY\.\SOC_RK3506BF.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!TF-20!\USB20_OTG1_DP\!!!!!!!! +S!!U1!1C8!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS15781\@\LIBRARY\.\SOC_RK3506BF.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!TF-20!\USB20_OTG_AVDD0V9\!!!!!!!! +S!!U1!1B9!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS15781\@\LIBRARY\.\SOC_RK3506BF.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!TF-20!\USB20_OTG_AVDD1V8\!!!!!!!! +S!!U1!1B10!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS15781\@\LIBRARY\.\SOC_RK3506BF.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!TF-20!\USB20_OTG_AVDD3V3\!!!!!!!! +S!VDD_CPU!U1!1C2!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS15156\@\LIBRARY\.\SOC_RK3506BG.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F11!\CPU_DVDD_0\!!!!!!!! +S!VDD_CPU!U1!1C3!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS15156\@\LIBRARY\.\SOC_RK3506BG.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F11!\CPU_DVDD_1\!!!!!!!! +S!VDD_CPU!U1!1C4!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS15156\@\LIBRARY\.\SOC_RK3506BG.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F11!\CPU_DVDD_2\!!!!!!!! +S!VDD_0V9!U1!1E4!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS15156\@\LIBRARY\.\SOC_RK3506BG.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F11!\LOGIC_DVDD_0\!!!!!!!! +S!VDD_0V9!U1!1E5!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS15156\@\LIBRARY\.\SOC_RK3506BG.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F11!\LOGIC_DVDD_1\!!!!!!!! +S!VDD_0V9!U1!1E6!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS15156\@\LIBRARY\.\SOC_RK3506BG.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F11!\LOGIC_DVDD_2\!!!!!!!! +S!VDD_0V9!U1!1F11!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS15156\@\LIBRARY\.\SOC_RK3506BG.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F11!\LOGIC_DVDD_3\!!!!!!!! +S!VDD_0V9!U1!1G11!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS15156\@\LIBRARY\.\SOC_RK3506BG.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F11!\LOGIC_DVDD_4\!!!!!!!! +S!VDD_0V9!U1!1H11!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS15156\@\LIBRARY\.\SOC_RK3506BG.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F11!\LOGIC_DVDD_5\!!!!!!!! +S!VDD_0V9!U1!1J10!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS15156\@\LIBRARY\.\SOC_RK3506BG.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F11!\LOGIC_DVDD_6\!!!!!!!! +S!!U1!W23!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS15564\@\LIBRARY\.\SOC_RK3506BH.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!TF-18!\DDR2_A0 | DDR3_A12\!!!!!!!! +S!!U1!1N13!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS15564\@\LIBRARY\.\SOC_RK3506BH.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!TF-18!\DDR2_A1 | DDR3_A3\!!!!!!!! +S!!U1!1N12!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS15564\@\LIBRARY\.\SOC_RK3506BH.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!TF-18!\DDR2_A10 | DDR3_BA0\!!!!!!!! +S!!U1!W22!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS15564\@\LIBRARY\.\SOC_RK3506BH.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!TF-18!\DDR2_A11 | DDR3_A11\!!!!!!!! +S!!U1!U22!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS15564\@\LIBRARY\.\SOC_RK3506BH.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!TF-18!\DDR2_A12 | DDR3_A9\!!!!!!!! +S!!U1!T23!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS15564\@\LIBRARY\.\SOC_RK3506BH.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!TF-18!\DDR2_A13 | DDR3_A13\!!!!!!!! +S!!U1!Y22!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS15564\@\LIBRARY\.\SOC_RK3506BH.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!TF-18!\DDR2_A14 | DDR3_A14\!!!!!!!! +S!!U1!Y17!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS15564\@\LIBRARY\.\SOC_RK3506BH.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!TF-18!\DDR2_A15 | DDR3_A15\!!!!!!!! +S!!U1!W18!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS15564\@\LIBRARY\.\SOC_RK3506BH.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!TF-18!\DDR2_A2 | DDR3_A4\!!!!!!!! +S!!U1!V23!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS15564\@\LIBRARY\.\SOC_RK3506BH.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!TF-18!\DDR2_A3 | DDR3_A0\!!!!!!!! +S!!U1!W20!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS15564\@\LIBRARY\.\SOC_RK3506BH.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!TF-18!\DDR2_A4 | DDR3_A1\!!!!!!!! +S!!U1!1N14!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS15564\@\LIBRARY\.\SOC_RK3506BH.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!TF-18!\DDR2_A5 | DDR3_A5\!!!!!!!! +S!!U1!Y20!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS15564\@\LIBRARY\.\SOC_RK3506BH.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!TF-18!\DDR2_A6 | DDR3_A6\!!!!!!!! +S!!U1!V22!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS15564\@\LIBRARY\.\SOC_RK3506BH.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!TF-18!\DDR2_A7 | DDR3_A2\!!!!!!!! +S!!U1!Y21!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS15564\@\LIBRARY\.\SOC_RK3506BH.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!TF-18!\DDR2_A8 | DDR3_A8\!!!!!!!! +S!!U1!T22!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS15564\@\LIBRARY\.\SOC_RK3506BH.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!TF-18!\DDR2_A9 | DDR3_A7\!!!!!!!! +S!!U1!1N8!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS15564\@\LIBRARY\.\SOC_RK3506BH.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!TF-18!\DDR2_BA0 | DDR3_CASN\!!!!!!!! +S!!U1!1M9!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS15564\@\LIBRARY\.\SOC_RK3506BH.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!TF-18!\DDR2_BA1 | DDR3_WEN\!!!!!!!! +S!!U1!1N9!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS15564\@\LIBRARY\.\SOC_RK3506BH.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!TF-18!\DDR2_BA2 | DDR3_BA2\!!!!!!!! +S!!U1!Y18!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS15564\@\LIBRARY\.\SOC_RK3506BH.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!TF-18!\DDR2_CASN | DDR3_BA1\!!!!!!!! +S!!U1!W17!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS15564\@\LIBRARY\.\SOC_RK3506BH.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!TF-18!\DDR2_RASN | DDR3_A10\!!!!!!!! +S!!U1!1M8!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS15564\@\LIBRARY\.\SOC_RK3506BH.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!TF-18!\DDR2_WEN | DDR3_RASN\!!!!!!!! +S!!U1!1M13!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS15564\@\LIBRARY\.\SOC_RK3506BH.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!TF-18!\DDR3_RESET\!!!!!!!! +S!!U1!W15!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS15564\@\LIBRARY\.\SOC_RK3506BH.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!TF-18!\DDR_CKE\!!!!!!!! +S!!U1!W14!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS15564\@\LIBRARY\.\SOC_RK3506BH.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!TF-18!\DDR_CLKN\!!!!!!!! +S!!U1!Y14!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS15564\@\LIBRARY\.\SOC_RK3506BH.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!TF-18!\DDR_CLKP\!!!!!!!! +S!!U1!1M11!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS15564\@\LIBRARY\.\SOC_RK3506BH.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!TF-18!\DDR_CSN\!!!!!!!! +S!!U1!1N4!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS15564\@\LIBRARY\.\SOC_RK3506BH.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!TF-18!\DDR_DM0\!!!!!!!! +S!!U1!1M4!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS15564\@\LIBRARY\.\SOC_RK3506BH.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!TF-18!\DDR_DM1\!!!!!!!! +S!!U1!Y13!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS15564\@\LIBRARY\.\SOC_RK3506BH.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!TF-18!\DDR_DQ0\!!!!!!!! +S!!U1!Y6!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS15564\@\LIBRARY\.\SOC_RK3506BH.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!TF-18!\DDR_DQ10\!!!!!!!! +S!!U1!Y3!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS15564\@\LIBRARY\.\SOC_RK3506BH.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!TF-18!\DDR_DQ11\!!!!!!!! +S!!U1!W6!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS15564\@\LIBRARY\.\SOC_RK3506BH.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!TF-18!\DDR_DQ12\!!!!!!!! +S!!U1!Y2!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS15564\@\LIBRARY\.\SOC_RK3506BH.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!TF-18!\DDR_DQ13\!!!!!!!! +S!!U1!1N1!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS15564\@\LIBRARY\.\SOC_RK3506BH.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!TF-18!\DDR_DQ14\!!!!!!!! +S!!U1!1N2!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS15564\@\LIBRARY\.\SOC_RK3506BH.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!TF-18!\DDR_DQ15\!!!!!!!! +S!!U1!Y12!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS15564\@\LIBRARY\.\SOC_RK3506BH.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!TF-18!\DDR_DQ1\!!!!!!!! +S!!U1!Y11!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS15564\@\LIBRARY\.\SOC_RK3506BH.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!TF-18!\DDR_DQ2\!!!!!!!! +S!!U1!1M6!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS15564\@\LIBRARY\.\SOC_RK3506BH.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!TF-18!\DDR_DQ3\!!!!!!!! +S!!U1!1M5!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS15564\@\LIBRARY\.\SOC_RK3506BH.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!TF-18!\DDR_DQ4\!!!!!!!! +S!!U1!1N6!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS15564\@\LIBRARY\.\SOC_RK3506BH.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!TF-18!\DDR_DQ5\!!!!!!!! +S!!U1!W9!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS15564\@\LIBRARY\.\SOC_RK3506BH.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!TF-18!\DDR_DQ6\!!!!!!!! +S!!U1!1N5!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS15564\@\LIBRARY\.\SOC_RK3506BH.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!TF-18!\DDR_DQ7\!!!!!!!! +S!!U1!Y7!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS15564\@\LIBRARY\.\SOC_RK3506BH.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!TF-18!\DDR_DQ8\!!!!!!!! +S!!U1!W7!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS15564\@\LIBRARY\.\SOC_RK3506BH.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!TF-18!\DDR_DQ9\!!!!!!!! +S!!U1!W10!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS15564\@\LIBRARY\.\SOC_RK3506BH.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!TF-18!\DDR_DQS0N\!!!!!!!! +S!!U1!Y10!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS15564\@\LIBRARY\.\SOC_RK3506BH.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!TF-18!\DDR_DQS0P\!!!!!!!! +S!!U1!W4!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS15564\@\LIBRARY\.\SOC_RK3506BH.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!TF-18!\DDR_DQS1N\!!!!!!!! +S!!U1!Y4!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS15564\@\LIBRARY\.\SOC_RK3506BH.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!TF-18!\DDR_DQS1P\!!!!!!!! +S!!U1!1N10!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS15564\@\LIBRARY\.\SOC_RK3506BH.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!TF-18!\DDR_ODT\!!!!!!!! +S!!U1!1L6!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS15564\@\LIBRARY\.\SOC_RK3506BH.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!TF-18!\DDR_OPEN0\!!!!!!!! +S!!U1!1K5!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS15564\@\LIBRARY\.\SOC_RK3506BH.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!TF-18!\DDR_OPEN1\!!!!!!!! +S!!U1!1L8!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS15564\@\LIBRARY\.\SOC_RK3506BH.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!TF-18!\DDR_RZQ\!!!!!!!! +S!!U1!1K6!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS15564\@\LIBRARY\.\SOC_RK3506BH.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!TF-18!\DDR_VDDQ_0\!!!!!!!! +S!!U1!1K7!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS15564\@\LIBRARY\.\SOC_RK3506BH.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!TF-18!\DDR_VDDQ_1\!!!!!!!! +S!!U1!1K8!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS15564\@\LIBRARY\.\SOC_RK3506BH.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!TF-18!\DDR_VDDQ_2\!!!!!!!! +S!!U1!1K9!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS15564\@\LIBRARY\.\SOC_RK3506BH.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!TF-18!\DDR_VDDQ_3\!!!!!!!! +S!!U1!1K10!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS15564\@\LIBRARY\.\SOC_RK3506BH.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!TF-18!\DDR_VDDQ_4\!!!!!!!! +S!!U1!1L10!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS15564\@\LIBRARY\.\SOC_RK3506BH.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!TF-18!\DDR_VREF_CA\!!!!!!!! +S!!U1!1L11!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS15564\@\LIBRARY\.\SOC_RK3506BH.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!TF-18!\DDR_VREF_DQ\!!!!!!!! +S!GND!U1!A1!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS14255\@\LIBRARY\.\SOC_RK3506BI.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F10!\VSS_0\!!!!!!!! +S!GND!U1!J3!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS14255\@\LIBRARY\.\SOC_RK3506BI.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F10!\VSS_10\!!!!!!!! +S!GND!U1!J22!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS14255\@\LIBRARY\.\SOC_RK3506BI.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F10!\VSS_11\!!!!!!!! +S!GND!U1!L3!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS14255\@\LIBRARY\.\SOC_RK3506BI.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F10!\VSS_12\!!!!!!!! +S!GND!U1!L21!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS14255\@\LIBRARY\.\SOC_RK3506BI.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F10!\VSS_13\!!!!!!!! +S!GND!U1!N22!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS14255\@\LIBRARY\.\SOC_RK3506BI.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F10!\VSS_14\!!!!!!!! +S!GND!U1!R21!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS14255\@\LIBRARY\.\SOC_RK3506BI.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F10!\VSS_15\!!!!!!!! +S!GND!U1!T21!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS14255\@\LIBRARY\.\SOC_RK3506BI.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F10!\VSS_16\!!!!!!!! +S!GND!U1!U21!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS14255\@\LIBRARY\.\SOC_RK3506BI.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F10!\VSS_17\!!!!!!!! +S!GND!U1!V21!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS14255\@\LIBRARY\.\SOC_RK3506BI.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F10!\VSS_18\!!!!!!!! +S!GND!U1!W3!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS14255\@\LIBRARY\.\SOC_RK3506BI.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F10!\VSS_19\!!!!!!!! +S!GND!U1!A13!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS14255\@\LIBRARY\.\SOC_RK3506BI.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F10!\VSS_1\!!!!!!!! +S!GND!U1!W5!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS14255\@\LIBRARY\.\SOC_RK3506BI.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F10!\VSS_20\!!!!!!!! +S!GND!U1!W8!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS14255\@\LIBRARY\.\SOC_RK3506BI.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F10!\VSS_21\!!!!!!!! +S!GND!U1!W11!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS14255\@\LIBRARY\.\SOC_RK3506BI.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F10!\VSS_22\!!!!!!!! +S!GND!U1!W12!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS14255\@\LIBRARY\.\SOC_RK3506BI.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F10!\VSS_23\!!!!!!!! +S!GND!U1!W13!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS14255\@\LIBRARY\.\SOC_RK3506BI.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F10!\VSS_24\!!!!!!!! +S!GND!U1!W16!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS14255\@\LIBRARY\.\SOC_RK3506BI.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F10!\VSS_25\!!!!!!!! +S!GND!U1!W19!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS14255\@\LIBRARY\.\SOC_RK3506BI.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F10!\VSS_26\!!!!!!!! +S!GND!U1!W21!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS14255\@\LIBRARY\.\SOC_RK3506BI.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F10!\VSS_27\!!!!!!!! +S!GND!U1!Y1!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS14255\@\LIBRARY\.\SOC_RK3506BI.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F10!\VSS_28\!!!!!!!! +S!GND!U1!Y9!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS14255\@\LIBRARY\.\SOC_RK3506BI.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F10!\VSS_29\!!!!!!!! +S!GND!U1!A17!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS14255\@\LIBRARY\.\SOC_RK3506BI.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F10!\VSS_2\!!!!!!!! +S!GND!U1!Y15!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS14255\@\LIBRARY\.\SOC_RK3506BI.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F10!\VSS_30\!!!!!!!! +S!GND!U1!Y23!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS14255\@\LIBRARY\.\SOC_RK3506BI.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F10!\VSS_31\!!!!!!!! +S!GND!U1!1A6!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS14255\@\LIBRARY\.\SOC_RK3506BI.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F10!\VSS_32\!!!!!!!! +S!GND!U1!1A7!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS14255\@\LIBRARY\.\SOC_RK3506BI.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F10!\VSS_33\!!!!!!!! +S!GND!U1!1A8!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS14255\@\LIBRARY\.\SOC_RK3506BI.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F10!\VSS_34\!!!!!!!! +S!GND!U1!1A9!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS14255\@\LIBRARY\.\SOC_RK3506BI.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F10!\VSS_35\!!!!!!!! +S!GND!U1!1A10!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS14255\@\LIBRARY\.\SOC_RK3506BI.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F10!\VSS_36\!!!!!!!! +S!GND!U1!1A11!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS14255\@\LIBRARY\.\SOC_RK3506BI.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F10!\VSS_37\!!!!!!!! +S!GND!U1!1A12!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS14255\@\LIBRARY\.\SOC_RK3506BI.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F10!\VSS_38\!!!!!!!! +S!GND!U1!1A14!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS14255\@\LIBRARY\.\SOC_RK3506BI.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F10!\VSS_39\!!!!!!!! +S!GND!U1!A23!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS14255\@\LIBRARY\.\SOC_RK3506BI.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F10!\VSS_3\!!!!!!!! +S!GND!U1!1B1!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS14255\@\LIBRARY\.\SOC_RK3506BI.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F10!\VSS_40\!!!!!!!! +S!GND!U1!1B2!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS14255\@\LIBRARY\.\SOC_RK3506BI.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F10!\VSS_41\!!!!!!!! +S!GND!U1!1B3!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS14255\@\LIBRARY\.\SOC_RK3506BI.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F10!\VSS_42\!!!!!!!! +S!GND!U1!1B4!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS14255\@\LIBRARY\.\SOC_RK3506BI.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F10!\VSS_43\!!!!!!!! +S!GND!U1!1B5!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS14255\@\LIBRARY\.\SOC_RK3506BI.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F10!\VSS_44\!!!!!!!! +S!GND!U1!1B8!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS14255\@\LIBRARY\.\SOC_RK3506BI.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F10!\VSS_45\!!!!!!!! +S!GND!U1!1C1!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS14255\@\LIBRARY\.\SOC_RK3506BI.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F10!\VSS_46\!!!!!!!! +S!GND!U1!1C5!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS14255\@\LIBRARY\.\SOC_RK3506BI.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F10!\VSS_47\!!!!!!!! +S!GND!U1!1C6!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS14255\@\LIBRARY\.\SOC_RK3506BI.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F10!\VSS_48\!!!!!!!! +S!GND!U1!1C9!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS14255\@\LIBRARY\.\SOC_RK3506BI.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F10!\VSS_49\!!!!!!!! +S!GND!U1!B4!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS14255\@\LIBRARY\.\SOC_RK3506BI.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F10!\VSS_4\!!!!!!!! +S!GND!U1!1C10!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS14255\@\LIBRARY\.\SOC_RK3506BI.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F10!\VSS_50\!!!!!!!! +S!GND!U1!1C11!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS14255\@\LIBRARY\.\SOC_RK3506BI.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F10!\VSS_51\!!!!!!!! +S!GND!U1!1C12!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS14255\@\LIBRARY\.\SOC_RK3506BI.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F10!\VSS_52\!!!!!!!! +S!GND!U1!1C13!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS14255\@\LIBRARY\.\SOC_RK3506BI.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F10!\VSS_53\!!!!!!!! +S!GND!U1!1C14!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS14255\@\LIBRARY\.\SOC_RK3506BI.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F10!\VSS_54\!!!!!!!! +S!GND!U1!1D1!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS14255\@\LIBRARY\.\SOC_RK3506BI.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F10!\VSS_55\!!!!!!!! +S!GND!U1!1D2!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS14255\@\LIBRARY\.\SOC_RK3506BI.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F10!\VSS_56\!!!!!!!! +S!GND!U1!1D3!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS14255\@\LIBRARY\.\SOC_RK3506BI.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F10!\VSS_57\!!!!!!!! +S!GND!U1!1D4!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS14255\@\LIBRARY\.\SOC_RK3506BI.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F10!\VSS_58\!!!!!!!! +S!GND!U1!1D5!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS14255\@\LIBRARY\.\SOC_RK3506BI.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F10!\VSS_59\!!!!!!!! +S!GND!U1!B6!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS14255\@\LIBRARY\.\SOC_RK3506BI.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F10!\VSS_5\!!!!!!!! +S!GND!U1!1D6!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS14255\@\LIBRARY\.\SOC_RK3506BI.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F10!\VSS_60\!!!!!!!! +S!GND!U1!1D7!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS14255\@\LIBRARY\.\SOC_RK3506BI.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F10!\VSS_61\!!!!!!!! +S!GND!U1!1D8!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS14255\@\LIBRARY\.\SOC_RK3506BI.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F10!\VSS_62\!!!!!!!! +S!GND!U1!1D9!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS14255\@\LIBRARY\.\SOC_RK3506BI.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F10!\VSS_63\!!!!!!!! +S!GND!U1!1D10!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS14255\@\LIBRARY\.\SOC_RK3506BI.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F10!\VSS_64\!!!!!!!! +S!GND!U1!1D11!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS14255\@\LIBRARY\.\SOC_RK3506BI.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F10!\VSS_65\!!!!!!!! +S!GND!U1!1D12!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS14255\@\LIBRARY\.\SOC_RK3506BI.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F10!\VSS_66\!!!!!!!! +S!GND!U1!1D13!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS14255\@\LIBRARY\.\SOC_RK3506BI.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F10!\VSS_67\!!!!!!!! +S!GND!U1!1D14!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS14255\@\LIBRARY\.\SOC_RK3506BI.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F10!\VSS_68\!!!!!!!! +S!GND!U1!1E1!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS14255\@\LIBRARY\.\SOC_RK3506BI.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F10!\VSS_69\!!!!!!!! +S!GND!U1!D2!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS14255\@\LIBRARY\.\SOC_RK3506BI.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F10!\VSS_6\!!!!!!!! +S!GND!U1!D22!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS14255\@\LIBRARY\.\SOC_RK3506BI.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F10!\VSS_7\!!!!!!!! +S!GND!U1!G2!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS14255\@\LIBRARY\.\SOC_RK3506BI.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F10!\VSS_8\!!!!!!!! +S!GND!U1!H21!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS14255\@\LIBRARY\.\SOC_RK3506BI.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F10!\VSS_9\!!!!!!!! +S!GND!U1!1H6!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS14712\@\LIBRARY\.\SOC_RK3506BJ.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F9!\VSS_100\!!!!!!!! +S!GND!U1!1H7!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS14712\@\LIBRARY\.\SOC_RK3506BJ.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F9!\VSS_101\!!!!!!!! +S!GND!U1!1H8!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS14712\@\LIBRARY\.\SOC_RK3506BJ.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F9!\VSS_102\!!!!!!!! +S!GND!U1!1H9!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS14712\@\LIBRARY\.\SOC_RK3506BJ.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F9!\VSS_103\!!!!!!!! +S!GND!U1!1H10!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS14712\@\LIBRARY\.\SOC_RK3506BJ.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F9!\VSS_104\!!!!!!!! +S!GND!U1!1H12!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS14712\@\LIBRARY\.\SOC_RK3506BJ.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F9!\VSS_105\!!!!!!!! +S!GND!U1!1H13!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS14712\@\LIBRARY\.\SOC_RK3506BJ.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F9!\VSS_106\!!!!!!!! +S!GND!U1!1J1!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS14712\@\LIBRARY\.\SOC_RK3506BJ.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F9!\VSS_107\!!!!!!!! +S!GND!U1!1J2!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS14712\@\LIBRARY\.\SOC_RK3506BJ.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F9!\VSS_108\!!!!!!!! +S!GND!U1!1J3!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS14712\@\LIBRARY\.\SOC_RK3506BJ.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F9!\VSS_109\!!!!!!!! +S!GND!U1!1J4!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS14712\@\LIBRARY\.\SOC_RK3506BJ.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F9!\VSS_110\!!!!!!!! +S!GND!U1!1J5!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS14712\@\LIBRARY\.\SOC_RK3506BJ.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F9!\VSS_111\!!!!!!!! +S!GND!U1!1J6!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS14712\@\LIBRARY\.\SOC_RK3506BJ.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F9!\VSS_112\!!!!!!!! +S!GND!U1!1J7!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS14712\@\LIBRARY\.\SOC_RK3506BJ.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F9!\VSS_113\!!!!!!!! +S!GND!U1!1J8!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS14712\@\LIBRARY\.\SOC_RK3506BJ.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F9!\VSS_114\!!!!!!!! +S!GND!U1!1J9!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS14712\@\LIBRARY\.\SOC_RK3506BJ.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F9!\VSS_115\!!!!!!!! +S!GND!U1!1J11!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS14712\@\LIBRARY\.\SOC_RK3506BJ.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F9!\VSS_116\!!!!!!!! +S!GND!U1!1J13!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS14712\@\LIBRARY\.\SOC_RK3506BJ.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F9!\VSS_117\!!!!!!!! +S!GND!U1!1J14!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS14712\@\LIBRARY\.\SOC_RK3506BJ.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F9!\VSS_118\!!!!!!!! +S!GND!U1!1K1!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS14712\@\LIBRARY\.\SOC_RK3506BJ.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F9!\VSS_119\!!!!!!!! +S!GND!U1!1K4!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS14712\@\LIBRARY\.\SOC_RK3506BJ.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F9!\VSS_120\!!!!!!!! +S!GND!U1!1K14!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS14712\@\LIBRARY\.\SOC_RK3506BJ.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F9!\VSS_121\!!!!!!!! +S!GND!U1!1L2!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS14712\@\LIBRARY\.\SOC_RK3506BJ.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F9!\VSS_122\!!!!!!!! +S!GND!U1!1L3!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS14712\@\LIBRARY\.\SOC_RK3506BJ.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F9!\VSS_123\!!!!!!!! +S!GND!U1!1L4!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS14712\@\LIBRARY\.\SOC_RK3506BJ.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F9!\VSS_124\!!!!!!!! +S!GND!U1!1L5!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS14712\@\LIBRARY\.\SOC_RK3506BJ.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F9!\VSS_125\!!!!!!!! +S!GND!U1!1L7!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS14712\@\LIBRARY\.\SOC_RK3506BJ.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F9!\VSS_126\!!!!!!!! +S!GND!U1!1L9!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS14712\@\LIBRARY\.\SOC_RK3506BJ.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F9!\VSS_127\!!!!!!!! +S!GND!U1!1L14!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS14712\@\LIBRARY\.\SOC_RK3506BJ.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F9!\VSS_128\!!!!!!!! +S!GND!U1!1M1!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS14712\@\LIBRARY\.\SOC_RK3506BJ.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F9!\VSS_129\!!!!!!!! +S!GND!U1!1M2!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS14712\@\LIBRARY\.\SOC_RK3506BJ.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F9!\VSS_130\!!!!!!!! +S!GND!U1!1M3!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS14712\@\LIBRARY\.\SOC_RK3506BJ.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F9!\VSS_131\!!!!!!!! +S!GND!U1!1M7!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS14712\@\LIBRARY\.\SOC_RK3506BJ.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F9!\VSS_132\!!!!!!!! +S!GND!U1!1M10!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS14712\@\LIBRARY\.\SOC_RK3506BJ.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F9!\VSS_133\!!!!!!!! +S!GND!U1!1M12!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS14712\@\LIBRARY\.\SOC_RK3506BJ.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F9!\VSS_134\!!!!!!!! +S!GND!U1!1M14!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS14712\@\LIBRARY\.\SOC_RK3506BJ.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F9!\VSS_135\!!!!!!!! +S!GND!U1!1N3!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS14712\@\LIBRARY\.\SOC_RK3506BJ.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F9!\VSS_136\!!!!!!!! +S!GND!U1!1N7!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS14712\@\LIBRARY\.\SOC_RK3506BJ.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F9!\VSS_137\!!!!!!!! +S!GND!U1!1N11!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS14712\@\LIBRARY\.\SOC_RK3506BJ.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F9!\VSS_138\!!!!!!!! +S!GND!U1!1E2!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS14712\@\LIBRARY\.\SOC_RK3506BJ.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F9!\VSS_70\!!!!!!!! +S!GND!U1!1E12!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS14712\@\LIBRARY\.\SOC_RK3506BJ.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F9!\VSS_71\!!!!!!!! +S!GND!U1!1E13!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS14712\@\LIBRARY\.\SOC_RK3506BJ.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F9!\VSS_72\!!!!!!!! +S!GND!U1!1E14!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS14712\@\LIBRARY\.\SOC_RK3506BJ.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F9!\VSS_73\!!!!!!!! +S!GND!U1!1F1!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS14712\@\LIBRARY\.\SOC_RK3506BJ.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F9!\VSS_74\!!!!!!!! +S!GND!U1!1F2!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS14712\@\LIBRARY\.\SOC_RK3506BJ.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F9!\VSS_75\!!!!!!!! +S!GND!U1!1F4!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS14712\@\LIBRARY\.\SOC_RK3506BJ.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F9!\VSS_76\!!!!!!!! +S!GND!U1!1F5!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS14712\@\LIBRARY\.\SOC_RK3506BJ.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F9!\VSS_77\!!!!!!!! +S!GND!U1!1F6!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS14712\@\LIBRARY\.\SOC_RK3506BJ.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F9!\VSS_78\!!!!!!!! +S!GND!U1!1F7!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS14712\@\LIBRARY\.\SOC_RK3506BJ.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F9!\VSS_79\!!!!!!!! +S!GND!U1!1F8!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS14712\@\LIBRARY\.\SOC_RK3506BJ.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F9!\VSS_80\!!!!!!!! +S!GND!U1!1F9!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS14712\@\LIBRARY\.\SOC_RK3506BJ.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F9!\VSS_81\!!!!!!!! +S!GND!U1!1F10!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS14712\@\LIBRARY\.\SOC_RK3506BJ.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F9!\VSS_82\!!!!!!!! +S!GND!U1!1F12!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS14712\@\LIBRARY\.\SOC_RK3506BJ.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F9!\VSS_83\!!!!!!!! +S!GND!U1!1F13!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS14712\@\LIBRARY\.\SOC_RK3506BJ.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F9!\VSS_84\!!!!!!!! +S!GND!U1!1G1!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS14712\@\LIBRARY\.\SOC_RK3506BJ.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F9!\VSS_85\!!!!!!!! +S!GND!U1!1G3!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS14712\@\LIBRARY\.\SOC_RK3506BJ.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F9!\VSS_86\!!!!!!!! +S!GND!U1!1G4!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS14712\@\LIBRARY\.\SOC_RK3506BJ.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F9!\VSS_87\!!!!!!!! +S!GND!U1!1G5!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS14712\@\LIBRARY\.\SOC_RK3506BJ.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F9!\VSS_88\!!!!!!!! +S!GND!U1!1G6!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS14712\@\LIBRARY\.\SOC_RK3506BJ.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F9!\VSS_89\!!!!!!!! +S!GND!U1!1G7!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS14712\@\LIBRARY\.\SOC_RK3506BJ.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F9!\VSS_90\!!!!!!!! +S!GND!U1!1G8!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS14712\@\LIBRARY\.\SOC_RK3506BJ.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F9!\VSS_91\!!!!!!!! +S!GND!U1!1G9!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS14712\@\LIBRARY\.\SOC_RK3506BJ.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F9!\VSS_92\!!!!!!!! +S!GND!U1!1G10!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS14712\@\LIBRARY\.\SOC_RK3506BJ.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F9!\VSS_93\!!!!!!!! +S!GND!U1!1G12!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS14712\@\LIBRARY\.\SOC_RK3506BJ.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F9!\VSS_94\!!!!!!!! +S!GND!U1!1G13!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS14712\@\LIBRARY\.\SOC_RK3506BJ.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F9!\VSS_95\!!!!!!!! +S!GND!U1!1H2!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS14712\@\LIBRARY\.\SOC_RK3506BJ.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F9!\VSS_96\!!!!!!!! +S!GND!U1!1H3!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS14712\@\LIBRARY\.\SOC_RK3506BJ.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F9!\VSS_97\!!!!!!!! +S!GND!U1!1H4!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS14712\@\LIBRARY\.\SOC_RK3506BJ.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F9!\VSS_98\!!!!!!!! +S!GND!U1!1H5!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS14712\@\LIBRARY\.\SOC_RK3506BJ.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!!!F9!\VSS_99\!!!!!!!! +S!!U2!11!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS20987\@d.s(v)!LAN8720A-CP-ABC_QFN24-6X6_MC_MCH_LAN8720A-CP-ABC!!!TF-15!\CRS_DV/*MODE2\!!!!!!!! +S!!U2!25!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS20987\@d.s(v)!LAN8720A-CP-ABC_QFN24-6X6_MC_MCH_LAN8720A-CP-ABC!!!TF-15!\EPAD\!!!!!!!! +S!!U2!3!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS20987\@d.s(v)!LAN8720A-CP-ABC_QFN24-6X6_MC_MCH_LAN8720A-CP-ABC!!!TF-15!\LED1/*REGOFF\!!!!!!!! +S!!U2!2!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS20987\@d.s(v)!LAN8720A-CP-ABC_QFN24-6X6_MC_MCH_LAN8720A-CP-ABC!!!TF-15!\LED2/*NINTSEL\!!!!!!!! +S!!U2!13!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS20987\@d.s(v)!LAN8720A-CP-ABC_QFN24-6X6_MC_MCH_LAN8720A-CP-ABC!!!TF-15!\MDC\!!!!!!!! +S!!U2!12!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS20987\@d.s(v)!LAN8720A-CP-ABC_QFN24-6X6_MC_MCH_LAN8720A-CP-ABC!!!TF-15!\MDIO\!!!!!!!! +S!!U2!14!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS20987\@d.s(v)!LAN8720A-CP-ABC_QFN24-6X6_MC_MCH_LAN8720A-CP-ABC!!!TF-15!\NINT/REFCLKO\!!!!!!!! +S!!U2!15!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS20987\@d.s(v)!LAN8720A-CP-ABC_QFN24-6X6_MC_MCH_LAN8720A-CP-ABC!!!TF-15!\NRST\!!!!!!!! +S!!U2!24!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS20987\@d.s(v)!LAN8720A-CP-ABC_QFN24-6X6_MC_MCH_LAN8720A-CP-ABC!!!TF-15!\RBIAS\!!!!!!!! +S!!U2!8!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS20987\@d.s(v)!LAN8720A-CP-ABC_QFN24-6X6_MC_MCH_LAN8720A-CP-ABC!!!TF-15!\RXD0/*MODE0\!!!!!!!! +S!!U2!7!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS20987\@d.s(v)!LAN8720A-CP-ABC_QFN24-6X6_MC_MCH_LAN8720A-CP-ABC!!!TF-15!\RXD1/*MODE1\!!!!!!!! +S!!U2!10!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS20987\@d.s(v)!LAN8720A-CP-ABC_QFN24-6X6_MC_MCH_LAN8720A-CP-ABC!!!TF-15!\RXER/*PHYAD0\!!!!!!!! +S!!U2!22!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS20987\@d.s(v)!LAN8720A-CP-ABC_QFN24-6X6_MC_MCH_LAN8720A-CP-ABC!!!TF-15!\RXN\!!!!!!!! +S!!U2!23!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS20987\@d.s(v)!LAN8720A-CP-ABC_QFN24-6X6_MC_MCH_LAN8720A-CP-ABC!!!TF-15!\RXP\!!!!!!!! +S!!U2!17!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS20987\@d.s(v)!LAN8720A-CP-ABC_QFN24-6X6_MC_MCH_LAN8720A-CP-ABC!!!TF-15!\TXD0\!!!!!!!! +S!!U2!18!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS20987\@d.s(v)!LAN8720A-CP-ABC_QFN24-6X6_MC_MCH_LAN8720A-CP-ABC!!!TF-15!\TXD1\!!!!!!!! +S!!U2!16!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS20987\@d.s(v)!LAN8720A-CP-ABC_QFN24-6X6_MC_MCH_LAN8720A-CP-ABC!!!TF-15!\TXEN\!!!!!!!! +S!!U2!20!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS20987\@d.s(v)!LAN8720A-CP-ABC_QFN24-6X6_MC_MCH_LAN8720A-CP-ABC!!!TF-15!\TXN\!!!!!!!! +S!!U2!21!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS20987\@d.s(v)!LAN8720A-CP-ABC_QFN24-6X6_MC_MCH_LAN8720A-CP-ABC!!!TF-15!\TXP\!!!!!!!! +S!!U2!5!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS20987\@d.s(v)!LAN8720A-CP-ABC_QFN24-6X6_MC_MCH_LAN8720A-CP-ABC!!!TF-15!\XTAL1/CLKIN\!!!!!!!! +S!!U2!4!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS20987\@d.s(v)!LAN8720A-CP-ABC_QFN24-6X6_MC_MCH_LAN8720A-CP-ABC!!!TF-15!\XTAL2\!!!!!!!! +S!VDD1A!U2!19!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS21054\@d.s(v)!LAN8720A-CP-ABC_QFN24-6X6_MC_MCH_LAN8720A-CP-ABC!!!F8!\VDD1A\!!!!!!!! +S!VDD2A!U2!1!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS21054\@d.s(v)!LAN8720A-CP-ABC_QFN24-6X6_MC_MCH_LAN8720A-CP-ABC!!!F8!\VDD2A\!!!!!!!! +S!VDDCR!U2!6!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS21054\@d.s(v)!LAN8720A-CP-ABC_QFN24-6X6_MC_MCH_LAN8720A-CP-ABC!!!F8!\VDDCR\!!!!!!!! +S!VDDIO!U2!9!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS21054\@d.s(v)!LAN8720A-CP-ABC_QFN24-6X6_MC_MCH_LAN8720A-CP-ABC!!!F8!\VDDIO\!!!!!!!! +S!!U3!11!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS21176\@d.s(v)!LAN8720A-CP-ABC_QFN24-6X6_MC_MCH_LAN8720A-CP-ABC!!!TF-13!\CRS_DV/*MODE2\!!!!!!!! +S!!U3!25!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS21176\@d.s(v)!LAN8720A-CP-ABC_QFN24-6X6_MC_MCH_LAN8720A-CP-ABC!!!TF-13!\EPAD\!!!!!!!! +S!!U3!3!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS21176\@d.s(v)!LAN8720A-CP-ABC_QFN24-6X6_MC_MCH_LAN8720A-CP-ABC!!!TF-13!\LED1/*REGOFF\!!!!!!!! +S!!U3!2!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS21176\@d.s(v)!LAN8720A-CP-ABC_QFN24-6X6_MC_MCH_LAN8720A-CP-ABC!!!TF-13!\LED2/*NINTSEL\!!!!!!!! +S!!U3!13!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS21176\@d.s(v)!LAN8720A-CP-ABC_QFN24-6X6_MC_MCH_LAN8720A-CP-ABC!!!TF-13!\MDC\!!!!!!!! +S!!U3!12!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS21176\@d.s(v)!LAN8720A-CP-ABC_QFN24-6X6_MC_MCH_LAN8720A-CP-ABC!!!TF-13!\MDIO\!!!!!!!! +S!!U3!14!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS21176\@d.s(v)!LAN8720A-CP-ABC_QFN24-6X6_MC_MCH_LAN8720A-CP-ABC!!!TF-13!\NINT/REFCLKO\!!!!!!!! +S!!U3!15!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS21176\@d.s(v)!LAN8720A-CP-ABC_QFN24-6X6_MC_MCH_LAN8720A-CP-ABC!!!TF-13!\NRST\!!!!!!!! +S!!U3!24!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS21176\@d.s(v)!LAN8720A-CP-ABC_QFN24-6X6_MC_MCH_LAN8720A-CP-ABC!!!TF-13!\RBIAS\!!!!!!!! +S!!U3!8!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS21176\@d.s(v)!LAN8720A-CP-ABC_QFN24-6X6_MC_MCH_LAN8720A-CP-ABC!!!TF-13!\RXD0/*MODE0\!!!!!!!! +S!!U3!7!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS21176\@d.s(v)!LAN8720A-CP-ABC_QFN24-6X6_MC_MCH_LAN8720A-CP-ABC!!!TF-13!\RXD1/*MODE1\!!!!!!!! +S!!U3!10!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS21176\@d.s(v)!LAN8720A-CP-ABC_QFN24-6X6_MC_MCH_LAN8720A-CP-ABC!!!TF-13!\RXER/*PHYAD0\!!!!!!!! +S!!U3!22!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS21176\@d.s(v)!LAN8720A-CP-ABC_QFN24-6X6_MC_MCH_LAN8720A-CP-ABC!!!TF-13!\RXN\!!!!!!!! +S!!U3!23!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS21176\@d.s(v)!LAN8720A-CP-ABC_QFN24-6X6_MC_MCH_LAN8720A-CP-ABC!!!TF-13!\RXP\!!!!!!!! +S!!U3!17!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS21176\@d.s(v)!LAN8720A-CP-ABC_QFN24-6X6_MC_MCH_LAN8720A-CP-ABC!!!TF-13!\TXD0\!!!!!!!! +S!!U3!18!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS21176\@d.s(v)!LAN8720A-CP-ABC_QFN24-6X6_MC_MCH_LAN8720A-CP-ABC!!!TF-13!\TXD1\!!!!!!!! +S!!U3!16!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS21176\@d.s(v)!LAN8720A-CP-ABC_QFN24-6X6_MC_MCH_LAN8720A-CP-ABC!!!TF-13!\TXEN\!!!!!!!! +S!!U3!20!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS21176\@d.s(v)!LAN8720A-CP-ABC_QFN24-6X6_MC_MCH_LAN8720A-CP-ABC!!!TF-13!\TXN\!!!!!!!! +S!!U3!21!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS21176\@d.s(v)!LAN8720A-CP-ABC_QFN24-6X6_MC_MCH_LAN8720A-CP-ABC!!!TF-13!\TXP\!!!!!!!! +S!!U3!5!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS21176\@d.s(v)!LAN8720A-CP-ABC_QFN24-6X6_MC_MCH_LAN8720A-CP-ABC!!!TF-13!\XTAL1/CLKIN\!!!!!!!! +S!!U3!4!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS21176\@d.s(v)!LAN8720A-CP-ABC_QFN24-6X6_MC_MCH_LAN8720A-CP-ABC!!!TF-13!\XTAL2\!!!!!!!! +S!VDD1A!U3!19!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS21243\@d.s(v)!LAN8720A-CP-ABC_QFN24-6X6_MC_MCH_LAN8720A-CP-ABC!!!F7!\VDD1A\!!!!!!!! +S!VDD2A!U3!1!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS21243\@d.s(v)!LAN8720A-CP-ABC_QFN24-6X6_MC_MCH_LAN8720A-CP-ABC!!!F7!\VDD2A\!!!!!!!! +S!VDDCR!U3!6!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS21243\@d.s(v)!LAN8720A-CP-ABC_QFN24-6X6_MC_MCH_LAN8720A-CP-ABC!!!F7!\VDDCR\!!!!!!!! +S!VDDIO!U3!9!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS21243\@d.s(v)!LAN8720A-CP-ABC_QFN24-6X6_MC_MCH_LAN8720A-CP-ABC!!!F7!\VDDIO\!!!!!!!! +S!!U4!1!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS22426\@d.s(v)!TLV62569DBVR_DBV0005A_N_TLV62569DBV!!!F6!\EN\!!!!!!!! +S!!U4!5!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS22426\@d.s(v)!TLV62569DBVR_DBV0005A_N_TLV62569DBV!!!F6!\FB\!!!!!!!! +S!GND!U4!2!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS22426\@d.s(v)!TLV62569DBVR_DBV0005A_N_TLV62569DBV!!!F6!\GND\!!!!!!!! +S!SW!U4!3!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS22426\@d.s(v)!TLV62569DBVR_DBV0005A_N_TLV62569DBV!!!F6!\SW\!!!!!!!! +S!VIN!U4!4!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS22426\@d.s(v)!TLV62569DBVR_DBV0005A_N_TLV62569DBV!!!F6!\VIN\!!!!!!!! +S!!U5!1!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS22454\@d.s(v)!TLV62569DBVR_DBV0005A_N_TLV62569DBV!!!F5!\EN\!!!!!!!! +S!!U5!5!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS22454\@d.s(v)!TLV62569DBVR_DBV0005A_N_TLV62569DBV!!!F5!\FB\!!!!!!!! +S!GND!U5!2!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS22454\@d.s(v)!TLV62569DBVR_DBV0005A_N_TLV62569DBV!!!F5!\GND\!!!!!!!! +S!SW!U5!3!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS22454\@d.s(v)!TLV62569DBVR_DBV0005A_N_TLV62569DBV!!!F5!\SW\!!!!!!!! +S!VIN!U5!4!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS22454\@d.s(v)!TLV62569DBVR_DBV0005A_N_TLV62569DBV!!!F5!\VIN\!!!!!!!! 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+S!GND!U9!34!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS52680\@\QF_IC\.\K922A.Normal\(chips)!K922_K922_K922!!!F1!\GND#34\!!!!!!!! +S!GND!U9!35!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS52680\@\QF_IC\.\K922A.Normal\(chips)!K922_K922_K922!!!F1!\GND#35\!!!!!!!! +S!GND!U9!37!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS52680\@\QF_IC\.\K922A.Normal\(chips)!K922_K922_K922!!!F1!\GND#37\!!!!!!!! +S!GND!U9!3!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS52680\@\QF_IC\.\K922A.Normal\(chips)!K922_K922_K922!!!F1!\GND#3\!!!!!!!! +S!GND!U9!41!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS52680\@\QF_IC\.\K922A.Normal\(chips)!K922_K922_K922!!!F1!\GND#41\!!!!!!!! +S!GND!U9!43!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS52680\@\QF_IC\.\K922A.Normal\(chips)!K922_K922_K922!!!F1!\GND#43\!!!!!!!! +S!GND!U9!45!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS52680\@\QF_IC\.\K922A.Normal\(chips)!K922_K922_K922!!!F1!\GND#45\!!!!!!!! +S!GND!U9!4!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS52680\@\QF_IC\.\K922A.Normal\(chips)!K922_K922_K922!!!F1!\GND#4\!!!!!!!! +S!VCC!U9!23!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS52680\@\QF_IC\.\K922A.Normal\(chips)!K922_K922_K922!!!F1!\VCC#23\!!!!!!!! +S!VCC!U9!24!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS52680\@\QF_IC\.\K922A.Normal\(chips)!K922_K922_K922!!!F1!\VCC#24\!!!!!!!! +S!V_BCKP!U9!5!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS52680\@\QF_IC\.\K922A.Normal\(chips)!K922_K922_K922!!!F1!\V_BCKP\!!!!!!!! +S!!U9!17!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS52780\@\QF_IC\.\K922B.Normal\(chips)!K922_K922_K922!!!TF-5!\COM1_RXD\!!!!!!!! +S!!U9!18!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS52780\@\QF_IC\.\K922B.Normal\(chips)!K922_K922_K922!!!TF-5!\COM1_TXD\!!!!!!!! +S!!U9!19!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS52780\@\QF_IC\.\K922B.Normal\(chips)!K922_K922_K922!!!TF-5!\COM2_RXD\!!!!!!!! +S!!U9!20!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS52780\@\QF_IC\.\K922B.Normal\(chips)!K922_K922_K922!!!TF-5!\COM2_TXD\!!!!!!!! +S!!U9!28!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS52780\@\QF_IC\.\K922B.Normal\(chips)!K922_K922_K922!!!TF-5!\COM3_RXD/CAN_RXD\!!!!!!!! +S!!U9!27!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS52780\@\QF_IC\.\K922B.Normal\(chips)!K922_K922_K922!!!TF-5!\COM3_TXD/CAN_TXD\!!!!!!!! +S!!U9!21!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS52780\@\QF_IC\.\K922B.Normal\(chips)!K922_K922_K922!!!TF-5!\I2C_SCL\!!!!!!!! +S!!U9!22!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS52780\@\QF_IC\.\K922B.Normal\(chips)!K922_K922_K922!!!TF-5!\I2C_SDA\!!!!!!!! +S!!U9!8!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS52780\@\QF_IC\.\K922B.Normal\(chips)!K922_K922_K922!!!TF-5!\SPI_CLK\!!!!!!!! +S!!U9!6!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS52780\@\QF_IC\.\K922B.Normal\(chips)!K922_K922_K922!!!TF-5!\SPI_CS\!!!!!!!! +S!!U9!9!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS52780\@\QF_IC\.\K922B.Normal\(chips)!K922_K922_K922!!!TF-5!\SPI_MISO\!!!!!!!! +S!!U9!7!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS52780\@\QF_IC\.\K922B.Normal\(chips)!K922_K922_K922!!!TF-5!\SPI_MOSI\!!!!!!!! +S!!U9!14!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS52850\@\QF_IC\.\K922C.Normal\(chips)!K922_K922_K922!!!TF-4!\ERR_STAT\!!!!!!!! +S!!U9!32!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS52850\@\QF_IC\.\K922C.Normal\(chips)!K922_K922_K922!!!TF-4!\EVENT\!!!!!!!! +S!!U9!30!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS52850\@\QF_IC\.\K922C.Normal\(chips)!K922_K922_K922!!!TF-4!\PPS\!!!!!!!! +S!!U9!15!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS52850\@\QF_IC\.\K922C.Normal\(chips)!K922_K922_K922!!!TF-4!\PVT_STAT\!!!!!!!! +S!!U9!16!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS52850\@\QF_IC\.\K922C.Normal\(chips)!K922_K922_K922!!!TF-4!\RTK_STAT\!!!!!!!! +S!!U9!33!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS52850\@\QF_IC\.\K922C.Normal\(chips)!K922_K922_K922!!!TF-4!\SYS_RSTN\!!!!!!!! +S!!U9!36!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS52892\@\QF_IC\.\K922D.Normal\(chips)!K922_K922_K922!!!TF-3!\ANT_IN_HEAD\!!!!!!!! +S!!U9!2!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS52892\@\QF_IC\.\K922D.Normal\(chips)!K922_K922_K922!!!TF-3!\ANT_IN_POS\!!!!!!!! +S!!U9!58!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS53122\@\QF_IC\.\K922E.Normal\(chips)!K922_K922_K922!!!TF-2!\EP10\!!!!!!!! +S!!U9!59!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS53122\@\QF_IC\.\K922E.Normal\(chips)!K922_K922_K922!!!TF-2!\EP11\!!!!!!!! +S!!U9!60!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS53122\@\QF_IC\.\K922E.Normal\(chips)!K922_K922_K922!!!TF-2!\EP12\!!!!!!!! +S!!U9!61!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS53122\@\QF_IC\.\K922E.Normal\(chips)!K922_K922_K922!!!TF-2!\EP13\!!!!!!!! +S!!U9!62!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS53122\@\QF_IC\.\K922E.Normal\(chips)!K922_K922_K922!!!TF-2!\EP14\!!!!!!!! +S!!U9!63!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS53122\@\QF_IC\.\K922E.Normal\(chips)!K922_K922_K922!!!TF-2!\EP15\!!!!!!!! +S!!U9!64!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS53122\@\QF_IC\.\K922E.Normal\(chips)!K922_K922_K922!!!TF-2!\EP16\!!!!!!!! +S!!U9!65!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS53122\@\QF_IC\.\K922E.Normal\(chips)!K922_K922_K922!!!TF-2!\EP17\!!!!!!!! +S!!U9!66!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS53122\@\QF_IC\.\K922E.Normal\(chips)!K922_K922_K922!!!TF-2!\EP18\!!!!!!!! +S!!U9!67!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS53122\@\QF_IC\.\K922E.Normal\(chips)!K922_K922_K922!!!TF-2!\EP19\!!!!!!!! +S!!U9!49!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS53122\@\QF_IC\.\K922E.Normal\(chips)!K922_K922_K922!!!TF-2!\EP1\!!!!!!!! +S!!U9!68!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS53122\@\QF_IC\.\K922E.Normal\(chips)!K922_K922_K922!!!TF-2!\EP20\!!!!!!!! +S!!U9!69!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS53122\@\QF_IC\.\K922E.Normal\(chips)!K922_K922_K922!!!TF-2!\EP21\!!!!!!!! +S!!U9!70!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS53122\@\QF_IC\.\K922E.Normal\(chips)!K922_K922_K922!!!TF-2!\EP22\!!!!!!!! +S!!U9!71!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS53122\@\QF_IC\.\K922E.Normal\(chips)!K922_K922_K922!!!TF-2!\EP23\!!!!!!!! +S!!U9!72!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS53122\@\QF_IC\.\K922E.Normal\(chips)!K922_K922_K922!!!TF-2!\EP24\!!!!!!!! +S!!U9!73!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS53122\@\QF_IC\.\K922E.Normal\(chips)!K922_K922_K922!!!TF-2!\EP25\!!!!!!!! +S!!U9!74!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS53122\@\QF_IC\.\K922E.Normal\(chips)!K922_K922_K922!!!TF-2!\EP26\!!!!!!!! +S!!U9!75!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS53122\@\QF_IC\.\K922E.Normal\(chips)!K922_K922_K922!!!TF-2!\EP27\!!!!!!!! +S!!U9!76!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS53122\@\QF_IC\.\K922E.Normal\(chips)!K922_K922_K922!!!TF-2!\EP28\!!!!!!!! +S!!U9!77!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS53122\@\QF_IC\.\K922E.Normal\(chips)!K922_K922_K922!!!TF-2!\EP29\!!!!!!!! +S!!U9!50!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS53122\@\QF_IC\.\K922E.Normal\(chips)!K922_K922_K922!!!TF-2!\EP2\!!!!!!!! +S!!U9!78!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS53122\@\QF_IC\.\K922E.Normal\(chips)!K922_K922_K922!!!TF-2!\EP30\!!!!!!!! +S!!U9!79!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS53122\@\QF_IC\.\K922E.Normal\(chips)!K922_K922_K922!!!TF-2!\EP31\!!!!!!!! +S!!U9!80!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS53122\@\QF_IC\.\K922E.Normal\(chips)!K922_K922_K922!!!TF-2!\EP32\!!!!!!!! +S!!U9!81!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS53122\@\QF_IC\.\K922E.Normal\(chips)!K922_K922_K922!!!TF-2!\EP33\!!!!!!!! +S!!U9!82!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS53122\@\QF_IC\.\K922E.Normal\(chips)!K922_K922_K922!!!TF-2!\EP34\!!!!!!!! +S!!U9!83!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS53122\@\QF_IC\.\K922E.Normal\(chips)!K922_K922_K922!!!TF-2!\EP35\!!!!!!!! +S!!U9!51!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS53122\@\QF_IC\.\K922E.Normal\(chips)!K922_K922_K922!!!TF-2!\EP3\!!!!!!!! +S!!U9!52!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS53122\@\QF_IC\.\K922E.Normal\(chips)!K922_K922_K922!!!TF-2!\EP4\!!!!!!!! +S!!U9!53!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS53122\@\QF_IC\.\K922E.Normal\(chips)!K922_K922_K922!!!TF-2!\EP5\!!!!!!!! +S!!U9!54!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS53122\@\QF_IC\.\K922E.Normal\(chips)!K922_K922_K922!!!TF-2!\EP6\!!!!!!!! +S!!U9!55!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS53122\@\QF_IC\.\K922E.Normal\(chips)!K922_K922_K922!!!TF-2!\EP7\!!!!!!!! +S!!U9!56!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS53122\@\QF_IC\.\K922E.Normal\(chips)!K922_K922_K922!!!TF-2!\EP8\!!!!!!!! +S!!U9!57!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS53122\@\QF_IC\.\K922E.Normal\(chips)!K922_K922_K922!!!TF-2!\EP9\!!!!!!!! +S!!U9!40!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS53122\@\QF_IC\.\K922E.Normal\(chips)!K922_K922_K922!!!TF-2!\RSV10\!!!!!!!! +S!!U9!42!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS53122\@\QF_IC\.\K922E.Normal\(chips)!K922_K922_K922!!!TF-2!\RSV11\!!!!!!!! +S!!U9!44!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS53122\@\QF_IC\.\K922E.Normal\(chips)!K922_K922_K922!!!TF-2!\RSV12\!!!!!!!! +S!!U9!46!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS53122\@\QF_IC\.\K922E.Normal\(chips)!K922_K922_K922!!!TF-2!\RSV13\!!!!!!!! +S!!U9!47!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS53122\@\QF_IC\.\K922E.Normal\(chips)!K922_K922_K922!!!TF-2!\RSV14\!!!!!!!! +S!!U9!48!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS53122\@\QF_IC\.\K922E.Normal\(chips)!K922_K922_K922!!!TF-2!\RSV15\!!!!!!!! +S!!U9!31!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS53122\@\QF_IC\.\K922E.Normal\(chips)!K922_K922_K922!!!TF-2!\RSV16\!!!!!!!! +S!!U9!10!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS53122\@\QF_IC\.\K922E.Normal\(chips)!K922_K922_K922!!!TF-2!\RSV1\!!!!!!!! +S!!U9!11!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS53122\@\QF_IC\.\K922E.Normal\(chips)!K922_K922_K922!!!TF-2!\RSV2\!!!!!!!! +S!!U9!12!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS53122\@\QF_IC\.\K922E.Normal\(chips)!K922_K922_K922!!!TF-2!\RSV3\!!!!!!!! +S!!U9!13!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS53122\@\QF_IC\.\K922E.Normal\(chips)!K922_K922_K922!!!TF-2!\RSV4\!!!!!!!! +S!!U9!25!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS53122\@\QF_IC\.\K922E.Normal\(chips)!K922_K922_K922!!!TF-2!\RSV5\!!!!!!!! +S!!U9!26!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS53122\@\QF_IC\.\K922E.Normal\(chips)!K922_K922_K922!!!TF-2!\RSV6\!!!!!!!! +S!!U9!29!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS53122\@\QF_IC\.\K922E.Normal\(chips)!K922_K922_K922!!!TF-2!\RSV7\!!!!!!!! +S!!U9!38!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS53122\@\QF_IC\.\K922E.Normal\(chips)!K922_K922_K922!!!TF-2!\RSV8\!!!!!!!! +S!!U9!39!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS53122\@\QF_IC\.\K922E.Normal\(chips)!K922_K922_K922!!!TF-2!\RSV9\!!!!!!!! +S!GND!X1!2!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS19052\@\OTHER\.\CRYSTAL 1-3_4Pin.Normal\(chips)!CRYSTAL 1-3_4PIN_XTAL3225_CRYSTAL 1-3_4PIN!!!F0!\GND#2\!!!!!!!! +S!GND!X1!4!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS19052\@\OTHER\.\CRYSTAL 1-3_4Pin.Normal\(chips)!CRYSTAL 1-3_4PIN_XTAL3225_CRYSTAL 1-3_4PIN!!!F0!\GND#4\!!!!!!!! +S!N19188!X1!1!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS19052\@\OTHER\.\CRYSTAL 1-3_4Pin.Normal\(chips)!CRYSTAL 1-3_4PIN_XTAL3225_CRYSTAL 1-3_4PIN!!!F0!\X1\!!!!!!!! +S!N19203!X1!3!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS19052\@\OTHER\.\CRYSTAL 1-3_4Pin.Normal\(chips)!CRYSTAL 1-3_4PIN_XTAL3225_CRYSTAL 1-3_4PIN!!!F0!\X3\!!!!!!!! diff --git a/allegro/pstdedb.cdsz b/allegro/pstdedb.cdsz new file mode 100644 index 0000000..6c1a8c2 Binary files /dev/null and b/allegro/pstdedb.cdsz differ diff --git a/allegro/rk3506_nav_rk3506_nav.json b/allegro/rk3506_nav_rk3506_nav.json new file mode 100644 index 0000000..fa91227 --- /dev/null +++ b/allegro/rk3506_nav_rk3506_nav.json @@ -0,0 +1,11 @@ +{ + "Gate Swap" : [], + "Ref Des" : [], + "Pin Swap" : [], + "Component Property" : [], + "Net Property" : [], + "Pin Property" : [], + "Component" : [], + "Net" : [], + "Connection" : [] +}