Files
rk3506_nav/allegro/netview.dat
T
2026-08-16 22:54:44 +08:00

131 lines
7.6 KiB
Plaintext

A!NET_NAME!NET_LOGICAL_PATH!NET_VOLTAGE!
J!D:/POLARIS/RK3506_NAV/rk3506_nav.brd!Sat Aug 15 10:52:42 2026!-100.0000!-100.0000!100.0000!100.0000!0.0001!millimeters!RK3506_NAV!28.800000 mil!4!UP TO DATE!
S!VDDK!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\VDDK\!1.2V!
S!VCC33!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\VCC33\!3.3V!
S!VCC5!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\VCC5\!3.3V!
S!VIO!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\VIO\!3.3V!
S!DDR3_A7!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\DDR3_A7\!!
S!DDR3_WEN!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\DDR3_WEN\!!
S!DDR3_A4!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\DDR3_A4\!!
S!DDR3_A9!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\DDR3_A9\!!
S!DDR3_RASN!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\DDR3_RASN\!!
S!DDR3_A12!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\DDR3_A12\!!
S!DDR3_A15!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\DDR3_A15\!!
S!ETH_CLK0_25M_OUT!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\ETH_CLK0_25M_OUT\!!
S!DDR3_A14!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\DDR3_A14\!!
S!DDR3_BA2!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\DDR3_BA2\!!
S!DDR3_A6!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\DDR3_A6\!!
S!DDR3_A2!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\DDR3_A2\!!
S!RMII0_RST!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\RMII0_RST\!!
S!DDR3_ODT!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\DDR3_ODT\!!
S!DDR3_A3!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\DDR3_A3\!!
S!DDR3_BA1!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\DDR3_BA1\!!
S!DDR3_CSN!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\DDR3_CSN\!!
S!VDDIO_RMII0!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\VDDIO_RMII0\!1.8V!
S!DDR3_A5!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\DDR3_A5\!!
S!DDR3_A11!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\DDR3_A11\!!
S!DDR3_A1!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\DDR3_A1\!!
S!DDR3_A8!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\DDR3_A8\!!
S!DDR3_A13!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\DDR3_A13\!!
S!DDR3_CASN!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\DDR3_CASN\!!
S!VDDIO_RMII1!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\VDDIO_RMII1\!1.8V!
S!DDR3_A10!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\DDR3_A10\!!
S!DDR3_BA0!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\DDR3_BA0\!!
S!N16785709!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\N16785709\!!
S!DDR3_RST!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\DDR3_RST\!!
S!DDR3_CLKN!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\DDR3_CLKN\!!
S!DDR3_A0!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\DDR3_A0\!!
S!N16785482!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\N16785482\!!
S!N16785446!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\N16785446\!!
S!RMII1_RST!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\RMII1_RST\!!
S!ETH_CLK1_25M_OUT!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\ETH_CLK1_25M_OUT\!!
S!DDR3_CKE!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\DDR3_CKE\!!
S!N16785007!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\N16785007\!!
S!EMMC_RSTN!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\EMMC_RSTN\!!
S!VDD_1V8!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\VDD_1V8\!1.8V!
S!N16792429!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\N16792429\!!
S!DDR_D10!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\DDR_D10\!!
S!DDR_D9!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\DDR_D9\!!
S!DDR_D7!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\DDR_D7\!!
S!DDR_D3!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\DDR_D3\!!
S!RMII1_CLK!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\RMII1_CLK\!!
S!DDR_D13!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\DDR_D13\!!
S!DDR_D8!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\DDR_D8\!!
S!DDR_DM1!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\DDR_DM1\!!
S!DDR_D11!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\DDR_D11\!!
S!DDR_DQS1N!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\DDR_DQS1N\!!
S!DDR_D4!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\DDR_D4\!!
S!DDR_D14!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\DDR_D14\!!
S!DDR_DQS0P!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\DDR_DQS0P\!!
S!DDR_D15!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\DDR_D15\!!
S!DDR_D0!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\DDR_D0\!!
S!DDR_D6!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\DDR_D6\!!
S!DDR_DQS0N!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\DDR_DQS0N\!!
S!DDR_D12!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\DDR_D12\!!
S!DDR_DQS1P!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\DDR_DQS1P\!!
S!DDR_DM0!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\DDR_DM0\!!
S!DDR_D2!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\DDR_D2\!!
S!DDR_D1!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\DDR_D1\!!
S!DDR_D5!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\DDR_D5\!!
S!GNSS_COM1_TX!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\GNSS_COM1_TX\!!
S!N16780119!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\N16780119\!!
S!DDR3_CLKP!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\DDR3_CLKP\!!
S!GNSS_COM3_RX!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\GNSS_COM3_RX\!!
S!GNSS_COM1_RX!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\GNSS_COM1_RX\!!
S!GNSS_COM2_RX!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\GNSS_COM2_RX\!!
S!VDDCR_RMII1!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\VDDCR_RMII1\!1.2V!
S!GNSS_COM3_TX!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\GNSS_COM3_TX\!!
S!GNSS_COM2_TX!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\GNSS_COM2_TX\!!
S!PPS!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\PPS\!!
S!VDD_GNSS!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\VDD_GNSS\!3.3V!
S!ANT2!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\ANT2\!!
S!ANT1!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\ANT1\!!
S!N61267!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\N61267\!!
S!N16777370!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\N16777370\!!
S!RMII0_RXDV_CRS!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\RMII0_RXDV_CRS\!!
S!DDR3_VREF_CA!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\DDR3_VREF_CA\!0.675V!
S!RMII0_MDIO!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\RMII0_MDIO\!!
S!RMII0_MDC!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\RMII0_MDC\!!
S!DDR3_VREF_DQ!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\DDR3_VREF_DQ\!0.675V!
S!N61054!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\N61054\!!
S!RMII0_TXEN!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\RMII0_TXEN\!!
S!RMII0_TXD1!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\RMII0_TXD1\!!
S!RMII0_TXD0!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\RMII0_TXD0\!!
S!VDDCR_RMII0!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\VDDCR_RMII0\!1.2V!
S!RMII0_CLK!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\RMII0_CLK\!!
S!RMII0_RXD1!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\RMII0_RXD1\!!
S!RMII0_RXD0!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\RMII0_RXD0\!!
S!RMII1_RXDV_CRS!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\RMII1_RXDV_CRS\!!
S!RMII1_MDC!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\RMII1_MDC\!!
S!RMII1_TXEN!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\RMII1_TXEN\!!
S!RMII1_TXD1!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\RMII1_TXD1\!!
S!RMII1_TXD0!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\RMII1_TXD0\!!
S!RMII1_RXD0!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\RMII1_RXD0\!!
S!RMII1_RXD1!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\RMII1_RXD1\!!
S!RMII1_MDIO!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\RMII1_MDIO\!!
S!EMMC_CLK!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\EMMC_CLK\!!
S!VDDA_RMII1!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\VDDA_RMII1\!3.3V!
S!VCC_DDR!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\VCC_DDR\!1.35V!
S!VDDA_RMII0!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\VDDA_RMII0\!3.3V!
S!VDD_3V3!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\VDD_3V3\!3.3V!
S!EMMC_CMD!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\EMMC_CMD\!!
S!EMMC_D1!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\EMMC_D1\!!
S!EMMC_D0!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\EMMC_D0\!!
S!EMMC_D3!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\EMMC_D3\!!
S!N16786486!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\N16786486\!!
S!EMMC_D2!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\EMMC_D2\!!
S!EMMC_CLKOUT!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\EMMC_CLKOUT\!!
S!N16786382!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\N16786382\!!
S!DDR_VREF_DQ!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\DDR_VREF_DQ\!!
S!DDR_VREF_CA!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\DDR_VREF_CA\!!
S!N16786362!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\N16786362\!!
S!VIN!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\VIN\!5V!
S!SW!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\SW\!3.3V!
S!V_BCKP!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\V_BCKP\!3.3V!
S!VCC_1V8!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\VCC_1V8\!1.5V!
S!VDD_0V9!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\VDD_0V9\!0.9V!
S!N19203!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\N19203\!1.5V!
S!N19188!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\N19188\!1.5V!
S!VDD_CPU!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\VDD_CPU\!0.95V!
S!GND!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\GND\!0.0V!