diff --git a/Core.SchDoc b/Core.SchDoc index 18d9423..03c25cb 100644 Binary files a/Core.SchDoc and b/Core.SchDoc differ diff --git a/LAN.SchDoc b/LAN.SchDoc index 82e4d8c..d1241a5 100644 Binary files a/LAN.SchDoc and b/LAN.SchDoc differ diff --git a/Project Outputs for rk3506_hw/Design Rule Check - PCB1.html b/Project Outputs for rk3506_hw/Design Rule Check - PCB1.html index b913c92..2fce8d9 100644 --- a/Project Outputs for rk3506_hw/Design Rule Check - PCB1.html +++ b/Project Outputs for rk3506_hw/Design Rule Check - PCB1.html @@ -219,17 +219,17 @@ Date: -2026/7/26 +2026/8/6 Time: -20:57:11 +14:34:29 Elapsed Time: -00:00:00 +00:00:01 Filename: @@ -247,10 +247,10 @@ Rule Violations: -0 +4 -

Summary

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Summary

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Warnings CountCount
Clearance Constraint (Gap=1mil) (All),(All)0Clearance Constraint (Gap=1mil) (All),(All)4
Clearance Constraint (Gap=7mil) (InNetClass('Signal')),(InNetClass('Signal'))Clearance Constraint (Gap=7mil) (InNetClass('Signal')),(InNetClass('Signal')) 0
Short-Circuit Constraint (Allowed=No) (All),(All)Short-Circuit Constraint (Allowed=No) (All),(All) 0
Un-Routed Net Constraint ( (All) )Un-Routed Net Constraint ( (All) ) 0
Modified Polygon (Allow modified: No), (Allow shelved: No)Modified Polygon (Allow modified: No), (Allow shelved: No) 0
Width Constraint (Min=5.9mil) (Max=6.2mil) (Preferred=5.9mil) (InNetClass('Signal'))Width Constraint (Min=5.9mil) (Max=6.2mil) (Preferred=5.9mil) (InNetClass('Signal')) 0
Width Constraint (Min=8mil) (Max=50mil) (Preferred=10mil) (InNetClass('PWR'))Width Constraint (Min=8mil) (Max=50mil) (Preferred=10mil) (InNetClass('PWR')) 0
Routing Topology Rule(Topology=Shortest) (All)Routing Topology Rule(Topology=Shortest) (All) 0
Power Plane Connect Rule(Direct Connect )(Expansion=20mil) (Conductor Width=10mil) (Air Gap=10mil) (Entries=4) (All)Power Plane Connect Rule(Direct Connect )(Expansion=20mil) (Conductor Width=10mil) (Air Gap=10mil) (Entries=4) (All) 0
Hole Size Constraint (Min=1mil) (Max=2000mil) (All)Hole Size Constraint (Min=1mil) (Max=2000mil) (All) 0
Hole To Hole Clearance (Gap=0mil) (All),(All)Hole To Hole Clearance (Gap=0mil) (All),(All) 0
Minimum Solder Mask Sliver (Gap=0mil) (All),(All)Minimum Solder Mask Sliver (Gap=0mil) (All),(All) 0
Silk To Solder Mask (Clearance=0mil) (IsPad),(All)Silk To Solder Mask (Clearance=0mil) (IsPad),(All) 0
Silk to Silk (Clearance=10mil) (All),(All)Silk to Silk (Clearance=10mil) (All),(All) 0
Net Antennae (Tolerance=0mil) (All)Net Antennae (Tolerance=0mil) (All) 0
Length Constraint (Min=1260mil) (Max=1280mil) (InNetClass('RMII0_TX'))Length Constraint (Min=1260mil) (Max=1280mil) (InNetClass('RMII0_TX')) 0
Length Constraint (Min=825mil) (Max=845mil) (InNetClass('RMII1_TX'))Length Constraint (Min=825mil) (Max=845mil) (InNetClass('RMII1_TX')) 0
Length Constraint (Min=0mil) (Max=100000mil) (InNetClass('All Nets'))Length Constraint (Min=0mil) (Max=100000mil) (InNetClass('All Nets')) 0
Height Constraint (Min=0mil) (Max=1000mil) (Prefered=500mil) (All)Height Constraint (Min=0mil) (Max=1000mil) (Prefered=500mil) (All) 0
Total04

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+ + + + + + + + + + + + + + + +
Clearance Constraint (Gap=1mil) (All),(All)
Clearance Constraint: (Collision < 1mil) Between Area Fill (820mil,2975mil) (925mil,3105mil) on Keep-Out Layer And Region (0 hole(s)) Top Layer
Clearance Constraint: (Collision < 1mil) Between Area Fill (820mil,2975mil) (925mil,3105mil) on Keep-Out Layer And Region (0 hole(s)) Top Layer
Clearance Constraint: (Collision < 1mil) Between Area Fill (820mil,2975mil) (925mil,3105mil) on Keep-Out Layer And Region (0 hole(s)) Top Layer
Clearance Constraint: (Collision < 1mil) Between Area Fill (820mil,2975mil) (925mil,3105mil) on Keep-Out Layer And Region (0 hole(s)) Top Layer

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