diff --git a/PCB1.PcbDoc b/PCB1.PcbDoc index 65720af..881a7ea 100644 Binary files a/PCB1.PcbDoc and b/PCB1.PcbDoc differ diff --git a/Project Outputs for rk3506_hw/Design Rule Check - PCB1.html b/Project Outputs for rk3506_hw/Design Rule Check - PCB1.html index 17a19c7..a163839 100644 --- a/Project Outputs for rk3506_hw/Design Rule Check - PCB1.html +++ b/Project Outputs for rk3506_hw/Design Rule Check - PCB1.html @@ -219,22 +219,22 @@ Date: -2026/7/16 +2026/7/17 Time: -21:12:25 +14:40:27 Elapsed Time: -00:00:00 +00:00:01 Filename: -C:\Project\polaris\rk3506_hw\PCB1.PcbDoc +D:\polaris\rk3506_nav_calculater\PCB1.PcbDoc @@ -247,10 +247,10 @@ Rule Violations: -0 +4 -

Summary

 +

Summary

 @@ -265,72 +265,100 @@ - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + + + + + + + + + + + + + - + -
Warnings CountCount
Clearance Constraint (Gap=10mil) (InNetClass('Signal')),(InNetClass('Signal'))0Clearance Constraint (Gap=7mil) (All),(All)4
Clearance Constraint (Gap=7mil) (All),(All)Clearance Constraint (Gap=7mil) (InNetClass('Signal')),(InNetClass('Signal')) 0
Short-Circuit Constraint (Allowed=No) (All),(All)Short-Circuit Constraint (Allowed=No) (All),(All) 0
Un-Routed Net Constraint ( (All) )Un-Routed Net Constraint ( (All) ) 0
Modified Polygon (Allow modified: No), (Allow shelved: No)Modified Polygon (Allow modified: No), (Allow shelved: No) 0
Width Constraint (Min=5.9mil) (Max=6.2mil) (Preferred=5.9mil) (InNetClass('Signal'))Width Constraint (Min=5.9mil) (Max=6.2mil) (Preferred=5.9mil) (InNetClass('Signal')) 0
Width Constraint (Min=8mil) (Max=50mil) (Preferred=10mil) (InNetClass('PWR'))Width Constraint (Min=8mil) (Max=50mil) (Preferred=10mil) (InNetClass('PWR')) 0
Routing Topology Rule(Topology=Shortest) (All)Routing Topology Rule(Topology=Shortest) (All) 0
Power Plane Connect Rule(Direct Connect )(Expansion=20mil) (Conductor Width=10mil) (Air Gap=10mil) (Entries=4) (All)Power Plane Connect Rule(Direct Connect )(Expansion=20mil) (Conductor Width=10mil) (Air Gap=10mil) (Entries=4) (All) 0
Hole Size Constraint (Min=1mil) (Max=2000mil) (All)Hole Size Constraint (Min=1mil) (Max=2000mil) (All) 0
Hole To Hole Clearance (Gap=0mil) (All),(All)Hole To Hole Clearance (Gap=0mil) (All),(All) 0
Minimum Solder Mask Sliver (Gap=0mil) (All),(All)Minimum Solder Mask Sliver (Gap=0mil) (All),(All) 0
Silk To Solder Mask (Clearance=0mil) (IsPad),(All)Silk To Solder Mask (Clearance=0mil) (IsPad),(All) 0
Silk to Silk (Clearance=10mil) (All),(All)Silk to Silk (Clearance=10mil) (All),(All) 0
Net Antennae (Tolerance=0mil) (All)Net Antennae (Tolerance=0mil) (All) 0
Height Constraint (Min=0mil) (Max=1000mil) (Prefered=500mil) (All)Length Constraint (Min=1260mil) (Max=1280mil) (InNetClass('RMII0_TX'))0
Length Constraint (Min=825mil) (Max=845mil) (InNetClass('RMII1_TX'))0
Length Constraint (Min=0mil) (Max=100000mil) (InNetClass('All Nets'))0
Height Constraint (Min=0mil) (Max=1000mil) (Prefered=500mil) (All) 0
Total04

+
+ + + + + + + + + + + + + + + +
Clearance Constraint (Gap=7mil) (All),(All)
Clearance Constraint: (Collision < 7mil) Between Area Fill (820mil,2975mil) (925mil,3105mil) on Keep-Out Layer And Region (0 hole(s)) Top Layer
Clearance Constraint: (Collision < 7mil) Between Area Fill (820mil,2975mil) (925mil,3105mil) on Keep-Out Layer And Region (0 hole(s)) Top Layer
Clearance Constraint: (Collision < 7mil) Between Area Fill (820mil,2975mil) (925mil,3105mil) on Keep-Out Layer And Region (0 hole(s)) Top Layer
Clearance Constraint: (Collision < 7mil) Between Area Fill (820mil,2975mil) (925mil,3105mil) on Keep-Out Layer And Region (0 hole(s)) Top Layer
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diff --git a/rk3506_hw.PrjPcb b/rk3506_hw.PrjPcb index 4a3efe5..8decfbc 100644 --- a/rk3506_hw.PrjPcb +++ b/rk3506_hw.PrjPcb @@ -33,7 +33,7 @@ FSMCodingStyle=eFMSDropDownList_OneProcess FSMEncodingStyle=eFMSDropDownList_OneHot IsProjectConflictPreventionWarningsEnabled=0 ConstraintManagerFlow=0 -IsVirtualBomDocumentRemoved=0 +IsVirtualBomDocumentRemoved=1 OutputPath= LogFolderPath= ManagedProjectGUID=