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index ff35fa4..82e4d8c 100644
Binary files a/LAN.SchDoc and b/LAN.SchDoc differ
diff --git a/PCB1.PcbDoc b/PCB1.PcbDoc
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Binary files a/PCB1.PcbDoc and b/PCB1.PcbDoc differ
diff --git a/Project Outputs for rk3506_hw/Design Rule Check - PCB1.html b/Project Outputs for rk3506_hw/Design Rule Check - PCB1.html
index cb834c7..b913c92 100644
--- a/Project Outputs for rk3506_hw/Design Rule Check - PCB1.html
+++ b/Project Outputs for rk3506_hw/Design Rule Check - PCB1.html
@@ -219,12 +219,12 @@
| Warnings |
Count |
@@ -265,79 +265,79 @@
Count |
-| Clearance Constraint (Gap=1mil) (All),(All) |
+Clearance Constraint (Gap=1mil) (All),(All) |
0 |
-| Clearance Constraint (Gap=7mil) (InNetClass('Signal')),(InNetClass('Signal')) |
+Clearance Constraint (Gap=7mil) (InNetClass('Signal')),(InNetClass('Signal')) |
0 |
-| Short-Circuit Constraint (Allowed=No) (All),(All) |
+Short-Circuit Constraint (Allowed=No) (All),(All) |
0 |
-| Un-Routed Net Constraint ( (All) ) |
+Un-Routed Net Constraint ( (All) ) |
0 |
-| Modified Polygon (Allow modified: No), (Allow shelved: No) |
+Modified Polygon (Allow modified: No), (Allow shelved: No) |
0 |
-| Width Constraint (Min=5.9mil) (Max=6.2mil) (Preferred=5.9mil) (InNetClass('Signal')) |
+Width Constraint (Min=5.9mil) (Max=6.2mil) (Preferred=5.9mil) (InNetClass('Signal')) |
0 |
-| Width Constraint (Min=8mil) (Max=50mil) (Preferred=10mil) (InNetClass('PWR')) |
+Width Constraint (Min=8mil) (Max=50mil) (Preferred=10mil) (InNetClass('PWR')) |
0 |
-| Routing Topology Rule(Topology=Shortest) (All) |
+Routing Topology Rule(Topology=Shortest) (All) |
0 |
-| Power Plane Connect Rule(Direct Connect )(Expansion=20mil) (Conductor Width=10mil) (Air Gap=10mil) (Entries=4) (All) |
+Power Plane Connect Rule(Direct Connect )(Expansion=20mil) (Conductor Width=10mil) (Air Gap=10mil) (Entries=4) (All) |
0 |
-| Hole Size Constraint (Min=1mil) (Max=2000mil) (All) |
+Hole Size Constraint (Min=1mil) (Max=2000mil) (All) |
0 |
-| Hole To Hole Clearance (Gap=0mil) (All),(All) |
+Hole To Hole Clearance (Gap=0mil) (All),(All) |
0 |
-| Minimum Solder Mask Sliver (Gap=0mil) (All),(All) |
+Minimum Solder Mask Sliver (Gap=0mil) (All),(All) |
0 |
-| Silk To Solder Mask (Clearance=0mil) (IsPad),(All) |
+Silk To Solder Mask (Clearance=0mil) (IsPad),(All) |
0 |
-| Silk to Silk (Clearance=10mil) (All),(All) |
+Silk to Silk (Clearance=10mil) (All),(All) |
0 |
-| Net Antennae (Tolerance=0mil) (All) |
+Net Antennae (Tolerance=0mil) (All) |
0 |
-| Length Constraint (Min=1260mil) (Max=1280mil) (InNetClass('RMII0_TX')) |
+Length Constraint (Min=1260mil) (Max=1280mil) (InNetClass('RMII0_TX')) |
0 |
-| Length Constraint (Min=825mil) (Max=845mil) (InNetClass('RMII1_TX')) |
+Length Constraint (Min=825mil) (Max=845mil) (InNetClass('RMII1_TX')) |
0 |
-| Length Constraint (Min=0mil) (Max=100000mil) (InNetClass('All Nets')) |
+Length Constraint (Min=0mil) (Max=100000mil) (InNetClass('All Nets')) |
0 |
-| Height Constraint (Min=0mil) (Max=1000mil) (Prefered=500mil) (All) |
+Height Constraint (Min=0mil) (Max=1000mil) (Prefered=500mil) (All) |
0 |