Add RXv1 port.
This commit is contained in:
Tiejun Zhou
158
ports/rxv1/gnu/src/tx_thread_context_save.S
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158
ports/rxv1/gnu/src/tx_thread_context_save.S
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;/**************************************************************************/
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;/* */
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;/* Copyright (c) Microsoft Corporation. All rights reserved. */
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;/* */
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;/* This software is licensed under the Microsoft Software License */
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;/* Terms for Microsoft Azure RTOS. Full text of the license can be */
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;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
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;/* and in the root directory of this software. */
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;/* */
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;/**************************************************************************/
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;
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;
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;/**************************************************************************/
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;/**************************************************************************/
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;/** */
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;/** ThreadX Component */
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;/** */
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;/** Thread */
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;/** */
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;/**************************************************************************/
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;/**************************************************************************/
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.global __tx_thread_system_state
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.global __tx_thread_current_ptr
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.global __tx_thread_system_stack_ptr
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.text
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;/**************************************************************************/
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;/* */
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;/* FUNCTION RELEASE */
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;/* */
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;/* _tx_thread_context_save RXv1/GNURX */
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;/* 6.1.8 */
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;/* AUTHOR */
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;/* */
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;/* William E. Lamie, Microsoft Corporation */
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;/* */
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;/* DESCRIPTION */
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;/* */
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;/* This function saves the context of an executing thread in the */
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;/* beginning of interrupt processing. The function also ensures that */
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;/* the system stack is used upon return to the calling ISR. */
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;/* */
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;/* INPUT */
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;/* */
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;/* None */
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;/* */
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;/* OUTPUT */
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;/* */
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;/* None */
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;/* */
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;/* CALLS */
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;/* */
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;/* None */
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;/* */
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;/* CALLED BY */
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;/* */
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;/* ISRs */
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;/* */
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;/* RELEASE HISTORY */
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;/* */
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;/* DATE NAME DESCRIPTION */
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;/* */
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;/* 08-02-2021 William E. Lamie Initial Version 6.1.8 */
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;/* */
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;/**************************************************************************/
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;VOID _tx_thread_context_save(VOID)
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;{
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.global __tx_thread_context_save
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__tx_thread_context_save:
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;
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; /* Upon entry to this routine, it is assumed that interrupts are locked
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; out and the (interrupt) stack frame looks like the following:
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;
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; (lower address) SP -> [return address of this call]
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; SP+4 -> Saved R1
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; SP+8 -> Saved R2
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; SP+12-> Interrupted PC
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; SP+16-> Interrupted PSW
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;
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; /* Check for a nested interrupt condition. */
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; if (_tx_thread_system_state++)
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; {
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;
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MOV.L #__tx_thread_system_state, R1 ; pick up address of system state
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MOV.L [R1], R2 ; pick up system state
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CMP #0, R2 ; 0 -> no nesting
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BEQ __tx_thread_not_nested_save
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;
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; /* Nested interrupt condition. */
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;
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ADD #1, r2 ; _tx_thread_system_state++
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MOV.L r2, [r1]
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;
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; /* Save the rest of the scratch registers on the interrupt stack and return to the
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; calling ISR. */
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POP R1 ; recuperate return address from stack
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PUSHM R3-R5
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PUSHM R14-R15
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JMP R1 ; return address was preserved in R1
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;
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__tx_thread_not_nested_save:
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; }
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;
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; /* Otherwise, not nested, check to see if a thread was running. */
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; else if (_tx_thread_current_ptr)
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; {
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;
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ADD #1, R2 ; _tx_thread_system_state++
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MOV.L R2, [R1]
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MOV.L #__tx_thread_current_ptr, R2 ; Pickup current thread pointer
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MOV.L [R2], R2
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CMP #0,R2 ; Is it NULL?
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BEQ __tx_thread_idle_system_save ; Yes, idle system is running - idle restore
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;
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; /* Move stack frame over to the current threads stack. */
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; /* complete stack frame with registers not saved yet (R3-R5, R14-R15, FPSW) */
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;
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MVFC USP, R1 ; pick up user stack pointer
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MOV.L 16[R0], R2
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MOV.L R2, [-R1] ; save PSW on thread stack
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MOV.L 12[R0], R2
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MOV.L R2, [-R1] ; save PC on thread stack
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MOV.L 8[R0], R2
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MOV.L R2, [-R1] ; save R2 on thread stack
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MOV.L 4[R0], R2
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MOV.L R2, [-R1] ; save R1 on thread stack
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MOV.L R5, [-R1] ; save R5 on thread stack
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MOV.L R4, [-R1] ; save R4 on thread stack
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MOV.L R3, [-R1] ; save R3 on thread stack
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MOV.L R15, [-R1] ; save R15 on thread stack
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MOV.L R14, [-R1] ; save R14 on thread stack
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POP R2 ; pick up return address from interrupt stack
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ADD #16, R0, R0 ; correct interrupt stack pointer back to the bottom
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MVTC R1, USP ; set user/thread stack pointer
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JMP R2 ; return to ISR
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; }
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; else
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; {
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;
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__tx_thread_idle_system_save:
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;
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; /* Interrupt occurred in the scheduling loop. */
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;
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POP R1 ; pick up return address
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ADD #16, R0, R0 ; correct interrupt stack pointer back to the bottom (PC), don't care about saved registers
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JMP R1 ; return to caller
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;
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; }
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;}
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.end
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