Release 6.1.5
This commit is contained in:
@@ -26,7 +26,7 @@
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/* PORT SPECIFIC C INFORMATION RELEASE */
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/* */
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/* tx_port.h Cortex-M33/AC6 */
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/* 6.1 */
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/* 6.1.5 */
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/* */
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/* AUTHOR */
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/* */
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@@ -47,7 +47,10 @@
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/* */
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/* DATE NAME DESCRIPTION */
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/* */
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/* 09-30-2020 Scott Larson Initial Version 6.1 */
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/* 09-30-2020 Scott Larson Initial Version 6.1 */
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/* 03-02-2021 Scott Larson Modified comment(s), added */
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/* ULONG64_DEFINED, */
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/* resulting in version 6.1.5 */
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/* */
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/**************************************************************************/
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@@ -82,6 +85,7 @@ typedef unsigned long ULONG;
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typedef unsigned long long ULONG64;
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typedef short SHORT;
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typedef unsigned short USHORT;
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#define ULONG64_DEFINED
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/* Function prototypes for this port. */
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struct TX_THREAD_STRUCT;
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@@ -15,7 +15,8 @@ Building the ThreadX library is easy; simply set the ThreadX_Library project
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as active, then then build the library. You should now observe the compilation
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and assembly of the ThreadX library. This project build produces the ThreadX
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library file ThreadX_Library.lib.
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Files tx_thread_stack_error_handler.c and tx_thread_stack_error_notify.c
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replace the common files of the same name.
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3. Demonstration System
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@@ -53,80 +54,80 @@ tx_thread_stack_ptr in the associated thread control block TX_THREAD.
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Non-FPU Stack Frame:
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Stack Offset Stack Contents
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Stack Offset Stack Contents
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0x00 LR Interrupted LR (LR at time of PENDSV)
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0x04 r4
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0x08 r5
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0x0C r6
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0x10 r7
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0x14 r8
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0x18 r9
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0x1C r10
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0x20 r11
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0x24 r0 (Hardware stack starts here!!)
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0x28 r1
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0x2C r2
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0x30 r3
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0x34 r12
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0x38 lr
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0x3C pc
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0x40 xPSR
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0x00 LR Interrupted LR (LR at time of PENDSV)
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0x04 r4 Software stacked GP registers
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0x08 r5
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0x0C r6
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0x10 r7
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0x14 r8
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0x18 r9
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0x1C r10
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0x20 r11
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0x24 r0 Hardware stacked registers
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0x28 r1
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0x2C r2
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0x30 r3
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0x34 r12
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0x38 lr
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0x3C pc
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0x40 xPSR
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FPU Stack Frame (only interrupted thread with FPU enabled):
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Stack Offset Stack Contents
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Stack Offset Stack Contents
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0x00 LR Interrupted LR (LR at time of PENDSV)
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0x04 s0
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0x08 s1
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0x0C s2
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0x10 s3
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0x14 s4
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0x18 s5
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0x1C s6
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0x20 s7
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0x24 s8
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0x28 s9
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0x2C s10
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0x30 s11
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0x34 s12
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0x38 s13
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0x3C s14
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0x40 s15
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0x44 s16
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0x48 s17
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0x4C s18
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0x50 s19
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0x54 s20
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0x58 s21
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0x5C s22
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0x60 s23
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0x64 s24
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0x68 s25
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0x6C s26
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0x70 s27
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0x74 s28
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0x78 s29
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0x7C s30
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0x80 s31
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0x84 fpscr
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0x88 r4
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0x8C r5
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0x90 r6
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0x94 r7
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0x98 r8
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0x9C r9
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0xA0 r10
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0xA4 r11
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0xA8 r0 (Hardware stack starts here!!)
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0xAC r1
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0xB0 r2
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0xB4 r3
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0xB8 r12
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0xBC lr
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0xC0 pc
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0xC4 xPSR
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0x00 LR Interrupted LR (LR at time of PENDSV)
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0x04 s16 Software stacked FPU registers
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0x08 s17
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0x0C s18
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0x10 s19
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0x14 s20
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0x18 s21
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0x1C s22
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0x20 s23
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0x24 s24
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0x28 s25
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0x2C s26
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0x30 s27
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0x34 s28
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0x38 s29
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0x3C s30
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0x40 s31
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0x44 r4 Software stacked registers
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0x48 r5
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0x4C r6
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0x50 r7
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0x54 r8
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0x58 r9
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0x5C r10
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0x60 r11
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0x64 r0 Hardware stacked registers
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0x68 r1
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0x6C r2
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0x70 r3
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0x74 r12
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0x78 lr
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0x7C pc
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0x80 xPSR
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0x84 s0 Hardware stacked FPU registers
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0x88 s1
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0x8C s2
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0x90 s3
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0x94 s4
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0x98 s5
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0x9C s6
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0xA0 s7
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0xA4 s8
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0xA8 s9
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0xAC s10
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0xB0 s11
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0xB4 s12
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0xB8 s13
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0xBC s14
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0xC0 s15
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0xC4 fpscr
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6. Improving Performance
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