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Release 6.1.5

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This commit is contained in:
Yuxin Zhou
2021-03-05 05:38:33 +00:00
parent 32e3b3b25f
commit 10a7932b9d
184 changed files with 15541 additions and 1830 deletions
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136
ports/cortex_m7/ac5/readme_threadx.txt
View File

@@ -57,78 +57,80 @@ tx_thread_stack_ptr in the associated thread control block TX_THREAD.
Non-FPU Stack Frame:
Stack Offset Stack Contents
Stack Offset Stack Contents
0x00 r4
0x04 r5
0x08 r6
0x0C r7
0x10 r8
0x14 r9
0x18 r10
0x1C r11
0x20 r0 (Hardware stack starts here!!)
0x24 r1
0x28 r2
0x2C r3
0x30 r12
0x34 lr
0x38 pc
0x3C xPSR
0x00 LR Interrupted LR (LR at time of PENDSV)
0x04 r4 Software stacked GP registers
0x08 r5
0x0C r6
0x10 r7
0x14 r8
0x18 r9
0x1C r10
0x20 r11
0x24 r0 Hardware stacked registers
0x28 r1
0x2C r2
0x30 r3
0x34 r12
0x38 lr
0x3C pc
0x40 xPSR
FPU Stack Frame (only interrupted thread with FPU enabled):
Stack Offset Stack Contents
Stack Offset Stack Contents
0x00 s0
0x04 s1
0x08 s2
0x0C s3
0x10 s4
0x14 s5
0x18 s6
0x1C s7
0x20 s8
0x24 s9
0x28 s10
0x2C s11
0x30 s12
0x34 s13
0x38 s14
0x3C s15
0x40 s16
0x44 s17
0x48 s18
0x4C s19
0x50 s20
0x54 s21
0x58 s22
0x5C s23
0x60 s24
0x64 s25
0x68 s26
0x6C s27
0x70 s28
0x74 s29
0x78 s30
0x7C s31
0x80 fpscr
0x84 r4
0x88 r5
0x8C r6
0x90 r7
0x94 r8
0x98 r9
0x9C r10 (sl)
0xA0 r11
0xA4 r0 (Hardware stack starts here!!)
0xA8 r1
0xAC r2
0xB0 r3
0xB4 r12
0xB8 lr
0xBC pc
0xC0 xPSR
0x00 LR Interrupted LR (LR at time of PENDSV)
0x04 s16 Software stacked FPU registers
0x08 s17
0x0C s18
0x10 s19
0x14 s20
0x18 s21
0x1C s22
0x20 s23
0x24 s24
0x28 s25
0x2C s26
0x30 s27
0x34 s28
0x38 s29
0x3C s30
0x40 s31
0x44 r4 Software stacked registers
0x48 r5
0x4C r6
0x50 r7
0x54 r8
0x58 r9
0x5C r10
0x60 r11
0x64 r0 Hardware stacked registers
0x68 r1
0x6C r2
0x70 r3
0x74 r12
0x78 lr
0x7C pc
0x80 xPSR
0x84 s0 Hardware stacked FPU registers
0x88 s1
0x8C s2
0x90 s3
0x94 s4
0x98 s5
0x9C s6
0xA0 s7
0xA4 s8
0xA8 s9
0xAC s10
0xB0 s11
0xB4 s12
0xB8 s13
0xBC s14
0xC0 s15
0xC4 fpscr
5. Improving Performance

27
ports/cortex_m7/ac5/src/tx_thread_schedule.s
View File

@@ -30,6 +30,10 @@
IMPORT _tx_execution_thread_enter
IMPORT _tx_execution_thread_exit
ENDIF
IF :DEF:TX_LOW_POWER
IMPORT tx_low_power_enter
IMPORT tx_low_power_exit
ENDIF
;
;
AREA ||.text||, CODE, READONLY
@@ -39,7 +43,7 @@
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_schedule Cortex-M7/AC5 */
;/* 6.1 */
;/* 6.1.5 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
@@ -72,7 +76,10 @@
;/* */
;/* DATE NAME DESCRIPTION */
;/* */
;/* 09-30-2020 William E. Lamie Initial Version 6.1 */
;/* 09-30-2020 William E. Lamie Initial Version 6.1 */
;/* 03-02-2021 Scott Larson Modified comment(s), add */
;/* low power code, */
;/* resulting in version 6.1.5 */
;/* */
;/**************************************************************************/
;VOID _tx_thread_schedule(VOID)
@@ -237,11 +244,25 @@ __tx_ts_wait
LDR r1, [r2] ; Pickup the next thread to execute pointer
STR r1, [r0] ; Store it in the current pointer
CBNZ r1, __tx_ts_ready ; If non-NULL, a new thread is ready!
IF :DEF:TX_ENABLE_WFI
IF:DEF:TX_LOW_POWER
PUSH {r0-r3}
BL tx_low_power_enter ; Possibly enter low power mode
POP {r0-r3}
ENDIF
IF:DEF:TX_ENABLE_WFI
DSB ; Ensure no outstanding memory transactions
WFI ; Wait for interrupt
ISB ; Ensure pipeline is flushed
ENDIF
IF:DEF:TX_LOW_POWER
PUSH {r0-r3}
BL tx_low_power_exit ; Exit low power mode
POP {r0-r3}
ENDIF
CPSIE i ; Enable interrupts
B __tx_ts_wait ; Loop to continue waiting
;

92
ports/cortex_m7/ac6/readme_threadx.txt
View File

@@ -55,24 +55,82 @@ ThreadX. The top of the suspended thread's stack is pointed to by
tx_thread_stack_ptr in the associated thread control block TX_THREAD.
Stack Offset Stack Contents
Non-FPU Stack Frame:
0x00 r4
0x04 r5
0x08 r6
0x0C r7
0x10 r8
0x14 r9
0x18 r10
0x1C r11
0x20 r0 (Hardware stack starts here!!)
0x24 r1
0x28 r2
0x2C r3
0x30 r12
0x34 lr
0x38 pc
0x3C xPSR
Stack Offset Stack Contents
0x00 LR Interrupted LR (LR at time of PENDSV)
0x04 r4 Software stacked GP registers
0x08 r5
0x0C r6
0x10 r7
0x14 r8
0x18 r9
0x1C r10
0x20 r11
0x24 r0 Hardware stacked registers
0x28 r1
0x2C r2
0x30 r3
0x34 r12
0x38 lr
0x3C pc
0x40 xPSR
FPU Stack Frame (only interrupted thread with FPU enabled):
Stack Offset Stack Contents
0x00 LR Interrupted LR (LR at time of PENDSV)
0x04 s16 Software stacked FPU registers
0x08 s17
0x0C s18
0x10 s19
0x14 s20
0x18 s21
0x1C s22
0x20 s23
0x24 s24
0x28 s25
0x2C s26
0x30 s27
0x34 s28
0x38 s29
0x3C s30
0x40 s31
0x44 r4 Software stacked registers
0x48 r5
0x4C r6
0x50 r7
0x54 r8
0x58 r9
0x5C r10
0x60 r11
0x64 r0 Hardware stacked registers
0x68 r1
0x6C r2
0x70 r3
0x74 r12
0x78 lr
0x7C pc
0x80 xPSR
0x84 s0 Hardware stacked FPU registers
0x88 s1
0x8C s2
0x90 s3
0x94 s4
0x98 s5
0x9C s6
0xA0 s7
0xA4 s8
0xA8 s9
0xAC s10
0xB0 s11
0xB4 s12
0xB8 s13
0xBC s14
0xC0 s15
0xC4 fpscr
6. Improving Performance

26
ports/cortex_m7/ac6/src/tx_thread_schedule.S
View File

@@ -25,6 +25,11 @@
.global _tx_thread_execute_ptr
.global _tx_timer_time_slice
.global _tx_thread_system_stack_ptr
#ifdef TX_LOW_POWER
.global tx_low_power_enter
.global tx_low_power_exit
#endif
@
@
.text
@@ -35,7 +40,7 @@
@/* FUNCTION RELEASE */
@/* */
@/* _tx_thread_schedule Cortex-M7/AC6 */
@/* 6.1 */
@/* 6.1.5 */
@/* AUTHOR */
@/* */
@/* William E. Lamie, Microsoft Corporation */
@@ -68,7 +73,10 @@
@/* */
@/* DATE NAME DESCRIPTION */
@/* */
@/* 09-30-2020 William E. Lamie Initial Version 6.1 */
@/* 09-30-2020 William E. Lamie Initial Version 6.1 */
@/* 03-02-2021 Scott Larson Modified comment(s), add */
@/* low power code, */
@/* resulting in version 6.1.5 */
@/* */
@/**************************************************************************/
@VOID _tx_thread_schedule(VOID)
@@ -237,11 +245,25 @@ __tx_ts_wait:
LDR r1, [r2] @ Pickup the next thread to execute pointer
STR r1, [r0] @ Store it in the current pointer
CBNZ r1, __tx_ts_ready @ If non-NULL, a new thread is ready!
#ifdef TX_LOW_POWER
PUSH {r0-r3}
BL tx_low_power_enter @ Possibly enter low power mode
POP {r0-r3}
#endif
#ifdef TX_ENABLE_WFI
DSB @ Ensure no outstanding memory transactions
WFI @ Wait for interrupt
ISB @ Ensure pipeline is flushed
#endif
#ifdef TX_LOW_POWER
PUSH {r0-r3}
BL tx_low_power_exit @ Exit low power mode
POP {r0-r3}
#endif
CPSIE i @ Enable interrupts
B __tx_ts_wait @ Loop to continue waiting
@

136
ports/cortex_m7/ghs/readme_threadx.txt
View File

@@ -81,78 +81,80 @@ tx_thread_stack_ptr in the associated thread control block TX_THREAD.
Non-FPU Stack Frame:
Stack Offset Stack Contents
Stack Offset Stack Contents
0x00 r4
0x04 r5
0x08 r6
0x0C r7
0x10 r8
0x14 r9
0x18 r10
0x1C r11
0x20 r0 (Hardware stack starts here!!)
0x24 r1
0x28 r2
0x2C r3
0x30 r12
0x34 lr
0x38 pc
0x3C xPSR
0x00 LR Interrupted LR (LR at time of PENDSV)
0x04 r4 Software stacked GP registers
0x08 r5
0x0C r6
0x10 r7
0x14 r8
0x18 r9
0x1C r10
0x20 r11
0x24 r0 Hardware stacked registers
0x28 r1
0x2C r2
0x30 r3
0x34 r12
0x38 lr
0x3C pc
0x40 xPSR
FPU Stack Frame (only interrupted thread with FPU enabled):
Stack Offset Stack Contents
Stack Offset Stack Contents
0x00 s0
0x04 s1
0x08 s2
0x0C s3
0x10 s4
0x14 s5
0x18 s6
0x1C s7
0x20 s8
0x24 s9
0x28 s10
0x2C s11
0x30 s12
0x34 s13
0x38 s14
0x3C s15
0x40 s16
0x44 s17
0x48 s18
0x4C s19
0x50 s20
0x54 s21
0x58 s22
0x5C s23
0x60 s24
0x64 s25
0x68 s26
0x6C s27
0x70 s28
0x74 s29
0x78 s30
0x7C s31
0x80 fpscr
0x84 r4
0x88 r5
0x8C r6
0x90 r7
0x94 r8
0x98 r9
0x9C r10 (sl)
0xA0 r11
0xA4 r0 (Hardware stack starts here!!)
0xA8 r1
0xAC r2
0xB0 r3
0xB4 r12
0xB8 lr
0xBC pc
0xC0 xPSR
0x00 LR Interrupted LR (LR at time of PENDSV)
0x04 s16 Software stacked FPU registers
0x08 s17
0x0C s18
0x10 s19
0x14 s20
0x18 s21
0x1C s22
0x20 s23
0x24 s24
0x28 s25
0x2C s26
0x30 s27
0x34 s28
0x38 s29
0x3C s30
0x40 s31
0x44 r4 Software stacked registers
0x48 r5
0x4C r6
0x50 r7
0x54 r8
0x58 r9
0x5C r10
0x60 r11
0x64 r0 Hardware stacked registers
0x68 r1
0x6C r2
0x70 r3
0x74 r12
0x78 lr
0x7C pc
0x80 xPSR
0x84 s0 Hardware stacked FPU registers
0x88 s1
0x8C s2
0x90 s3
0x94 s4
0x98 s5
0x9C s6
0xA0 s7
0xA4 s8
0xA8 s9
0xAC s10
0xB0 s11
0xB4 s12
0xB8 s13
0xBC s14
0xC0 s15
0xC4 fpscr
7. Improving Performance

21
ports/cortex_m7/ghs/src/tx_thread_schedule.arm
View File

@@ -28,7 +28,7 @@
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_schedule Cortex-M7/GHS */
;/* 6.1 */
;/* 6.1.5 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
@@ -61,7 +61,10 @@
;/* */
;/* DATE NAME DESCRIPTION */
;/* */
;/* 09-30-2020 William E. Lamie Initial Version 6.1 */
;/* 09-30-2020 William E. Lamie Initial Version 6.1 */
;/* 03-02-2021 Scott Larson Modified comment(s), add */
;/* low power code, */
;/* resulting in version 6.1.5 */
;/* */
;/**************************************************************************/
;VOID _tx_thread_schedule(VOID)
@@ -230,11 +233,25 @@ __tx_ts_wait:
LDR r1, [r2] ; Pickup the next thread to execute pointer
STR r1, [r0] ; Store it in the current pointer
CBNZ r1, __tx_ts_ready ; If non-NULL, a new thread is ready!
#ifdef TX_LOW_POWER
PUSH {r0-r3}
BL tx_low_power_enter ; Possibly enter low power mode
POP {r0-r3}
#endif
#ifdef TX_ENABLE_WFI
DSB ; Ensure no outstanding memory transactions
WFI ; Wait for interrupt
ISB ; Ensure pipeline is flushed
#endif
#ifdef TX_LOW_POWER
PUSH {r0-r3}
BL tx_low_power_exit ; Exit low power mode
POP {r0-r3}
#endif
CPSIE i ; Enable interrupts
B __tx_ts_wait ; Loop to continue waiting
;

0
ports/cortex_m7/gnu/CMakeLists.txt Normal file → Executable file
View File

92
ports/cortex_m7/gnu/readme_threadx.txt
View File

@@ -52,24 +52,82 @@ ThreadX. The top of the suspended thread's stack is pointed to by
tx_thread_stack_ptr in the associated thread control block TX_THREAD.
Stack Offset Stack Contents
Non-FPU Stack Frame:
0x00 r4
0x04 r5
0x08 r6
0x0C r7
0x10 r8
0x14 r9
0x18 r10
0x1C r11
0x20 r0 (Hardware stack starts here!!)
0x24 r1
0x28 r2
0x2C r3
0x30 r12
0x34 lr
0x38 pc
0x3C xPSR
Stack Offset Stack Contents
0x00 LR Interrupted LR (LR at time of PENDSV)
0x04 r4 Software stacked GP registers
0x08 r5
0x0C r6
0x10 r7
0x14 r8
0x18 r9
0x1C r10
0x20 r11
0x24 r0 Hardware stacked registers
0x28 r1
0x2C r2
0x30 r3
0x34 r12
0x38 lr
0x3C pc
0x40 xPSR
FPU Stack Frame (only interrupted thread with FPU enabled):
Stack Offset Stack Contents
0x00 LR Interrupted LR (LR at time of PENDSV)
0x04 s16 Software stacked FPU registers
0x08 s17
0x0C s18
0x10 s19
0x14 s20
0x18 s21
0x1C s22
0x20 s23
0x24 s24
0x28 s25
0x2C s26
0x30 s27
0x34 s28
0x38 s29
0x3C s30
0x40 s31
0x44 r4 Software stacked registers
0x48 r5
0x4C r6
0x50 r7
0x54 r8
0x58 r9
0x5C r10
0x60 r11
0x64 r0 Hardware stacked registers
0x68 r1
0x6C r2
0x70 r3
0x74 r12
0x78 lr
0x7C pc
0x80 xPSR
0x84 s0 Hardware stacked FPU registers
0x88 s1
0x8C s2
0x90 s3
0x94 s4
0x98 s5
0x9C s6
0xA0 s7
0xA4 s8
0xA8 s9
0xAC s10
0xB0 s11
0xB4 s12
0xB8 s13
0xBC s14
0xC0 s15
0xC4 fpscr
5. Improving Performance

0
ports/cortex_m7/gnu/src/tx_thread_context_restore.S Executable file → Normal file
View File

0
ports/cortex_m7/gnu/src/tx_thread_context_save.S Executable file → Normal file
View File

0
ports/cortex_m7/gnu/src/tx_thread_interrupt_control.S Executable file → Normal file
View File

29
ports/cortex_m7/gnu/src/tx_thread_schedule.S Executable file → Normal file
View File

@@ -27,6 +27,10 @@
.global _tx_thread_system_stack_ptr
.global _tx_execution_thread_enter
.global _tx_execution_thread_exit
#ifdef TX_LOW_POWER
.global tx_low_power_enter
.global tx_low_power_exit
#endif
@
@
.text
@@ -37,7 +41,7 @@
@/* FUNCTION RELEASE */
@/* */
@/* _tx_thread_schedule Cortex-M7/GNU */
@/* 6.1 */
@/* 6.1.5 */
@/* AUTHOR */
@/* */
@/* William E. Lamie, Microsoft Corporation */
@@ -70,9 +74,12 @@
@/* */
@/* DATE NAME DESCRIPTION */
@/* */
@/* 05-19-2020 William E. Lamie Initial Version 6.0 */
@/* 09-30-2020 William E. Lamie Modified comment(s), */
@/* resulting in version 6.1 */
@/* 05-19-2020 William E. Lamie Initial Version 6.0 */
@/* 09-30-2020 William E. Lamie Modified comment(s), */
@/* resulting in version 6.1 */
@/* 03-02-2021 Scott Larson Modified comment(s), add */
@/* low power code, */
@/* resulting in version 6.1.5 */
@/* */
@/**************************************************************************/
@VOID _tx_thread_schedule(VOID)
@@ -241,11 +248,25 @@ __tx_ts_wait:
LDR r1, [r2] @ Pickup the next thread to execute pointer
STR r1, [r0] @ Store it in the current pointer
CBNZ r1, __tx_ts_ready @ If non-NULL, a new thread is ready!
#ifdef TX_LOW_POWER
PUSH {r0-r3}
BL tx_low_power_enter @ Possibly enter low power mode
POP {r0-r3}
#endif
#ifdef TX_ENABLE_WFI
DSB @ Ensure no outstanding memory transactions
WFI @ Wait for interrupt
ISB @ Ensure pipeline is flushed
#endif
#ifdef TX_LOW_POWER
PUSH {r0-r3}
BL tx_low_power_exit @ Exit low power mode
POP {r0-r3}
#endif
CPSIE i @ Enable interrupts
B __tx_ts_wait @ Loop to continue waiting
@

0
ports/cortex_m7/gnu/src/tx_thread_stack_build.S Executable file → Normal file
View File

0
ports/cortex_m7/gnu/src/tx_thread_system_return.S Executable file → Normal file
View File

0
ports/cortex_m7/gnu/src/tx_timer_interrupt.S Executable file → Normal file
View File

138
ports/cortex_m7/iar/readme_threadx.txt
View File

@@ -58,80 +58,80 @@ tx_thread_stack_ptr in the associated thread control block TX_THREAD.
Non-FPU Stack Frame:
Stack Offset Stack Contents
Stack Offset Stack Contents
0x00 LR Interrupted LR (LR at time of PENDSV)
0x04 r4
0x08 r5
0x0C r6
0x10 r7
0x14 r8
0x18 r9
0x1C r10 (sl)
0x20 r11
0x24 r0 (Hardware stack starts here!!)
0x28 r1
0x2C r2
0x30 r3
0x34 r12
0x38 lr
0x3C pc
0x40 xPSR
0x00 LR Interrupted LR (LR at time of PENDSV)
0x04 r4 Software stacked GP registers
0x08 r5
0x0C r6
0x10 r7
0x14 r8
0x18 r9
0x1C r10
0x20 r11
0x24 r0 Hardware stacked registers
0x28 r1
0x2C r2
0x30 r3
0x34 r12
0x38 lr
0x3C pc
0x40 xPSR
FPU Stack Frame (only interrupted thread with FPU enabled):
Stack Offset Stack Contents
Stack Offset Stack Contents
0x00 LR Interrupted LR (LR at time of PENDSV)
0x04 s0
0x08 s1
0x0C s2
0x10 s3
0x14 s4
0x18 s5
0x1C s6
0x20 s7
0x24 s8
0x28 s9
0x2C s10
0x30 s11
0x34 s12
0x38 s13
0x3C s14
0x40 s15
0x44 s16
0x48 s17
0x4C s18
0x50 s19
0x54 s20
0x58 s21
0x5C s22
0x60 s23
0x64 s24
0x68 s25
0x6C s26
0x70 s27
0x74 s28
0x78 s29
0x7C s30
0x80 s31
0x84 fpscr
0x88 r4
0x8C r5
0x90 r6
0x94 r7
0x98 r8
0x9C r9
0xA0 r10 (sl)
0xA4 r11
0xA8 r0 (Hardware stack starts here!!)
0xAC r1
0xB0 r2
0xB4 r3
0xB8 r12
0xBC lr
0xC0 pc
0xC4 xPSR
0x00 LR Interrupted LR (LR at time of PENDSV)
0x04 s16 Software stacked FPU registers
0x08 s17
0x0C s18
0x10 s19
0x14 s20
0x18 s21
0x1C s22
0x20 s23
0x24 s24
0x28 s25
0x2C s26
0x30 s27
0x34 s28
0x38 s29
0x3C s30
0x40 s31
0x44 r4 Software stacked registers
0x48 r5
0x4C r6
0x50 r7
0x54 r8
0x58 r9
0x5C r10
0x60 r11
0x64 r0 Hardware stacked registers
0x68 r1
0x6C r2
0x70 r3
0x74 r12
0x78 lr
0x7C pc
0x80 xPSR
0x84 s0 Hardware stacked FPU registers
0x88 s1
0x8C s2
0x90 s3
0x94 s4
0x98 s5
0x9C s6
0xA0 s7
0xA4 s8
0xA8 s9
0xAC s10
0xB0 s11
0xB4 s12
0xB8 s13
0xBC s14
0xC0 s15
0xC4 fpscr
5. Improving Performance

25
ports/cortex_m7/iar/src/tx_thread_schedule.s
View File

@@ -28,6 +28,10 @@
EXTERN _tx_execution_thread_enter
EXTERN _tx_execution_thread_exit
EXTERN _tx_thread_preempt_disable
#ifdef TX_LOW_POWER
EXTERN tx_low_power_enter
EXTERN tx_low_power_exit
#endif
;
;
SECTION `.text`:CODE:NOROOT(2)
@@ -37,7 +41,7 @@
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_schedule Cortex-M7/IAR */
;/* 6.1 */
;/* 6.1.5 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
@@ -70,7 +74,10 @@
;/* */
;/* DATE NAME DESCRIPTION */
;/* */
;/* 09-30-2020 William E. Lamie Initial Version 6.1 */
;/* 09-30-2020 William E. Lamie Initial Version 6.1 */
;/* 03-02-2021 Scott Larson Modified comment(s), add */
;/* low power code, */
;/* resulting in version 6.1.5 */
;/* */
;/**************************************************************************/
;VOID _tx_thread_schedule(VOID)
@@ -236,11 +243,25 @@ __tx_ts_wait:
LDR r1, [r2] ; Pickup the next thread to execute pointer
STR r1, [r0] ; Store it in the current pointer
CBNZ r1, __tx_ts_ready ; If non-NULL, a new thread is ready!
#ifdef TX_LOW_POWER
PUSH {r0-r3}
BL tx_low_power_enter ; Possibly enter low power mode
POP {r0-r3}
#endif
#ifdef TX_ENABLE_WFI
DSB ; Ensure no outstanding memory transactions
WFI ; Wait for interrupt
ISB ; Ensure pipeline is flushed
#endif
#ifdef TX_LOW_POWER
PUSH {r0-r3}
BL tx_low_power_exit ; Exit low power mode
POP {r0-r3}
#endif
CPSIE i ; Enable interrupts
B __tx_ts_wait ; Loop to continue waiting
;