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Release 6.1.9

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This commit is contained in:
Yuxin Zhou
2021-10-14 00:51:26 +00:00
parent 215df45d4b
commit 1af8404c54
1812 changed files with 60698 additions and 249862 deletions
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2
ports/cortex_a7/iar/inc/tx_port.h
View File

@@ -383,7 +383,7 @@ void tx_thread_vfp_disable(void);
#ifdef TX_THREAD_INIT
CHAR _tx_version_id[] =
"Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A7/IAR Version 6.1.6 *";
"Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A7/IAR Version 6.1.9 *";
#else
extern CHAR _tx_version_id[];
#endif

7
ports/cortex_a7/iar/src/tx_thread_context_restore.s
View File

@@ -57,7 +57,7 @@ SVC_MODE_BITS DEFINE 0x13 ; SVC mode value
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_context_restore Cortex-A7/IAR */
;/* 6.1 */
;/* 6.1.9 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
@@ -90,6 +90,9 @@ SVC_MODE_BITS DEFINE 0x13 ; SVC mode value
;/* DATE NAME DESCRIPTION */
;/* */
;/* 09-30-2020 William E. Lamie Initial Version 6.1 */
;/* 10-15-2021 William E. Lamie Modified comment(s), added */
;/* execution profile support, */
;/* resulting in version 6.1.9 */
;/* */
;/**************************************************************************/
;VOID _tx_thread_context_restore(VOID)
@@ -105,7 +108,7 @@ _tx_thread_context_restore
ORR r0, r3, #DISABLE_INTS ; Build interrupt disable value
MSR CPSR_cxsf, r0 ; Lockout interrupts
#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE))
;
; /* Call the ISR exit function to indicate an ISR is complete. */
;

11
ports/cortex_a7/iar/src/tx_thread_context_save.s
View File

@@ -49,7 +49,7 @@ DISABLE_INTS DEFINE 0x80 ; IRQ interrupts disabled
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_context_save Cortex-A7/IAR */
;/* 6.1 */
;/* 6.1.9 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
@@ -81,6 +81,9 @@ DISABLE_INTS DEFINE 0x80 ; IRQ interrupts disabled
;/* DATE NAME DESCRIPTION */
;/* */
;/* 09-30-2020 William E. Lamie Initial Version 6.1 */
;/* 10-15-2021 William E. Lamie Modified comment(s), added */
;/* execution profile support, */
;/* resulting in version 6.1.9 */
;/* */
;/**************************************************************************/
;VOID _tx_thread_context_save(VOID)
@@ -124,7 +127,7 @@ _tx_thread_context_save
;
MOV r10, #0 ; Clear stack limit
#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE))
;
; /* Call the ISR enter function to indicate an ISR is executing. */
;
@@ -164,7 +167,7 @@ __tx_thread_not_nested_save
;
MOV r10, #0 ; Clear stack limit
#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE))
;
; /* Call the ISR enter function to indicate an ISR is executing. */
;
@@ -188,7 +191,7 @@ __tx_thread_idle_system_save
;
MOV r10, #0 ; Clear stack limit
#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE))
;
; /* Call the ISR enter function to indicate an ISR is executing. */
;

7
ports/cortex_a7/iar/src/tx_thread_fiq_context_restore.s
View File

@@ -58,7 +58,7 @@ SVC_MODE_BITS DEFINE 0x13 ; SVC mode value
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_fiq_context_restore Cortex-A7/IAR */
;/* 6.1 */
;/* 6.1.9 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
@@ -91,6 +91,9 @@ SVC_MODE_BITS DEFINE 0x13 ; SVC mode value
;/* DATE NAME DESCRIPTION */
;/* */
;/* 09-30-2020 William E. Lamie Initial Version 6.1 */
;/* 10-15-2021 William E. Lamie Modified comment(s), added */
;/* execution profile support, */
;/* resulting in version 6.1.9 */
;/* */
;/**************************************************************************/
;VOID _tx_thread_fiq_context_restore(VOID)
@@ -106,7 +109,7 @@ _tx_thread_fiq_context_restore
ORR r0, r3, #DISABLE_INTS ; Build interrupt disable value
MSR CPSR_cxsf, r0 ; Lockout interrupts
#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE))
;
; /* Call the ISR exit function to indicate an ISR is complete. */
;

11
ports/cortex_a7/iar/src/tx_thread_fiq_context_save.s
View File

@@ -42,7 +42,7 @@
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_fiq_context_save Cortex-A7/IAR */
;/* 6.1 */
;/* 6.1.9 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
@@ -74,6 +74,9 @@
;/* DATE NAME DESCRIPTION */
;/* */
;/* 09-30-2020 William E. Lamie Initial Version 6.1 */
;/* 10-15-2021 William E. Lamie Modified comment(s), added */
;/* execution profile support, */
;/* resulting in version 6.1.9 */
;/* */
;/**************************************************************************/
; VOID _tx_thread_fiq_context_save(VOID)
@@ -112,7 +115,7 @@ _tx_thread_fiq_context_save
;
MOV r10, #0 ; Clear stack limit
#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE))
;
; /* Call the ISR enter function to indicate an ISR is executing. */
;
@@ -156,7 +159,7 @@ __tx_thread_fiq_not_nested_save
;
MOV r10, #0 ; Clear stack limit
#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE))
;
; /* Call the ISR enter function to indicate an ISR is executing. */
;
@@ -175,7 +178,7 @@ __tx_thread_fiq_idle_system_save
;
; /* Interrupt occurred in the scheduling loop. */
;
#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE))
;
; /* Call the ISR enter function to indicate an ISR is executing. */
;

7
ports/cortex_a7/iar/src/tx_thread_schedule.s
View File

@@ -49,7 +49,7 @@ ENABLE_INTS DEFINE 0x80 ; IRQ Interrupts enabled mask
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_schedule Cortex-A7/IAR */
;/* 6.1 */
;/* 6.1.9 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
@@ -83,6 +83,9 @@ ENABLE_INTS DEFINE 0x80 ; IRQ Interrupts enabled mask
;/* DATE NAME DESCRIPTION */
;/* */
;/* 09-30-2020 William E. Lamie Initial Version 6.1 */
;/* 10-15-2021 William E. Lamie Modified comment(s), added */
;/* execution profile support, */
;/* resulting in version 6.1.9 */
;/* */
;/**************************************************************************/
;VOID _tx_thread_schedule(VOID)
@@ -143,7 +146,7 @@ __tx_thread_schedule_loop
; /* Switch to the thread's stack. */
; sp = _tx_thread_execute_ptr -> tx_thread_stack_ptr;
;
#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE))
;
; /* Call the thread entry function to indicate the thread is executing. */
;

7
ports/cortex_a7/iar/src/tx_thread_system_return.s
View File

@@ -48,7 +48,7 @@ DISABLE_INTS DEFINE 0x80 ; IRQ interrupts disabled
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_system_return Cortex-A7/IAR */
;/* 6.1 */
;/* 6.1.9 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
@@ -81,6 +81,9 @@ DISABLE_INTS DEFINE 0x80 ; IRQ interrupts disabled
;/* DATE NAME DESCRIPTION */
;/* */
;/* 09-30-2020 William E. Lamie Initial Version 6.1 */
;/* 10-15-2021 William E. Lamie Modified comment(s), added */
;/* execution profile support, */
;/* resulting in version 6.1.9 */
;/* */
;/**************************************************************************/
;VOID _tx_thread_system_return(VOID)
@@ -117,7 +120,7 @@ _tx_skip_solicited_vfp_save:
ORR r2, r1, #DISABLE_INTS ; Build disable interrupt CPSR
MSR CPSR_cxsf, r2 ; Disable interrupts
#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE))
;
; /* Call the thread exit function to indicate the thread is no longer executing. */
;

11
ports/cortex_a7/iar/src/tx_thread_vectored_context_save.s
View File

@@ -47,7 +47,7 @@ DISABLE_INTS DEFINE 0x80 ; IRQ interrupts disabled
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_vectored_context_save Cortex-A7/IAR */
;/* 6.1 */
;/* 6.1.9 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
@@ -79,6 +79,9 @@ DISABLE_INTS DEFINE 0x80 ; IRQ interrupts disabled
;/* DATE NAME DESCRIPTION */
;/* */
;/* 09-30-2020 William E. Lamie Initial Version 6.1 */
;/* 10-15-2021 William E. Lamie Modified comment(s), added */
;/* execution profile support, */
;/* resulting in version 6.1.9 */
;/* */
;/**************************************************************************/
;VOID _tx_thread_vectored_context_save(VOID)
@@ -117,7 +120,7 @@ _tx_thread_vectored_context_save
;
MOV r10, #0 ; Clear stack limit
#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE))
;
; /* Call the ISR enter function to indicate an ISR is executing. */
;
@@ -153,7 +156,7 @@ __tx_thread_not_nested_save
;
MOV r10, #0 ; Clear stack limit
#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE))
;
; /* Call the ISR enter function to indicate an ISR is executing. */
;
@@ -177,7 +180,7 @@ __tx_thread_idle_system_save
;
MOV r10, #0 ; Clear stack limit
#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE))
;
; /* Call the ISR enter function to indicate an ISR is executing. */
;