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Release 6.1.9

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This commit is contained in:
Yuxin Zhou
2021-10-14 00:51:26 +00:00
parent 215df45d4b
commit 1af8404c54
1812 changed files with 60698 additions and 249862 deletions
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2
ports_module/cortex_a35/ac6/inc/tx_port.h
View File

@@ -387,7 +387,7 @@ VOID tx_thread_fp_disable(VOID);
#ifdef TX_THREAD_INIT
CHAR _tx_version_id[] =
"Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Modules Cortex-A35/AC6 Version 6.1.3 *";
"Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Modules Cortex-A35/AC6 Version 6.1.9 *";
#else
extern CHAR _tx_version_id[];
#endif

2
ports_module/cortex_a35/ac6/inc/txm_module_port.h
View File

@@ -279,6 +279,6 @@ ALIGN_TYPE _txm_module_manager_port_dispatch(TXM_MODULE_INSTANCE *module_instanc
#define TXM_MODULE_MANAGER_VERSION_ID \
CHAR _txm_module_manager_version_id[] = \
"Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-A35/AC6 Version 6.1.3 *";
"Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-A35/AC6 Version 6.1.9 *";
#endif

2
ports_module/cortex_a35/gnu/inc/tx_port.h
View File

@@ -387,7 +387,7 @@ VOID tx_thread_fp_disable(VOID);
#ifdef TX_THREAD_INIT
CHAR _tx_version_id[] =
"Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Modules Cortex-A35/GNU Version 6.1.3 *";
"Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Modules Cortex-A35/GNU Version 6.1.9 *";
#else
extern CHAR _tx_version_id[];
#endif

2
ports_module/cortex_a35/gnu/inc/txm_module_port.h
View File

@@ -279,6 +279,6 @@ ALIGN_TYPE _txm_module_manager_port_dispatch(TXM_MODULE_INSTANCE *module_instanc
#define TXM_MODULE_MANAGER_VERSION_ID \
CHAR _txm_module_manager_version_id[] = \
"Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-A35/GNU Version 6.1.3 *";
"Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-A35/GNU Version 6.1.9 *";
#endif

2
ports_module/cortex_a35_smp/ac6/example_build/sample_threadx/.cproject
View File

@@ -31,7 +31,7 @@
<option id="com.arm.toolchain.v6.base.options.target.cpu_fpu.1337922098" superClass="com.arm.toolchain.v6.base.options.target.cpu_fpu" useByScannerDiscovery="false" value="Cortex-A35.AArch64.ARMv8.Neon.Crypto" valueType="string"/>
<option id="com.arm.toolchain.v6.base.options.debug.level.1596377417" superClass="com.arm.toolchain.v6.base.options.debug.level" value="com.arm.tool.c.compiler.v6.base.options.debug.level.std" valueType="enumerated"/>
<option id="com.arm.toolchain.v6.base.options.debug.level.1596377417" name="Debug Level" superClass="com.arm.toolchain.v6.base.options.debug.level" value="com.arm.tool.c.compiler.v6.base.options.debug.level.std" valueType="enumerated"/>
<targetPlatform id="com.arm.toolchain.v6.base.var.arm_compiler_6-6.1592753597.2060144338" name=""/>

46
ports_module/cortex_a35_smp/ac6/example_build/sample_threadx/sample_threadx.c
View File

@@ -1,5 +1,5 @@
/* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight
threads of different priorities, using a message queue, semaphore, mutex, event flags group,
threads of different priorities, using a message queue, semaphore, mutex, event flags group,
byte pool, and block pool. */
#include "tx_api.h"
@@ -104,41 +104,41 @@ CHAR *pointer = TX_NULL;
tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
/* Create the main thread. */
tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0,
pointer, DEMO_STACK_SIZE,
tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0,
pointer, DEMO_STACK_SIZE,
1, 1, TX_NO_TIME_SLICE, TX_AUTO_START);
/* Allocate the stack for thread 1. */
tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
/* Create threads 1 and 2. These threads pass information through a ThreadX
/* Create threads 1 and 2. These threads pass information through a ThreadX
message queue. It is also interesting to note that these threads have a time
slice. */
tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1,
pointer, DEMO_STACK_SIZE,
pointer, DEMO_STACK_SIZE,
16, 16, 4, TX_AUTO_START);
/* Allocate the stack for thread 2. */
tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2,
pointer, DEMO_STACK_SIZE,
pointer, DEMO_STACK_SIZE,
16, 16, 4, TX_AUTO_START);
/* Allocate the stack for thread 3. */
tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
/* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore.
/* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore.
An interesting thing here is that both threads share the same instruction area. */
tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3,
pointer, DEMO_STACK_SIZE,
tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3,
pointer, DEMO_STACK_SIZE,
8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
/* Allocate the stack for thread 4. */
tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4,
pointer, DEMO_STACK_SIZE,
tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4,
pointer, DEMO_STACK_SIZE,
8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
/* Allocate the stack for thread 5. */
@@ -146,23 +146,23 @@ CHAR *pointer = TX_NULL;
/* Create thread 5. This thread simply pends on an event flag which will be set
by thread_0. */
tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5,
pointer, DEMO_STACK_SIZE,
tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5,
pointer, DEMO_STACK_SIZE,
4, 4, TX_NO_TIME_SLICE, TX_AUTO_START);
/* Allocate the stack for thread 6. */
tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
/* Create threads 6 and 7. These threads compete for a ThreadX mutex. */
tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6,
pointer, DEMO_STACK_SIZE,
tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6,
pointer, DEMO_STACK_SIZE,
8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
/* Allocate the stack for thread 7. */
tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7,
pointer, DEMO_STACK_SIZE,
tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7,
pointer, DEMO_STACK_SIZE,
8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
/* Allocate the message queue. */
@@ -264,11 +264,11 @@ UINT status;
/* Retrieve a message from the queue. */
status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER);
/* Check completion status and make sure the message is what we
/* Check completion status and make sure the message is what we
expected. */
if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received))
break;
/* Otherwise, all is okay. Increment the received message count. */
thread_2_messages_received++;
}
@@ -327,7 +327,7 @@ ULONG actual_flags;
thread_5_counter++;
/* Wait for event flag 0. */
status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR,
status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR,
&actual_flags, TX_WAIT_FOREVER);
/* Check status. */
@@ -380,7 +380,7 @@ UINT status;
if (status != TX_SUCCESS)
break;
/* Release the mutex again. This will actually
/* Release the mutex again. This will actually
release ownership since it was obtained twice. */
status = tx_mutex_put(&mutex_0);

4
ports_module/cortex_a35_smp/ac6/example_build/sample_threadx/startup.S
View File

@@ -328,7 +328,7 @@ el1_entry_aarch64:
//
// Cortex-A processors automatically invalidate their caches on reset
// (unless suppressed with the DBGL1RSTDISABLE or L2RSTDISABLE pins).
// It is therefore not necessary for software to invalidate the caches
// It is therefore not necessary for software to invalidate the caches
// on startup, however, this is done here in case of a warm reset.
bl InvalidateUDCaches
tlbi VMALLE1
@@ -800,4 +800,4 @@ __user_setup_stackheap:
ADRP X0, Image$$ARM_LIB_HEAP$$ZI$$Base
ADRP X2, Image$$ARM_LIB_HEAP$$ZI$$Limit
RET

42
ports_module/cortex_a35_smp/ac6/example_build/sample_threadx_module/sample_threadx_module.c
View File

@@ -1,5 +1,5 @@
/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes
examples of eight threads of different priorities, using a message queue, semaphore, mutex,
/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes
examples of eight threads of different priorities, using a message queue, semaphore, mutex,
event flags group, byte pool, and block pool. */
/* Specify that this is a module! */
@@ -20,7 +20,7 @@
#define DEMO_QUEUE_SIZE 100
/* Define the pool space in the bss section of the module. ULONG is used to
/* Define the pool space in the bss section of the module. ULONG is used to
get the word alignment. */
ULONG demo_module_pool_space[DEMO_BYTE_POOL_SIZE / sizeof(ULONG)];
@@ -103,7 +103,7 @@ CHAR *pointer;
/* Allocate all the objects. In MMU mode, modules cannot allocate control blocks within
their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting
their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting
the control block(s). */
status = txm_module_object_allocate((void*)&thread_0, sizeof(TX_THREAD));
while (status != TX_SUCCESS);
@@ -133,7 +133,7 @@ CHAR *pointer;
while (status != TX_SUCCESS);
status = txm_module_object_allocate((void*)&block_pool_0, sizeof(TX_BLOCK_POOL));
while (status != TX_SUCCESS);
/* Create a byte memory pool from which to allocate the thread stacks. */
status = tx_byte_pool_create(byte_pool_0, "module byte pool 0", demo_module_pool_space, DEMO_BYTE_POOL_SIZE);
@@ -193,7 +193,7 @@ CHAR *pointer;
/* Create the main thread. */
status = tx_thread_create(thread_0, "module thread 0", thread_0_entry, 0,
pointer, DEMO_STACK_SIZE,
pointer, DEMO_STACK_SIZE,
1, 1, TX_NO_TIME_SLICE, TX_AUTO_START);
while (status != TX_SUCCESS);
@@ -201,11 +201,11 @@ CHAR *pointer;
status = tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
while (status != TX_SUCCESS);
/* Create threads 1 and 2. These threads pass information through a ThreadX
/* Create threads 1 and 2. These threads pass information through a ThreadX
message queue. It is also interesting to note that these threads have a time
slice. */
status = tx_thread_create(thread_1, "module thread 1", thread_1_entry, 1,
pointer, DEMO_STACK_SIZE,
pointer, DEMO_STACK_SIZE,
16, 16, 4, TX_AUTO_START);
while (status != TX_SUCCESS);
@@ -214,7 +214,7 @@ CHAR *pointer;
while (status != TX_SUCCESS);
status = tx_thread_create(thread_2, "module thread 2", thread_2_entry, 2,
pointer, DEMO_STACK_SIZE,
pointer, DEMO_STACK_SIZE,
16, 16, 4, TX_AUTO_START);
while (status != TX_SUCCESS);
@@ -222,10 +222,10 @@ CHAR *pointer;
status = tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
while (status != TX_SUCCESS);
/* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore.
/* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore.
An interesting thing here is that both threads share the same instruction area. */
status = tx_thread_create(thread_3, "module thread 3", thread_3_and_4_entry, 3,
pointer, DEMO_STACK_SIZE,
pointer, DEMO_STACK_SIZE,
8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
while (status != TX_SUCCESS);
@@ -234,7 +234,7 @@ CHAR *pointer;
while (status != TX_SUCCESS);
status = tx_thread_create(thread_4, "module thread 4", thread_3_and_4_entry, 4,
pointer, DEMO_STACK_SIZE,
pointer, DEMO_STACK_SIZE,
8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
while (status != TX_SUCCESS);
@@ -245,7 +245,7 @@ CHAR *pointer;
/* Create thread 5. This thread simply pends on an event flag which will be set
by thread_0. */
status = tx_thread_create(thread_5, "module thread 5", thread_5_entry, 5,
pointer, DEMO_STACK_SIZE,
pointer, DEMO_STACK_SIZE,
4, 4, TX_NO_TIME_SLICE, TX_AUTO_START);
while (status != TX_SUCCESS);
@@ -255,7 +255,7 @@ CHAR *pointer;
/* Create threads 6 and 7. These threads compete for a ThreadX mutex. */
status = tx_thread_create(thread_6, "module thread 6", thread_6_and_7_entry, 6,
pointer, DEMO_STACK_SIZE,
pointer, DEMO_STACK_SIZE,
8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
while (status != TX_SUCCESS);
@@ -264,7 +264,7 @@ CHAR *pointer;
while (status != TX_SUCCESS);
status = tx_thread_create(thread_7, "module thread 7", thread_6_and_7_entry, 7,
pointer, DEMO_STACK_SIZE,
pointer, DEMO_STACK_SIZE,
8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
while (status != TX_SUCCESS);
}
@@ -276,7 +276,7 @@ void thread_0_entry(ULONG thread_input)
{
UINT status;
/* This thread simply sits in while-forever-sleep loop. */
while(1)
{
@@ -286,7 +286,7 @@ UINT status;
/* Sleep for 10 ticks. */
tx_thread_sleep(10);
/* Set event flag 0 to wakeup thread 5. */
status = tx_event_flags_set(event_flags_0, 0x1, TX_OR);
@@ -338,11 +338,11 @@ UINT status;
/* Retrieve a message from the queue. */
status = tx_queue_receive(queue_0, &received_message, TX_WAIT_FOREVER);
/* Check completion status and make sure the message is what we
/* Check completion status and make sure the message is what we
expected. */
if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received))
break;
/* Otherwise, all is okay. Increment the received message count. */
thread_2_messages_received++;
}
@@ -401,7 +401,7 @@ ULONG actual_flags;
thread_5_counter++;
/* Wait for event flag 0. */
status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR,
status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR,
&actual_flags, TX_WAIT_FOREVER);
/* Check status. */
@@ -454,7 +454,7 @@ UINT status;
if (status != TX_SUCCESS)
break;
/* Release the mutex again. This will actually
/* Release the mutex again. This will actually
release ownership since it was obtained twice. */
status = tx_mutex_put(mutex_0);

2
ports_module/cortex_a35_smp/ac6/example_build/sample_threadx_module/txm_module_preamble.S
View File

@@ -1,7 +1,7 @@
.text
.align 4
.section Init
// External references
.global _txm_module_thread_shell_entry
.global _txm_module_callback_request_thread_entry

2
ports_module/cortex_a35_smp/ac6/example_build/sample_threadx_module_manager/.cproject
View File

@@ -103,7 +103,7 @@
</option>
<option id="com.arm.tool.assembler.v6.base.option.force.preproc.70495432" superClass="com.arm.tool.assembler.v6.base.option.force.preproc" useByScannerDiscovery="false" value="true" valueType="boolean"/>
<option id="com.arm.tool.assembler.v6.base.option.force.preproc.70495432" name="Preprocess input files (-x assembler-with-cpp)" superClass="com.arm.tool.assembler.v6.base.option.force.preproc" useByScannerDiscovery="false" value="true" valueType="boolean"/>
<inputType id="com.arm.tool.assembler.v6.base.input.1024953339" superClass="com.arm.tool.assembler.v6.base.input"/>

10
ports_module/cortex_a35_smp/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c
View File

@@ -115,7 +115,7 @@ void module_manager_entry(ULONG thread_input)
/* Load the module with absolute address linkage, in this example it is placed there by the multiple image download. */
txm_module_manager_absolute_load(&my_module, "my module", (void *) MODULE_CODE);
/* Start the module. */
txm_module_manager_start(&my_module);
@@ -127,10 +127,10 @@ void module_manager_entry(ULONG thread_input)
tx_thread_sleep(10);
}
}
/* Stop the module. */
txm_module_manager_stop(&my_module);
/* Unload the module. */
txm_module_manager_unload(&my_module);
@@ -139,11 +139,11 @@ void module_manager_entry(ULONG thread_input)
/* Start the module again. */
txm_module_manager_start(&my_module);
/* Now just spin... */
while(1)
{
tx_thread_sleep(10);
}
}

4
ports_module/cortex_a35_smp/ac6/example_build/sample_threadx_module_manager/startup.S
View File

@@ -328,7 +328,7 @@ el1_entry_aarch64:
//
// Cortex-A processors automatically invalidate their caches on reset
// (unless suppressed with the DBGL1RSTDISABLE or L2RSTDISABLE pins).
// It is therefore not necessary for software to invalidate the caches
// It is therefore not necessary for software to invalidate the caches
// on startup, however, this is done here in case of a warm reset.
bl InvalidateUDCaches
tlbi VMALLE1
@@ -800,4 +800,4 @@ __user_setup_stackheap:
ADRP X0, Image$$ARM_LIB_HEAP$$ZI$$Base
ADRP X2, Image$$ARM_LIB_HEAP$$ZI$$Limit
RET

72
ports_module/cortex_a35_smp/ac6/example_build/tx/.cproject
View File

@@ -200,78 +200,6 @@
<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
</cconfiguration>
<cconfiguration id="com.arm.eclipse.build.config.v6.lib.release.base.597173224">
<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.arm.eclipse.build.config.v6.lib.release.base.597173224" moduleId="org.eclipse.cdt.core.settings" name="Release">
<externalSettings/>
<extensions>
<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="com.arm.eclipse.builder.armcc.error" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
</extensions>
</storageModule>
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
<configuration artifactExtension="a" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.staticLib" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.staticLib,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.release" cleanCommand="clean" description="" id="com.arm.eclipse.build.config.v6.lib.release.base.597173224" name="Release" parent="com.arm.eclipse.build.config.v6.lib.release.base">
<folderInfo id="com.arm.eclipse.build.config.v6.lib.release.base.597173224." name="/" resourcePath="">
<toolChain id="com.arm.toolchain.v6.lib.release.base.var.arm_compiler_6-6.1176479246" name="Arm Compiler 6" superClass="com.arm.toolchain.v6.lib.release.base.var.arm_compiler_6-6">
<targetPlatform id="com.arm.toolchain.v6.lib.release.base.var.arm_compiler_6-6.1176479246.1337532818" name=""/>
<builder autoBuildTarget="all" buildPath="${workspace_loc:/tx}/Release" cleanBuildTarget="clean" enableAutoBuild="false" enableCleanBuild="true" enabledIncrementalBuild="true" id="com.arm.toolchain.v6.builder.1329350735" incrementalBuildTarget="all" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" parallelBuildOn="false" superClass="com.arm.toolchain.v6.builder"/>
<tool id="com.arm.tool.c.compiler.v6.base.var.arm_compiler_6-6.599090274" name="Arm C Compiler 6" superClass="com.arm.tool.c.compiler.v6.base.var.arm_compiler_6-6">
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<tool id="com.arm.tool.c.linker.v6.base.var.arm_compiler_6-6.1174783096" name="Arm Linker 6" superClass="com.arm.tool.c.linker.v6.base.var.arm_compiler_6-6"/>
<tool id="com.arm.tool.librarian.v6.base.var.arm_compiler_6-6.121864210" name="Arm Librarian 6" superClass="com.arm.tool.librarian.v6.base.var.arm_compiler_6-6"/>
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</folderInfo>
<sourceEntries>
<entry excluding="src_generic/tx_misra.c|src_generic/tx_thread_timeout.c" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
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</configuration>
</storageModule>
<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
</cconfiguration>
</storageModule>

2
ports_module/cortex_a35_smp/ac6/example_build/txm/.cproject
View File

@@ -137,7 +137,7 @@
</option>
<option id="com.arm.tool.assembler.v6.base.option.force.preproc.2015328324" superClass="com.arm.tool.assembler.v6.base.option.force.preproc" useByScannerDiscovery="false" value="true" valueType="boolean"/>
<option id="com.arm.tool.assembler.v6.base.option.force.preproc.2015328324" name="Preprocess input files (-x assembler-with-cpp)" superClass="com.arm.tool.assembler.v6.base.option.force.preproc" useByScannerDiscovery="false" value="true" valueType="boolean"/>
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9
ports_module/cortex_a35_smp/ac6/inc/tx_port.h
View File

@@ -26,7 +26,7 @@
/* PORT SPECIFIC C INFORMATION RELEASE */
/* */
/* tx_port.h Cortex-A35-SMP/AC6 */
/* 6.1.3 */
/* 6.1.9 */
/* */
/* AUTHOR */
/* */
@@ -48,6 +48,9 @@
/* DATE NAME DESCRIPTION */
/* */
/* 12-31-2020 Andres Mlinar Initial Version 6.1.3 */
/* 10-15-2021 William E. Lamie Modified comment(s), added */
/* symbol ULONG64_DEFINED, */
/* resulting in version 6.1.9 */
/* */
/**************************************************************************/
@@ -152,7 +155,7 @@ typedef unsigned int ULONG;
typedef unsigned long long ULONG64;
typedef short SHORT;
typedef unsigned short USHORT;
#define ULONG64_DEFINED
/* Override the alignment type to use 64-bit alignment and storage for pointers. */
@@ -441,7 +444,7 @@ VOID tx_thread_fp_disable(VOID);
#ifdef TX_THREAD_INIT
CHAR _tx_version_id[] =
"Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Modules Cortex-A35-SMP/AC6 Version 6.1.3 *";
"Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Modules Cortex-A35-SMP/AC6 Version 6.1.9 *";
#else
extern CHAR _tx_version_id[];
#endif

2
ports_module/cortex_a35_smp/ac6/inc/txm_module_port.h
View File

@@ -274,6 +274,6 @@ ALIGN_TYPE _txm_module_manager_port_dispatch(TXM_MODULE_INSTANCE *module_instanc
#define TXM_MODULE_MANAGER_VERSION_ID \
CHAR _txm_module_manager_version_id[] = \
"Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-A35/AC6 Version 6.1.3 *";
"Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-A35/AC6 Version 6.1.9 *";
#endif

2
ports_module/cortex_a35_smp/ac6/module_lib/src/txm_module_thread_shell_entry.c
View File

@@ -121,7 +121,7 @@ VOID (*entry_exit_notify)(TX_THREAD *notify_thread_ptr, UINT type);
An error here typically indicates the resident portion of _tx_thread_schedule
is not supporting the trap to obtain the function pointer. */
}
/* Resume the module's callback thread, already created in the manager. */
_txe_thread_resume(thread_info -> txm_module_thread_entry_info_callback_request_thread);
}

13
ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_smp_core_get.S
View File

@@ -28,7 +28,7 @@
/* FUNCTION RELEASE */
/* */
/* _tx_thread_smp_core_get Cortex-A35-SMP/AC6 */
/* 6.1 */
/* 6.1.9 */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
@@ -58,17 +58,28 @@
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 10-15-2021 Andres Mlinar Updated comments, */
/* added ARMv8.2-A support, */
/* resulting in version 6.1.9 */
/* */
/**************************************************************************/
.global _tx_thread_smp_core_get
.type _tx_thread_smp_core_get, @function
_tx_thread_smp_core_get:
MRS x0, MPIDR_EL1 // Pickup the core ID
#ifdef TX_ARMV8_2
#if TX_THREAD_SMP_CLUSTERS > 1
UBFX x1, x0, #16, #8 // Isolate cluster ID
#endif
UBFX x0, x0, #8, #8 // Isolate core ID
#else
#if TX_THREAD_SMP_CLUSTERS > 1
UBFX x1, x0, #8, #8 // Isolate cluster ID
#endif
UBFX x0, x0, #0, #8 // Isolate core ID
#endif
#if TX_THREAD_SMP_CLUSTERS > 1
ADDS x0, x0, x1, LSL #2 // Calculate CPU ID
#endif
RET

39
ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_smp_protect.S
View File

@@ -32,7 +32,7 @@
/* FUNCTION RELEASE */
/* */
/* _tx_thread_smp_protect Cortex-A35-SMP/AC6 */
/* 6.1 */
/* 6.1.9 */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
@@ -64,6 +64,10 @@
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 10-15-2021 Andres Mlinar Updated comments, */
/* added ARMv8.2-A support, */
/* improved SMP code, */
/* resulting in version 6.1.9 */
/* */
/**************************************************************************/
.global _tx_thread_smp_protect
@@ -78,10 +82,17 @@ _tx_thread_smp_protect:
/* Pickup the CPU ID. */
MRS x1, MPIDR_EL1 // Pickup the core ID
#ifdef TX_ARMV8_2
#if TX_THREAD_SMP_CLUSTERS > 1
UBFX x7, x1, #16, #8 // Isolate cluster ID
#endif
UBFX x1, x1, #8, #8 // Isolate core ID
#else
#if TX_THREAD_SMP_CLUSTERS > 1
UBFX x7, x1, #8, #8 // Isolate cluster ID
#endif
UBFX x1, x1, #0, #8 // Isolate core ID
#endif
#if TX_THREAD_SMP_CLUSTERS > 1
ADDS x1, x1, x7, LSL #2 // Calculate CPU ID
#endif
@@ -163,7 +174,7 @@ _list_not_empty:
// if (_tx_thread_smp_protection.tx_thread_smp_protect_in_force == 0)
// {
LDR w3, [x2, #0] // Pickup the protection flag
LDAXR w3, [x2, #0] // Pickup the protection flag
CMP w3, #0
BNE _start_waiting // No, protection not available
@@ -171,7 +182,9 @@ _list_not_empty:
// _tx_thread_smp_protection.tx_thread_smp_protect_in_force = 1;
MOV w3, #1 // Build lock value
STR w3, [x2, #0] // Store lock value
STXR w4, w3, [x2, #0] // Attempt to get the protection
CMP w4, #0
BNE _start_waiting // Did it fail?
DMB ISH //
/* Got the lock. */
@@ -217,7 +230,7 @@ _already_in_list0:
/* Restore interrupts. */
MSR DAIF, x0 // Restore interrupts
ISB //
ISB //
#ifdef TX_ENABLE_WFE
WFE // Go into standby
#endif
@@ -236,10 +249,17 @@ _try_to_get_lock:
/* Pickup the CPU ID. */
MRS x1, MPIDR_EL1 // Pickup the core ID
#ifdef TX_ARMV8_2
#if TX_THREAD_SMP_CLUSTERS > 1
UBFX x7, x1, #16, #8 // Isolate cluster ID
#endif
UBFX x1, x1, #8, #8 // Isolate core ID
#else
#if TX_THREAD_SMP_CLUSTERS > 1
UBFX x7, x1, #8, #8 // Isolate cluster ID
#endif
UBFX x1, x1, #0, #8 // Isolate core ID
#endif
#if TX_THREAD_SMP_CLUSTERS > 1
ADDS x1, x1, x7, LSL #2 // Calculate CPU ID
#endif
@@ -257,7 +277,7 @@ _try_to_get_lock:
/* Are we at the front of the list? */
// if (this_core == _tx_thread_smp_protect_wait_list[_tx_thread_smp_protect_wait_list_head])
// {/
// {
LDR x3, =_tx_thread_smp_protect_wait_list_head // Get the address of the head
LDR w3, [x3] // Get the value of the head
@@ -271,7 +291,7 @@ _try_to_get_lock:
// if (_tx_thread_smp_protection.tx_thread_smp_protect_in_force == 0)
// {
LDR w3, [x2, #0] // Pickup the protection flag
LDAXR w3, [x2, #0] // Pickup the protection flag
CMP w3, #0
BNE _did_not_get_lock // No, protection not available
@@ -279,7 +299,9 @@ _try_to_get_lock:
// _tx_thread_smp_protection.tx_thread_smp_protect_in_force = 1;
MOV w3, #1 // Build lock value
STR w3, [x2, #0] // Store lock value
STXR w4, w3, [x2, #0] // Attempt to get the protection
CMP w4, #0
BNE _did_not_get_lock // Did it fail?
DMB ISH //
/* Got the lock. */
@@ -328,7 +350,7 @@ _already_in_list1:
/* Restore interrupts and try again. */
MSR DAIF, x0 // Restore interrupts
ISB //
ISB //
#ifdef TX_ENABLE_WFE
WFE // Go into standby
#endif
@@ -349,4 +371,3 @@ _got_lock_after_waiting:
_return:
RET

116
ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_smp_protection_wait_list_macros.h
View File

@@ -23,12 +23,12 @@
.macro _tx_thread_smp_protect_lock_got
/* Set the currently owned core. */
/* _tx_thread_smp_protection.tx_thread_smp_protect_core = this_core; */
// _tx_thread_smp_protection.tx_thread_smp_protect_core = this_core;
STR w1, [x2, #4] // Store this core
/* Increment the protection count. */
/* _tx_thread_smp_protection.tx_thread_smp_protect_count++; */
// _tx_thread_smp_protection.tx_thread_smp_protect_count++;
LDR w3, [x2, #8] // Pickup ownership count
ADD w3, w3, #1 // Increment ownership count
@@ -40,7 +40,7 @@
.macro _tx_thread_smp_protect_remove_from_front_of_list
/* Remove ourselves from the list. */
/* _tx_thread_smp_protect_wait_list[_tx_thread_smp_protect_wait_list_head++] = 0xFFFFFFFF; */
// _tx_thread_smp_protect_wait_list[_tx_thread_smp_protect_wait_list_head++] = 0xFFFFFFFF;
MOV w3, #0xFFFFFFFF // Build the invalid core value
LDR x4, =_tx_thread_smp_protect_wait_list_head // Get the address of the head
@@ -50,53 +50,55 @@
ADD w5, w5, #1 // Increment the head
/* Did we wrap? */
/* if (_tx_thread_smp_protect_wait_list_head == TX_THREAD_SMP_MAX_CORES + 1)
{ */
// if (_tx_thread_smp_protect_wait_list_head == TX_THREAD_SMP_MAX_CORES + 1)
// {
LDR x3, =_tx_thread_smp_protect_wait_list_size // Load address of core list size
LDR w3, [x3] // Load the max cores value
CMP w5, w3 // Compare the head to it
BNE _store_new_head\@ // Are we at the max?
/* _tx_thread_smp_protect_wait_list_head = 0; */
// _tx_thread_smp_protect_wait_list_head = 0;
EOR w5, w5, w5 // We're at the max. Set it to zero
/* } */
// }
_store_new_head\@:
STR w5, [x4] // Store the new head
/* We have the lock! */
/* return; */
DMB ISH // Ensure write to protection finishes
// return;
.endm
.macro _tx_thread_smp_protect_wait_list_lock_get
/* VOID _tx_thread_smp_protect_wait_list_lock_get()
{ */
// VOID _tx_thread_smp_protect_wait_list_lock_get()
// {
/* We do this until we have the lock. */
/* while (1)
{ */
// while (1)
// {
_tx_thread_smp_protect_wait_list_lock_get__try_to_get_lock\@:
/* Is the list lock available? */
/* _tx_thread_smp_protect_wait_list_lock_protect_in_force = load_exclusive(&_tx_thread_smp_protect_wait_list_lock_protect_in_force); */
// Is the list lock available? */
// _tx_thread_smp_protect_wait_list_lock_protect_in_force = load_exclusive(&_tx_thread_smp_protect_wait_list_lock_protect_in_force);
LDR x1, =_tx_thread_smp_protect_wait_list_lock_protect_in_force
LDAXR w2, [x1] // Pickup the protection flag
/* if (protect_in_force == 0)
{ */
// if (protect_in_force == 0)
// {
CMP w2, #0
BNE _tx_thread_smp_protect_wait_list_lock_get__try_to_get_lock\@ // No, protection not available
/* Try to get the list. */
/* int status = store_exclusive(&_tx_thread_smp_protect_wait_list_lock_protect_in_force, 1); */
// int status = store_exclusive(&_tx_thread_smp_protect_wait_list_lock_protect_in_force, 1);
MOV w2, #1 // Build lock value
STXR w3, w2, [x1] // Attempt to get the protection
@@ -107,17 +109,17 @@ _tx_thread_smp_protect_wait_list_lock_get__try_to_get_lock\@:
BNE _tx_thread_smp_protect_wait_list_lock_get__try_to_get_lock\@ // Did it fail? If so, try again.
/* We have the lock! */
/* return; */
// return;
.endm
.macro _tx_thread_smp_protect_wait_list_add
/* VOID _tx_thread_smp_protect_wait_list_add(UINT new_core)
{ */
// VOID _tx_thread_smp_protect_wait_list_add(UINT new_core)
// {
/* We're about to modify the list, so get the list lock. */
/* _tx_thread_smp_protect_wait_list_lock_get(); */
// _tx_thread_smp_protect_wait_list_lock_get();
STP x1, x2, [sp, #-16]! // Save registers we'll be using
@@ -126,7 +128,7 @@ _tx_thread_smp_protect_wait_list_lock_get__try_to_get_lock\@:
LDP x1, x2, [sp], #16
/* Add this core. */
/* _tx_thread_smp_protect_wait_list[_tx_thread_smp_protect_wait_list_tail++] = new_core; */
// _tx_thread_smp_protect_wait_list[_tx_thread_smp_protect_wait_list_tail++] = new_core;
LDR x3, =_tx_thread_smp_protect_wait_list_tail // Get the address of the tail
LDR w4, [x3] // Get the value of tail
@@ -135,64 +137,66 @@ _tx_thread_smp_protect_wait_list_lock_get__try_to_get_lock\@:
ADD w4, w4, #1 // Increment the tail
/* Did we wrap? */
/* if (_tx_thread_smp_protect_wait_list_tail == _tx_thread_smp_protect_wait_list_size)
{ */
// if (_tx_thread_smp_protect_wait_list_tail == _tx_thread_smp_protect_wait_list_size)
// {
LDR x5, =_tx_thread_smp_protect_wait_list_size // Load max cores address
LDR w5, [x5] // Load max cores value
CMP w4, w5 // Compare max cores to tail
BNE _tx_thread_smp_protect_wait_list_add__no_wrap\@ // Did we wrap?
/* _tx_thread_smp_protect_wait_list_tail = 0; */
// _tx_thread_smp_protect_wait_list_tail = 0;
MOV w4, #0
/* } */
// }
_tx_thread_smp_protect_wait_list_add__no_wrap\@:
STR w4, [x3] // Store the new tail value.
DMB ISH // Ensure that accesses to shared resource have completed
/* Release the list lock. */
/* _tx_thread_smp_protect_wait_list_lock_protect_in_force = 0; */
// _tx_thread_smp_protect_wait_list_lock_protect_in_force = 0;
MOV w3, #0 // Build lock value
LDR x4, =_tx_thread_smp_protect_wait_list_lock_protect_in_force
STR w3, [x4] // Store the new value
DMB ISH // Ensure write to protection finishes
.endm
.macro _tx_thread_smp_protect_wait_list_remove
/* VOID _tx_thread_smp_protect_wait_list_remove(UINT core)
{ */
// VOID _tx_thread_smp_protect_wait_list_remove(UINT core)
// {
/* Get the core index. */
/* UINT core_index;
for (core_index = 0;; core_index++) */
// UINT core_index;
// for (core_index = 0;; core_index++)
EOR w4, w4, w4 // Clear for 'core_index'
LDR x2, =_tx_thread_smp_protect_wait_list // Get the address of the list
/* { */
// {
_tx_thread_smp_protect_wait_list_remove__check_cur_core\@:
/* Is this the core? */
/* if (_tx_thread_smp_protect_wait_list[core_index] == core)
{
break; */
// if (_tx_thread_smp_protect_wait_list[core_index] == core)
// {
// break;
LDR w3, [x2, x4, LSL #2] // Get the value at the current index
CMP w3, w8 // Did we find the core?
BEQ _tx_thread_smp_protect_wait_list_remove__found_core\@
/* } */
// }
ADD w4, w4, #1 // Increment cur index
B _tx_thread_smp_protect_wait_list_remove__check_cur_core\@ // Restart the loop
/* } */
// }
_tx_thread_smp_protect_wait_list_remove__found_core\@:
@@ -200,15 +204,15 @@ _tx_thread_smp_protect_wait_list_remove__found_core\@:
core could be simultaneously adding (a core is simultaneously trying to get
the inter-core lock) or removing (a core is simultaneously being preempted,
like what is currently happening). */
/* _tx_thread_smp_protect_wait_list_lock_get(); */
// _tx_thread_smp_protect_wait_list_lock_get();
MOV x6, x1
_tx_thread_smp_protect_wait_list_lock_get
MOV x1, x6
/* We remove by shifting. */
/* while (core_index != _tx_thread_smp_protect_wait_list_tail)
{ */
// while (core_index != _tx_thread_smp_protect_wait_list_tail)
// {
_tx_thread_smp_protect_wait_list_remove__compare_index_to_tail\@:
@@ -217,76 +221,78 @@ _tx_thread_smp_protect_wait_list_remove__compare_index_to_tail\@:
CMP w4, w2 // Compare cur index and tail
BEQ _tx_thread_smp_protect_wait_list_remove__removed\@
/* UINT next_index = core_index + 1; */
// UINT next_index = core_index + 1;
MOV w2, w4 // Move current index to next index register
ADD w2, w2, #1 // Add 1
/* if (next_index == _tx_thread_smp_protect_wait_list_size)
{ */
// if (next_index == _tx_thread_smp_protect_wait_list_size)
// {
LDR x3, =_tx_thread_smp_protect_wait_list_size
LDR w3, [x3]
CMP w2, w3
BNE _tx_thread_smp_protect_wait_list_remove__next_index_no_wrap\@
/* next_index = 0; */
// next_index = 0;
MOV w2, #0
/* } */
// }
_tx_thread_smp_protect_wait_list_remove__next_index_no_wrap\@:
/* list_cores[core_index] = list_cores[next_index]; */
// list_cores[core_index] = list_cores[next_index];
LDR x5, =_tx_thread_smp_protect_wait_list // Get the address of the list
LDR w3, [x5, x2, LSL #2] // Get the value at the next index
STR w3, [x5, x4, LSL #2] // Store the value at the current index
/* core_index = next_index; */
// core_index = next_index;
MOV w4, w2
B _tx_thread_smp_protect_wait_list_remove__compare_index_to_tail\@
/* } */
// }
_tx_thread_smp_protect_wait_list_remove__removed\@:
/* Now update the tail. */
/* if (_tx_thread_smp_protect_wait_list_tail == 0)
{ */
// if (_tx_thread_smp_protect_wait_list_tail == 0)
// {
LDR x5, =_tx_thread_smp_protect_wait_list_tail // Load tail address
LDR w4, [x5] // Load tail value
CMP w4, #0
BNE _tx_thread_smp_protect_wait_list_remove__tail_not_zero\@
/* _tx_thread_smp_protect_wait_list_tail = _tx_thread_smp_protect_wait_list_size; */
// _tx_thread_smp_protect_wait_list_tail = _tx_thread_smp_protect_wait_list_size;
LDR x2, =_tx_thread_smp_protect_wait_list_size
LDR w4, [x2]
/* } */
// }
_tx_thread_smp_protect_wait_list_remove__tail_not_zero\@:
/* _tx_thread_smp_protect_wait_list_tail--; */
// _tx_thread_smp_protect_wait_list_tail--;
SUB w4, w4, #1
STR w4, [x5] // Store new tail value
DMB ISH // Ensure that accesses to shared resource have completed
/* Release the list lock. */
/* _tx_thread_smp_protect_wait_list_lock_protect_in_force = 0; */
// _tx_thread_smp_protect_wait_list_lock_protect_in_force = 0;
MOV w2, #0 // Build lock value
LDR x4, =_tx_thread_smp_protect_wait_list_lock_protect_in_force // Load lock address
STR w2, [x4] // Store the new value
DMB ISH // Ensure write to protection finishes
/* We're no longer waiting. Note that this should be zero since, again,
this function is only called when a thread preemption is occurring. */
/* _tx_thread_smp_protect_wait_counts[core]--; */
// _tx_thread_smp_protect_wait_counts[core]--;
LDR x4, =_tx_thread_smp_protect_wait_counts // Load wait list counts
LDR w2, [x4, x8, LSL #2] // Load waiting value
SUB w2, w2, #1 // Subtract 1

13
ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_smp_unprotect.S
View File

@@ -28,7 +28,7 @@
/* FUNCTION RELEASE */
/* */
/* _tx_thread_smp_unprotect Cortex-A35-SMP/AC6 */
/* 6.1 */
/* 6.1.9 */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
@@ -61,6 +61,9 @@
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 10-15-2021 Andres Mlinar Updated comments, */
/* added ARMv8.2-A support, */
/* resulting in version 6.1.9 */
/* */
/**************************************************************************/
.global _tx_thread_smp_unprotect
@@ -69,10 +72,17 @@ _tx_thread_smp_unprotect:
MSR DAIFSet, 0x3 // Lockout interrupts
MRS x1, MPIDR_EL1 // Pickup the core ID
#ifdef TX_ARMV8_2
#if TX_THREAD_SMP_CLUSTERS > 1
UBFX x2, x1, #16, #8 // Isolate cluster ID
#endif
UBFX x1, x1, #8, #8 // Isolate core ID
#else
#if TX_THREAD_SMP_CLUSTERS > 1
UBFX x2, x1, #8, #8 // Isolate cluster ID
#endif
UBFX x1, x1, #0, #8 // Isolate core ID
#endif
#if TX_THREAD_SMP_CLUSTERS > 1
ADDS x1, x1, x2, LSL #2 // Calculate CPU ID
#endif
@@ -114,4 +124,3 @@ _still_protected:
#endif
MSR DAIF, x0 // Restore interrupt posture
RET

9
ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_timeout.c
View File

@@ -12,8 +12,8 @@
/**************************************************************************/
/**************************************************************************/
/** */
/** ThreadX Component */
/** */
/** ThreadX Component */
/** */
/** Thread */
/** */
@@ -79,7 +79,7 @@ VOID _tx_thread_timeout(ULONG timeout_input)
TX_INTERRUPT_SAVE_AREA
TX_THREAD *thread_ptr;
TX_THREAD *thread_ptr;
VOID (*suspend_cleanup)(struct TX_THREAD_STRUCT *suspend_thread_ptr, ULONG suspension_sequence);
ULONG suspension_sequence;
@@ -126,7 +126,7 @@ ULONG suspension_sequence;
/* Increment the number of timeouts for this thread. */
thread_ptr -> tx_thread_performance_timeout_count++;
#endif
/* Pickup the cleanup routine address. */
suspend_cleanup = thread_ptr -> tx_thread_suspend_cleanup;
@@ -162,4 +162,3 @@ ULONG suspension_sequence;
#endif
}
}

2
ports_module/cortex_a35_smp/ac6/module_manager/src/txm_module_manager_port_dispatch.c
View File

@@ -80,6 +80,6 @@ ALIGN_TYPE return_value = TX_NOT_AVAILABLE;
break;
}
}
return(return_value);
}

2
ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/GICv3.h
View File

@@ -3,7 +3,7 @@
*
* Copyright (c) 2014-2017 Arm Limited (or its affiliates). All rights reserved.
* Use, modification and redistribution of this file is subject to your possession of a
* valid End User License Agreement for the Arm Product of which these examples are part of
* valid End User License Agreement for the Arm Product of which these examples are part of
* and your compliance with all applicable terms and conditions of such licence agreement.
*/
#ifndef GICV3_h

2
ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/GICv3_aliases.h
View File

@@ -3,7 +3,7 @@
//
// Copyright (c) 2016-2017 Arm Limited (or its affiliates). All rights reserved.
// Use, modification and redistribution of this file is subject to your possession of a
// valid End User License Agreement for the Arm Product of which these examples are part of
// valid End User License Agreement for the Arm Product of which these examples are part of
// and your compliance with all applicable terms and conditions of such licence agreement.
//

2
ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/GICv3_gicc.h
View File

@@ -3,7 +3,7 @@
*
* Copyright (c) 2014-2017 Arm Limited (or its affiliates). All rights reserved.
* Use, modification and redistribution of this file is subject to your possession of a
* valid End User License Agreement for the Arm Product of which these examples are part of
* valid End User License Agreement for the Arm Product of which these examples are part of
* and your compliance with all applicable terms and conditions of such licence agreement.
*/
#ifndef GICV3_gicc_h

2
ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/GICv3_gicd.c
View File

@@ -3,7 +3,7 @@
*
* Copyright (c) 2014-2017 Arm Limited (or its affiliates). All rights reserved.
* Use, modification and redistribution of this file is subject to your possession of a
* valid End User License Agreement for the Arm Product of which these examples are part of
* valid End User License Agreement for the Arm Product of which these examples are part of
* and your compliance with all applicable terms and conditions of such licence agreement.
*/
#include <stdint.h>

2
ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/GICv3_gicr.c
View File

@@ -3,7 +3,7 @@
*
* Copyright (c) 2014-2018 Arm Limited (or its affiliates). All rights reserved.
* Use, modification and redistribution of this file is subject to your possession of a
* valid End User License Agreement for the Arm Product of which these examples are part of
* valid End User License Agreement for the Arm Product of which these examples are part of
* and your compliance with all applicable terms and conditions of such licence agreement.
*/
#include "GICv3.h"

2
ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/MP_Mutexes.S
View File

@@ -3,7 +3,7 @@
//
// Copyright (c) 2012-2017 Arm Limited (or its affiliates). All rights reserved.
// Use, modification and redistribution of this file is subject to your possession of a
// valid End User License Agreement for the Arm Product of which these examples are part of
// valid End User License Agreement for the Arm Product of which these examples are part of
// and your compliance with all applicable terms and conditions of such licence agreement.
//

2
ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/PPM_AEM.h
View File

@@ -3,7 +3,7 @@
//
// Copyright (c) 2012-2017 Arm Limited (or its affiliates). All rights reserved.
// Use, modification and redistribution of this file is subject to your possession of a
// valid End User License Agreement for the Arm Product of which these examples are part of
// valid End User License Agreement for the Arm Product of which these examples are part of
// and your compliance with all applicable terms and conditions of such licence agreement.
//

46
ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/sample_threadx.c
View File

@@ -1,5 +1,5 @@
/* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight
threads of different priorities, using a message queue, semaphore, mutex, event flags group,
threads of different priorities, using a message queue, semaphore, mutex, event flags group,
byte pool, and block pool. */
#include "tx_api.h"
@@ -104,41 +104,41 @@ CHAR *pointer = TX_NULL;
tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
/* Create the main thread. */
tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0,
pointer, DEMO_STACK_SIZE,
tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0,
pointer, DEMO_STACK_SIZE,
1, 1, TX_NO_TIME_SLICE, TX_AUTO_START);
/* Allocate the stack for thread 1. */
tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
/* Create threads 1 and 2. These threads pass information through a ThreadX
/* Create threads 1 and 2. These threads pass information through a ThreadX
message queue. It is also interesting to note that these threads have a time
slice. */
tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1,
pointer, DEMO_STACK_SIZE,
pointer, DEMO_STACK_SIZE,
16, 16, 4, TX_AUTO_START);
/* Allocate the stack for thread 2. */
tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2,
pointer, DEMO_STACK_SIZE,
pointer, DEMO_STACK_SIZE,
16, 16, 4, TX_AUTO_START);
/* Allocate the stack for thread 3. */
tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
/* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore.
/* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore.
An interesting thing here is that both threads share the same instruction area. */
tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3,
pointer, DEMO_STACK_SIZE,
tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3,
pointer, DEMO_STACK_SIZE,
8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
/* Allocate the stack for thread 4. */
tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4,
pointer, DEMO_STACK_SIZE,
tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4,
pointer, DEMO_STACK_SIZE,
8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
/* Allocate the stack for thread 5. */
@@ -146,23 +146,23 @@ CHAR *pointer = TX_NULL;
/* Create thread 5. This thread simply pends on an event flag which will be set
by thread_0. */
tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5,
pointer, DEMO_STACK_SIZE,
tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5,
pointer, DEMO_STACK_SIZE,
4, 4, TX_NO_TIME_SLICE, TX_AUTO_START);
/* Allocate the stack for thread 6. */
tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
/* Create threads 6 and 7. These threads compete for a ThreadX mutex. */
tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6,
pointer, DEMO_STACK_SIZE,
tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6,
pointer, DEMO_STACK_SIZE,
8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
/* Allocate the stack for thread 7. */
tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7,
pointer, DEMO_STACK_SIZE,
tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7,
pointer, DEMO_STACK_SIZE,
8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
/* Allocate the message queue. */
@@ -264,11 +264,11 @@ UINT status;
/* Retrieve a message from the queue. */
status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER);
/* Check completion status and make sure the message is what we
/* Check completion status and make sure the message is what we
expected. */
if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received))
break;
/* Otherwise, all is okay. Increment the received message count. */
thread_2_messages_received++;
}
@@ -327,7 +327,7 @@ ULONG actual_flags;
thread_5_counter++;
/* Wait for event flag 0. */
status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR,
status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR,
&actual_flags, TX_WAIT_FOREVER);
/* Check status. */
@@ -380,7 +380,7 @@ UINT status;
if (status != TX_SUCCESS)
break;
/* Release the mutex again. This will actually
/* Release the mutex again. This will actually
release ownership since it was obtained twice. */
status = tx_mutex_put(&mutex_0);

2
ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/sp804_timer.c
View File

@@ -3,7 +3,7 @@
//
// Copyright (c) 2009-2017 Arm Limited (or its affiliates). All rights reserved.
// Use, modification and redistribution of this file is subject to your possession of a
// valid End User License Agreement for the Arm Product of which these examples are part of
// valid End User License Agreement for the Arm Product of which these examples are part of
// and your compliance with all applicable terms and conditions of such licence agreement.
// ------------------------------------------------------------

2
ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/sp804_timer.h
View File

@@ -4,7 +4,7 @@
//
// Copyright (c) 2009-2017 Arm Limited (or its affiliates). All rights reserved.
// Use, modification and redistribution of this file is subject to your possession of a
// valid End User License Agreement for the Arm Product of which these examples are part of
// valid End User License Agreement for the Arm Product of which these examples are part of
// and your compliance with all applicable terms and conditions of such licence agreement.
// ------------------------------------------------------------

10
ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/startup.S
View File

@@ -7,7 +7,7 @@
//
// Copyright (c) 2014-2017 Arm Limited (or its affiliates). All rights reserved.
// Use, modification and redistribution of this file is subject to your possession of a
// valid End User License Agreement for the Arm Product of which these examples are part of
// valid End User License Agreement for the Arm Product of which these examples are part of
// and your compliance with all applicable terms and conditions of such licence agreement.
// ------------------------------------------------------------
@@ -326,7 +326,7 @@ el1_entry_aarch64:
//
// Cortex-A processors automatically invalidate their caches on reset
// (unless suppressed with the DBGL1RSTDISABLE or L2RSTDISABLE pins).
// It is therefore not necessary for software to invalidate the caches
// It is therefore not necessary for software to invalidate the caches
// on startup, however, this is done here in case of a warm reset.
bl InvalidateUDCaches
tlbi VMALLE1
@@ -685,7 +685,7 @@ nol2setup:
bic x1, x1, #SCTLR_ELx_A // Disable alignment fault checking. To enable, change bic to orr
msr SCTLR_EL1, x1
isb
//
// The Arm Architecture Reference Manual for Armv8-A states:
//
@@ -740,7 +740,7 @@ arg0:
bl main
b exit // Will not return
// ------------------------------------------------------------
// EL1 - secondary CPU init code
//
@@ -795,4 +795,4 @@ loop_wfi:
// Branch to thread start
//
//B MainApp

2
ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/v8_aarch64.S
View File

@@ -3,7 +3,7 @@
//
// Copyright (c) 2012-2018 Arm Limited (or its affiliates). All rights reserved.
// Use, modification and redistribution of this file is subject to your possession of a
// valid End User License Agreement for the Arm Product of which these examples are part of
// valid End User License Agreement for the Arm Product of which these examples are part of
// and your compliance with all applicable terms and conditions of such licence agreement.
// ------------------------------------------------------------

2
ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/v8_mmu.h
View File

@@ -3,7 +3,7 @@
//
// Copyright (c) 2012-2016 Arm Limited (or its affiliates). All rights reserved.
// Use, modification and redistribution of this file is subject to your possession of a
// valid End User License Agreement for the Arm Product of which these examples are part of
// valid End User License Agreement for the Arm Product of which these examples are part of
// and your compliance with all applicable terms and conditions of such licence agreement.
//

2
ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/v8_system.h
View File

@@ -3,7 +3,7 @@
//
// Copyright (c) 2012-2016 Arm Limited (or its affiliates). All rights reserved.
// Use, modification and redistribution of this file is subject to your possession of a
// valid End User License Agreement for the Arm Product of which these examples are part of
// valid End User License Agreement for the Arm Product of which these examples are part of
// and your compliance with all applicable terms and conditions of such licence agreement.
//

2
ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/v8_utils.S
View File

@@ -3,7 +3,7 @@
//
// Copyright (c) 2013-2017 Arm Limited (or its affiliates). All rights reserved.
// Use, modification and redistribution of this file is subject to your possession of a
// valid End User License Agreement for the Arm Product of which these examples are part of
// valid End User License Agreement for the Arm Product of which these examples are part of
// and your compliance with all applicable terms and conditions of such licence agreement.
//

2
ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/vectors.S
View File

@@ -3,7 +3,7 @@
//
// Copyright (c) 2014-2016 Arm Limited (or its affiliates). All rights reserved.
// Use, modification and redistribution of this file is subject to your possession of a
// valid End User License Agreement for the Arm Product of which these examples are part of
// valid End User License Agreement for the Arm Product of which these examples are part of
// and your compliance with all applicable terms and conditions of such licence agreement.
// ------------------------------------------------------------

14
ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module/gcc_setup.s
View File

@@ -17,7 +17,7 @@ _gcc_setup:
ldr x9, =__RAM_segment_start__
/* Copy GOT table. */
ldr x0, =__got_load_start__
sub x0 ,x0, x3
add x0, x0, x5
@@ -51,7 +51,7 @@ got_setup_done:
/* Copy initialised sections into RAM if required. */
ldr x0, =__data_load_start__
sub x0, x0, x3
add x0, x0, x5
@@ -62,9 +62,9 @@ got_setup_done:
sub x2, x2, x4
add x2, x2, x9
bl crt0_memory_copy
/* Zero bss. */
ldr x0, =__bss_start__
sub x0, x0, x4
add x0, x0, x9
@@ -88,12 +88,12 @@ got_setup_done:
str x2, [x0]
add x0, x0, #4
str x1, [x0]
ldr x30, [sp] // Restore other preserved registers
add sp, sp, 16
ret // Return to caller
/* Startup helper functions. */
@@ -126,4 +126,4 @@ memory_set_done:
/* Setup attibutes of heap section so it doesn't take up room in the elf file */
.section .heap, "wa", %nobits

42
ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module/sample_threadx_module.c
View File

@@ -1,5 +1,5 @@
/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes
examples of eight threads of different priorities, using a message queue, semaphore, mutex,
/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes
examples of eight threads of different priorities, using a message queue, semaphore, mutex,
event flags group, byte pool, and block pool. */
/* Specify that this is a module! */
@@ -20,7 +20,7 @@
#define DEMO_QUEUE_SIZE 100
/* Define the pool space in the bss section of the module. ULONG is used to
/* Define the pool space in the bss section of the module. ULONG is used to
get the word alignment. */
ULONG demo_module_pool_space[DEMO_BYTE_POOL_SIZE / sizeof(ULONG)];
@@ -103,7 +103,7 @@ CHAR *pointer;
/* Allocate all the objects. In MMU mode, modules cannot allocate control blocks within
their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting
their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting
the control block(s). */
status = txm_module_object_allocate((void*)&thread_0, sizeof(TX_THREAD));
while (status != TX_SUCCESS);
@@ -133,7 +133,7 @@ CHAR *pointer;
while (status != TX_SUCCESS);
status = txm_module_object_allocate((void*)&block_pool_0, sizeof(TX_BLOCK_POOL));
while (status != TX_SUCCESS);
/* Create a byte memory pool from which to allocate the thread stacks. */
status = tx_byte_pool_create(byte_pool_0, "module byte pool 0", demo_module_pool_space, DEMO_BYTE_POOL_SIZE);
@@ -193,7 +193,7 @@ CHAR *pointer;
/* Create the main thread. */
status = tx_thread_create(thread_0, "module thread 0", thread_0_entry, 0,
pointer, DEMO_STACK_SIZE,
pointer, DEMO_STACK_SIZE,
1, 1, TX_NO_TIME_SLICE, TX_AUTO_START);
while (status != TX_SUCCESS);
@@ -201,11 +201,11 @@ CHAR *pointer;
status = tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
while (status != TX_SUCCESS);
/* Create threads 1 and 2. These threads pass information through a ThreadX
/* Create threads 1 and 2. These threads pass information through a ThreadX
message queue. It is also interesting to note that these threads have a time
slice. */
status = tx_thread_create(thread_1, "module thread 1", thread_1_entry, 1,
pointer, DEMO_STACK_SIZE,
pointer, DEMO_STACK_SIZE,
16, 16, 4, TX_AUTO_START);
while (status != TX_SUCCESS);
@@ -214,7 +214,7 @@ CHAR *pointer;
while (status != TX_SUCCESS);
status = tx_thread_create(thread_2, "module thread 2", thread_2_entry, 2,
pointer, DEMO_STACK_SIZE,
pointer, DEMO_STACK_SIZE,
16, 16, 4, TX_AUTO_START);
while (status != TX_SUCCESS);
@@ -222,10 +222,10 @@ CHAR *pointer;
status = tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
while (status != TX_SUCCESS);
/* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore.
/* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore.
An interesting thing here is that both threads share the same instruction area. */
status = tx_thread_create(thread_3, "module thread 3", thread_3_and_4_entry, 3,
pointer, DEMO_STACK_SIZE,
pointer, DEMO_STACK_SIZE,
8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
while (status != TX_SUCCESS);
@@ -234,7 +234,7 @@ CHAR *pointer;
while (status != TX_SUCCESS);
status = tx_thread_create(thread_4, "module thread 4", thread_3_and_4_entry, 4,
pointer, DEMO_STACK_SIZE,
pointer, DEMO_STACK_SIZE,
8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
while (status != TX_SUCCESS);
@@ -245,7 +245,7 @@ CHAR *pointer;
/* Create thread 5. This thread simply pends on an event flag which will be set
by thread_0. */
status = tx_thread_create(thread_5, "module thread 5", thread_5_entry, 5,
pointer, DEMO_STACK_SIZE,
pointer, DEMO_STACK_SIZE,
4, 4, TX_NO_TIME_SLICE, TX_AUTO_START);
while (status != TX_SUCCESS);
@@ -255,7 +255,7 @@ CHAR *pointer;
/* Create threads 6 and 7. These threads compete for a ThreadX mutex. */
status = tx_thread_create(thread_6, "module thread 6", thread_6_and_7_entry, 6,
pointer, DEMO_STACK_SIZE,
pointer, DEMO_STACK_SIZE,
8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
while (status != TX_SUCCESS);
@@ -264,7 +264,7 @@ CHAR *pointer;
while (status != TX_SUCCESS);
status = tx_thread_create(thread_7, "module thread 7", thread_6_and_7_entry, 7,
pointer, DEMO_STACK_SIZE,
pointer, DEMO_STACK_SIZE,
8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
while (status != TX_SUCCESS);
}
@@ -276,7 +276,7 @@ void thread_0_entry(ULONG thread_input)
{
UINT status;
/* This thread simply sits in while-forever-sleep loop. */
while(1)
{
@@ -286,7 +286,7 @@ UINT status;
/* Sleep for 10 ticks. */
tx_thread_sleep(10);
/* Set event flag 0 to wakeup thread 5. */
status = tx_event_flags_set(event_flags_0, 0x1, TX_OR);
@@ -338,11 +338,11 @@ UINT status;
/* Retrieve a message from the queue. */
status = tx_queue_receive(queue_0, &received_message, TX_WAIT_FOREVER);
/* Check completion status and make sure the message is what we
/* Check completion status and make sure the message is what we
expected. */
if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received))
break;
/* Otherwise, all is okay. Increment the received message count. */
thread_2_messages_received++;
}
@@ -401,7 +401,7 @@ ULONG actual_flags;
thread_5_counter++;
/* Wait for event flag 0. */
status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR,
status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR,
&actual_flags, TX_WAIT_FOREVER);
/* Check status. */
@@ -454,7 +454,7 @@ UINT status;
if (status != TX_SUCCESS)
break;
/* Release the mutex again. This will actually
/* Release the mutex again. This will actually
release ownership since it was obtained twice. */
status = tx_mutex_put(mutex_0);

2
ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module/txm_module_preamble.S
View File

@@ -1,6 +1,6 @@
.section .txm_module_preamble
.align 4
// External references
.global _txm_module_thread_shell_entry
.global _txm_module_callback_request_thread_entry

2
ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/GICv3.h
View File

@@ -3,7 +3,7 @@
*
* Copyright (c) 2014-2017 Arm Limited (or its affiliates). All rights reserved.
* Use, modification and redistribution of this file is subject to your possession of a
* valid End User License Agreement for the Arm Product of which these examples are part of
* valid End User License Agreement for the Arm Product of which these examples are part of
* and your compliance with all applicable terms and conditions of such licence agreement.
*/
#ifndef GICV3_h

2
ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/GICv3_aliases.h
View File

@@ -3,7 +3,7 @@
//
// Copyright (c) 2016-2017 Arm Limited (or its affiliates). All rights reserved.
// Use, modification and redistribution of this file is subject to your possession of a
// valid End User License Agreement for the Arm Product of which these examples are part of
// valid End User License Agreement for the Arm Product of which these examples are part of
// and your compliance with all applicable terms and conditions of such licence agreement.
//

2
ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/GICv3_gicc.h
View File

@@ -3,7 +3,7 @@
*
* Copyright (c) 2014-2017 Arm Limited (or its affiliates). All rights reserved.
* Use, modification and redistribution of this file is subject to your possession of a
* valid End User License Agreement for the Arm Product of which these examples are part of
* valid End User License Agreement for the Arm Product of which these examples are part of
* and your compliance with all applicable terms and conditions of such licence agreement.
*/
#ifndef GICV3_gicc_h

2
ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/GICv3_gicd.c
View File

@@ -3,7 +3,7 @@
*
* Copyright (c) 2014-2017 Arm Limited (or its affiliates). All rights reserved.
* Use, modification and redistribution of this file is subject to your possession of a
* valid End User License Agreement for the Arm Product of which these examples are part of
* valid End User License Agreement for the Arm Product of which these examples are part of
* and your compliance with all applicable terms and conditions of such licence agreement.
*/
#include <stdint.h>

2
ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/GICv3_gicr.c
View File

@@ -3,7 +3,7 @@
*
* Copyright (c) 2014-2018 Arm Limited (or its affiliates). All rights reserved.
* Use, modification and redistribution of this file is subject to your possession of a
* valid End User License Agreement for the Arm Product of which these examples are part of
* valid End User License Agreement for the Arm Product of which these examples are part of
* and your compliance with all applicable terms and conditions of such licence agreement.
*/
#include "GICv3.h"

2
ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/MP_Mutexes.S
View File

@@ -3,7 +3,7 @@
//
// Copyright (c) 2012-2017 Arm Limited (or its affiliates). All rights reserved.
// Use, modification and redistribution of this file is subject to your possession of a
// valid End User License Agreement for the Arm Product of which these examples are part of
// valid End User License Agreement for the Arm Product of which these examples are part of
// and your compliance with all applicable terms and conditions of such licence agreement.
//

2
ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/PPM_AEM.h
View File

@@ -3,7 +3,7 @@
//
// Copyright (c) 2012-2017 Arm Limited (or its affiliates). All rights reserved.
// Use, modification and redistribution of this file is subject to your possession of a
// valid End User License Agreement for the Arm Product of which these examples are part of
// valid End User License Agreement for the Arm Product of which these examples are part of
// and your compliance with all applicable terms and conditions of such licence agreement.
//

10
ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c
View File

@@ -115,7 +115,7 @@ void module_manager_entry(ULONG thread_input)
/* Load the module with absolute address linkage, in this example it is placed there by the multiple image download. */
txm_module_manager_absolute_load(&my_module, "my module", (void *) MODULE_CODE);
/* Start the module. */
txm_module_manager_start(&my_module);
@@ -127,10 +127,10 @@ void module_manager_entry(ULONG thread_input)
tx_thread_sleep(10);
}
}
/* Stop the module. */
txm_module_manager_stop(&my_module);
/* Unload the module. */
txm_module_manager_unload(&my_module);
@@ -139,11 +139,11 @@ void module_manager_entry(ULONG thread_input)
/* Start the module again. */
txm_module_manager_start(&my_module);
/* Now just spin... */
while(1)
{
tx_thread_sleep(10);
}
}

2
ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/sp804_timer.c
View File

@@ -3,7 +3,7 @@
//
// Copyright (c) 2009-2017 Arm Limited (or its affiliates). All rights reserved.
// Use, modification and redistribution of this file is subject to your possession of a
// valid End User License Agreement for the Arm Product of which these examples are part of
// valid End User License Agreement for the Arm Product of which these examples are part of
// and your compliance with all applicable terms and conditions of such licence agreement.
// ------------------------------------------------------------

2
ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/sp804_timer.h
View File

@@ -4,7 +4,7 @@
//
// Copyright (c) 2009-2017 Arm Limited (or its affiliates). All rights reserved.
// Use, modification and redistribution of this file is subject to your possession of a
// valid End User License Agreement for the Arm Product of which these examples are part of
// valid End User License Agreement for the Arm Product of which these examples are part of
// and your compliance with all applicable terms and conditions of such licence agreement.
// ------------------------------------------------------------

10
ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/startup.S
View File

@@ -7,7 +7,7 @@
//
// Copyright (c) 2014-2017 Arm Limited (or its affiliates). All rights reserved.
// Use, modification and redistribution of this file is subject to your possession of a
// valid End User License Agreement for the Arm Product of which these examples are part of
// valid End User License Agreement for the Arm Product of which these examples are part of
// and your compliance with all applicable terms and conditions of such licence agreement.
// ------------------------------------------------------------
@@ -326,7 +326,7 @@ el1_entry_aarch64:
//
// Cortex-A processors automatically invalidate their caches on reset
// (unless suppressed with the DBGL1RSTDISABLE or L2RSTDISABLE pins).
// It is therefore not necessary for software to invalidate the caches
// It is therefore not necessary for software to invalidate the caches
// on startup, however, this is done here in case of a warm reset.
bl InvalidateUDCaches
tlbi VMALLE1
@@ -685,7 +685,7 @@ nol2setup:
bic x1, x1, #SCTLR_ELx_A // Disable alignment fault checking. To enable, change bic to orr
msr SCTLR_EL1, x1
isb
//
// The Arm Architecture Reference Manual for Armv8-A states:
//
@@ -740,7 +740,7 @@ arg0:
bl main
b exit // Will not return
// ------------------------------------------------------------
// EL1 - secondary CPU init code
//
@@ -795,4 +795,4 @@ loop_wfi:
// Branch to thread start
//
//B MainApp

2
ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/v8_aarch64.S
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@@ -3,7 +3,7 @@
//
// Copyright (c) 2012-2018 Arm Limited (or its affiliates). All rights reserved.
// Use, modification and redistribution of this file is subject to your possession of a
// valid End User License Agreement for the Arm Product of which these examples are part of
// valid End User License Agreement for the Arm Product of which these examples are part of
// and your compliance with all applicable terms and conditions of such licence agreement.
// ------------------------------------------------------------

2
ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/v8_mmu.h
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@@ -3,7 +3,7 @@
//
// Copyright (c) 2012-2016 Arm Limited (or its affiliates). All rights reserved.
// Use, modification and redistribution of this file is subject to your possession of a
// valid End User License Agreement for the Arm Product of which these examples are part of
// valid End User License Agreement for the Arm Product of which these examples are part of
// and your compliance with all applicable terms and conditions of such licence agreement.
//

2
ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/v8_system.h
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@@ -3,7 +3,7 @@
//
// Copyright (c) 2012-2016 Arm Limited (or its affiliates). All rights reserved.
// Use, modification and redistribution of this file is subject to your possession of a
// valid End User License Agreement for the Arm Product of which these examples are part of
// valid End User License Agreement for the Arm Product of which these examples are part of
// and your compliance with all applicable terms and conditions of such licence agreement.
//

2
ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/v8_utils.S
View File

@@ -3,7 +3,7 @@
//
// Copyright (c) 2013-2017 Arm Limited (or its affiliates). All rights reserved.
// Use, modification and redistribution of this file is subject to your possession of a
// valid End User License Agreement for the Arm Product of which these examples are part of
// valid End User License Agreement for the Arm Product of which these examples are part of
// and your compliance with all applicable terms and conditions of such licence agreement.
//

2
ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/vectors.S
View File

@@ -3,7 +3,7 @@
//
// Copyright (c) 2014-2016 Arm Limited (or its affiliates). All rights reserved.
// Use, modification and redistribution of this file is subject to your possession of a
// valid End User License Agreement for the Arm Product of which these examples are part of
// valid End User License Agreement for the Arm Product of which these examples are part of
// and your compliance with all applicable terms and conditions of such licence agreement.
// ------------------------------------------------------------

9
ports_module/cortex_a35_smp/gnu/inc/tx_port.h
View File

@@ -26,7 +26,7 @@
/* PORT SPECIFIC C INFORMATION RELEASE */
/* */
/* tx_port.h Cortex-A35-SMP/GNU */
/* 6.1.3 */
/* 6.1.9 */
/* */
/* AUTHOR */
/* */
@@ -48,6 +48,9 @@
/* DATE NAME DESCRIPTION */
/* */
/* 12-31-2020 Andres Mlinar Initial Version 6.1.3 */
/* 10-15-2021 William E. Lamie Modified comment(s), added */
/* symbol ULONG64_DEFINED, */
/* resulting in version 6.1.9 */
/* */
/**************************************************************************/
@@ -152,7 +155,7 @@ typedef unsigned int ULONG;
typedef unsigned long long ULONG64;
typedef short SHORT;
typedef unsigned short USHORT;
#define ULONG64_DEFINED
/* Override the alignment type to use 64-bit alignment and storage for pointers. */
@@ -441,7 +444,7 @@ VOID tx_thread_fp_disable(VOID);
#ifdef TX_THREAD_INIT
CHAR _tx_version_id[] =
"Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Modules Cortex-A35-SMP/GNU Version 6.1.3 *";
"Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Modules Cortex-A35-SMP/GNU Version 6.1.9 *";
#else
extern CHAR _tx_version_id[];
#endif

2
ports_module/cortex_a35_smp/gnu/inc/txm_module_port.h
View File

@@ -274,6 +274,6 @@ ALIGN_TYPE _txm_module_manager_port_dispatch(TXM_MODULE_INSTANCE *module_instanc
#define TXM_MODULE_MANAGER_VERSION_ID \
CHAR _txm_module_manager_version_id[] = \
"Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-A35/GNU Version 6.1.3 *";
"Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-A35/GNU Version 6.1.9 *";
#endif

2
ports_module/cortex_a35_smp/gnu/module_lib/src/txm_module_thread_shell_entry.c
View File

@@ -121,7 +121,7 @@ VOID (*entry_exit_notify)(TX_THREAD *notify_thread_ptr, UINT type);
An error here typically indicates the resident portion of _tx_thread_schedule
is not supporting the trap to obtain the function pointer. */
}
/* Resume the module's callback thread, already created in the manager. */
_txe_thread_resume(thread_info -> txm_module_thread_entry_info_callback_request_thread);
}

15
ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_smp_core_get.S
View File

@@ -27,8 +27,8 @@
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_smp_core_get Cortex-A35-SMP/GNU */
/* 6.1 */
/* _tx_thread_smp_core_get Cortex-A35-SMP/GCC */
/* 6.1.9 */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
@@ -58,17 +58,28 @@
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 10-15-2021 Andres Mlinar Updated comments, */
/* added ARMv8.2-A support, */
/* resulting in version 6.1.9 */
/* */
/**************************************************************************/
.global _tx_thread_smp_core_get
.type _tx_thread_smp_core_get, @function
_tx_thread_smp_core_get:
MRS x0, MPIDR_EL1 // Pickup the core ID
#ifdef TX_ARMV8_2
#if TX_THREAD_SMP_CLUSTERS > 1
UBFX x1, x0, #16, #8 // Isolate cluster ID
#endif
UBFX x0, x0, #8, #8 // Isolate core ID
#else
#if TX_THREAD_SMP_CLUSTERS > 1
UBFX x1, x0, #8, #8 // Isolate cluster ID
#endif
UBFX x0, x0, #0, #8 // Isolate core ID
#endif
#if TX_THREAD_SMP_CLUSTERS > 1
ADDS x0, x0, x1, LSL #2 // Calculate CPU ID
#endif
RET

41
ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_smp_protect.S
View File

@@ -31,8 +31,8 @@
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_smp_protect Cortex-A35-SMP/GNU */
/* 6.1 */
/* _tx_thread_smp_protect Cortex-A35-SMP/GCC */
/* 6.1.9 */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
@@ -64,6 +64,10 @@
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 10-15-2021 Andres Mlinar Updated comments, */
/* added ARMv8.2-A support, */
/* improved SMP code, */
/* resulting in version 6.1.9 */
/* */
/**************************************************************************/
.global _tx_thread_smp_protect
@@ -78,10 +82,17 @@ _tx_thread_smp_protect:
/* Pickup the CPU ID. */
MRS x1, MPIDR_EL1 // Pickup the core ID
#ifdef TX_ARMV8_2
#if TX_THREAD_SMP_CLUSTERS > 1
UBFX x7, x1, #16, #8 // Isolate cluster ID
#endif
UBFX x1, x1, #8, #8 // Isolate core ID
#else
#if TX_THREAD_SMP_CLUSTERS > 1
UBFX x7, x1, #8, #8 // Isolate cluster ID
#endif
UBFX x1, x1, #0, #8 // Isolate core ID
#endif
#if TX_THREAD_SMP_CLUSTERS > 1
ADDS x1, x1, x7, LSL #2 // Calculate CPU ID
#endif
@@ -163,7 +174,7 @@ _list_not_empty:
// if (_tx_thread_smp_protection.tx_thread_smp_protect_in_force == 0)
// {
LDR w3, [x2, #0] // Pickup the protection flag
LDAXR w3, [x2, #0] // Pickup the protection flag
CMP w3, #0
BNE _start_waiting // No, protection not available
@@ -171,7 +182,9 @@ _list_not_empty:
// _tx_thread_smp_protection.tx_thread_smp_protect_in_force = 1;
MOV w3, #1 // Build lock value
STR w3, [x2, #0] // Store lock value
STXR w4, w3, [x2, #0] // Attempt to get the protection
CMP w4, #0
BNE _start_waiting // Did it fail?
DMB ISH //
/* Got the lock. */
@@ -217,7 +230,7 @@ _already_in_list0:
/* Restore interrupts. */
MSR DAIF, x0 // Restore interrupts
ISB //
ISB //
#ifdef TX_ENABLE_WFE
WFE // Go into standby
#endif
@@ -236,10 +249,17 @@ _try_to_get_lock:
/* Pickup the CPU ID. */
MRS x1, MPIDR_EL1 // Pickup the core ID
#ifdef TX_ARMV8_2
#if TX_THREAD_SMP_CLUSTERS > 1
UBFX x7, x1, #16, #8 // Isolate cluster ID
#endif
UBFX x1, x1, #8, #8 // Isolate core ID
#else
#if TX_THREAD_SMP_CLUSTERS > 1
UBFX x7, x1, #8, #8 // Isolate cluster ID
#endif
UBFX x1, x1, #0, #8 // Isolate core ID
#endif
#if TX_THREAD_SMP_CLUSTERS > 1
ADDS x1, x1, x7, LSL #2 // Calculate CPU ID
#endif
@@ -257,7 +277,7 @@ _try_to_get_lock:
/* Are we at the front of the list? */
// if (this_core == _tx_thread_smp_protect_wait_list[_tx_thread_smp_protect_wait_list_head])
// {/
// {
LDR x3, =_tx_thread_smp_protect_wait_list_head // Get the address of the head
LDR w3, [x3] // Get the value of the head
@@ -271,7 +291,7 @@ _try_to_get_lock:
// if (_tx_thread_smp_protection.tx_thread_smp_protect_in_force == 0)
// {
LDR w3, [x2, #0] // Pickup the protection flag
LDAXR w3, [x2, #0] // Pickup the protection flag
CMP w3, #0
BNE _did_not_get_lock // No, protection not available
@@ -279,7 +299,9 @@ _try_to_get_lock:
// _tx_thread_smp_protection.tx_thread_smp_protect_in_force = 1;
MOV w3, #1 // Build lock value
STR w3, [x2, #0] // Store lock value
STXR w4, w3, [x2, #0] // Attempt to get the protection
CMP w4, #0
BNE _did_not_get_lock // Did it fail?
DMB ISH //
/* Got the lock. */
@@ -328,7 +350,7 @@ _already_in_list1:
/* Restore interrupts and try again. */
MSR DAIF, x0 // Restore interrupts
ISB //
ISB //
#ifdef TX_ENABLE_WFE
WFE // Go into standby
#endif
@@ -349,4 +371,3 @@ _got_lock_after_waiting:
_return:
RET

116
ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_smp_protection_wait_list_macros.h
View File

@@ -23,12 +23,12 @@
.macro _tx_thread_smp_protect_lock_got
/* Set the currently owned core. */
/* _tx_thread_smp_protection.tx_thread_smp_protect_core = this_core; */
// _tx_thread_smp_protection.tx_thread_smp_protect_core = this_core;
STR w1, [x2, #4] // Store this core
/* Increment the protection count. */
/* _tx_thread_smp_protection.tx_thread_smp_protect_count++; */
// _tx_thread_smp_protection.tx_thread_smp_protect_count++;
LDR w3, [x2, #8] // Pickup ownership count
ADD w3, w3, #1 // Increment ownership count
@@ -40,7 +40,7 @@
.macro _tx_thread_smp_protect_remove_from_front_of_list
/* Remove ourselves from the list. */
/* _tx_thread_smp_protect_wait_list[_tx_thread_smp_protect_wait_list_head++] = 0xFFFFFFFF; */
// _tx_thread_smp_protect_wait_list[_tx_thread_smp_protect_wait_list_head++] = 0xFFFFFFFF;
MOV w3, #0xFFFFFFFF // Build the invalid core value
LDR x4, =_tx_thread_smp_protect_wait_list_head // Get the address of the head
@@ -50,53 +50,55 @@
ADD w5, w5, #1 // Increment the head
/* Did we wrap? */
/* if (_tx_thread_smp_protect_wait_list_head == TX_THREAD_SMP_MAX_CORES + 1)
{ */
// if (_tx_thread_smp_protect_wait_list_head == TX_THREAD_SMP_MAX_CORES + 1)
// {
LDR x3, =_tx_thread_smp_protect_wait_list_size // Load address of core list size
LDR w3, [x3] // Load the max cores value
CMP w5, w3 // Compare the head to it
BNE _store_new_head\@ // Are we at the max?
/* _tx_thread_smp_protect_wait_list_head = 0; */
// _tx_thread_smp_protect_wait_list_head = 0;
EOR w5, w5, w5 // We're at the max. Set it to zero
/* } */
// }
_store_new_head\@:
STR w5, [x4] // Store the new head
/* We have the lock! */
/* return; */
DMB ISH // Ensure write to protection finishes
// return;
.endm
.macro _tx_thread_smp_protect_wait_list_lock_get
/* VOID _tx_thread_smp_protect_wait_list_lock_get()
{ */
// VOID _tx_thread_smp_protect_wait_list_lock_get()
// {
/* We do this until we have the lock. */
/* while (1)
{ */
// while (1)
// {
_tx_thread_smp_protect_wait_list_lock_get__try_to_get_lock\@:
/* Is the list lock available? */
/* _tx_thread_smp_protect_wait_list_lock_protect_in_force = load_exclusive(&_tx_thread_smp_protect_wait_list_lock_protect_in_force); */
// Is the list lock available? */
// _tx_thread_smp_protect_wait_list_lock_protect_in_force = load_exclusive(&_tx_thread_smp_protect_wait_list_lock_protect_in_force);
LDR x1, =_tx_thread_smp_protect_wait_list_lock_protect_in_force
LDAXR w2, [x1] // Pickup the protection flag
/* if (protect_in_force == 0)
{ */
// if (protect_in_force == 0)
// {
CMP w2, #0
BNE _tx_thread_smp_protect_wait_list_lock_get__try_to_get_lock\@ // No, protection not available
/* Try to get the list. */
/* int status = store_exclusive(&_tx_thread_smp_protect_wait_list_lock_protect_in_force, 1); */
// int status = store_exclusive(&_tx_thread_smp_protect_wait_list_lock_protect_in_force, 1);
MOV w2, #1 // Build lock value
STXR w3, w2, [x1] // Attempt to get the protection
@@ -107,17 +109,17 @@ _tx_thread_smp_protect_wait_list_lock_get__try_to_get_lock\@:
BNE _tx_thread_smp_protect_wait_list_lock_get__try_to_get_lock\@ // Did it fail? If so, try again.
/* We have the lock! */
/* return; */
// return;
.endm
.macro _tx_thread_smp_protect_wait_list_add
/* VOID _tx_thread_smp_protect_wait_list_add(UINT new_core)
{ */
// VOID _tx_thread_smp_protect_wait_list_add(UINT new_core)
// {
/* We're about to modify the list, so get the list lock. */
/* _tx_thread_smp_protect_wait_list_lock_get(); */
// _tx_thread_smp_protect_wait_list_lock_get();
STP x1, x2, [sp, #-16]! // Save registers we'll be using
@@ -126,7 +128,7 @@ _tx_thread_smp_protect_wait_list_lock_get__try_to_get_lock\@:
LDP x1, x2, [sp], #16
/* Add this core. */
/* _tx_thread_smp_protect_wait_list[_tx_thread_smp_protect_wait_list_tail++] = new_core; */
// _tx_thread_smp_protect_wait_list[_tx_thread_smp_protect_wait_list_tail++] = new_core;
LDR x3, =_tx_thread_smp_protect_wait_list_tail // Get the address of the tail
LDR w4, [x3] // Get the value of tail
@@ -135,64 +137,66 @@ _tx_thread_smp_protect_wait_list_lock_get__try_to_get_lock\@:
ADD w4, w4, #1 // Increment the tail
/* Did we wrap? */
/* if (_tx_thread_smp_protect_wait_list_tail == _tx_thread_smp_protect_wait_list_size)
{ */
// if (_tx_thread_smp_protect_wait_list_tail == _tx_thread_smp_protect_wait_list_size)
// {
LDR x5, =_tx_thread_smp_protect_wait_list_size // Load max cores address
LDR w5, [x5] // Load max cores value
CMP w4, w5 // Compare max cores to tail
BNE _tx_thread_smp_protect_wait_list_add__no_wrap\@ // Did we wrap?
/* _tx_thread_smp_protect_wait_list_tail = 0; */
// _tx_thread_smp_protect_wait_list_tail = 0;
MOV w4, #0
/* } */
// }
_tx_thread_smp_protect_wait_list_add__no_wrap\@:
STR w4, [x3] // Store the new tail value.
DMB ISH // Ensure that accesses to shared resource have completed
/* Release the list lock. */
/* _tx_thread_smp_protect_wait_list_lock_protect_in_force = 0; */
// _tx_thread_smp_protect_wait_list_lock_protect_in_force = 0;
MOV w3, #0 // Build lock value
LDR x4, =_tx_thread_smp_protect_wait_list_lock_protect_in_force
STR w3, [x4] // Store the new value
DMB ISH // Ensure write to protection finishes
.endm
.macro _tx_thread_smp_protect_wait_list_remove
/* VOID _tx_thread_smp_protect_wait_list_remove(UINT core)
{ */
// VOID _tx_thread_smp_protect_wait_list_remove(UINT core)
// {
/* Get the core index. */
/* UINT core_index;
for (core_index = 0;; core_index++) */
// UINT core_index;
// for (core_index = 0;; core_index++)
EOR w4, w4, w4 // Clear for 'core_index'
LDR x2, =_tx_thread_smp_protect_wait_list // Get the address of the list
/* { */
// {
_tx_thread_smp_protect_wait_list_remove__check_cur_core\@:
/* Is this the core? */
/* if (_tx_thread_smp_protect_wait_list[core_index] == core)
{
break; */
// if (_tx_thread_smp_protect_wait_list[core_index] == core)
// {
// break;
LDR w3, [x2, x4, LSL #2] // Get the value at the current index
CMP w3, w8 // Did we find the core?
BEQ _tx_thread_smp_protect_wait_list_remove__found_core\@
/* } */
// }
ADD w4, w4, #1 // Increment cur index
B _tx_thread_smp_protect_wait_list_remove__check_cur_core\@ // Restart the loop
/* } */
// }
_tx_thread_smp_protect_wait_list_remove__found_core\@:
@@ -200,15 +204,15 @@ _tx_thread_smp_protect_wait_list_remove__found_core\@:
core could be simultaneously adding (a core is simultaneously trying to get
the inter-core lock) or removing (a core is simultaneously being preempted,
like what is currently happening). */
/* _tx_thread_smp_protect_wait_list_lock_get(); */
// _tx_thread_smp_protect_wait_list_lock_get();
MOV x6, x1
_tx_thread_smp_protect_wait_list_lock_get
MOV x1, x6
/* We remove by shifting. */
/* while (core_index != _tx_thread_smp_protect_wait_list_tail)
{ */
// while (core_index != _tx_thread_smp_protect_wait_list_tail)
// {
_tx_thread_smp_protect_wait_list_remove__compare_index_to_tail\@:
@@ -217,76 +221,78 @@ _tx_thread_smp_protect_wait_list_remove__compare_index_to_tail\@:
CMP w4, w2 // Compare cur index and tail
BEQ _tx_thread_smp_protect_wait_list_remove__removed\@
/* UINT next_index = core_index + 1; */
// UINT next_index = core_index + 1;
MOV w2, w4 // Move current index to next index register
ADD w2, w2, #1 // Add 1
/* if (next_index == _tx_thread_smp_protect_wait_list_size)
{ */
// if (next_index == _tx_thread_smp_protect_wait_list_size)
// {
LDR x3, =_tx_thread_smp_protect_wait_list_size
LDR w3, [x3]
CMP w2, w3
BNE _tx_thread_smp_protect_wait_list_remove__next_index_no_wrap\@
/* next_index = 0; */
// next_index = 0;
MOV w2, #0
/* } */
// }
_tx_thread_smp_protect_wait_list_remove__next_index_no_wrap\@:
/* list_cores[core_index] = list_cores[next_index]; */
// list_cores[core_index] = list_cores[next_index];
LDR x5, =_tx_thread_smp_protect_wait_list // Get the address of the list
LDR w3, [x5, x2, LSL #2] // Get the value at the next index
STR w3, [x5, x4, LSL #2] // Store the value at the current index
/* core_index = next_index; */
// core_index = next_index;
MOV w4, w2
B _tx_thread_smp_protect_wait_list_remove__compare_index_to_tail\@
/* } */
// }
_tx_thread_smp_protect_wait_list_remove__removed\@:
/* Now update the tail. */
/* if (_tx_thread_smp_protect_wait_list_tail == 0)
{ */
// if (_tx_thread_smp_protect_wait_list_tail == 0)
// {
LDR x5, =_tx_thread_smp_protect_wait_list_tail // Load tail address
LDR w4, [x5] // Load tail value
CMP w4, #0
BNE _tx_thread_smp_protect_wait_list_remove__tail_not_zero\@
/* _tx_thread_smp_protect_wait_list_tail = _tx_thread_smp_protect_wait_list_size; */
// _tx_thread_smp_protect_wait_list_tail = _tx_thread_smp_protect_wait_list_size;
LDR x2, =_tx_thread_smp_protect_wait_list_size
LDR w4, [x2]
/* } */
// }
_tx_thread_smp_protect_wait_list_remove__tail_not_zero\@:
/* _tx_thread_smp_protect_wait_list_tail--; */
// _tx_thread_smp_protect_wait_list_tail--;
SUB w4, w4, #1
STR w4, [x5] // Store new tail value
DMB ISH // Ensure that accesses to shared resource have completed
/* Release the list lock. */
/* _tx_thread_smp_protect_wait_list_lock_protect_in_force = 0; */
// _tx_thread_smp_protect_wait_list_lock_protect_in_force = 0;
MOV w2, #0 // Build lock value
LDR x4, =_tx_thread_smp_protect_wait_list_lock_protect_in_force // Load lock address
STR w2, [x4] // Store the new value
DMB ISH // Ensure write to protection finishes
/* We're no longer waiting. Note that this should be zero since, again,
this function is only called when a thread preemption is occurring. */
/* _tx_thread_smp_protect_wait_counts[core]--; */
// _tx_thread_smp_protect_wait_counts[core]--;
LDR x4, =_tx_thread_smp_protect_wait_counts // Load wait list counts
LDR w2, [x4, x8, LSL #2] // Load waiting value
SUB w2, w2, #1 // Subtract 1

15
ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_smp_unprotect.S
View File

@@ -27,8 +27,8 @@
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_smp_unprotect Cortex-A35-SMP/GNU */
/* 6.1 */
/* _tx_thread_smp_unprotect Cortex-A35-SMP/GCC */
/* 6.1.9 */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
@@ -61,6 +61,9 @@
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 10-15-2021 Andres Mlinar Updated comments, */
/* added ARMv8.2-A support, */
/* resulting in version 6.1.9 */
/* */
/**************************************************************************/
.global _tx_thread_smp_unprotect
@@ -69,10 +72,17 @@ _tx_thread_smp_unprotect:
MSR DAIFSet, 0x3 // Lockout interrupts
MRS x1, MPIDR_EL1 // Pickup the core ID
#ifdef TX_ARMV8_2
#if TX_THREAD_SMP_CLUSTERS > 1
UBFX x2, x1, #16, #8 // Isolate cluster ID
#endif
UBFX x1, x1, #8, #8 // Isolate core ID
#else
#if TX_THREAD_SMP_CLUSTERS > 1
UBFX x2, x1, #8, #8 // Isolate cluster ID
#endif
UBFX x1, x1, #0, #8 // Isolate core ID
#endif
#if TX_THREAD_SMP_CLUSTERS > 1
ADDS x1, x1, x2, LSL #2 // Calculate CPU ID
#endif
@@ -114,4 +124,3 @@ _still_protected:
#endif
MSR DAIF, x0 // Restore interrupt posture
RET

9
ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_timeout.c
View File

@@ -12,8 +12,8 @@
/**************************************************************************/
/**************************************************************************/
/** */
/** ThreadX Component */
/** */
/** ThreadX Component */
/** */
/** Thread */
/** */
@@ -79,7 +79,7 @@ VOID _tx_thread_timeout(ULONG timeout_input)
TX_INTERRUPT_SAVE_AREA
TX_THREAD *thread_ptr;
TX_THREAD *thread_ptr;
VOID (*suspend_cleanup)(struct TX_THREAD_STRUCT *suspend_thread_ptr, ULONG suspension_sequence);
ULONG suspension_sequence;
@@ -126,7 +126,7 @@ ULONG suspension_sequence;
/* Increment the number of timeouts for this thread. */
thread_ptr -> tx_thread_performance_timeout_count++;
#endif
/* Pickup the cleanup routine address. */
suspend_cleanup = thread_ptr -> tx_thread_suspend_cleanup;
@@ -162,4 +162,3 @@ ULONG suspension_sequence;
#endif
}
}

2
ports_module/cortex_a7/ac5/inc/tx_port.h
View File

@@ -345,7 +345,7 @@ void tx_thread_vfp_disable(void);
#ifdef TX_THREAD_INIT
CHAR _tx_version_id[] =
"Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A7/AC5 Version 6.1.6 *";
"Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A7/AC5 Version 6.1.9 *";
#else
extern CHAR _tx_version_id[];
#endif

2
ports_module/cortex_a7/ac5/inc/txm_module_port.h
View File

@@ -407,7 +407,7 @@ UINT _txm_module_manager_inside_data_check(ULONG pointer);
#define TXM_MODULE_MANAGER_VERSION_ID \
CHAR _txm_module_manager_version_id[] = \
"Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-A7/MMU/AC5 Version 6.1 *";
"Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-A7/MMU/AC5 Version 6.1.9 *";
#endif

2
ports_module/cortex_m23/ac6/inc/tx_port.h
View File

@@ -573,7 +573,7 @@ unsigned int was_masked;
#ifdef TX_THREAD_INIT
CHAR _tx_version_id[] =
"Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M23/AC6 Version 6.1.6 *";
"Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M23/AC6 Version 6.1.9 *";
#else
#ifdef TX_MISRA_ENABLE
extern CHAR _tx_version_id[100];

2
ports_module/cortex_m23/ac6/inc/txm_module_port.h
View File

@@ -347,6 +347,6 @@ ALIGN_TYPE _txm_module_manager_port_dispatch(TXM_MODULE_INSTANCE *module_instanc
#define TXM_MODULE_MANAGER_VERSION_ID \
CHAR _txm_module_manager_version_id[] = \
"Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M23/AC6 Version 6.1.6 *";
"Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M23/AC6 Version 6.1.9 *";
#endif

2
ports_module/cortex_m23/gnu/inc/tx_port.h
View File

@@ -483,7 +483,7 @@ unsigned int interrupt_save;
#ifdef TX_THREAD_INIT
CHAR _tx_version_id[] =
"Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M23/GNU Version 6.1.6 *";
"Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M23/GNU Version 6.1.9 *";
#else
#ifdef TX_MISRA_ENABLE
extern CHAR _tx_version_id[100];

2
ports_module/cortex_m23/gnu/inc/txm_module_port.h
View File

@@ -347,6 +347,6 @@ ALIGN_TYPE _txm_module_manager_port_dispatch(TXM_MODULE_INSTANCE *module_instanc
#define TXM_MODULE_MANAGER_VERSION_ID \
CHAR _txm_module_manager_version_id[] = \
"Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M23/GNU Version 6.1.6 *";
"Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M23/GNU Version 6.1.9 *";
#endif

2
ports_module/cortex_m23/iar/inc/tx_port.h
View File

@@ -701,7 +701,7 @@ VOID _tx_thread_interrupt_restore(UIN
#ifdef TX_THREAD_INIT
CHAR _tx_version_id[] =
"Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Modules ARMv8-M Version 6.1.6 *";
"Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Modules ARMv8-M Version 6.1.9 *";
#else
#ifdef TX_MISRA_ENABLE
extern CHAR _tx_version_id[100];

2
ports_module/cortex_m23/iar/inc/txm_module_port.h
View File

@@ -350,6 +350,6 @@ ALIGN_TYPE _txm_module_manager_port_dispatch(TXM_MODULE_INSTANCE *module_instanc
#define TXM_MODULE_MANAGER_VERSION_ID \
CHAR _txm_module_manager_version_id[] = \
"Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M23/IAR Version 6.1.6 *";
"Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M23/IAR Version 6.1.9 *";
#endif

26
ports_module/cortex_m3/ac5/inc/tx_port.h
View File

@@ -26,7 +26,7 @@
/* PORT SPECIFIC C INFORMATION RELEASE */
/* */
/* tx_port.h Cortex-M3/AC5 */
/* 6.1.6 */
/* 6.1.9 */
/* */
/* AUTHOR */
/* */
@@ -47,10 +47,7 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */
/* macro definition, */
/* resulting in version 6.1.6 */
/* 10-15-2021 Scott Larson Initial Version 6.1.9 */
/* */
/**************************************************************************/
@@ -142,7 +139,7 @@ typedef unsigned short USHORT;
/* Define the port specific options for the _tx_build_options variable. This variable indicates
how the ThreadX library was built. */
#define TX_PORT_SPECIFIC_BUILD_OPTIONS 0
#define TX_PORT_SPECIFIC_BUILD_OPTIONS (0)
/* Define the in-line initialization constant so that modules with in-line
@@ -344,8 +341,6 @@ void _tx_vfp_access(void);
#endif
/* Define the ThreadX object creation extensions for the remaining objects. */
#define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr)
@@ -386,7 +381,7 @@ ULONG _tx_misra_ipsr_get(VOID);
zero after initialization for Cortex-M ports. */
#ifndef TX_THREAD_SYSTEM_RETURN_CHECK
#define TX_THREAD_SYSTEM_RETURN_CHECK(c) (c) = ((ULONG) _tx_thread_preempt_disable);
#define TX_THREAD_SYSTEM_RETURN_CHECK(c) (c) = ((ULONG) _tx_thread_preempt_disable);
#endif
@@ -452,11 +447,18 @@ unsigned int was_masked;
#endif
/* Define FPU extension for the Cortex-M3. Each is assumed to be called in the context of the executing
thread. These are no longer needed, but are preserved for backward compatibility only. */
void tx_thread_fpu_enable(void);
void tx_thread_fpu_disable(void);
/* Define the version ID of ThreadX. This may be utilized by the application. */
#ifdef TX_THREAD_INIT
CHAR _tx_version_id[] =
"Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M3/AC5 Version 6.1 *";
"Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M3/AC5 Version 6.1.9 *";
#else
#ifdef TX_MISRA_ENABLE
extern CHAR _tx_version_id[100];
@@ -467,7 +469,3 @@ extern CHAR _tx_version_id[];
#endif

82
ports_module/cortex_m3/ac5/inc/txm_module_port.h
View File

@@ -25,8 +25,8 @@
/* */
/* APPLICATION INTERFACE DEFINITION RELEASE */
/* */
/* txm_module_port.h Cortex-M3/MPU/AC5 */
/* 6.1.6 */
/* txm_module_port.h Cortex-M3/AC5 */
/* 6.1.9 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -40,10 +40,7 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* 04-02-2021 Scott Larson Modified comment(s) and */
/* added check for overflow, */
/* resulting in version 6.1.6 */
/* 10-15-2021 Scott Larson Initial Version 6.1.9 */
/* */
/**************************************************************************/
@@ -94,16 +91,26 @@ The following extensions must also be defined in tx_port.h:
VOID (*tx_timer_module_expiration_function)(ULONG id);
*/
/* Size of module heap. */
#define TXM_MODULE_HEAP_SIZE 512
/* Define the kernel stack size for a module thread. */
#ifndef TXM_MODULE_KERNEL_STACK_SIZE
#define TXM_MODULE_KERNEL_STACK_SIZE 768
#endif
/* For the following 3 access control settings, change TEX and C, B, S (bits 21 through 16 of MPU_RASR)
* to reflect your system memory attributes (cache, shareable, memory type). */
/* Code region access control: privileged read-only, outer & inner write-back, normal memory, shareable. */
#ifndef TXM_MODULE_MPU_CODE_ACCESS_CONTROL
#define TXM_MODULE_MPU_CODE_ACCESS_CONTROL 0x06070000
#endif
/* Data region access control: execute never, read/write, outer & inner write-back, normal memory, shareable. */
#ifndef TXM_MODULE_MPU_DATA_ACCESS_CONTROL
#define TXM_MODULE_MPU_DATA_ACCESS_CONTROL 0x13070000
#endif
/* Shared region access control: execute never, read-only, outer & inner write-back, normal memory, shareable. */
#ifndef TXM_MODULE_MPU_SHARED_ACCESS_CONTROL
#define TXM_MODULE_MPU_SHARED_ACCESS_CONTROL 0x12070000
#endif
/* Define constants specific to the tools the module can be built with for this particular modules port. */
#define TXM_MODULE_IAR_COMPILER 0x00000000
@@ -154,12 +161,47 @@ The following extensions must also be defined in tx_port.h:
/* Define other module port-specific constants. */
/* Define INLINE_DECLARE to inline for AC5 compiler. */
/* Define INLINE_DECLARE to inline for ARM compiler. */
#define INLINE_DECLARE inline
#ifdef TXM_MODULE_MANAGER_16_MPU
/* Define the number of MPU entries assigned to the code and data sections.
On Cortex-M3 parts, there are 8 total entries. ThreadX uses one for access
On some Cortex-M7 parts, there are 16 total entries. ThreadX uses one for access
to the kernel entry function, thus 15 remain for code and data protection. */
#define TXM_MODULE_MPU_TOTAL_ENTRIES 16
#define TXM_MODULE_MPU_CODE_ENTRIES 4
#define TXM_MODULE_MPU_DATA_ENTRIES 4
#define TXM_MODULE_MPU_SHARED_ENTRIES 3
#define TXM_MODULE_MPU_KERNEL_ENTRY_INDEX 0
#define TXM_MODULE_MPU_SHARED_INDEX 9
#define TXM_ENABLE_REGION 0x01
/* There are 2 registers to set up each MPU region: MPU_RBAR, MPU_RASR. */
typedef struct TXM_MODULE_MPU_INFO_STRUCT
{
ULONG txm_module_mpu_region_address;
ULONG txm_module_mpu_region_attribute_size;
} TXM_MODULE_MPU_INFO;
/* Shared memory region attributes. */
#define TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE 1
#define TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT 0x01000000
/* Define the port-extensions to the module manager instance structure. */
#define TXM_MODULE_MANAGER_PORT_EXTENSION \
TXM_MODULE_MPU_INFO txm_module_instance_mpu_registers[TXM_MODULE_MPU_TOTAL_ENTRIES]; \
ULONG txm_module_instance_shared_memory_count; \
ULONG txm_module_instance_shared_memory_address[TXM_MODULE_MPU_SHARED_ENTRIES]; \
ULONG txm_module_instance_shared_memory_length[TXM_MODULE_MPU_SHARED_ENTRIES];
#else /* TXM_MODULE_MANAGER_16_MPU is not defined */
/* Define the number of MPU entries assigned to the code and data sections.
On Cortex-M3, M4, and some M7 parts, there are 8 total entries. ThreadX uses one for access
to the kernel entry function, thus 7 remain for code and data protection. */
#define TXM_MODULE_MANAGER_CODE_MPU_ENTRIES 4
#define TXM_MODULE_MANAGER_DATA_MPU_ENTRIES 3
@@ -177,6 +219,7 @@ The following extensions must also be defined in tx_port.h:
ULONG txm_module_instance_shared_memory_address; \
ULONG txm_module_instance_shared_memory_length;
#endif /* TXM_MODULE_MANAGER_16_MPU */
/* Define the memory fault information structure that is populated when a memory fault occurs. */
@@ -299,6 +342,10 @@ typedef struct TXM_MODULE_MANAGER_MEMORY_FAULT_INFO_STRUCT
/* Define the macros to perform port-specific checks when passing pointers to the kernel. */
/* Define macro to make sure object is inside the module's data. */
#ifdef TXM_MODULE_MANAGER_16_MPU
#define TXM_MODULE_MANAGER_CHECK_INSIDE_DATA(module_instance, obj_ptr, obj_size) \
_txm_module_manager_inside_data_check(module_instance, obj_ptr, obj_size)
#else
#define TXM_MODULE_MANAGER_CHECK_INSIDE_DATA(module_instance, obj_ptr, obj_size) \
/* Check for overflow. */ \
(((obj_ptr) < ((obj_ptr) + (obj_size))) && \
@@ -308,7 +355,7 @@ typedef struct TXM_MODULE_MANAGER_MEMORY_FAULT_INFO_STRUCT
/* Check if it's inside shared memory. */ \
(((obj_ptr) >= (ALIGN_TYPE) module_instance -> txm_module_instance_shared_memory_address) && \
(((obj_ptr) + (obj_size)) <= (ALIGN_TYPE) (module_instance -> txm_module_instance_shared_memory_address + module_instance -> txm_module_instance_shared_memory_length)))))
#endif
/* Define some internal prototypes to this module port. */
@@ -324,10 +371,11 @@ UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD
VOID _txm_module_manager_mm_register_setup(TXM_MODULE_INSTANCE *module_instance); \
ULONG _txm_power_of_two_block_size(ULONG size); \
ULONG _txm_module_manager_calculate_srd_bits(ULONG block_size, ULONG length); \
ULONG _txm_module_manager_region_size_get(ULONG block_size);
ULONG _txm_module_manager_region_size_get(ULONG block_size); \
UINT _txm_module_manager_inside_data_check(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE obj_ptr, UINT obj_size);
#define TXM_MODULE_MANAGER_VERSION_ID \
CHAR _txm_module_manager_version_id[] = \
"Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M3/MPU/AC5 Version 6.1.8 *";
CHAR _txm_module_manager_version_id[] = \
"Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M3/AC5 Version 6.1.9 *";
#endif

6
ports_module/cortex_m3/ac5/module_lib/src/txm_module_initialize.S → ports_module/cortex_m3/ac5/module_lib/src/txm_module_initialize.s
View File

@@ -29,8 +29,8 @@
/* */
/* FUNCTION RELEASE */
/* */
/* _txm_module_initialize Cortex-M3/MPU/AC5 */
/* 6.1 */
/* _txm_module_initialize Cortex-M3/AC5 */
/* 6.1.9 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -59,7 +59,7 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* 10-15-2021 Scott Larson Initial Version 6.1.9 */
/* */
/**************************************************************************/
// VOID _txm_module_initialize(VOID)

15
ports_module/cortex_m3/ac5/module_lib/src/txm_module_thread_shell_entry.c
View File

@@ -44,7 +44,9 @@ TXM_MODULE_THREAD_ENTRY_INFO *_txm_module_entry_info;
ULONG (*_txm_module_kernel_call_dispatcher)(ULONG kernel_request, ULONG param_1, ULONG param_2, ULONG param3);
/* Define the ARM cstartup code. */
/* Define the startup code that clears the uninitialized global data and sets up the
preset global variables. */
extern VOID _txm_module_initialize(VOID);
__align(8) UCHAR txm_heap[TXM_MODULE_HEAP_SIZE];
@@ -53,15 +55,15 @@ __align(8) UCHAR txm_heap[TXM_MODULE_HEAP_SIZE];
/* */
/* FUNCTION RELEASE */
/* */
/* _txm_module_thread_shell_entry Cortex-M3/MPU/AC5 */
/* 6.1 */
/* _txm_module_thread_shell_entry Cortex-M3/AC5 */
/* 6.1.9 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
/* */
/* DESCRIPTION */
/* */
/* This function calls the specified entry function of the thread. It */
/* This function calls the specified entry function of the thread. It */
/* also provides a place for the thread's entry function to return. */
/* If the thread returns, this function places the thread in a */
/* "COMPLETED" state. */
@@ -90,7 +92,7 @@ __align(8) UCHAR txm_heap[TXM_MODULE_HEAP_SIZE];
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* 10-15-2021 Scott Larson Initial Version 6.1.9 */
/* */
/**************************************************************************/
VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_ENTRY_INFO *thread_info)
@@ -105,7 +107,7 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN
execution. If not, simply skip the C startup code. */
if (thread_info -> txm_module_thread_entry_info_start_thread)
{
/* Initialize the ARM C environment. */
/* Initialize the C environment. */
_txm_module_initialize();
/* Save the entry info pointer, for later use. */
@@ -170,4 +172,3 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN
TX_SAFETY_CRITICAL_EXCEPTION(__FILE__, __LINE__, 0);
#endif
}

6
ports_module/cortex_m4/ac5/module_manager/src/tx_thread_context_restore.S → ports_module/cortex_m3/ac5/module_manager/src/tx_thread_context_restore.s
View File

@@ -30,8 +30,8 @@
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_context_restore Cortex-Mx/AC5 */
/* 6.1.8 */
/* _tx_thread_context_restore Cortex-M3/AC5 */
/* 6.1.7 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -61,7 +61,7 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 08-02-2021 Scott Larson Initial Version 6.1.8 */
/* 06-02-2021 Scott Larson Initial Version 6.1.7 */
/* */
/**************************************************************************/
// VOID _tx_thread_context_restore(VOID)

6
ports_module/cortex_m7/ac5/module_manager/src/tx_thread_context_save.S → ports_module/cortex_m3/ac5/module_manager/src/tx_thread_context_save.s
View File

@@ -30,8 +30,8 @@
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_context_save Cortex-Mx/AC5 */
/* 6.1.8 */
/* _tx_thread_context_save Cortex-M3/AC5 */
/* 6.1.7 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -61,7 +61,7 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 08-02-2021 Scott Larson Initial Version 6.1.8 */
/* 06-02-2021 Scott Larson Initial Version 6.1.7 */
/* */
/**************************************************************************/
// VOID _tx_thread_context_save(VOID)

6
ports_module/cortex_m7/ac5/module_manager/src/tx_thread_interrupt_control.S → ports_module/cortex_m3/ac5/module_manager/src/tx_thread_interrupt_control.s
View File

@@ -25,8 +25,8 @@
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_interrupt_control Cortex-Mx/AC5 */
/* 6.1.8 */
/* _tx_thread_interrupt_control Cortex-M3/AC5 */
/* 6.1.7 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -56,7 +56,7 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 08-02-2021 Scott Larson Initial Version 6.1.8 */
/* 06-02-2021 Scott Larson Initial Version 6.1.7 */
/* */
/**************************************************************************/
// UINT _tx_thread_interrupt_control(UINT new_posture)

6
ports_module/cortex_m3/ac5/module_manager/src/tx_thread_interrupt_disable.S → ports_module/cortex_m3/ac5/module_manager/src/tx_thread_interrupt_disable.s
View File

@@ -25,8 +25,8 @@
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_interrupt_disable Cortex-Mx/AC5 */
/* 6.1.8 */
/* _tx_thread_interrupt_disable Cortex-M3/AC5 */
/* 6.1.7 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -56,7 +56,7 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 08-02-2021 Scott Larson Initial Version 6.1.8 */
/* 06-02-2021 Scott Larson Initial Version 6.1.7 */
/* */
/**************************************************************************/
// UINT _tx_thread_interrupt_disable(VOID)

6
ports_module/cortex_m7/ac5/module_manager/src/tx_thread_interrupt_restore.S → ports_module/cortex_m3/ac5/module_manager/src/tx_thread_interrupt_restore.s
View File

@@ -25,8 +25,8 @@
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_interrupt_restore Cortex-Mx/AC5 */
/* 6.1.8 */
/* _tx_thread_interrupt_restore Cortex-M3/AC5 */
/* 6.1.7 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -56,7 +56,7 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 08-02-2021 Scott Larson Initial Version 6.1.8 */
/* 06-02-2021 Scott Larson Initial Version 6.1.7 */
/* */
/**************************************************************************/
// VOID _tx_thread_interrupt_restore(UINT previous_posture)

16
ports_module/cortex_m7/ac5/module_manager/src/tx_thread_schedule.S → ports_module/cortex_m3/ac5/module_manager/src/tx_thread_schedule.s
View File

@@ -39,8 +39,8 @@
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_schedule Cortex-M7/MPU/AC5 */
/* 6.1.7 */
/* _tx_thread_schedule Cortex-M3/AC5 */
/* 6.1.9 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -73,15 +73,7 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* 11-09-2020 Scott Larson Modified comment(s), arrange */
/* code to fix link error when */
/* VFP is enabled, resulting */
/* in version 6.1.2 */
/* 06-02-2021 Scott Larson Fixed extended stack handling */
/* when calling kernel APIs, */
/* added support for 8 MPU, */
/* resulting in version 6.1.7 */
/* 10-15-2021 Scott Larson Initial Version 6.1.9 */
/* */
/**************************************************************************/
// VOID _tx_thread_schedule(VOID)
@@ -360,7 +352,7 @@ __tx_ts_restore
// Use alias registers to quickly load MPU
ADD r0, r0, #100 // Build address of MPU register start in thread control block
#ifndef TXM_MODULE_MANAGER_8_MPU
#ifdef TXM_MODULE_MANAGER_16_MPU
LDM r0!,{r2-r9} // Load MPU regions 0-3
STM r1,{r2-r9} // Store MPU regions 0-3
LDM r0!,{r2-r9} // Load MPU regions 4-7

6
ports_module/cortex_m3/ac5/module_manager/src/tx_thread_stack_build.S → ports_module/cortex_m3/ac5/module_manager/src/tx_thread_stack_build.s
View File

@@ -25,8 +25,8 @@
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_stack_build Cortex-Mx/AC5 */
/* 6.1.8 */
/* _tx_thread_stack_build Cortex-M3/AC5 */
/* 6.1.7 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -58,7 +58,7 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 08-02-2021 Scott Larson Initial Version 6.1.8 */
/* 06-02-2021 Scott Larson Initial Version 6.1.7 */
/* */
/**************************************************************************/
// VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID))

6
ports_module/cortex_m7/ac5/module_manager/src/tx_thread_system_return.S → ports_module/cortex_m3/ac5/module_manager/src/tx_thread_system_return.s
View File

@@ -25,8 +25,8 @@
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_system_return Cortex-Mx/AC5 */
/* 6.1.8 */
/* _tx_thread_system_return Cortex-M3/AC5 */
/* 6.1.7 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -58,7 +58,7 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 08-02-2021 Scott Larson Initial Version 6.1.8 */
/* 06-02-2021 Scott Larson Initial Version 6.1.7 */
/* */
/**************************************************************************/
// VOID _tx_thread_system_return(VOID)

6
ports_module/cortex_m7/ac5/module_manager/src/tx_timer_interrupt.S → ports_module/cortex_m3/ac5/module_manager/src/tx_timer_interrupt.s
View File

@@ -39,8 +39,8 @@
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_timer_interrupt Cortex-Mx/AC5 */
/* 6.1.8 */
/* _tx_timer_interrupt Cortex-M3/AC5 */
/* 6.1.7 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -73,7 +73,7 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 08-02-2021 Scott Larson Initial Version 6.1.8 */
/* 06-02-2021 Scott Larson Initial Version 6.1.7 */
/* */
/**************************************************************************/
// VOID _tx_timer_interrupt(VOID)

61
ports_module/cortex_m3/ac5/module_manager/src/txm_module_manager_alignment_adjust.c
View File

@@ -30,8 +30,8 @@
/* */
/* FUNCTION RELEASE */
/* */
/* _txm_power_of_two_block_size Cortex-M3/MPU */
/* 6.1 */
/* _txm_power_of_two_block_size Cortex-M3 */
/* 6.1.9 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -61,7 +61,7 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* 10-15-2021 Scott Larson Initial Version 6.1.9 */
/* */
/**************************************************************************/
ULONG _txm_power_of_two_block_size(ULONG size)
@@ -93,8 +93,8 @@ ULONG _txm_power_of_two_block_size(ULONG size)
/* */
/* FUNCTION RELEASE */
/* */
/* _txm_module_manager_alignment_adjust Cortex-M3/MPU */
/* 6.1 */
/* _txm_module_manager_alignment_adjust Cortex-M3 */
/* 6.1.9 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -128,7 +128,7 @@ ULONG _txm_power_of_two_block_size(ULONG size)
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* 10-15-2021 Scott Larson Initial Version 6.1.9 */
/* */
/**************************************************************************/
VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble,
@@ -137,6 +137,53 @@ VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble,
ULONG *data_size,
ULONG *data_alignment)
{
#ifdef TXM_MODULE_MANAGER_16_MPU
ULONG local_code_size;
ULONG local_code_alignment;
ULONG local_data_size;
ULONG local_data_alignment;
ULONG code_size_accum;
ULONG data_size_accum;
/* Copy the input parameters into local variables for ease of use. */
local_code_size = *code_size;
local_code_alignment = *code_alignment;
local_data_size = *data_size;
local_data_alignment = *data_alignment;
/* Determine code block sizes. Minimize the alignment requirement.
There are 4 MPU code entries available. The following is how the code size
will be distributed:
1. 1/4 of the largest power of two that is greater than or equal to code size.
2. 1/4 of the largest power of two that is greater than or equal to code size.
3. Largest power of 2 that fits in the remaining space.
4. Smallest power of 2 that exceeds the remaining space, minimum 32. */
local_code_alignment = _txm_power_of_two_block_size(local_code_size) >> 2;
code_size_accum = local_code_alignment + local_code_alignment;
code_size_accum = code_size_accum + (_txm_power_of_two_block_size(local_code_size - code_size_accum) >> 1);
code_size_accum = code_size_accum + _txm_power_of_two_block_size(local_code_size - code_size_accum);
local_code_size = code_size_accum;
/* Determine data block sizes. Minimize the alignment requirement.
There are 4 MPU data entries available. The following is how the data size
will be distributed:
1. 1/4 of the largest power of two that is greater than or equal to data size.
2. 1/4 of the largest power of two that is greater than or equal to data size.
3. Largest power of 2 that fits in the remaining space.
4. Smallest power of 2 that exceeds the remaining space, minimum 32. */
local_data_alignment = _txm_power_of_two_block_size(local_data_size) >> 2;
data_size_accum = local_data_alignment + local_data_alignment;
data_size_accum = data_size_accum + (_txm_power_of_two_block_size(local_data_size - data_size_accum) >> 1);
data_size_accum = data_size_accum + _txm_power_of_two_block_size(local_data_size - data_size_accum);
local_data_size = data_size_accum;
/* Return all the information to the caller. */
*code_size = local_code_size;
*code_alignment = local_code_alignment;
*data_size = local_data_size;
*data_alignment = local_data_alignment;
#else
ULONG local_code_size;
ULONG local_code_alignment;
@@ -396,4 +443,6 @@ ULONG data_size_accum;
*code_alignment = local_code_alignment;
*data_size = local_data_size;
*data_alignment = local_data_alignment;
#endif
}

119
ports_module/cortex_m3/ac5/module_manager/src/txm_module_manager_external_memory_enable.c
View File

@@ -33,8 +33,8 @@
/* */
/* FUNCTION RELEASE */
/* */
/* _txm_module_manager_external_memory_enable Cortex-M3/MPU */
/* 6.1 */
/* _txm_module_manager_external_memory_enable Cortex-M3 */
/* 6.1.9 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -70,7 +70,7 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* 10-15-2021 Scott Larson Initial Version 6.1.9 */
/* */
/**************************************************************************/
UINT _txm_module_manager_external_memory_enable(TXM_MODULE_INSTANCE *module_instance,
@@ -78,6 +78,117 @@ UINT _txm_module_manager_external_memory_enable(TXM_MODULE_INSTANCE *module_ins
ULONG length,
UINT attributes)
{
#ifdef TXM_MODULE_MANAGER_16_MPU
ULONG block_size;
ULONG region_size;
ULONG srd_bits;
ULONG size_register;
ULONG address;
ULONG shared_index;
ULONG attributes_check = 0;
/* Determine if the module manager has not been initialized yet. */
if (_txm_module_manager_ready != TX_TRUE)
{
/* Module manager has not been initialized. */
return(TX_NOT_AVAILABLE);
}
/* Determine if the module is valid. */
if (module_instance == TX_NULL)
{
/* Invalid module pointer. */
return(TX_PTR_ERROR);
}
/* Get module manager protection mutex. */
_tx_mutex_get(&_txm_module_manager_mutex, TX_WAIT_FOREVER);
/* Determine if the module instance is valid. */
if (module_instance -> txm_module_instance_id != TXM_MODULE_ID)
{
/* Release the protection mutex. */
_tx_mutex_put(&_txm_module_manager_mutex);
/* Invalid module pointer. */
return(TX_PTR_ERROR);
}
/* Determine if the module instance is in the loaded state. */
if (module_instance -> txm_module_instance_state != TXM_MODULE_LOADED)
{
/* Release the protection mutex. */
_tx_mutex_put(&_txm_module_manager_mutex);
/* Return error if the module is not ready. */
return(TX_START_ERROR);
}
/* Determine if there are shared memory entries available. */
if(module_instance -> txm_module_instance_shared_memory_count >= TXM_MODULE_MPU_SHARED_ENTRIES)
{
/* Release the protection mutex. */
_tx_mutex_put(&_txm_module_manager_mutex);
/* No more entries available. */
return(TX_NO_MEMORY);
}
/* Start address and length must adhere to Cortex-M7 MPU.
The address must align with the block size. */
block_size = _txm_power_of_two_block_size(length);
address = (ULONG) start_address;
if(address != (address & ~(block_size - 1)))
{
/* Release the protection mutex. */
_tx_mutex_put(&_txm_module_manager_mutex);
/* Return alignment error. */
return(TXM_MODULE_ALIGNMENT_ERROR);
}
/* At this point, we have a valid address and block size.
Set up MPU registers. */
/* Pick up index into shared memory entries. */
shared_index = TXM_MODULE_MPU_SHARED_INDEX + module_instance -> txm_module_instance_shared_memory_count;
/* Save address register with address, MPU region, set Valid bit. */
module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_address = address | shared_index | 0x10;
/* Calculate the region size. */
region_size = (_txm_module_manager_region_size_get(block_size) << 1);
/* Calculate the subregion bits. */
srd_bits = _txm_module_manager_calculate_srd_bits(block_size, length);
/* Generate SRD, size, and enable attributes. */
size_register = srd_bits | region_size | TXM_ENABLE_REGION | TXM_MODULE_MPU_SHARED_ACCESS_CONTROL;
/* Check for optional write attribute. */
if(attributes & TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE)
{
attributes_check = TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT;
}
/* Save attribute-size register. */
module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_attribute_size = attributes_check | size_register;
/* Keep track of shared memory address and length in module instance. */
module_instance -> txm_module_instance_shared_memory_address[module_instance -> txm_module_instance_shared_memory_count] = address;
module_instance -> txm_module_instance_shared_memory_length[module_instance -> txm_module_instance_shared_memory_count] = length;
/* Increment counter. */
module_instance -> txm_module_instance_shared_memory_count++;
/* Release the protection mutex. */
_tx_mutex_put(&_txm_module_manager_mutex);
/* Return success. */
return(TX_SUCCESS);
#else
ULONG block_size;
ULONG region_size;
@@ -179,4 +290,6 @@ TXM_MODULE_PREAMBLE *module_preamble;
/* Return success. */
return(TX_SUCCESS);
#endif
}

6
ports_module/cortex_m3/ac5/module_manager/src/txm_module_manager_memory_fault_handler.c
View File

@@ -45,8 +45,8 @@ TXM_MODULE_MANAGER_FAULT_INFO
/* */
/* FUNCTION RELEASE */
/* */
/* _txm_module_manager_memory_fault_handler Cortex-M3/MPU/AC6 */
/* 6.1 */
/* _txm_module_manager_memory_fault_handler Cortex-M3 */
/* 6.1.9 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -76,7 +76,7 @@ TXM_MODULE_MANAGER_FAULT_INFO
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* 10-15-2021 Scott Larson Initial Version 6.1.9 */
/* */
/**************************************************************************/
VOID _txm_module_manager_memory_fault_handler(VOID)

6
ports_module/cortex_m3/ac5/module_manager/src/txm_module_manager_memory_fault_notify.c
View File

@@ -38,8 +38,8 @@ extern VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTA
/* */
/* FUNCTION RELEASE */
/* */
/* _txm_module_manager_memory_fault_notify Cortex-M3/MPU/AC5 */
/* 6.1 */
/* _txm_module_manager_memory_fault_notify Cortex-M3 */
/* 6.1.9 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -71,7 +71,7 @@ extern VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTA
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* 10-15-2021 Scott Larson Initial Version 6.1.9 */
/* */
/**************************************************************************/
UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *))

309
ports_module/cortex_m3/ac5/module_manager/src/txm_module_manager_mm_register_setup.c
View File

@@ -30,8 +30,8 @@
/* */
/* FUNCTION RELEASE */
/* */
/* _txm_module_manager_region_size_get Cortex-M3/MPU */
/* 6.1 */
/* _txm_module_manager_region_size_get Cortex-M3 */
/* 6.1.9 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -61,7 +61,7 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* 10-15-2021 Scott Larson Initial Version 6.1.9 */
/* */
/**************************************************************************/
ULONG _txm_module_manager_region_size_get(ULONG block_size)
@@ -152,8 +152,8 @@ ULONG return_value;
/* */
/* FUNCTION RELEASE */
/* */
/* _txm_module_manager_calculate_srd_bits Cortex-M3/MPU */
/* 6.1 */
/* _txm_module_manager_calculate_srd_bits Cortex-M3 */
/* 6.1.9 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -184,7 +184,7 @@ ULONG return_value;
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* 10-15-2021 Scott Larson Initial Version 6.1.9 */
/* */
/**************************************************************************/
ULONG _txm_module_manager_calculate_srd_bits(ULONG block_size, ULONG length)
@@ -230,16 +230,48 @@ UINT srd_bit_index;
/* */
/* FUNCTION RELEASE */
/* */
/* _txm_module_manager_mm_register_setup Cortex-M3/MPU */
/* 6.1 */
/* _txm_module_manager_mm_register_setup Cortex-M3 */
/* 6.1.9 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
/* */
/* DESCRIPTION */
/* */
/* This function sets up the Cortex-M3 MPU register definitions based */
/* on the module's memory characteristics. */
/* This function sets up the MPU register definitions based on the */
/* module's memory characteristics. */
/* */
/* Default MPU layout: */
/* Entry Description */
/* 0 Kernel mode entry */
/* 1 Module code region */
/* 2 Module code region */
/* 3 Module code region */
/* 4 Module code region */
/* 5 Module data region */
/* 6 Module data region */
/* 7 Module data region */
/* */
/* If TXM_MODULE_MANAGER_16_MPU is defined, there are 16 MPU slots. */
/* MPU layout for the Cortex-M7: */
/* Entry Description */
/* 0 Kernel mode entry */
/* 1 Module code region */
/* 2 Module code region */
/* 3 Module code region */
/* 4 Module code region */
/* 5 Module data region */
/* 6 Module data region */
/* 7 Module data region */
/* 8 Module data region */
/* 9 Module shared memory region */
/* 10 Module shared memory region */
/* 11 Module shared memory region */
/* 12 Unused region */
/* 13 Unused region */
/* 14 Unused region */
/* 15 Unused region */
/* */
/* */
/* INPUT */
/* */
@@ -261,11 +293,181 @@ UINT srd_bit_index;
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* 10-15-2021 Scott Larson Initial Version 6.1.9 */
/* */
/**************************************************************************/
VOID _txm_module_manager_mm_register_setup(TXM_MODULE_INSTANCE *module_instance)
{
#ifdef TXM_MODULE_MANAGER_16_MPU
ULONG code_address;
ULONG code_size;
ULONG data_address;
ULONG data_size;
ULONG start_stop_stack_size;
ULONG callback_stack_size;
ULONG block_size;
ULONG region_size;
ULONG srd_bits = 0;
UINT mpu_table_index;
UINT i;
/* Setup the first MPU region for kernel mode entry. */
/* Set address register to user mode entry function address, which is guaranteed to be at least 32-byte aligned.
Mask address to proper range, region 0, set Valid bit. */
module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MPU_KERNEL_ENTRY_INDEX].txm_module_mpu_region_address = ((ULONG) _txm_module_manager_user_mode_entry & 0xFFFFFFE0) | 0x10;
/* Set the attributes, size (32 bytes) and enable bit. */
module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MPU_KERNEL_ENTRY_INDEX].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_CODE_ACCESS_CONTROL | (_txm_module_manager_region_size_get(32) << 1) | TXM_ENABLE_REGION;
/* End of kernel mode entry setup. */
/* Setup code protection. */
/* Initialize the MPU table index. */
mpu_table_index = 1;
/* Pickup code starting address and actual size. */
code_address = (ULONG) module_instance -> txm_module_instance_code_start;
code_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_code_size;
/* Determine code block sizes. Minimize the alignment requirement.
There are 4 MPU code entries available. The following is how the code size
will be distributed:
1. 1/4 of the largest power of two that is greater than or equal to code size.
2. 1/4 of the largest power of two that is greater than or equal to code size.
3. Largest power of 2 that fits in the remaining space.
4. Smallest power of 2 that exceeds the remaining space, minimum 32. */
/* Now loop through to setup MPU protection for the code area. */
for (i = 0; i < TXM_MODULE_MPU_CODE_ENTRIES; i++)
{
/* First two MPU blocks are 1/4 of the largest power of two
that is greater than or equal to code size. */
if (i < 2)
{
block_size = _txm_power_of_two_block_size(code_size) >> 2;
}
/* Third MPU block is the largest power of 2 that fits in the remaining space. */
else if (i == 2)
{
/* Subtract (block_size*2) from code_size to calculate remaining space. */
code_size = code_size - (block_size << 1);
block_size = _txm_power_of_two_block_size(code_size) >> 1;
}
/* Last MPU block is the smallest power of 2 that exceeds the remaining space, minimum 32. */
else
{
/* Calculate remaining space. */
code_size = code_size - block_size;
block_size = _txm_power_of_two_block_size(code_size);
srd_bits = _txm_module_manager_calculate_srd_bits(block_size, code_size);
}
/* Calculate the region size information. */
region_size = (_txm_module_manager_region_size_get(block_size) << 1);
/* Build the base address register with address, MPU region, set Valid bit. */
module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = (code_address & ~(block_size - 1)) | mpu_table_index | 0x10;
/* Build the attribute-size register with permissions, SRD, size, enable. */
module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_CODE_ACCESS_CONTROL | srd_bits | region_size | TXM_ENABLE_REGION;
/* Adjust the code address. */
code_address = code_address + block_size;
/* Increment MPU table index. */
mpu_table_index++;
}
/* End of code protection. */
/* Setup data protection. */
/* Reset SRD bitfield. */
srd_bits = 0;
/* Pickup data starting address and actual size. */
data_address = (ULONG) module_instance -> txm_module_instance_data_start;
/* Adjust the size of the module elements to be aligned to the default alignment. We do this
so that when we partition the allocated memory, we can simply place these regions right beside
each other without having to align their pointers. Note this only works when they all have
the same alignment. */
data_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_data_size;
start_stop_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_start_stop_stack_size;
callback_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_callback_stack_size;
data_size = ((data_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT;
start_stop_stack_size = ((start_stop_stack_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT;
callback_stack_size = ((callback_stack_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT;
/* Update the data size to include thread stacks. */
data_size = data_size + start_stop_stack_size + callback_stack_size;
/* Determine data block sizes. Minimize the alignment requirement.
There are 4 MPU data entries available. The following is how the data size
will be distributed:
1. 1/4 of the largest power of two that is greater than or equal to data size.
2. 1/4 of the largest power of two that is greater than or equal to data size.
3. Largest power of 2 that fits in the remaining space.
4. Smallest power of 2 that exceeds the remaining space, minimum 32. */
/* Now loop through to setup MPU protection for the data area. */
for (i = 0; i < TXM_MODULE_MPU_DATA_ENTRIES; i++)
{
/* First two MPU blocks are 1/4 of the largest power of two
that is greater than or equal to data size. */
if (i < 2)
{
block_size = _txm_power_of_two_block_size(data_size) >> 2;
}
/* Third MPU block is the largest power of 2 that fits in the remaining space. */
else if (i == 2)
{
/* Subtract (block_size*2) from data_size to calculate remaining space. */
data_size = data_size - (block_size << 1);
block_size = _txm_power_of_two_block_size(data_size) >> 1;
}
/* Last MPU block is the smallest power of 2 that exceeds the remaining space, minimum 32. */
else
{
/* Calculate remaining space. */
data_size = data_size - block_size;
block_size = _txm_power_of_two_block_size(data_size);
srd_bits = _txm_module_manager_calculate_srd_bits(block_size, data_size);
}
/* Calculate the region size information. */
region_size = (_txm_module_manager_region_size_get(block_size) << 1);
/* Build the base address register with address, MPU region, set Valid bit. */
module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = (data_address & ~(block_size - 1)) | mpu_table_index | 0x10;
/* Build the attribute-size register with permissions, SRD, size, enable. */
module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_DATA_ACCESS_CONTROL | srd_bits | region_size | TXM_ENABLE_REGION;
/* Adjust the data address. */
data_address = data_address + block_size;
/* Increment MPU table index. */
mpu_table_index++;
}
/* Setup MPU for the remaining regions. */
while (mpu_table_index < TXM_MODULE_MPU_TOTAL_ENTRIES)
{
/* Build the base address register with address, MPU region, set Valid bit. */
module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = mpu_table_index | 0x10;
/* Increment MPU table index. */
mpu_table_index++;
}
#else
ULONG code_address;
ULONG code_size;
@@ -382,7 +584,7 @@ UINT i;
for (i = 0; i < TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1; i++)
{
/* Build the base address register. */
base_address_register = code_address & ~(block_size - 1) | mpu_register | 0x10;
base_address_register = (code_address & ~(block_size - 1)) | mpu_register | 0x10;
/* Check if SRD bits need to be set. */
if (code_size < block_size)
@@ -509,4 +711,87 @@ UINT i;
/* Increment the MPU register index. */
mpu_register++;
}
#endif
}
#ifdef TXM_MODULE_MANAGER_16_MPU
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _txm_module_manager_inside_data_check Cortex-M3 */
/* 6.1.9 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
/* */
/* DESCRIPTION */
/* */
/* This function checks if the specified object is inside shared */
/* memory. */
/* */
/* INPUT */
/* */
/* module_instance Pointer to module instance */
/* obj_ptr Pointer to the object */
/* obj_size Size of the object */
/* */
/* OUTPUT */
/* */
/* Whether the object is inside the shared memory region. */
/* */
/* CALLS */
/* */
/* None */
/* */
/* CALLED BY */
/* */
/* Module dispatch check functions */
/* */
/* RELEASE HISTORY */
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 10-15-2021 Scott Larson Initial Version 6.1.9 */
/* */
/**************************************************************************/
UINT _txm_module_manager_inside_data_check(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE obj_ptr, UINT obj_size)
{
UINT shared_memory_index;
UINT num_shared_memory_mpu_entries;
ALIGN_TYPE shared_memory_address_start;
ALIGN_TYPE shared_memory_address_end;
/* Check for overflow. */
if ((obj_ptr) > ((obj_ptr) + (obj_size)))
{
return(TX_FALSE);
}
/* Check if the object is inside the module data. */
if ((obj_ptr >= (ALIGN_TYPE) module_instance -> txm_module_instance_data_start) &&
((obj_ptr + obj_size) <= ((ALIGN_TYPE) module_instance -> txm_module_instance_data_end + 1)))
{
return(TX_TRUE);
}
/* Check if the object is inside the shared memory. */
num_shared_memory_mpu_entries = module_instance -> txm_module_instance_shared_memory_count;
for (shared_memory_index = 0; shared_memory_index < num_shared_memory_mpu_entries; shared_memory_index++)
{
shared_memory_address_start = (ALIGN_TYPE) module_instance -> txm_module_instance_shared_memory_address[shared_memory_index];
shared_memory_address_end = shared_memory_address_start + module_instance -> txm_module_instance_shared_memory_length[shared_memory_index];
if ((obj_ptr >= (ALIGN_TYPE) shared_memory_address_start) &&
((obj_ptr + obj_size) <= (ALIGN_TYPE) shared_memory_address_end))
{
return(TX_TRUE);
}
}
return(TX_FALSE);
}
#endif

8
ports_module/cortex_m3/ac5/module_manager/src/txm_module_manager_thread_stack_build.S → ports_module/cortex_m3/ac5/module_manager/src/txm_module_manager_thread_stack_build.s
View File

@@ -26,8 +26,8 @@
/* */
/* FUNCTION RELEASE */
/* */
/* _txm_module_manager_thread_stack_build Cortex-M3/MPU/AC5 */
/* 6.1 */
/* _txm_module_manager_thread_stack_build Cortex-M3/AC5 */
/* 6.1.9 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -59,7 +59,7 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* 10-15-2021 Scott Larson Initial Version 6.1.9 */
/* */
/**************************************************************************/
// VOID _txm_module_manager_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(TX_THREAD *, TXM_MODULE_INSTANCE *))
@@ -71,7 +71,7 @@ _txm_module_manager_thread_stack_build
on the Cortex-M should look like the following after it is built:
Stack Top:
LR Interrupted LR (LR at time of PENDSV)
lr Interrupted lr (lr at time of PENDSV)
r4 Initial value for r4
r5 Initial value for r5
r6 Initial value for r6

78
ports_module/cortex_m3/ac5/module_manager/src/txm_module_manager_user_mode_entry.S → ports_module/cortex_m3/ac5/module_manager/src/txm_module_manager_user_mode_entry.s
View File

@@ -10,57 +10,57 @@
/**************************************************************************/
/**************************************************************************/
/**************************************************************************/
/** */
/** ThreadX Component */
/** */
/** Module Manager */
/** */
/**************************************************************************/
/**************************************************************************/
/**************************************************************************/
/**************************************************************************/
/** */
/** ThreadX Component */
/** */
/** Module Manager */
/** */
/**************************************************************************/
/**************************************************************************/
IMPORT _txm_module_manager_kernel_dispatch
IMPORT _tx_thread_current_ptr
AREA ||.text||, CODE, READONLY, ALIGN=5
THUMB
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _txm_module_manager_user_mode_entry Cortex-M3/MPU/AC5 */
/* 6.1 */
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _txm_module_manager_user_mode_entry Cortex-M3/AC5 */
/* 6.1.9 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
/* */
/* DESCRIPTION */
/* */
/* This function allows modules to enter kernel mode. */
/* */
/* INPUT */
/* */
/* None */
/* */
/* OUTPUT */
/* */
/* None */
/* */
/* CALLS */
/* */
/* SVC 1 Enter kernel mode */
/* SVC 2 Exit kernel mode */
/* */
/* CALLED BY */
/* */
/* Modules in user mode */
/* */
/* RELEASE HISTORY */
/* */
/* DESCRIPTION */
/* */
/* This function allows modules to enter kernel mode. */
/* */
/* INPUT */
/* */
/* None */
/* */
/* OUTPUT */
/* */
/* None */
/* */
/* CALLS */
/* */
/* SVC 1 Enter kernel mode */
/* SVC 2 Exit kernel mode */
/* */
/* CALLED BY */
/* */
/* Modules in user mode */
/* */
/* RELEASE HISTORY */
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* 10-15-2021 Scott Larson Initial Version 6.1.9 */
/* */
/**************************************************************************/
// VOID _txm_module_manager_user_mode_entry(VOID)

150
ports_module/cortex_m3/ac6/inc/tx_port.h
View File

@@ -26,7 +26,7 @@
/* PORT SPECIFIC C INFORMATION RELEASE */
/* */
/* tx_port.h Cortex-M3/AC6 */
/* 6.1 */
/* 6.1.9 */
/* */
/* AUTHOR */
/* */
@@ -47,10 +47,7 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */
/* macro definition, */
/* resulting in version 6.1.6 */
/* 10-15-2021 Scott Larson Initial Version 6.1.9 */
/* */
/**************************************************************************/
@@ -142,7 +139,7 @@ typedef unsigned short USHORT;
/* Define the port specific options for the _tx_build_options variable. This variable indicates
how the ThreadX library was built. */
#define TX_PORT_SPECIFIC_BUILD_OPTIONS 0
#define TX_PORT_SPECIFIC_BUILD_OPTIONS (0)
/* Define the in-line initialization constant so that modules with in-line
@@ -218,9 +215,140 @@ typedef unsigned short USHORT;
#define TX_THREAD_CREATE_EXTENSION(thread_ptr)
#define TX_THREAD_DELETE_EXTENSION(thread_ptr)
#ifdef TX_ENABLE_FPU_SUPPORT
#ifdef TX_MISRA_ENABLE
ULONG _tx_misra_control_get(void);
void _tx_misra_control_set(ULONG value);
ULONG _tx_misra_fpccr_get(void);
void _tx_misra_vfp_touch(void);
#else
__attribute__( ( always_inline ) ) static inline ULONG __get_control(void)
{
ULONG control_value;
__asm__ volatile (" MRS %0,CONTROL ": "=r" (control_value) );
return(control_value);
}
__attribute__( ( always_inline ) ) static inline void __set_control(ULONG control_value)
{
__asm__ volatile (" MSR CONTROL,%0": : "r" (control_value): "memory" );
}
#endif
/* A completed thread falls into _thread_shell_entry and we can simply deactivate the FPU via CONTROL.FPCA
in order to ensure no lazy stacking will occur. */
#ifndef TX_MISRA_ENABLE
#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) { \
ULONG _tx_vfp_state; \
_tx_vfp_state = __get_control(); \
_tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \
__set_control(_tx_vfp_state); \
}
#else
#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) { \
ULONG _tx_vfp_state; \
_tx_vfp_state = _tx_misra_control_get(); \
_tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \
_tx_misra_control_set(_tx_vfp_state); \
}
#endif
/* A thread can be terminated by another thread, so we first check if it's self-terminating and not in an ISR.
If so, deactivate the FPU via CONTROL.FPCA. Otherwise we are in an interrupt or another thread is terminating
this one, so if the FPCCR.LSPACT bit is set, we need to save the CONTROL.FPCA state, touch the FPU to flush
the lazy FPU save, then restore the CONTROL.FPCA state. */
#ifndef TX_MISRA_ENABLE
#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) { \
ULONG _tx_system_state; \
_tx_system_state = TX_THREAD_GET_SYSTEM_STATE(); \
if ((_tx_system_state == ((ULONG) 0)) && ((thread_ptr) == _tx_thread_current_ptr)) \
{ \
ULONG _tx_vfp_state; \
_tx_vfp_state = __get_control(); \
_tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \
__set_control(_tx_vfp_state); \
} \
else \
{ \
ULONG _tx_fpccr; \
_tx_fpccr = *((ULONG *) 0xE000EF34); \
_tx_fpccr = _tx_fpccr & ((ULONG) 0x01); \
if (_tx_fpccr == ((ULONG) 0x01)) \
{ \
ULONG _tx_vfp_state; \
_tx_vfp_state = __get_control(); \
_tx_vfp_state = _tx_vfp_state & ((ULONG) 0x4); \
__asm__ volatile ("vmov.f32 s0, s0"); \
if (_tx_vfp_state == ((ULONG) 0)) \
{ \
_tx_vfp_state = __get_control(); \
_tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \
__set_control(_tx_vfp_state); \
} \
} \
} \
}
#else
#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) { \
ULONG _tx_system_state; \
_tx_system_state = TX_THREAD_GET_SYSTEM_STATE(); \
if ((_tx_system_state == ((ULONG) 0)) && ((thread_ptr) == _tx_thread_current_ptr)) \
{ \
ULONG _tx_vfp_state; \
_tx_vfp_state = _tx_misra_control_get(); \
_tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \
_tx_misra_control_set(_tx_vfp_state); \
} \
else \
{ \
ULONG _tx_fpccr; \
_tx_fpccr = _tx_misra_fpccr_get(); \
_tx_fpccr = _tx_fpccr & ((ULONG) 0x01); \
if (_tx_fpccr == ((ULONG) 0x01)) \
{ \
ULONG _tx_vfp_state; \
_tx_vfp_state = _tx_misra_control_get(); \
_tx_vfp_state = _tx_vfp_state & ((ULONG) 0x4); \
_tx_misra_vfp_touch(); \
if (_tx_vfp_state == ((ULONG) 0)) \
{ \
_tx_vfp_state = _tx_misra_control_get(); \
_tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \
_tx_misra_control_set(_tx_vfp_state); \
} \
} \
} \
}
#endif
#else
#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr)
#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr)
#endif
/* Define the ThreadX object creation extensions for the remaining objects. */
@@ -274,6 +402,7 @@ ULONG _tx_misra_ipsr_get(VOID);
#define TX_THREAD_SYSTEM_RETURN_CHECK(c) (c) = ((ULONG) _tx_thread_preempt_disable);
#endif
/* Define the macro to ensure _tx_thread_preempt_disable is set early in initialization in order to
prevent early scheduling on Cortex-M parts. */
@@ -368,11 +497,18 @@ unsigned int interrupt_save;
#endif
/* Define FPU extension for the Cortex-M7. Each is assumed to be called in the context of the executing
thread. These are no longer needed, but are preserved for backward compatibility only. */
void tx_thread_fpu_enable(void);
void tx_thread_fpu_disable(void);
/* Define the version ID of ThreadX. This may be utilized by the application. */
#ifdef TX_THREAD_INIT
CHAR _tx_version_id[] =
"Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M3/AC6 Version 6.1.6 *";
"Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M3/AC6 Version 6.1.9 *";
#else
extern CHAR _tx_version_id[];
#endif

82
ports_module/cortex_m3/ac6/inc/txm_module_port.h
View File

@@ -25,8 +25,8 @@
/* */
/* APPLICATION INTERFACE DEFINITION RELEASE */
/* */
/* txm_module_port.h Cortex-M3/MPU/AC6 */
/* 6.1.6 */
/* txm_module_port.h Cortex-M3/AC6 */
/* 6.1.9 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -40,10 +40,7 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Andres Mlinar Initial Version 6.1 */
/* 04-02-2021 Scott Larson Modified comment(s) and */
/* added check for overflow, */
/* resulting in version 6.1.6 */
/* 10-15-2021 Scott Larson Initial Version 6.1.9 */
/* */
/**************************************************************************/
@@ -94,16 +91,26 @@ The following extensions must also be defined in tx_port.h:
VOID (*tx_timer_module_expiration_function)(ULONG id);
*/
/* Size of module heap. */
#define TXM_MODULE_HEAP_SIZE 512
/* Define the kernel stack size for a module thread. */
#ifndef TXM_MODULE_KERNEL_STACK_SIZE
#define TXM_MODULE_KERNEL_STACK_SIZE 768
#endif
/* For the following 3 access control settings, change TEX and C, B, S (bits 21 through 16 of MPU_RASR)
* to reflect your system memory attributes (cache, shareable, memory type). */
/* Code region access control: privileged read-only, outer & inner write-back, normal memory, shareable. */
#ifndef TXM_MODULE_MPU_CODE_ACCESS_CONTROL
#define TXM_MODULE_MPU_CODE_ACCESS_CONTROL 0x06070000
#endif
/* Data region access control: execute never, read/write, outer & inner write-back, normal memory, shareable. */
#ifndef TXM_MODULE_MPU_DATA_ACCESS_CONTROL
#define TXM_MODULE_MPU_DATA_ACCESS_CONTROL 0x13070000
#endif
/* Shared region access control: execute never, read-only, outer & inner write-back, normal memory, shareable. */
#ifndef TXM_MODULE_MPU_SHARED_ACCESS_CONTROL
#define TXM_MODULE_MPU_SHARED_ACCESS_CONTROL 0x12070000
#endif
/* Define constants specific to the tools the module can be built with for this particular modules port. */
#define TXM_MODULE_IAR_COMPILER 0x00000000
@@ -154,12 +161,47 @@ The following extensions must also be defined in tx_port.h:
/* Define other module port-specific constants. */
/* Define INLINE_DECLARE to inline for AC6 compiler. */
/* Define INLINE_DECLARE to inline for ARM compiler. */
#define INLINE_DECLARE inline
#ifdef TXM_MODULE_MANAGER_16_MPU
/* Define the number of MPU entries assigned to the code and data sections.
On Cortex-M3 parts, there are 8 total entries. ThreadX uses one for access
On some Cortex-M7 parts, there are 16 total entries. ThreadX uses one for access
to the kernel entry function, thus 15 remain for code and data protection. */
#define TXM_MODULE_MPU_TOTAL_ENTRIES 16
#define TXM_MODULE_MPU_CODE_ENTRIES 4
#define TXM_MODULE_MPU_DATA_ENTRIES 4
#define TXM_MODULE_MPU_SHARED_ENTRIES 3
#define TXM_MODULE_MPU_KERNEL_ENTRY_INDEX 0
#define TXM_MODULE_MPU_SHARED_INDEX 9
#define TXM_ENABLE_REGION 0x01
/* There are 2 registers to set up each MPU region: MPU_RBAR, MPU_RASR. */
typedef struct TXM_MODULE_MPU_INFO_STRUCT
{
ULONG txm_module_mpu_region_address;
ULONG txm_module_mpu_region_attribute_size;
} TXM_MODULE_MPU_INFO;
/* Shared memory region attributes. */
#define TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE 1
#define TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT 0x01000000
/* Define the port-extensions to the module manager instance structure. */
#define TXM_MODULE_MANAGER_PORT_EXTENSION \
TXM_MODULE_MPU_INFO txm_module_instance_mpu_registers[TXM_MODULE_MPU_TOTAL_ENTRIES]; \
ULONG txm_module_instance_shared_memory_count; \
ULONG txm_module_instance_shared_memory_address[TXM_MODULE_MPU_SHARED_ENTRIES]; \
ULONG txm_module_instance_shared_memory_length[TXM_MODULE_MPU_SHARED_ENTRIES];
#else /* TXM_MODULE_MANAGER_16_MPU is not defined */
/* Define the number of MPU entries assigned to the code and data sections.
On Cortex-M3, M4, and some M7 parts, there are 8 total entries. ThreadX uses one for access
to the kernel entry function, thus 7 remain for code and data protection. */
#define TXM_MODULE_MANAGER_CODE_MPU_ENTRIES 4
#define TXM_MODULE_MANAGER_DATA_MPU_ENTRIES 3
@@ -177,6 +219,7 @@ The following extensions must also be defined in tx_port.h:
ULONG txm_module_instance_shared_memory_address; \
ULONG txm_module_instance_shared_memory_length;
#endif /* TXM_MODULE_MANAGER_16_MPU */
/* Define the memory fault information structure that is populated when a memory fault occurs. */
@@ -299,6 +342,10 @@ typedef struct TXM_MODULE_MANAGER_MEMORY_FAULT_INFO_STRUCT
/* Define the macros to perform port-specific checks when passing pointers to the kernel. */
/* Define macro to make sure object is inside the module's data. */
#ifdef TXM_MODULE_MANAGER_16_MPU
#define TXM_MODULE_MANAGER_CHECK_INSIDE_DATA(module_instance, obj_ptr, obj_size) \
_txm_module_manager_inside_data_check(module_instance, obj_ptr, obj_size)
#else
#define TXM_MODULE_MANAGER_CHECK_INSIDE_DATA(module_instance, obj_ptr, obj_size) \
/* Check for overflow. */ \
(((obj_ptr) < ((obj_ptr) + (obj_size))) && \
@@ -308,7 +355,7 @@ typedef struct TXM_MODULE_MANAGER_MEMORY_FAULT_INFO_STRUCT
/* Check if it's inside shared memory. */ \
(((obj_ptr) >= (ALIGN_TYPE) module_instance -> txm_module_instance_shared_memory_address) && \
(((obj_ptr) + (obj_size)) <= (ALIGN_TYPE) (module_instance -> txm_module_instance_shared_memory_address + module_instance -> txm_module_instance_shared_memory_length)))))
#endif
/* Define some internal prototypes to this module port. */
@@ -324,10 +371,11 @@ UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD
VOID _txm_module_manager_mm_register_setup(TXM_MODULE_INSTANCE *module_instance); \
ULONG _txm_power_of_two_block_size(ULONG size); \
ULONG _txm_module_manager_calculate_srd_bits(ULONG block_size, ULONG length); \
ULONG _txm_module_manager_region_size_get(ULONG block_size);
ULONG _txm_module_manager_region_size_get(ULONG block_size); \
UINT _txm_module_manager_inside_data_check(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE obj_ptr, UINT obj_size);
#define TXM_MODULE_MANAGER_VERSION_ID \
CHAR _txm_module_manager_version_id[] = \
"Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M3/MPU/AC6 Version 6.1.8 *";
CHAR _txm_module_manager_version_id[] = \
"Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M3/AC6 Version 6.1.9 *";
#endif

6
ports_module/cortex_m3/ac6/module_lib/src/txm_module_initialize.S
View File

@@ -32,8 +32,8 @@
/* */
/* FUNCTION RELEASE */
/* */
/* _txm_module_initialize Cortex-M4/MPU/AC6 */
/* 6.1 */
/* _txm_module_initialize Cortex-M3/AC6 */
/* 6.1.9 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -62,7 +62,7 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Andres Mlinar Initial Version 6.1 */
/* 10-15-2021 Scott Larson Initial Version 6.1.9 */
/* */
/**************************************************************************/
// VOID _txm_module_initialize(VOID)

15
ports_module/cortex_m3/ac6/module_lib/src/txm_module_thread_shell_entry.c
View File

@@ -44,7 +44,9 @@ TXM_MODULE_THREAD_ENTRY_INFO *_txm_module_entry_info;
ULONG (*_txm_module_kernel_call_dispatcher)(ULONG kernel_request, ULONG param_1, ULONG param_2, ULONG param3);
/* Define the ARM cstartup code. */
/* Define the startup code that clears the uninitialized global data and sets up the
preset global variables. */
extern VOID _txm_module_initialize(VOID);
@@ -52,15 +54,15 @@ extern VOID _txm_module_initialize(VOID);
/* */
/* FUNCTION RELEASE */
/* */
/* _txm_module_thread_shell_entry Cortex-M3/MPU/AC6 */
/* 6.1 */
/* _txm_module_thread_shell_entry Cortex-M3/AC6 */
/* 6.1.9 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
/* */
/* DESCRIPTION */
/* */
/* This function calls the specified entry function of the thread. It */
/* This function calls the specified entry function of the thread. It */
/* also provides a place for the thread's entry function to return. */
/* If the thread returns, this function places the thread in a */
/* "COMPLETED" state. */
@@ -89,7 +91,7 @@ extern VOID _txm_module_initialize(VOID);
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* 10-15-2021 Scott Larson Initial Version 6.1.9 */
/* */
/**************************************************************************/
VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_ENTRY_INFO *thread_info)
@@ -104,7 +106,7 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN
execution. If not, simply skip the C startup code. */
if (thread_info -> txm_module_thread_entry_info_start_thread)
{
/* Initialize the ARM C environment. */
/* Initialize the C environment. */
_txm_module_initialize();
/* Save the entry info pointer, for later use. */
@@ -169,4 +171,3 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN
TX_SAFETY_CRITICAL_EXCEPTION(__FILE__, __LINE__, 0);
#endif
}

6
ports_module/cortex_m3/ac6/module_manager/src/tx_thread_context_restore.S
View File

@@ -31,8 +31,8 @@
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_context_restore Cortex-Mx/AC6 */
/* 6.1.8 */
/* _tx_thread_context_restore Cortex-M3/AC6 */
/* 6.1.7 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -62,7 +62,7 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 08-02-2021 Scott Larson Initial Version 6.1.8 */
/* 06-02-2021 Scott Larson Initial Version 6.1.7 */
/* */
/**************************************************************************/
// VOID _tx_thread_context_restore(VOID)

6
ports_module/cortex_m3/ac6/module_manager/src/tx_thread_context_save.S
View File

@@ -30,8 +30,8 @@
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_context_save Cortex-Mx/AC6 */
/* 6.1.8 */
/* _tx_thread_context_save Cortex-M3/AC6 */
/* 6.1.7 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -61,7 +61,7 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 08-02-2021 Scott Larson Initial Version 6.1.8 */
/* 06-02-2021 Scott Larson Initial Version 6.1.7 */
/* */
/**************************************************************************/
// VOID _tx_thread_context_save(VOID)

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