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Release 6.1.9

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This commit is contained in:
Yuxin Zhou
2021-10-14 00:51:26 +00:00
parent 215df45d4b
commit 1af8404c54
1812 changed files with 60698 additions and 249862 deletions
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21
ports_module/cortex_m4/ac5/inc/tx_port.h
View File

@@ -26,7 +26,7 @@
/* PORT SPECIFIC C INFORMATION RELEASE */
/* */
/* tx_port.h Cortex-M4/AC5 */
/* 6.1.6 */
/* 6.1.9 */
/* */
/* AUTHOR */
/* */
@@ -47,10 +47,7 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */
/* macro definition, */
/* resulting in version 6.1.6 */
/* 10-15-2021 Scott Larson Initial Version 6.1.9 */
/* */
/**************************************************************************/
@@ -142,7 +139,7 @@ typedef unsigned short USHORT;
/* Define the port specific options for the _tx_build_options variable. This variable indicates
how the ThreadX library was built. */
#define TX_PORT_SPECIFIC_BUILD_OPTIONS 0
#define TX_PORT_SPECIFIC_BUILD_OPTIONS (0)
/* Define the in-line initialization constant so that modules with in-line
@@ -344,8 +341,6 @@ void _tx_vfp_access(void);
#endif
/* Define the ThreadX object creation extensions for the remaining objects. */
#define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr)
@@ -386,7 +381,7 @@ ULONG _tx_misra_ipsr_get(VOID);
zero after initialization for Cortex-M ports. */
#ifndef TX_THREAD_SYSTEM_RETURN_CHECK
#define TX_THREAD_SYSTEM_RETURN_CHECK(c) (c) = ((ULONG) _tx_thread_preempt_disable);
#define TX_THREAD_SYSTEM_RETURN_CHECK(c) (c) = ((ULONG) _tx_thread_preempt_disable);
#endif
@@ -452,7 +447,7 @@ unsigned int was_masked;
#endif
/* Define FPU extension for the Cortex-M4. Each is assumed to be called in the context of the executing
/* Define FPU extension for the Cortex-M4. Each is assumed to be called in the context of the executing
thread. These are no longer needed, but are preserved for backward compatibility only. */
void tx_thread_fpu_enable(void);
@@ -463,7 +458,7 @@ void tx_thread_fpu_disable(void);
#ifdef TX_THREAD_INIT
CHAR _tx_version_id[] =
"Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M4/AC5 Version 6.1 *";
"Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M4/AC5 Version 6.1.9 *";
#else
#ifdef TX_MISRA_ENABLE
extern CHAR _tx_version_id[100];
@@ -474,7 +469,3 @@ extern CHAR _tx_version_id[];
#endif

66
ports_module/cortex_m4/ac5/inc/txm_module_port.h
View File

@@ -25,8 +25,8 @@
/* */
/* APPLICATION INTERFACE DEFINITION RELEASE */
/* */
/* txm_module_port.h Cortex-M4/MPU/AC5 */
/* 6.1.6 */
/* txm_module_port.h Cortex-M4/AC5 */
/* 6.1.9 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -40,13 +40,7 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* 11-09-2020 Scott Larson Modified comment(s), */
/* increase kernel stack size, */
/* resulting in version 6.1.2 */
/* 04-02-2021 Scott Larson Modified comment(s), */
/* added check for overflow, */
/* resulting in version 6.1.6 */
/* 10-15-2021 Scott Larson Initial Version 6.1.9 */
/* */
/**************************************************************************/
@@ -97,11 +91,6 @@ The following extensions must also be defined in tx_port.h:
VOID (*tx_timer_module_expiration_function)(ULONG id);
*/
/* Size of module heap. */
#define TXM_MODULE_HEAP_SIZE 512
/* Define the kernel stack size for a module thread. */
#ifndef TXM_MODULE_KERNEL_STACK_SIZE
#define TXM_MODULE_KERNEL_STACK_SIZE 768
@@ -176,8 +165,43 @@ The following extensions must also be defined in tx_port.h:
#define INLINE_DECLARE inline
#ifdef TXM_MODULE_MANAGER_16_MPU
/* Define the number of MPU entries assigned to the code and data sections.
On Cortex-M4 parts, there are 8 total entries. ThreadX uses one for access
On some Cortex-M7 parts, there are 16 total entries. ThreadX uses one for access
to the kernel entry function, thus 15 remain for code and data protection. */
#define TXM_MODULE_MPU_TOTAL_ENTRIES 16
#define TXM_MODULE_MPU_CODE_ENTRIES 4
#define TXM_MODULE_MPU_DATA_ENTRIES 4
#define TXM_MODULE_MPU_SHARED_ENTRIES 3
#define TXM_MODULE_MPU_KERNEL_ENTRY_INDEX 0
#define TXM_MODULE_MPU_SHARED_INDEX 9
#define TXM_ENABLE_REGION 0x01
/* There are 2 registers to set up each MPU region: MPU_RBAR, MPU_RASR. */
typedef struct TXM_MODULE_MPU_INFO_STRUCT
{
ULONG txm_module_mpu_region_address;
ULONG txm_module_mpu_region_attribute_size;
} TXM_MODULE_MPU_INFO;
/* Shared memory region attributes. */
#define TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE 1
#define TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT 0x01000000
/* Define the port-extensions to the module manager instance structure. */
#define TXM_MODULE_MANAGER_PORT_EXTENSION \
TXM_MODULE_MPU_INFO txm_module_instance_mpu_registers[TXM_MODULE_MPU_TOTAL_ENTRIES]; \
ULONG txm_module_instance_shared_memory_count; \
ULONG txm_module_instance_shared_memory_address[TXM_MODULE_MPU_SHARED_ENTRIES]; \
ULONG txm_module_instance_shared_memory_length[TXM_MODULE_MPU_SHARED_ENTRIES];
#else /* TXM_MODULE_MANAGER_16_MPU is not defined */
/* Define the number of MPU entries assigned to the code and data sections.
On Cortex-M3, M4, and some M7 parts, there are 8 total entries. ThreadX uses one for access
to the kernel entry function, thus 7 remain for code and data protection. */
#define TXM_MODULE_MANAGER_CODE_MPU_ENTRIES 4
#define TXM_MODULE_MANAGER_DATA_MPU_ENTRIES 3
@@ -195,6 +219,7 @@ The following extensions must also be defined in tx_port.h:
ULONG txm_module_instance_shared_memory_address; \
ULONG txm_module_instance_shared_memory_length;
#endif /* TXM_MODULE_MANAGER_16_MPU */
/* Define the memory fault information structure that is populated when a memory fault occurs. */
@@ -317,6 +342,10 @@ typedef struct TXM_MODULE_MANAGER_MEMORY_FAULT_INFO_STRUCT
/* Define the macros to perform port-specific checks when passing pointers to the kernel. */
/* Define macro to make sure object is inside the module's data. */
#ifdef TXM_MODULE_MANAGER_16_MPU
#define TXM_MODULE_MANAGER_CHECK_INSIDE_DATA(module_instance, obj_ptr, obj_size) \
_txm_module_manager_inside_data_check(module_instance, obj_ptr, obj_size)
#else
#define TXM_MODULE_MANAGER_CHECK_INSIDE_DATA(module_instance, obj_ptr, obj_size) \
/* Check for overflow. */ \
(((obj_ptr) < ((obj_ptr) + (obj_size))) && \
@@ -326,7 +355,7 @@ typedef struct TXM_MODULE_MANAGER_MEMORY_FAULT_INFO_STRUCT
/* Check if it's inside shared memory. */ \
(((obj_ptr) >= (ALIGN_TYPE) module_instance -> txm_module_instance_shared_memory_address) && \
(((obj_ptr) + (obj_size)) <= (ALIGN_TYPE) (module_instance -> txm_module_instance_shared_memory_address + module_instance -> txm_module_instance_shared_memory_length)))))
#endif
/* Define some internal prototypes to this module port. */
@@ -342,10 +371,11 @@ UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD
VOID _txm_module_manager_mm_register_setup(TXM_MODULE_INSTANCE *module_instance); \
ULONG _txm_power_of_two_block_size(ULONG size); \
ULONG _txm_module_manager_calculate_srd_bits(ULONG block_size, ULONG length); \
ULONG _txm_module_manager_region_size_get(ULONG block_size);
ULONG _txm_module_manager_region_size_get(ULONG block_size); \
UINT _txm_module_manager_inside_data_check(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE obj_ptr, UINT obj_size);
#define TXM_MODULE_MANAGER_VERSION_ID \
CHAR _txm_module_manager_version_id[] = \
"Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M4/MPU/AC5 Version 6.1.2 *";
"Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M4/AC5 Version 6.1.9 *";
#endif

8
ports_module/cortex_m4/ac5/module_lib/src/txm_module_initialize.S → ports_module/cortex_m4/ac5/module_lib/src/txm_module_initialize.s
View File

@@ -29,8 +29,8 @@
/* */
/* FUNCTION RELEASE */
/* */
/* _txm_module_initialize Cortex-M4/MPU/AC5 */
/* 6.1.2 */
/* _txm_module_initialize Cortex-M4/AC5 */
/* 6.1.9 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -59,9 +59,7 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* 11-09-2020 Scott Larson Modified comment(s), */
/* resulting in version 6.1.2 */
/* 10-15-2021 Scott Larson Initial Version 6.1.9 */
/* */
/**************************************************************************/
// VOID _txm_module_initialize(VOID)

15
ports_module/cortex_m4/ac5/module_lib/src/txm_module_thread_shell_entry.c
View File

@@ -44,7 +44,9 @@ TXM_MODULE_THREAD_ENTRY_INFO *_txm_module_entry_info;
ULONG (*_txm_module_kernel_call_dispatcher)(ULONG kernel_request, ULONG param_1, ULONG param_2, ULONG param3);
/* Define the ARM cstartup code. */
/* Define the startup code that clears the uninitialized global data and sets up the
preset global variables. */
extern VOID _txm_module_initialize(VOID);
__align(8) UCHAR txm_heap[TXM_MODULE_HEAP_SIZE];
@@ -53,15 +55,15 @@ __align(8) UCHAR txm_heap[TXM_MODULE_HEAP_SIZE];
/* */
/* FUNCTION RELEASE */
/* */
/* _txm_module_thread_shell_entry Cortex-M4/MPU/AC5 */
/* 6.1 */
/* _txm_module_thread_shell_entry Cortex-M4/AC5 */
/* 6.1.9 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
/* */
/* DESCRIPTION */
/* */
/* This function calls the specified entry function of the thread. It */
/* This function calls the specified entry function of the thread. It */
/* also provides a place for the thread's entry function to return. */
/* If the thread returns, this function places the thread in a */
/* "COMPLETED" state. */
@@ -90,7 +92,7 @@ __align(8) UCHAR txm_heap[TXM_MODULE_HEAP_SIZE];
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* 10-15-2021 Scott Larson Initial Version 6.1.9 */
/* */
/**************************************************************************/
VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_ENTRY_INFO *thread_info)
@@ -105,7 +107,7 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN
execution. If not, simply skip the C startup code. */
if (thread_info -> txm_module_thread_entry_info_start_thread)
{
/* Initialize the ARM C environment. */
/* Initialize the C environment. */
_txm_module_initialize();
/* Save the entry info pointer, for later use. */
@@ -170,4 +172,3 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN
TX_SAFETY_CRITICAL_EXCEPTION(__FILE__, __LINE__, 0);
#endif
}

6
ports_module/cortex_m4/ac5/module_manager/src/tx_thread_context_restore.S → ports_module/cortex_m4/ac5/module_manager/src/tx_thread_context_restore.s
View File

@@ -30,8 +30,8 @@
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_context_restore Cortex-Mx/AC5 */
/* 6.1.8 */
/* _tx_thread_context_restore Cortex-M4/AC5 */
/* 6.1.7 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -61,7 +61,7 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 08-02-2021 Scott Larson Initial Version 6.1.8 */
/* 06-02-2021 Scott Larson Initial Version 6.1.7 */
/* */
/**************************************************************************/
// VOID _tx_thread_context_restore(VOID)

6
ports_module/cortex_m4/ac5/module_manager/src/tx_thread_context_save.S → ports_module/cortex_m4/ac5/module_manager/src/tx_thread_context_save.s
View File

@@ -30,8 +30,8 @@
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_context_save Cortex-Mx/AC5 */
/* 6.1.8 */
/* _tx_thread_context_save Cortex-M4/AC5 */
/* 6.1.7 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -61,7 +61,7 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 08-02-2021 Scott Larson Initial Version 6.1.8 */
/* 06-02-2021 Scott Larson Initial Version 6.1.7 */
/* */
/**************************************************************************/
// VOID _tx_thread_context_save(VOID)

6
ports_module/cortex_m4/ac5/module_manager/src/tx_thread_interrupt_control.S → ports_module/cortex_m4/ac5/module_manager/src/tx_thread_interrupt_control.s
View File

@@ -25,8 +25,8 @@
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_interrupt_control Cortex-Mx/AC5 */
/* 6.1.8 */
/* _tx_thread_interrupt_control Cortex-M4/AC5 */
/* 6.1.7 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -56,7 +56,7 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 08-02-2021 Scott Larson Initial Version 6.1.8 */
/* 06-02-2021 Scott Larson Initial Version 6.1.7 */
/* */
/**************************************************************************/
// UINT _tx_thread_interrupt_control(UINT new_posture)

6
ports_module/cortex_m4/ac5/module_manager/src/tx_thread_interrupt_disable.S → ports_module/cortex_m4/ac5/module_manager/src/tx_thread_interrupt_disable.s
View File

@@ -25,8 +25,8 @@
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_interrupt_disable Cortex-Mx/AC5 */
/* 6.1.8 */
/* _tx_thread_interrupt_disable Cortex-M4/AC5 */
/* 6.1.7 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -56,7 +56,7 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 08-02-2021 Scott Larson Initial Version 6.1.8 */
/* 06-02-2021 Scott Larson Initial Version 6.1.7 */
/* */
/**************************************************************************/
// UINT _tx_thread_interrupt_disable(VOID)

6
ports_module/cortex_m4/ac5/module_manager/src/tx_thread_interrupt_restore.S → ports_module/cortex_m4/ac5/module_manager/src/tx_thread_interrupt_restore.s
View File

@@ -25,8 +25,8 @@
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_interrupt_restore Cortex-Mx/AC5 */
/* 6.1.8 */
/* _tx_thread_interrupt_restore Cortex-M4/AC5 */
/* 6.1.7 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -56,7 +56,7 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 08-02-2021 Scott Larson Initial Version 6.1.8 */
/* 06-02-2021 Scott Larson Initial Version 6.1.7 */
/* */
/**************************************************************************/
// VOID _tx_thread_interrupt_restore(UINT previous_posture)

24
ports_module/cortex_m4/ac5/module_manager/src/tx_thread_schedule.S → ports_module/cortex_m4/ac5/module_manager/src/tx_thread_schedule.s
View File

@@ -39,8 +39,8 @@
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_schedule Cortex-M4/MPU/AC5 */
/* 6.1.7 */
/* _tx_thread_schedule Cortex-M4/AC5 */
/* 6.1.9 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -73,14 +73,7 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* 11-09-2020 Scott Larson Modified comment(s), arrange */
/* code to fix link error when */
/* VFP is enabled, resulting */
/* in version 6.1.2 */
/* 06-02-2021 Scott Larson Fixed extended stack handling */
/* when calling kernel APIs, */
/* resulting in version 6.1.7 */
/* 10-15-2021 Scott Larson Initial Version 6.1.9 */
/* */
/**************************************************************************/
// VOID _tx_thread_schedule(VOID)
@@ -359,10 +352,21 @@ __tx_ts_restore
// Use alias registers to quickly load MPU
ADD r0, r0, #100 // Build address of MPU register start in thread control block
#ifdef TXM_MODULE_MANAGER_16_MPU
LDM r0!,{r2-r9} // Load MPU regions 0-3
STM r1,{r2-r9} // Store MPU regions 0-3
LDM r0!,{r2-r9} // Load MPU regions 4-7
STM r1,{r2-r9} // Store MPU regions 4-7
LDM r0!,{r2-r9} // Load MPU regions 8-11
STM r1,{r2-r9} // Store MPU regions 8-11
LDM r0,{r2-r9} // Load MPU regions 12-15
STM r1,{r2-r9} // Store MPU regions 12-15
#else
LDM r0!,{r2-r9} // Load first four MPU regions
STM r1,{r2-r9} // Store first four MPU regions
LDM r0,{r2-r9} // Load second four MPU regions
STM r1,{r2-r9} // Store second four MPU regions
#endif
LDR r0, =0xE000ED94 // Build MPU control reg address
MOV r1, #5 // Build enable value with background region enabled
STR r1, [r0] // Enable MPU

6
ports_module/cortex_m4/ac5/module_manager/src/tx_thread_stack_build.S → ports_module/cortex_m4/ac5/module_manager/src/tx_thread_stack_build.s
View File

@@ -25,8 +25,8 @@
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_stack_build Cortex-Mx/AC5 */
/* 6.1.8 */
/* _tx_thread_stack_build Cortex-M4/AC5 */
/* 6.1.7 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -58,7 +58,7 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 08-02-2021 Scott Larson Initial Version 6.1.8 */
/* 06-02-2021 Scott Larson Initial Version 6.1.7 */
/* */
/**************************************************************************/
// VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID))

6
ports_module/cortex_m4/ac5/module_manager/src/tx_thread_system_return.S → ports_module/cortex_m4/ac5/module_manager/src/tx_thread_system_return.s
View File

@@ -25,8 +25,8 @@
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_system_return Cortex-Mx/AC5 */
/* 6.1.8 */
/* _tx_thread_system_return Cortex-M4/AC5 */
/* 6.1.7 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -58,7 +58,7 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 08-02-2021 Scott Larson Initial Version 6.1.8 */
/* 06-02-2021 Scott Larson Initial Version 6.1.7 */
/* */
/**************************************************************************/
// VOID _tx_thread_system_return(VOID)

6
ports_module/cortex_m4/ac5/module_manager/src/tx_timer_interrupt.S → ports_module/cortex_m4/ac5/module_manager/src/tx_timer_interrupt.s
View File

@@ -39,8 +39,8 @@
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_timer_interrupt Cortex-Mx/AC5 */
/* 6.1.8 */
/* _tx_timer_interrupt Cortex-M4/AC5 */
/* 6.1.7 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -73,7 +73,7 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 08-02-2021 Scott Larson Initial Version 6.1.8 */
/* 06-02-2021 Scott Larson Initial Version 6.1.7 */
/* */
/**************************************************************************/
// VOID _tx_timer_interrupt(VOID)

61
ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_alignment_adjust.c
View File

@@ -30,8 +30,8 @@
/* */
/* FUNCTION RELEASE */
/* */
/* _txm_power_of_two_block_size Cortex-M4/MPU/AC5 */
/* 6.1 */
/* _txm_power_of_two_block_size Cortex-M4 */
/* 6.1.9 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -61,7 +61,7 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* 10-15-2021 Scott Larson Initial Version 6.1.9 */
/* */
/**************************************************************************/
ULONG _txm_power_of_two_block_size(ULONG size)
@@ -93,8 +93,8 @@ ULONG _txm_power_of_two_block_size(ULONG size)
/* */
/* FUNCTION RELEASE */
/* */
/* _txm_module_manager_alignment_adjust Cortex-M4/MPU/AC5 */
/* 6.1 */
/* _txm_module_manager_alignment_adjust Cortex-M4 */
/* 6.1.9 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -128,7 +128,7 @@ ULONG _txm_power_of_two_block_size(ULONG size)
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* 10-15-2021 Scott Larson Initial Version 6.1.9 */
/* */
/**************************************************************************/
VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble,
@@ -137,6 +137,53 @@ VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble,
ULONG *data_size,
ULONG *data_alignment)
{
#ifdef TXM_MODULE_MANAGER_16_MPU
ULONG local_code_size;
ULONG local_code_alignment;
ULONG local_data_size;
ULONG local_data_alignment;
ULONG code_size_accum;
ULONG data_size_accum;
/* Copy the input parameters into local variables for ease of use. */
local_code_size = *code_size;
local_code_alignment = *code_alignment;
local_data_size = *data_size;
local_data_alignment = *data_alignment;
/* Determine code block sizes. Minimize the alignment requirement.
There are 4 MPU code entries available. The following is how the code size
will be distributed:
1. 1/4 of the largest power of two that is greater than or equal to code size.
2. 1/4 of the largest power of two that is greater than or equal to code size.
3. Largest power of 2 that fits in the remaining space.
4. Smallest power of 2 that exceeds the remaining space, minimum 32. */
local_code_alignment = _txm_power_of_two_block_size(local_code_size) >> 2;
code_size_accum = local_code_alignment + local_code_alignment;
code_size_accum = code_size_accum + (_txm_power_of_two_block_size(local_code_size - code_size_accum) >> 1);
code_size_accum = code_size_accum + _txm_power_of_two_block_size(local_code_size - code_size_accum);
local_code_size = code_size_accum;
/* Determine data block sizes. Minimize the alignment requirement.
There are 4 MPU data entries available. The following is how the data size
will be distributed:
1. 1/4 of the largest power of two that is greater than or equal to data size.
2. 1/4 of the largest power of two that is greater than or equal to data size.
3. Largest power of 2 that fits in the remaining space.
4. Smallest power of 2 that exceeds the remaining space, minimum 32. */
local_data_alignment = _txm_power_of_two_block_size(local_data_size) >> 2;
data_size_accum = local_data_alignment + local_data_alignment;
data_size_accum = data_size_accum + (_txm_power_of_two_block_size(local_data_size - data_size_accum) >> 1);
data_size_accum = data_size_accum + _txm_power_of_two_block_size(local_data_size - data_size_accum);
local_data_size = data_size_accum;
/* Return all the information to the caller. */
*code_size = local_code_size;
*code_alignment = local_code_alignment;
*data_size = local_data_size;
*data_alignment = local_data_alignment;
#else
ULONG local_code_size;
ULONG local_code_alignment;
@@ -396,4 +443,6 @@ ULONG data_size_accum;
*code_alignment = local_code_alignment;
*data_size = local_data_size;
*data_alignment = local_data_alignment;
#endif
}

119
ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_external_memory_enable.c
View File

@@ -33,8 +33,8 @@
/* */
/* FUNCTION RELEASE */
/* */
/* _txm_module_manager_external_memory_enable Cortex-M4/MPU/AC5 */
/* 6.1 */
/* _txm_module_manager_external_memory_enable Cortex-M4 */
/* 6.1.9 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -70,7 +70,7 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* 10-15-2021 Scott Larson Initial Version 6.1.9 */
/* */
/**************************************************************************/
UINT _txm_module_manager_external_memory_enable(TXM_MODULE_INSTANCE *module_instance,
@@ -78,6 +78,117 @@ UINT _txm_module_manager_external_memory_enable(TXM_MODULE_INSTANCE *module_ins
ULONG length,
UINT attributes)
{
#ifdef TXM_MODULE_MANAGER_16_MPU
ULONG block_size;
ULONG region_size;
ULONG srd_bits;
ULONG size_register;
ULONG address;
ULONG shared_index;
ULONG attributes_check = 0;
/* Determine if the module manager has not been initialized yet. */
if (_txm_module_manager_ready != TX_TRUE)
{
/* Module manager has not been initialized. */
return(TX_NOT_AVAILABLE);
}
/* Determine if the module is valid. */
if (module_instance == TX_NULL)
{
/* Invalid module pointer. */
return(TX_PTR_ERROR);
}
/* Get module manager protection mutex. */
_tx_mutex_get(&_txm_module_manager_mutex, TX_WAIT_FOREVER);
/* Determine if the module instance is valid. */
if (module_instance -> txm_module_instance_id != TXM_MODULE_ID)
{
/* Release the protection mutex. */
_tx_mutex_put(&_txm_module_manager_mutex);
/* Invalid module pointer. */
return(TX_PTR_ERROR);
}
/* Determine if the module instance is in the loaded state. */
if (module_instance -> txm_module_instance_state != TXM_MODULE_LOADED)
{
/* Release the protection mutex. */
_tx_mutex_put(&_txm_module_manager_mutex);
/* Return error if the module is not ready. */
return(TX_START_ERROR);
}
/* Determine if there are shared memory entries available. */
if(module_instance -> txm_module_instance_shared_memory_count >= TXM_MODULE_MPU_SHARED_ENTRIES)
{
/* Release the protection mutex. */
_tx_mutex_put(&_txm_module_manager_mutex);
/* No more entries available. */
return(TX_NO_MEMORY);
}
/* Start address and length must adhere to Cortex-M7 MPU.
The address must align with the block size. */
block_size = _txm_power_of_two_block_size(length);
address = (ULONG) start_address;
if(address != (address & ~(block_size - 1)))
{
/* Release the protection mutex. */
_tx_mutex_put(&_txm_module_manager_mutex);
/* Return alignment error. */
return(TXM_MODULE_ALIGNMENT_ERROR);
}
/* At this point, we have a valid address and block size.
Set up MPU registers. */
/* Pick up index into shared memory entries. */
shared_index = TXM_MODULE_MPU_SHARED_INDEX + module_instance -> txm_module_instance_shared_memory_count;
/* Save address register with address, MPU region, set Valid bit. */
module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_address = address | shared_index | 0x10;
/* Calculate the region size. */
region_size = (_txm_module_manager_region_size_get(block_size) << 1);
/* Calculate the subregion bits. */
srd_bits = _txm_module_manager_calculate_srd_bits(block_size, length);
/* Generate SRD, size, and enable attributes. */
size_register = srd_bits | region_size | TXM_ENABLE_REGION | TXM_MODULE_MPU_SHARED_ACCESS_CONTROL;
/* Check for optional write attribute. */
if(attributes & TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE)
{
attributes_check = TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT;
}
/* Save attribute-size register. */
module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_attribute_size = attributes_check | size_register;
/* Keep track of shared memory address and length in module instance. */
module_instance -> txm_module_instance_shared_memory_address[module_instance -> txm_module_instance_shared_memory_count] = address;
module_instance -> txm_module_instance_shared_memory_length[module_instance -> txm_module_instance_shared_memory_count] = length;
/* Increment counter. */
module_instance -> txm_module_instance_shared_memory_count++;
/* Release the protection mutex. */
_tx_mutex_put(&_txm_module_manager_mutex);
/* Return success. */
return(TX_SUCCESS);
#else
ULONG block_size;
ULONG region_size;
@@ -179,4 +290,6 @@ TXM_MODULE_PREAMBLE *module_preamble;
/* Return success. */
return(TX_SUCCESS);
#endif
}

6
ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_memory_fault_handler.c
View File

@@ -45,8 +45,8 @@ TXM_MODULE_MANAGER_FAULT_INFO
/* */
/* FUNCTION RELEASE */
/* */
/* _txm_module_manager_memory_fault_handler Cortex-M4/MPU/AC5 */
/* 6.1 */
/* _txm_module_manager_memory_fault_handler Cortex-M4 */
/* 6.1.9 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -76,7 +76,7 @@ TXM_MODULE_MANAGER_FAULT_INFO
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* 10-15-2021 Scott Larson Initial Version 6.1.9 */
/* */
/**************************************************************************/
VOID _txm_module_manager_memory_fault_handler(VOID)

6
ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_memory_fault_notify.c
View File

@@ -38,8 +38,8 @@ extern VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTA
/* */
/* FUNCTION RELEASE */
/* */
/* _txm_module_manager_memory_fault_notify Cortex-M4/MPU/AC5 */
/* 6.1 */
/* _txm_module_manager_memory_fault_notify Cortex-M4 */
/* 6.1.9 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -71,7 +71,7 @@ extern VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTA
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* 10-15-2021 Scott Larson Initial Version 6.1.9 */
/* */
/**************************************************************************/
UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *))

309
ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_mm_register_setup.c
View File

@@ -30,8 +30,8 @@
/* */
/* FUNCTION RELEASE */
/* */
/* _txm_module_manager_region_size_get Cortex-M4/MPU/AC5 */
/* 6.1 */
/* _txm_module_manager_region_size_get Cortex-M4 */
/* 6.1.9 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -61,7 +61,7 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* 10-15-2021 Scott Larson Initial Version 6.1.9 */
/* */
/**************************************************************************/
ULONG _txm_module_manager_region_size_get(ULONG block_size)
@@ -152,8 +152,8 @@ ULONG return_value;
/* */
/* FUNCTION RELEASE */
/* */
/* _txm_module_manager_calculate_srd_bits Cortex-M4/MPU/AC5 */
/* 6.1 */
/* _txm_module_manager_calculate_srd_bits Cortex-M4 */
/* 6.1.9 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -184,7 +184,7 @@ ULONG return_value;
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* 10-15-2021 Scott Larson Initial Version 6.1.9 */
/* */
/**************************************************************************/
ULONG _txm_module_manager_calculate_srd_bits(ULONG block_size, ULONG length)
@@ -230,16 +230,48 @@ UINT srd_bit_index;
/* */
/* FUNCTION RELEASE */
/* */
/* _txm_module_manager_mm_register_setup Cortex-M4/MPU/AC5 */
/* 6.1 */
/* _txm_module_manager_mm_register_setup Cortex-M4 */
/* 6.1.9 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
/* */
/* DESCRIPTION */
/* */
/* This function sets up the Cortex-M4 MPU register definitions based */
/* on the module's memory characteristics. */
/* This function sets up the MPU register definitions based on the */
/* module's memory characteristics. */
/* */
/* Default MPU layout: */
/* Entry Description */
/* 0 Kernel mode entry */
/* 1 Module code region */
/* 2 Module code region */
/* 3 Module code region */
/* 4 Module code region */
/* 5 Module data region */
/* 6 Module data region */
/* 7 Module data region */
/* */
/* If TXM_MODULE_MANAGER_16_MPU is defined, there are 16 MPU slots. */
/* MPU layout for the Cortex-M7: */
/* Entry Description */
/* 0 Kernel mode entry */
/* 1 Module code region */
/* 2 Module code region */
/* 3 Module code region */
/* 4 Module code region */
/* 5 Module data region */
/* 6 Module data region */
/* 7 Module data region */
/* 8 Module data region */
/* 9 Module shared memory region */
/* 10 Module shared memory region */
/* 11 Module shared memory region */
/* 12 Unused region */
/* 13 Unused region */
/* 14 Unused region */
/* 15 Unused region */
/* */
/* */
/* INPUT */
/* */
@@ -261,11 +293,181 @@ UINT srd_bit_index;
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* 10-15-2021 Scott Larson Initial Version 6.1.9 */
/* */
/**************************************************************************/
VOID _txm_module_manager_mm_register_setup(TXM_MODULE_INSTANCE *module_instance)
{
#ifdef TXM_MODULE_MANAGER_16_MPU
ULONG code_address;
ULONG code_size;
ULONG data_address;
ULONG data_size;
ULONG start_stop_stack_size;
ULONG callback_stack_size;
ULONG block_size;
ULONG region_size;
ULONG srd_bits = 0;
UINT mpu_table_index;
UINT i;
/* Setup the first MPU region for kernel mode entry. */
/* Set address register to user mode entry function address, which is guaranteed to be at least 32-byte aligned.
Mask address to proper range, region 0, set Valid bit. */
module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MPU_KERNEL_ENTRY_INDEX].txm_module_mpu_region_address = ((ULONG) _txm_module_manager_user_mode_entry & 0xFFFFFFE0) | 0x10;
/* Set the attributes, size (32 bytes) and enable bit. */
module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MPU_KERNEL_ENTRY_INDEX].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_CODE_ACCESS_CONTROL | (_txm_module_manager_region_size_get(32) << 1) | TXM_ENABLE_REGION;
/* End of kernel mode entry setup. */
/* Setup code protection. */
/* Initialize the MPU table index. */
mpu_table_index = 1;
/* Pickup code starting address and actual size. */
code_address = (ULONG) module_instance -> txm_module_instance_code_start;
code_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_code_size;
/* Determine code block sizes. Minimize the alignment requirement.
There are 4 MPU code entries available. The following is how the code size
will be distributed:
1. 1/4 of the largest power of two that is greater than or equal to code size.
2. 1/4 of the largest power of two that is greater than or equal to code size.
3. Largest power of 2 that fits in the remaining space.
4. Smallest power of 2 that exceeds the remaining space, minimum 32. */
/* Now loop through to setup MPU protection for the code area. */
for (i = 0; i < TXM_MODULE_MPU_CODE_ENTRIES; i++)
{
/* First two MPU blocks are 1/4 of the largest power of two
that is greater than or equal to code size. */
if (i < 2)
{
block_size = _txm_power_of_two_block_size(code_size) >> 2;
}
/* Third MPU block is the largest power of 2 that fits in the remaining space. */
else if (i == 2)
{
/* Subtract (block_size*2) from code_size to calculate remaining space. */
code_size = code_size - (block_size << 1);
block_size = _txm_power_of_two_block_size(code_size) >> 1;
}
/* Last MPU block is the smallest power of 2 that exceeds the remaining space, minimum 32. */
else
{
/* Calculate remaining space. */
code_size = code_size - block_size;
block_size = _txm_power_of_two_block_size(code_size);
srd_bits = _txm_module_manager_calculate_srd_bits(block_size, code_size);
}
/* Calculate the region size information. */
region_size = (_txm_module_manager_region_size_get(block_size) << 1);
/* Build the base address register with address, MPU region, set Valid bit. */
module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = (code_address & ~(block_size - 1)) | mpu_table_index | 0x10;
/* Build the attribute-size register with permissions, SRD, size, enable. */
module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_CODE_ACCESS_CONTROL | srd_bits | region_size | TXM_ENABLE_REGION;
/* Adjust the code address. */
code_address = code_address + block_size;
/* Increment MPU table index. */
mpu_table_index++;
}
/* End of code protection. */
/* Setup data protection. */
/* Reset SRD bitfield. */
srd_bits = 0;
/* Pickup data starting address and actual size. */
data_address = (ULONG) module_instance -> txm_module_instance_data_start;
/* Adjust the size of the module elements to be aligned to the default alignment. We do this
so that when we partition the allocated memory, we can simply place these regions right beside
each other without having to align their pointers. Note this only works when they all have
the same alignment. */
data_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_data_size;
start_stop_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_start_stop_stack_size;
callback_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_callback_stack_size;
data_size = ((data_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT;
start_stop_stack_size = ((start_stop_stack_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT;
callback_stack_size = ((callback_stack_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT;
/* Update the data size to include thread stacks. */
data_size = data_size + start_stop_stack_size + callback_stack_size;
/* Determine data block sizes. Minimize the alignment requirement.
There are 4 MPU data entries available. The following is how the data size
will be distributed:
1. 1/4 of the largest power of two that is greater than or equal to data size.
2. 1/4 of the largest power of two that is greater than or equal to data size.
3. Largest power of 2 that fits in the remaining space.
4. Smallest power of 2 that exceeds the remaining space, minimum 32. */
/* Now loop through to setup MPU protection for the data area. */
for (i = 0; i < TXM_MODULE_MPU_DATA_ENTRIES; i++)
{
/* First two MPU blocks are 1/4 of the largest power of two
that is greater than or equal to data size. */
if (i < 2)
{
block_size = _txm_power_of_two_block_size(data_size) >> 2;
}
/* Third MPU block is the largest power of 2 that fits in the remaining space. */
else if (i == 2)
{
/* Subtract (block_size*2) from data_size to calculate remaining space. */
data_size = data_size - (block_size << 1);
block_size = _txm_power_of_two_block_size(data_size) >> 1;
}
/* Last MPU block is the smallest power of 2 that exceeds the remaining space, minimum 32. */
else
{
/* Calculate remaining space. */
data_size = data_size - block_size;
block_size = _txm_power_of_two_block_size(data_size);
srd_bits = _txm_module_manager_calculate_srd_bits(block_size, data_size);
}
/* Calculate the region size information. */
region_size = (_txm_module_manager_region_size_get(block_size) << 1);
/* Build the base address register with address, MPU region, set Valid bit. */
module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = (data_address & ~(block_size - 1)) | mpu_table_index | 0x10;
/* Build the attribute-size register with permissions, SRD, size, enable. */
module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_DATA_ACCESS_CONTROL | srd_bits | region_size | TXM_ENABLE_REGION;
/* Adjust the data address. */
data_address = data_address + block_size;
/* Increment MPU table index. */
mpu_table_index++;
}
/* Setup MPU for the remaining regions. */
while (mpu_table_index < TXM_MODULE_MPU_TOTAL_ENTRIES)
{
/* Build the base address register with address, MPU region, set Valid bit. */
module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = mpu_table_index | 0x10;
/* Increment MPU table index. */
mpu_table_index++;
}
#else
ULONG code_address;
ULONG code_size;
@@ -382,7 +584,7 @@ UINT i;
for (i = 0; i < TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1; i++)
{
/* Build the base address register. */
base_address_register = code_address & ~(block_size - 1) | mpu_register | 0x10;
base_address_register = (code_address & ~(block_size - 1)) | mpu_register | 0x10;
/* Check if SRD bits need to be set. */
if (code_size < block_size)
@@ -509,4 +711,87 @@ UINT i;
/* Increment the MPU register index. */
mpu_register++;
}
#endif
}
#ifdef TXM_MODULE_MANAGER_16_MPU
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _txm_module_manager_inside_data_check Cortex-M4 */
/* 6.1.9 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
/* */
/* DESCRIPTION */
/* */
/* This function checks if the specified object is inside shared */
/* memory. */
/* */
/* INPUT */
/* */
/* module_instance Pointer to module instance */
/* obj_ptr Pointer to the object */
/* obj_size Size of the object */
/* */
/* OUTPUT */
/* */
/* Whether the object is inside the shared memory region. */
/* */
/* CALLS */
/* */
/* None */
/* */
/* CALLED BY */
/* */
/* Module dispatch check functions */
/* */
/* RELEASE HISTORY */
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 10-15-2021 Scott Larson Initial Version 6.1.9 */
/* */
/**************************************************************************/
UINT _txm_module_manager_inside_data_check(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE obj_ptr, UINT obj_size)
{
UINT shared_memory_index;
UINT num_shared_memory_mpu_entries;
ALIGN_TYPE shared_memory_address_start;
ALIGN_TYPE shared_memory_address_end;
/* Check for overflow. */
if ((obj_ptr) > ((obj_ptr) + (obj_size)))
{
return(TX_FALSE);
}
/* Check if the object is inside the module data. */
if ((obj_ptr >= (ALIGN_TYPE) module_instance -> txm_module_instance_data_start) &&
((obj_ptr + obj_size) <= ((ALIGN_TYPE) module_instance -> txm_module_instance_data_end + 1)))
{
return(TX_TRUE);
}
/* Check if the object is inside the shared memory. */
num_shared_memory_mpu_entries = module_instance -> txm_module_instance_shared_memory_count;
for (shared_memory_index = 0; shared_memory_index < num_shared_memory_mpu_entries; shared_memory_index++)
{
shared_memory_address_start = (ALIGN_TYPE) module_instance -> txm_module_instance_shared_memory_address[shared_memory_index];
shared_memory_address_end = shared_memory_address_start + module_instance -> txm_module_instance_shared_memory_length[shared_memory_index];
if ((obj_ptr >= (ALIGN_TYPE) shared_memory_address_start) &&
((obj_ptr + obj_size) <= (ALIGN_TYPE) shared_memory_address_end))
{
return(TX_TRUE);
}
}
return(TX_FALSE);
}
#endif

10
ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_thread_stack_build.S → ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_thread_stack_build.s
View File

@@ -26,8 +26,8 @@
/* */
/* FUNCTION RELEASE */
/* */
/* _txm_module_manager_thread_stack_build Cortex-M4/MPU/AC5 */
/* 6.1.2 */
/* _txm_module_manager_thread_stack_build Cortex-M4/AC5 */
/* 6.1.9 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -59,9 +59,7 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* 11-09-2020 Scott Larson Modified comment(s), */
/* resulting in version 6.1.2 */
/* 10-15-2021 Scott Larson Initial Version 6.1.9 */
/* */
/**************************************************************************/
// VOID _txm_module_manager_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(TX_THREAD *, TXM_MODULE_INSTANCE *))
@@ -73,7 +71,7 @@ _txm_module_manager_thread_stack_build
on the Cortex-M should look like the following after it is built:
Stack Top:
LR Interrupted LR (LR at time of PENDSV)
lr Interrupted lr (lr at time of PENDSV)
r4 Initial value for r4
r5 Initial value for r5
r6 Initial value for r6

80
ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_user_mode_entry.S → ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_user_mode_entry.s
View File

@@ -10,59 +10,57 @@
/**************************************************************************/
/**************************************************************************/
/**************************************************************************/
/** */
/** ThreadX Component */
/** */
/** Module Manager */
/** */
/**************************************************************************/
/**************************************************************************/
/**************************************************************************/
/**************************************************************************/
/** */
/** ThreadX Component */
/** */
/** Module Manager */
/** */
/**************************************************************************/
/**************************************************************************/
IMPORT _txm_module_manager_kernel_dispatch
IMPORT _tx_thread_current_ptr
AREA ||.text||, CODE, READONLY, ALIGN=5
THUMB
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _txm_module_manager_user_mode_entry Cortex-M4/MPU/AC5 */
/* 6.1.2 */
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _txm_module_manager_user_mode_entry Cortex-M4/AC5 */
/* 6.1.9 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
/* */
/* DESCRIPTION */
/* */
/* This function allows modules to enter kernel mode. */
/* */
/* INPUT */
/* */
/* None */
/* */
/* OUTPUT */
/* */
/* None */
/* */
/* CALLS */
/* */
/* SVC 1 Enter kernel mode */
/* SVC 2 Exit kernel mode */
/* */
/* CALLED BY */
/* */
/* Modules in user mode */
/* */
/* RELEASE HISTORY */
/* */
/* DESCRIPTION */
/* */
/* This function allows modules to enter kernel mode. */
/* */
/* INPUT */
/* */
/* None */
/* */
/* OUTPUT */
/* */
/* None */
/* */
/* CALLS */
/* */
/* SVC 1 Enter kernel mode */
/* SVC 2 Exit kernel mode */
/* */
/* CALLED BY */
/* */
/* Modules in user mode */
/* */
/* RELEASE HISTORY */
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* 11-09-2020 Scott Larson Modified comment(s), */
/* resulting in version 6.1.2 */
/* 10-15-2021 Scott Larson Initial Version 6.1.9 */
/* */
/**************************************************************************/
// VOID _txm_module_manager_user_mode_entry(VOID)