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Release 6.1.9

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This commit is contained in:
Yuxin Zhou
2021-10-14 00:51:26 +00:00
parent 215df45d4b
commit 1af8404c54
1812 changed files with 60698 additions and 249862 deletions
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21
ports_module/cortex_m7/ac5/inc/tx_port.h
View File

@@ -26,7 +26,7 @@
/* PORT SPECIFIC C INFORMATION RELEASE */
/* */
/* tx_port.h Cortex-M7/AC5 */
/* 6.1.6 */
/* 6.1.9 */
/* */
/* AUTHOR */
/* */
@@ -47,10 +47,7 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */
/* macro definition, */
/* resulting in version 6.1.6 */
/* 10-15-2021 Scott Larson Initial Version 6.1.9 */
/* */
/**************************************************************************/
@@ -142,7 +139,7 @@ typedef unsigned short USHORT;
/* Define the port specific options for the _tx_build_options variable. This variable indicates
how the ThreadX library was built. */
#define TX_PORT_SPECIFIC_BUILD_OPTIONS 0
#define TX_PORT_SPECIFIC_BUILD_OPTIONS (0)
/* Define the in-line initialization constant so that modules with in-line
@@ -344,8 +341,6 @@ void _tx_vfp_access(void);
#endif
/* Define the ThreadX object creation extensions for the remaining objects. */
#define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr)
@@ -386,7 +381,7 @@ ULONG _tx_misra_ipsr_get(VOID);
zero after initialization for Cortex-M ports. */
#ifndef TX_THREAD_SYSTEM_RETURN_CHECK
#define TX_THREAD_SYSTEM_RETURN_CHECK(c) (c) = ((ULONG) _tx_thread_preempt_disable);
#define TX_THREAD_SYSTEM_RETURN_CHECK(c) (c) = ((ULONG) _tx_thread_preempt_disable);
#endif
@@ -452,7 +447,7 @@ unsigned int was_masked;
#endif
/* Define FPU extension for the Cortex-M7. Each is assumed to be called in the context of the executing
/* Define FPU extension for the Cortex-M7. Each is assumed to be called in the context of the executing
thread. These are no longer needed, but are preserved for backward compatibility only. */
void tx_thread_fpu_enable(void);
@@ -463,7 +458,7 @@ void tx_thread_fpu_disable(void);
#ifdef TX_THREAD_INIT
CHAR _tx_version_id[] =
"Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M7/AC5 Version 6.1 *";
"Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M7/AC5 Version 6.1.9 *";
#else
#ifdef TX_MISRA_ENABLE
extern CHAR _tx_version_id[100];
@@ -474,7 +469,3 @@ extern CHAR _tx_version_id[];
#endif

30
ports_module/cortex_m7/ac5/inc/txm_module_port.h
View File

@@ -25,8 +25,8 @@
/* */
/* APPLICATION INTERFACE DEFINITION RELEASE */
/* */
/* txm_module_port.h Cortex-M7/MPU/AC5 */
/* 6.1.7 */
/* txm_module_port.h Cortex-M7/AC5 */
/* 6.1.9 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -40,12 +40,7 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* 11-09-2020 Scott Larson Modified comment(s), */
/* increase kernel stack size, */
/* resulting in version 6.1.2 */
/* 06-02-2021 Scott Larson Added support for 8 MPU, */
/* resulting in version 6.1.7 */
/* 10-15-2021 Scott Larson Initial Version 6.1.9 */
/* */
/**************************************************************************/
@@ -96,11 +91,6 @@ The following extensions must also be defined in tx_port.h:
VOID (*tx_timer_module_expiration_function)(ULONG id);
*/
/* Size of module heap. */
#define TXM_MODULE_HEAP_SIZE 512
/* Define the kernel stack size for a module thread. */
#ifndef TXM_MODULE_KERNEL_STACK_SIZE
#define TXM_MODULE_KERNEL_STACK_SIZE 768
@@ -175,10 +165,10 @@ The following extensions must also be defined in tx_port.h:
#define INLINE_DECLARE inline
#ifndef TXM_MODULE_MANAGER_8_MPU
#ifdef TXM_MODULE_MANAGER_16_MPU
/* Define the number of MPU entries assigned to the code and data sections.
On Cortex-M7 parts, there are 16 total entries. ThreadX uses one for access
On some Cortex-M7 parts, there are 16 total entries. ThreadX uses one for access
to the kernel entry function, thus 15 remain for code and data protection. */
#define TXM_MODULE_MPU_TOTAL_ENTRIES 16
#define TXM_MODULE_MPU_CODE_ENTRIES 4
@@ -208,10 +198,10 @@ typedef struct TXM_MODULE_MPU_INFO_STRUCT
ULONG txm_module_instance_shared_memory_address[TXM_MODULE_MPU_SHARED_ENTRIES]; \
ULONG txm_module_instance_shared_memory_length[TXM_MODULE_MPU_SHARED_ENTRIES];
#else /* TXM_MODULE_MANAGER_8_MPU is defined */
#else /* TXM_MODULE_MANAGER_16_MPU is not defined */
/* Define the number of MPU entries assigned to the code and data sections.
If TXM_MODULE_MANAGER_8_MPU is defined, there are 8 total entries. ThreadX uses one for access
On Cortex-M3, M4, and some M7 parts, there are 8 total entries. ThreadX uses one for access
to the kernel entry function, thus 7 remain for code and data protection. */
#define TXM_MODULE_MANAGER_CODE_MPU_ENTRIES 4
#define TXM_MODULE_MANAGER_DATA_MPU_ENTRIES 3
@@ -229,7 +219,7 @@ typedef struct TXM_MODULE_MPU_INFO_STRUCT
ULONG txm_module_instance_shared_memory_address; \
ULONG txm_module_instance_shared_memory_length;
#endif /* TXM_MODULE_MANAGER_8_MPU */
#endif /* TXM_MODULE_MANAGER_16_MPU */
/* Define the memory fault information structure that is populated when a memory fault occurs. */
@@ -352,7 +342,7 @@ typedef struct TXM_MODULE_MANAGER_MEMORY_FAULT_INFO_STRUCT
/* Define the macros to perform port-specific checks when passing pointers to the kernel. */
/* Define macro to make sure object is inside the module's data. */
#ifndef TXM_MODULE_MANAGER_8_MPU
#ifdef TXM_MODULE_MANAGER_16_MPU
#define TXM_MODULE_MANAGER_CHECK_INSIDE_DATA(module_instance, obj_ptr, obj_size) \
_txm_module_manager_inside_data_check(module_instance, obj_ptr, obj_size)
#else
@@ -386,6 +376,6 @@ UINT _txm_module_manager_inside_data_check(TXM_MODULE_INSTANCE *module_instance
#define TXM_MODULE_MANAGER_VERSION_ID \
CHAR _txm_module_manager_version_id[] = \
"Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M7/MPU/AC5 Version 6.1.7 *";
"Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M7/AC5 Version 6.1.9 *";
#endif

8
ports_module/cortex_m7/ac5/module_lib/src/txm_module_initialize.S → ports_module/cortex_m7/ac5/module_lib/src/txm_module_initialize.s
View File

@@ -29,8 +29,8 @@
/* */
/* FUNCTION RELEASE */
/* */
/* _txm_module_initialize Cortex-M7/MPU/AC5 */
/* 6.1.2 */
/* _txm_module_initialize Cortex-M7/AC5 */
/* 6.1.9 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -59,9 +59,7 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* 11-09-2020 Scott Larson Modified comment(s), */
/* resulting in version 6.1.2 */
/* 10-15-2021 Scott Larson Initial Version 6.1.9 */
/* */
/**************************************************************************/
// VOID _txm_module_initialize(VOID)

15
ports_module/cortex_m7/ac5/module_lib/src/txm_module_thread_shell_entry.c
View File

@@ -44,7 +44,9 @@ TXM_MODULE_THREAD_ENTRY_INFO *_txm_module_entry_info;
ULONG (*_txm_module_kernel_call_dispatcher)(ULONG kernel_request, ULONG param_1, ULONG param_2, ULONG param3);
/* Define the ARM cstartup code. */
/* Define the startup code that clears the uninitialized global data and sets up the
preset global variables. */
extern VOID _txm_module_initialize(VOID);
__align(8) UCHAR txm_heap[TXM_MODULE_HEAP_SIZE];
@@ -53,15 +55,15 @@ __align(8) UCHAR txm_heap[TXM_MODULE_HEAP_SIZE];
/* */
/* FUNCTION RELEASE */
/* */
/* _txm_module_thread_shell_entry Cortex-M7/MPU/AC5 */
/* 6.1 */
/* _txm_module_thread_shell_entry Cortex-M7/AC5 */
/* 6.1.9 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
/* */
/* DESCRIPTION */
/* */
/* This function calls the specified entry function of the thread. It */
/* This function calls the specified entry function of the thread. It */
/* also provides a place for the thread's entry function to return. */
/* If the thread returns, this function places the thread in a */
/* "COMPLETED" state. */
@@ -90,7 +92,7 @@ __align(8) UCHAR txm_heap[TXM_MODULE_HEAP_SIZE];
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* 10-15-2021 Scott Larson Initial Version 6.1.9 */
/* */
/**************************************************************************/
VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_ENTRY_INFO *thread_info)
@@ -105,7 +107,7 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN
execution. If not, simply skip the C startup code. */
if (thread_info -> txm_module_thread_entry_info_start_thread)
{
/* Initialize the ARM C environment. */
/* Initialize the C environment. */
_txm_module_initialize();
/* Save the entry info pointer, for later use. */
@@ -170,4 +172,3 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN
TX_SAFETY_CRITICAL_EXCEPTION(__FILE__, __LINE__, 0);
#endif
}

6
ports_module/cortex_m7/ac5/module_manager/src/tx_thread_context_restore.S → ports_module/cortex_m7/ac5/module_manager/src/tx_thread_context_restore.s
View File

@@ -30,8 +30,8 @@
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_context_restore Cortex-Mx/AC5 */
/* 6.1.8 */
/* _tx_thread_context_restore Cortex-M7/AC5 */
/* 6.1.7 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -61,7 +61,7 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 08-02-2021 Scott Larson Initial Version 6.1.8 */
/* 06-02-2021 Scott Larson Initial Version 6.1.7 */
/* */
/**************************************************************************/
// VOID _tx_thread_context_restore(VOID)

6
ports_module/cortex_m7/ac5/module_manager/src/tx_thread_context_save.S → ports_module/cortex_m7/ac5/module_manager/src/tx_thread_context_save.s
View File

@@ -30,8 +30,8 @@
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_context_save Cortex-Mx/AC5 */
/* 6.1.8 */
/* _tx_thread_context_save Cortex-M7/AC5 */
/* 6.1.7 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -61,7 +61,7 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 08-02-2021 Scott Larson Initial Version 6.1.8 */
/* 06-02-2021 Scott Larson Initial Version 6.1.7 */
/* */
/**************************************************************************/
// VOID _tx_thread_context_save(VOID)

6
ports_module/cortex_m7/ac5/module_manager/src/tx_thread_interrupt_control.S → ports_module/cortex_m7/ac5/module_manager/src/tx_thread_interrupt_control.s
View File

@@ -25,8 +25,8 @@
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_interrupt_control Cortex-Mx/AC5 */
/* 6.1.8 */
/* _tx_thread_interrupt_control Cortex-M7/AC5 */
/* 6.1.7 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -56,7 +56,7 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 08-02-2021 Scott Larson Initial Version 6.1.8 */
/* 06-02-2021 Scott Larson Initial Version 6.1.7 */
/* */
/**************************************************************************/
// UINT _tx_thread_interrupt_control(UINT new_posture)

6
ports_module/cortex_m7/ac5/module_manager/src/tx_thread_interrupt_disable.S → ports_module/cortex_m7/ac5/module_manager/src/tx_thread_interrupt_disable.s
View File

@@ -25,8 +25,8 @@
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_interrupt_disable Cortex-Mx/AC5 */
/* 6.1.8 */
/* _tx_thread_interrupt_disable Cortex-M7/AC5 */
/* 6.1.7 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -56,7 +56,7 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 08-02-2021 Scott Larson Initial Version 6.1.8 */
/* 06-02-2021 Scott Larson Initial Version 6.1.7 */
/* */
/**************************************************************************/
// UINT _tx_thread_interrupt_disable(VOID)

6
ports_module/cortex_m7/ac5/module_manager/src/tx_thread_interrupt_restore.S → ports_module/cortex_m7/ac5/module_manager/src/tx_thread_interrupt_restore.s
View File

@@ -25,8 +25,8 @@
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_interrupt_restore Cortex-Mx/AC5 */
/* 6.1.8 */
/* _tx_thread_interrupt_restore Cortex-M7/AC5 */
/* 6.1.7 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -56,7 +56,7 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 08-02-2021 Scott Larson Initial Version 6.1.8 */
/* 06-02-2021 Scott Larson Initial Version 6.1.7 */
/* */
/**************************************************************************/
// VOID _tx_thread_interrupt_restore(UINT previous_posture)

16
ports_module/cortex_m7/ac5/module_manager/src/tx_thread_schedule.S → ports_module/cortex_m7/ac5/module_manager/src/tx_thread_schedule.s
View File

@@ -39,8 +39,8 @@
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_schedule Cortex-M7/MPU/AC5 */
/* 6.1.7 */
/* _tx_thread_schedule Cortex-M7/AC5 */
/* 6.1.9 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -73,15 +73,7 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* 11-09-2020 Scott Larson Modified comment(s), arrange */
/* code to fix link error when */
/* VFP is enabled, resulting */
/* in version 6.1.2 */
/* 06-02-2021 Scott Larson Fixed extended stack handling */
/* when calling kernel APIs, */
/* added support for 8 MPU, */
/* resulting in version 6.1.7 */
/* 10-15-2021 Scott Larson Initial Version 6.1.9 */
/* */
/**************************************************************************/
// VOID _tx_thread_schedule(VOID)
@@ -360,7 +352,7 @@ __tx_ts_restore
// Use alias registers to quickly load MPU
ADD r0, r0, #100 // Build address of MPU register start in thread control block
#ifndef TXM_MODULE_MANAGER_8_MPU
#ifdef TXM_MODULE_MANAGER_16_MPU
LDM r0!,{r2-r9} // Load MPU regions 0-3
STM r1,{r2-r9} // Store MPU regions 0-3
LDM r0!,{r2-r9} // Load MPU regions 4-7

6
ports_module/cortex_m7/ac5/module_manager/src/tx_thread_stack_build.S → ports_module/cortex_m7/ac5/module_manager/src/tx_thread_stack_build.s
View File

@@ -25,8 +25,8 @@
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_stack_build Cortex-Mx/AC5 */
/* 6.1.8 */
/* _tx_thread_stack_build Cortex-M7/AC5 */
/* 6.1.7 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -58,7 +58,7 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 08-02-2021 Scott Larson Initial Version 6.1.8 */
/* 06-02-2021 Scott Larson Initial Version 6.1.7 */
/* */
/**************************************************************************/
// VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID))

6
ports_module/cortex_m7/ac5/module_manager/src/tx_thread_system_return.S → ports_module/cortex_m7/ac5/module_manager/src/tx_thread_system_return.s
View File

@@ -25,8 +25,8 @@
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_system_return Cortex-Mx/AC5 */
/* 6.1.8 */
/* _tx_thread_system_return Cortex-M7/AC5 */
/* 6.1.7 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -58,7 +58,7 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 08-02-2021 Scott Larson Initial Version 6.1.8 */
/* 06-02-2021 Scott Larson Initial Version 6.1.7 */
/* */
/**************************************************************************/
// VOID _tx_thread_system_return(VOID)

6
ports_module/cortex_m7/ac5/module_manager/src/tx_timer_interrupt.S → ports_module/cortex_m7/ac5/module_manager/src/tx_timer_interrupt.s
View File

@@ -39,8 +39,8 @@
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_timer_interrupt Cortex-Mx/AC5 */
/* 6.1.8 */
/* _tx_timer_interrupt Cortex-M7/AC5 */
/* 6.1.7 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -73,7 +73,7 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 08-02-2021 Scott Larson Initial Version 6.1.8 */
/* 06-02-2021 Scott Larson Initial Version 6.1.7 */
/* */
/**************************************************************************/
// VOID _tx_timer_interrupt(VOID)

16
ports_module/cortex_m7/ac5/module_manager/src/txm_module_manager_alignment_adjust.c
View File

@@ -30,8 +30,8 @@
/* */
/* FUNCTION RELEASE */
/* */
/* _txm_power_of_two_block_size Cortex-M7/MPU/AC5 */
/* 6.1 */
/* _txm_power_of_two_block_size Cortex-M7 */
/* 6.1.9 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -61,7 +61,7 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* 10-15-2021 Scott Larson Initial Version 6.1.9 */
/* */
/**************************************************************************/
ULONG _txm_power_of_two_block_size(ULONG size)
@@ -93,8 +93,8 @@ ULONG _txm_power_of_two_block_size(ULONG size)
/* */
/* FUNCTION RELEASE */
/* */
/* _txm_module_manager_alignment_adjust Cortex-M7/MPU/AC5 */
/* 6.1.7 */
/* _txm_module_manager_alignment_adjust Cortex-M7 */
/* 6.1.9 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -128,9 +128,7 @@ ULONG _txm_power_of_two_block_size(ULONG size)
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* 06-02-2021 Scott Larson Added support for 8 MPU, */
/* resulting in version 6.1.7 */
/* 10-15-2021 Scott Larson Initial Version 6.1.9 */
/* */
/**************************************************************************/
VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble,
@@ -139,7 +137,7 @@ VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble,
ULONG *data_size,
ULONG *data_alignment)
{
#ifndef TXM_MODULE_MANAGER_8_MPU
#ifdef TXM_MODULE_MANAGER_16_MPU
ULONG local_code_size;
ULONG local_code_alignment;
ULONG local_data_size;

11
ports_module/cortex_m7/ac5/module_manager/src/txm_module_manager_external_memory_enable.c
View File

@@ -33,8 +33,8 @@
/* */
/* FUNCTION RELEASE */
/* */
/* _txm_module_manager_external_memory_enable Cortex-M7/MPU/AC5 */
/* 6.1.7 */
/* _txm_module_manager_external_memory_enable Cortex-M7 */
/* 6.1.9 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -60,6 +60,7 @@
/* _tx_mutex_get Get protection mutex */
/* _tx_mutex_put Release protection mutex */
/* _txm_power_of_two_block_size Round length to power of two */
/* _txm_module_manager_mm_register_setup Reconfigure MPU registers */
/* */
/* CALLED BY */
/* */
@@ -69,9 +70,7 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* 06-02-2021 Scott Larson Added support for 8 MPU, */
/* resulting in verison 6.1.7 */
/* 10-15-2021 Scott Larson Initial Version 6.1.9 */
/* */
/**************************************************************************/
UINT _txm_module_manager_external_memory_enable(TXM_MODULE_INSTANCE *module_instance,
@@ -79,7 +78,7 @@ UINT _txm_module_manager_external_memory_enable(TXM_MODULE_INSTANCE *module_ins
ULONG length,
UINT attributes)
{
#ifndef TXM_MODULE_MANAGER_8_MPU
#ifdef TXM_MODULE_MANAGER_16_MPU
ULONG block_size;
ULONG region_size;
ULONG srd_bits;

6
ports_module/cortex_m7/ac5/module_manager/src/txm_module_manager_memory_fault_handler.c
View File

@@ -45,8 +45,8 @@ TXM_MODULE_MANAGER_FAULT_INFO
/* */
/* FUNCTION RELEASE */
/* */
/* _txm_module_manager_memory_fault_handler Cortex-M7/MPU/AC5 */
/* 6.1 */
/* _txm_module_manager_memory_fault_handler Cortex-M7 */
/* 6.1.9 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -76,7 +76,7 @@ TXM_MODULE_MANAGER_FAULT_INFO
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* 10-15-2021 Scott Larson Initial Version 6.1.9 */
/* */
/**************************************************************************/
VOID _txm_module_manager_memory_fault_handler(VOID)

6
ports_module/cortex_m7/ac5/module_manager/src/txm_module_manager_memory_fault_notify.c
View File

@@ -38,8 +38,8 @@ extern VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTA
/* */
/* FUNCTION RELEASE */
/* */
/* _txm_module_manager_memory_fault_notify Cortex-M7/MPU/AC5 */
/* 6.1 */
/* _txm_module_manager_memory_fault_notify Cortex-M7 */
/* 6.1.9 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -71,7 +71,7 @@ extern VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTA
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* 10-15-2021 Scott Larson Initial Version 6.1.9 */
/* */
/**************************************************************************/
UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *))

49
ports_module/cortex_m7/ac5/module_manager/src/txm_module_manager_mm_register_setup.c
View File

@@ -30,8 +30,8 @@
/* */
/* FUNCTION RELEASE */
/* */
/* _txm_module_manager_region_size_get Cortex-M7/MPU/AC5 */
/* 6.1 */
/* _txm_module_manager_region_size_get Cortex-M7 */
/* 6.1.9 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -61,7 +61,7 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* 10-15-2021 Scott Larson Initial Version 6.1.9 */
/* */
/**************************************************************************/
ULONG _txm_module_manager_region_size_get(ULONG block_size)
@@ -152,8 +152,8 @@ ULONG return_value;
/* */
/* FUNCTION RELEASE */
/* */
/* _txm_module_manager_calculate_srd_bits Cortex-M7/MPU/AC5 */
/* 6.1 */
/* _txm_module_manager_calculate_srd_bits Cortex-M7 */
/* 6.1.9 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -184,7 +184,7 @@ ULONG return_value;
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* 10-15-2021 Scott Larson Initial Version 6.1.9 */
/* */
/**************************************************************************/
ULONG _txm_module_manager_calculate_srd_bits(ULONG block_size, ULONG length)
@@ -230,8 +230,8 @@ UINT srd_bit_index;
/* */
/* FUNCTION RELEASE */
/* */
/* _txm_module_manager_mm_register_setup Cortex-M7/MPU/AC5 */
/* 6.1 */
/* _txm_module_manager_mm_register_setup Cortex-M7 */
/* 6.1.9 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -240,6 +240,19 @@ UINT srd_bit_index;
/* */
/* This function sets up the MPU register definitions based on the */
/* module's memory characteristics. */
/* */
/* Default MPU layout: */
/* Entry Description */
/* 0 Kernel mode entry */
/* 1 Module code region */
/* 2 Module code region */
/* 3 Module code region */
/* 4 Module code region */
/* 5 Module data region */
/* 6 Module data region */
/* 7 Module data region */
/* */
/* If TXM_MODULE_MANAGER_16_MPU is defined, there are 16 MPU slots. */
/* MPU layout for the Cortex-M7: */
/* Entry Description */
/* 0 Kernel mode entry */
@@ -259,7 +272,6 @@ UINT srd_bit_index;
/* 14 Unused region */
/* 15 Unused region */
/* */
/* If TXM_MODULE_MANAGER_8_MPU is defined, there are only 8 MPU slots. */
/* */
/* INPUT */
/* */
@@ -281,14 +293,12 @@ UINT srd_bit_index;
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* 06-02-2021 Scott Larson Added support for 8 MPU, */
/* resulting in version 6.1.7 */
/* 10-15-2021 Scott Larson Initial Version 6.1.9 */
/* */
/**************************************************************************/
VOID _txm_module_manager_mm_register_setup(TXM_MODULE_INSTANCE *module_instance)
{
#ifndef TXM_MODULE_MANAGER_8_MPU
#ifdef TXM_MODULE_MANAGER_16_MPU
ULONG code_address;
ULONG code_size;
@@ -574,7 +584,7 @@ UINT i;
for (i = 0; i < TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1; i++)
{
/* Build the base address register. */
base_address_register = code_address & ~(block_size - 1) | mpu_register | 0x10;
base_address_register = (code_address & ~(block_size - 1)) | mpu_register | 0x10;
/* Check if SRD bits need to be set. */
if (code_size < block_size)
@@ -705,13 +715,13 @@ UINT i;
#endif
}
#ifndef TXM_MODULE_MANAGER_8_MPU
#ifdef TXM_MODULE_MANAGER_16_MPU
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _txm_module_manager_inside_data_check Cortex-M7/MPU/AC5 */
/* 6.1.6 */
/* _txm_module_manager_inside_data_check Cortex-M7 */
/* 6.1.9 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -743,10 +753,7 @@ UINT i;
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* 04-02-2021 Scott Larson Modified comments, added */
/* check for overflow, */
/* resulting in version 6.1.6 */
/* 10-15-2021 Scott Larson Initial Version 6.1.9 */
/* */
/**************************************************************************/
UINT _txm_module_manager_inside_data_check(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE obj_ptr, UINT obj_size)

10
ports_module/cortex_m7/ac5/module_manager/src/txm_module_manager_thread_stack_build.S → ports_module/cortex_m7/ac5/module_manager/src/txm_module_manager_thread_stack_build.s
View File

@@ -26,8 +26,8 @@
/* */
/* FUNCTION RELEASE */
/* */
/* _txm_module_manager_thread_stack_build Cortex-M7/MPU/AC5 */
/* 6.1.2 */
/* _txm_module_manager_thread_stack_build Cortex-M7/AC5 */
/* 6.1.9 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -59,9 +59,7 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* 11-09-2020 Scott Larson Modified comment(s), */
/* resulting in version 6.1.2 */
/* 10-15-2021 Scott Larson Initial Version 6.1.9 */
/* */
/**************************************************************************/
// VOID _txm_module_manager_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(TX_THREAD *, TXM_MODULE_INSTANCE *))
@@ -73,7 +71,7 @@ _txm_module_manager_thread_stack_build
on the Cortex-M should look like the following after it is built:
Stack Top:
LR Interrupted LR (LR at time of PENDSV)
lr Interrupted lr (lr at time of PENDSV)
r4 Initial value for r4
r5 Initial value for r5
r6 Initial value for r6

80
ports_module/cortex_m7/ac5/module_manager/src/txm_module_manager_user_mode_entry.S → ports_module/cortex_m7/ac5/module_manager/src/txm_module_manager_user_mode_entry.s
View File

@@ -10,59 +10,57 @@
/**************************************************************************/
/**************************************************************************/
/**************************************************************************/
/** */
/** ThreadX Component */
/** */
/** Module Manager */
/** */
/**************************************************************************/
/**************************************************************************/
/**************************************************************************/
/**************************************************************************/
/** */
/** ThreadX Component */
/** */
/** Module Manager */
/** */
/**************************************************************************/
/**************************************************************************/
IMPORT _txm_module_manager_kernel_dispatch
IMPORT _tx_thread_current_ptr
AREA ||.text||, CODE, READONLY, ALIGN=5
THUMB
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _txm_module_manager_user_mode_entry Cortex-M7/MPU/AC5 */
/* 6.1.2 */
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _txm_module_manager_user_mode_entry Cortex-M7/AC5 */
/* 6.1.9 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
/* */
/* DESCRIPTION */
/* */
/* This function allows modules to enter kernel mode. */
/* */
/* INPUT */
/* */
/* None */
/* */
/* OUTPUT */
/* */
/* None */
/* */
/* CALLS */
/* */
/* SVC 1 Enter kernel mode */
/* SVC 2 Exit kernel mode */
/* */
/* CALLED BY */
/* */
/* Modules in user mode */
/* */
/* RELEASE HISTORY */
/* */
/* DESCRIPTION */
/* */
/* This function allows modules to enter kernel mode. */
/* */
/* INPUT */
/* */
/* None */
/* */
/* OUTPUT */
/* */
/* None */
/* */
/* CALLS */
/* */
/* SVC 1 Enter kernel mode */
/* SVC 2 Exit kernel mode */
/* */
/* CALLED BY */
/* */
/* Modules in user mode */
/* */
/* RELEASE HISTORY */
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* 11-09-2020 Scott Larson Modified comment(s), */
/* resulting in version 6.1.2 */
/* 10-15-2021 Scott Larson Initial Version 6.1.9 */
/* */
/**************************************************************************/
// VOID _txm_module_manager_user_mode_entry(VOID)

12
ports_module/cortex_m7/ac6/inc/tx_port.h
View File

@@ -26,7 +26,7 @@
/* PORT SPECIFIC C INFORMATION RELEASE */
/* */
/* tx_port.h Cortex-M7/AC6 */
/* 6.1 */
/* 6.1.9 */
/* */
/* AUTHOR */
/* */
@@ -47,10 +47,7 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */
/* macro definition, */
/* resulting in version 6.1.6 */
/* 10-15-2021 Scott Larson Initial Version 6.1.9 */
/* */
/**************************************************************************/
@@ -142,7 +139,7 @@ typedef unsigned short USHORT;
/* Define the port specific options for the _tx_build_options variable. This variable indicates
how the ThreadX library was built. */
#define TX_PORT_SPECIFIC_BUILD_OPTIONS 0
#define TX_PORT_SPECIFIC_BUILD_OPTIONS (0)
/* Define the in-line initialization constant so that modules with in-line
@@ -405,6 +402,7 @@ ULONG _tx_misra_ipsr_get(VOID);
#define TX_THREAD_SYSTEM_RETURN_CHECK(c) (c) = ((ULONG) _tx_thread_preempt_disable);
#endif
/* Define the macro to ensure _tx_thread_preempt_disable is set early in initialization in order to
prevent early scheduling on Cortex-M parts. */
@@ -510,7 +508,7 @@ void tx_thread_fpu_disable(void);
#ifdef TX_THREAD_INIT
CHAR _tx_version_id[] =
"Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M7/AC6 Version 6.1.6 *";
"Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M7/AC6 Version 6.1.9 *";
#else
extern CHAR _tx_version_id[];
#endif

24
ports_module/cortex_m7/ac6/inc/txm_module_port.h
View File

@@ -25,8 +25,8 @@
/* */
/* APPLICATION INTERFACE DEFINITION RELEASE */
/* */
/* txm_module_port.h Cortex-M7/MPU/AC6 */
/* 6.1.7 */
/* txm_module_port.h Cortex-M7/AC6 */
/* 6.1.9 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -40,11 +40,7 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* 11-09-2020 Scott Larson Modified comment(s), */
/* resulting in version 6.1.2 */
/* 06-02-2021 Scott Larson Added support for 8 MPU, */
/* resulting in version 6.1.7 */
/* 10-15-2021 Scott Larson Initial Version 6.1.9 */
/* */
/**************************************************************************/
@@ -169,10 +165,10 @@ The following extensions must also be defined in tx_port.h:
#define INLINE_DECLARE inline
#ifndef TXM_MODULE_MANAGER_8_MPU
#ifdef TXM_MODULE_MANAGER_16_MPU
/* Define the number of MPU entries assigned to the code and data sections.
On Cortex-M7 parts, there are 16 total entries. ThreadX uses one for access
On some Cortex-M7 parts, there are 16 total entries. ThreadX uses one for access
to the kernel entry function, thus 15 remain for code and data protection. */
#define TXM_MODULE_MPU_TOTAL_ENTRIES 16
#define TXM_MODULE_MPU_CODE_ENTRIES 4
@@ -202,10 +198,10 @@ typedef struct TXM_MODULE_MPU_INFO_STRUCT
ULONG txm_module_instance_shared_memory_address[TXM_MODULE_MPU_SHARED_ENTRIES]; \
ULONG txm_module_instance_shared_memory_length[TXM_MODULE_MPU_SHARED_ENTRIES];
#else /* TXM_MODULE_MANAGER_8_MPU is defined */
#else /* TXM_MODULE_MANAGER_16_MPU is not defined */
/* Define the number of MPU entries assigned to the code and data sections.
On Cortex-M4 parts, there are 8 total entries. ThreadX uses one for access
On Cortex-M3, M4, and some M7 parts, there are 8 total entries. ThreadX uses one for access
to the kernel entry function, thus 7 remain for code and data protection. */
#define TXM_MODULE_MANAGER_CODE_MPU_ENTRIES 4
#define TXM_MODULE_MANAGER_DATA_MPU_ENTRIES 3
@@ -223,7 +219,7 @@ typedef struct TXM_MODULE_MPU_INFO_STRUCT
ULONG txm_module_instance_shared_memory_address; \
ULONG txm_module_instance_shared_memory_length;
#endif /* TXM_MODULE_MANAGER_8_MPU */
#endif /* TXM_MODULE_MANAGER_16_MPU */
/* Define the memory fault information structure that is populated when a memory fault occurs. */
@@ -346,7 +342,7 @@ typedef struct TXM_MODULE_MANAGER_MEMORY_FAULT_INFO_STRUCT
/* Define the macros to perform port-specific checks when passing pointers to the kernel. */
/* Define macro to make sure object is inside the module's data. */
#ifndef TXM_MODULE_MANAGER_8_MPU
#ifdef TXM_MODULE_MANAGER_16_MPU
#define TXM_MODULE_MANAGER_CHECK_INSIDE_DATA(module_instance, obj_ptr, obj_size) \
_txm_module_manager_inside_data_check(module_instance, obj_ptr, obj_size)
#else
@@ -380,6 +376,6 @@ UINT _txm_module_manager_inside_data_check(TXM_MODULE_INSTANCE *module_instance
#define TXM_MODULE_MANAGER_VERSION_ID \
CHAR _txm_module_manager_version_id[] = \
"Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M7/MPU/AC6 Version 6.1.7 *";
"Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M7/AC6 Version 6.1.9 *";
#endif

8
ports_module/cortex_m7/ac6/module_lib/src/txm_module_initialize.S
View File

@@ -32,8 +32,8 @@
/* */
/* FUNCTION RELEASE */
/* */
/* _txm_module_initialize Cortex-M7/MPU/AC6 */
/* 6.1.2 */
/* _txm_module_initialize Cortex-M7/AC6 */
/* 6.1.9 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -62,9 +62,7 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Andres Mlinar Initial Version 6.1 */
/* 11-09-2020 Scott Larson Modified comment(s), */
/* resulting in version 6.1.2 */
/* 10-15-2021 Scott Larson Initial Version 6.1.9 */
/* */
/**************************************************************************/
// VOID _txm_module_initialize(VOID)

15
ports_module/cortex_m7/ac6/module_lib/src/txm_module_thread_shell_entry.c
View File

@@ -44,7 +44,9 @@ TXM_MODULE_THREAD_ENTRY_INFO *_txm_module_entry_info;
ULONG (*_txm_module_kernel_call_dispatcher)(ULONG kernel_request, ULONG param_1, ULONG param_2, ULONG param3);
/* Define the ARM cstartup code. */
/* Define the startup code that clears the uninitialized global data and sets up the
preset global variables. */
extern VOID _txm_module_initialize(VOID);
@@ -52,15 +54,15 @@ extern VOID _txm_module_initialize(VOID);
/* */
/* FUNCTION RELEASE */
/* */
/* _txm_module_thread_shell_entry Cortex-M7/MPU/AC6 */
/* 6.1 */
/* _txm_module_thread_shell_entry Cortex-M7/AC6 */
/* 6.1.9 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
/* */
/* DESCRIPTION */
/* */
/* This function calls the specified entry function of the thread. It */
/* This function calls the specified entry function of the thread. It */
/* also provides a place for the thread's entry function to return. */
/* If the thread returns, this function places the thread in a */
/* "COMPLETED" state. */
@@ -89,7 +91,7 @@ extern VOID _txm_module_initialize(VOID);
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* 10-15-2021 Scott Larson Initial Version 6.1.9 */
/* */
/**************************************************************************/
VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_ENTRY_INFO *thread_info)
@@ -104,7 +106,7 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN
execution. If not, simply skip the C startup code. */
if (thread_info -> txm_module_thread_entry_info_start_thread)
{
/* Initialize the ARM C environment. */
/* Initialize the C environment. */
_txm_module_initialize();
/* Save the entry info pointer, for later use. */
@@ -169,4 +171,3 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN
TX_SAFETY_CRITICAL_EXCEPTION(__FILE__, __LINE__, 0);
#endif
}

6
ports_module/cortex_m7/ac6/module_manager/src/tx_thread_context_restore.S
View File

@@ -31,8 +31,8 @@
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_context_restore Cortex-Mx/AC6 */
/* 6.1.8 */
/* _tx_thread_context_restore Cortex-M7/AC6 */
/* 6.1.7 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -62,7 +62,7 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 08-02-2021 Scott Larson Initial Version 6.1.8 */
/* 06-02-2021 Scott Larson Initial Version 6.1.7 */
/* */
/**************************************************************************/
// VOID _tx_thread_context_restore(VOID)

6
ports_module/cortex_m7/ac6/module_manager/src/tx_thread_context_save.S
View File

@@ -30,8 +30,8 @@
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_context_save Cortex-Mx/AC6 */
/* 6.1.8 */
/* _tx_thread_context_save Cortex-M7/AC6 */
/* 6.1.7 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -61,7 +61,7 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 08-02-2021 Scott Larson Initial Version 6.1.8 */
/* 06-02-2021 Scott Larson Initial Version 6.1.7 */
/* */
/**************************************************************************/
// VOID _tx_thread_context_save(VOID)

6
ports_module/cortex_m7/ac6/module_manager/src/tx_thread_interrupt_control.S
View File

@@ -27,8 +27,8 @@
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_interrupt_control Cortex-Mx/AC6 */
/* 6.1.8 */
/* _tx_thread_interrupt_control Cortex-M7/AC6 */
/* 6.1.7 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -58,7 +58,7 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 08-02-2021 Scott Larson Initial Version 6.1.8 */
/* 06-02-2021 Scott Larson Initial Version 6.1.7 */
/* */
/**************************************************************************/
// UINT _tx_thread_interrupt_control(UINT new_posture)

79
ports_module/cortex_m7/ac6/module_manager/src/tx_thread_interrupt_disable.S Normal file
View File

@@ -0,0 +1,79 @@
/**************************************************************************/
/* */
/* Copyright (c) Microsoft Corporation. All rights reserved. */
/* */
/* This software is licensed under the Microsoft Software License */
/* Terms for Microsoft Azure RTOS. Full text of the license can be */
/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
/* and in the root directory of this software. */
/* */
/**************************************************************************/
/**************************************************************************/
/**************************************************************************/
/** */
/** ThreadX Component */
/** */
/** Thread */
/** */
/**************************************************************************/
/**************************************************************************/
.text 32
.align 4
.syntax unified
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_interrupt_disable Cortex-M7/AC6 */
/* 6.1.7 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
/* */
/* DESCRIPTION */
/* */
/* This function is responsible for disabling interrupts and returning */
/* the previous interrupt lockout posture. */
/* */
/* INPUT */
/* */
/* None */
/* */
/* OUTPUT */
/* */
/* old_posture Old interrupt lockout posture */
/* */
/* CALLS */
/* */
/* None */
/* */
/* CALLED BY */
/* */
/* Application Code */
/* */
/* RELEASE HISTORY */
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 06-02-2021 Scott Larson Initial Version 6.1.7 */
/* */
/**************************************************************************/
// UINT _tx_thread_interrupt_disable(VOID)
// {
.global _tx_thread_interrupt_disable
.thumb_func
_tx_thread_interrupt_disable:
/* Return current interrupt lockout posture. */
#ifdef TX_PORT_USE_BASEPRI
MRS r0, BASEPRI
LDR r1, =TX_PORT_BASEPRI
MSR BASEPRI, r1
#else
MRS r0, PRIMASK
CPSID i
#endif
BX lr
// }

76
ports_module/cortex_m7/ac6/module_manager/src/tx_thread_interrupt_restore.S Normal file
View File

@@ -0,0 +1,76 @@
/**************************************************************************/
/* */
/* Copyright (c) Microsoft Corporation. All rights reserved. */
/* */
/* This software is licensed under the Microsoft Software License */
/* Terms for Microsoft Azure RTOS. Full text of the license can be */
/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
/* and in the root directory of this software. */
/* */
/**************************************************************************/
/**************************************************************************/
/**************************************************************************/
/** */
/** ThreadX Component */
/** */
/** Thread */
/** */
/**************************************************************************/
/**************************************************************************/
.text 32
.align 4
.syntax unified
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_interrupt_restore Cortex-M7/AC6 */
/* 6.1.7 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
/* */
/* DESCRIPTION */
/* */
/* This function is responsible for restoring the previous */
/* interrupt lockout posture. */
/* */
/* INPUT */
/* */
/* previous_posture Previous interrupt posture */
/* */
/* OUTPUT */
/* */
/* None */
/* */
/* CALLS */
/* */
/* None */
/* */
/* CALLED BY */
/* */
/* Application Code */
/* */
/* RELEASE HISTORY */
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 06-02-2021 Scott Larson Initial Version 6.1.7 */
/* */
/**************************************************************************/
// VOID _tx_thread_interrupt_restore(UINT previous_posture)
// {
.global _tx_thread_interrupt_restore
.thumb_func
_tx_thread_interrupt_restore:
/* Restore previous interrupt lockout posture. */
#ifdef TX_PORT_USE_BASEPRI
MSR BASEPRI, r0
#else
MSR PRIMASK, r0
#endif
BX lr
// }

27
ports_module/cortex_m7/ac6/module_manager/src/tx_thread_schedule.S
View File

@@ -41,8 +41,8 @@
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_schedule Cortex-M7/MPU/AC6 */
/* 6.1.7 */
/* _tx_thread_schedule Cortex-M7/AC6 */
/* 6.1.9 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -75,15 +75,7 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* 11-09-2020 Scott Larson Modified comment(s), arrange */
/* code to fix link error when */
/* VFP is enabled, resulting */
/* in version 6.1.2 */
/* 06-02-2021 Scott Larson Fixed extended stack handling */
/* when calling kernel APIs, */
/* added support for 8 MPU, */
/* resulting in version 6.1.7 */
/* 10-15-2021 Scott Larson Initial Version 6.1.9 */
/* */
/**************************************************************************/
// VOID _tx_thread_schedule(VOID)
@@ -110,7 +102,6 @@ _tx_thread_schedule:
#endif
/* Enable memory fault registers. */
LDR r0, =0xE000ED24 // Build SHCSR address
LDR r1, =0x70000 // Enable Usage, Bus, and MemManage faults
STR r1, [r0] //
@@ -374,7 +365,7 @@ __tx_ts_restore:
// Use alias registers to quickly load MPU
ADD r0, r0, #100 // Build address of MPU register start in thread control block
#ifndef TXM_MODULE_MANAGER_8_MPU
#ifdef TXM_MODULE_MANAGER_16_MPU
LDM r0!,{r2-r9} // Load MPU regions 0-3
STM r1,{r2-r9} // Store MPU regions 0-3
LDM r0!,{r2-r9} // Load MPU regions 4-7
@@ -458,13 +449,17 @@ __tx_SVCallHandler:
#endif
MRS r3, PSP // Pickup thread stack pointer
#ifdef __ARM_FP
TST lr, #0x10 // Test for extended module stack
ITT EQ
ORREQ r3, r3, #1 // If so, set LSB in thread stack pointer to indicate extended frame
ORREQ lr, lr, #0x10 // Set bit, return with standard frame
#endif
STR r3, [r2, #0xB0] // Save thread stack pointer
#ifdef __ARM_FP
BIC r3, #1 // Clear possibly OR'd bit
#endif
/* Build kernel stack by copying thread stack two registers at a time */
ADD r3, r3, #32 // Start at bottom of hardware stack
LDMDB r3!, {r1-r2}
@@ -534,11 +529,13 @@ _tx_no_lazy_clear:
LDR r0, [r2, #0xB0] // Load the module thread stack pointer
MRS r3, PSP // Pickup kernel stack pointer
#ifdef __ARM_FP
TST r0, #1 // Is module stack extended?
ITTE NE // If so...
BICNE lr, #0x10 // Clear bit, return with extended frame
BICNE r0, #1 // Clear bit that indicates extended module frame
ORREQ lr, lr, #0x10 // Else set bit, return with standard frame
#endif
/* Copy kernel hardware stack to module thread stack. */
LDM r3!, {r1-r2}
@@ -563,7 +560,7 @@ _tx_skip_kernel_stack_exit:
BX lr // Return to thread
/* Kernel entry function from user mode. */
/* Kernel entry function from user mode. */
.global _txm_module_manager_kernel_dispatch
.align 5

6
ports_module/cortex_m7/ac6/module_manager/src/tx_thread_stack_build.S
View File

@@ -27,8 +27,8 @@
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_stack_build Cortex-Mx/AC6 */
/* 6.1.8 */
/* _tx_thread_stack_build Cortex-M7/AC6 */
/* 6.1.7 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -60,7 +60,7 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 08-02-2021 Scott Larson Initial Version 6.1.8 */
/* 06-02-2021 Scott Larson Initial Version 6.1.7 */
/* */
/**************************************************************************/
// VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID))

6
ports_module/cortex_m7/ac6/module_manager/src/tx_thread_system_return.S
View File

@@ -27,8 +27,8 @@
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_system_return Cortex-Mx/AC6 */
/* 6.1.8 */
/* _tx_thread_system_return Cortex-M7/AC6 */
/* 6.1.7 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -60,7 +60,7 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 08-02-2021 Scott Larson Initial Version 6.1.8 */
/* 06-02-2021 Scott Larson Initial Version 6.1.7 */
/* */
/**************************************************************************/
// VOID _tx_thread_system_return(VOID)

6
ports_module/cortex_m7/ac6/module_manager/src/tx_timer_interrupt.S
View File

@@ -37,8 +37,8 @@
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_timer_interrupt Cortex-Mx/AC6 */
/* 6.1.8 */
/* _tx_timer_interrupt Cortex-M7/AC6 */
/* 6.1.7 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -71,7 +71,7 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 08-02-2021 Scott Larson Initial Version 6.1.8 */
/* 06-02-2021 Scott Larson Initial Version 6.1.7 */
/* */
/**************************************************************************/
// VOID _tx_timer_interrupt(VOID)

16
ports_module/cortex_m7/ac6/module_manager/src/txm_module_manager_alignment_adjust.c
View File

@@ -30,8 +30,8 @@
/* */
/* FUNCTION RELEASE */
/* */
/* _txm_power_of_two_block_size Cortex-M7/MPU/AC6 */
/* 6.1 */
/* _txm_power_of_two_block_size Cortex-M7 */
/* 6.1.9 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -61,7 +61,7 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* 10-15-2021 Scott Larson Initial Version 6.1.9 */
/* */
/**************************************************************************/
ULONG _txm_power_of_two_block_size(ULONG size)
@@ -93,8 +93,8 @@ ULONG _txm_power_of_two_block_size(ULONG size)
/* */
/* FUNCTION RELEASE */
/* */
/* _txm_module_manager_alignment_adjust Cortex-M7/MPU/AC6 */
/* 6.1.7 */
/* _txm_module_manager_alignment_adjust Cortex-M7 */
/* 6.1.9 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -128,9 +128,7 @@ ULONG _txm_power_of_two_block_size(ULONG size)
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* 06-02-2021 Scott Larson Added support for 8 MPU, */
/* resulting in version 6.1.7 */
/* 10-15-2021 Scott Larson Initial Version 6.1.9 */
/* */
/**************************************************************************/
VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble,
@@ -139,7 +137,7 @@ VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble,
ULONG *data_size,
ULONG *data_alignment)
{
#ifndef TXM_MODULE_MANAGER_8_MPU
#ifdef TXM_MODULE_MANAGER_16_MPU
ULONG local_code_size;
ULONG local_code_alignment;
ULONG local_data_size;

11
ports_module/cortex_m7/ac6/module_manager/src/txm_module_manager_external_memory_enable.c
View File

@@ -33,8 +33,8 @@
/* */
/* FUNCTION RELEASE */
/* */
/* _txm_module_manager_external_memory_enable Cortex-M7/MPU/AC6 */
/* 6.1.7 */
/* _txm_module_manager_external_memory_enable Cortex-M7 */
/* 6.1.9 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -60,6 +60,7 @@
/* _tx_mutex_get Get protection mutex */
/* _tx_mutex_put Release protection mutex */
/* _txm_power_of_two_block_size Round length to power of two */
/* _txm_module_manager_mm_register_setup Reconfigure MPU registers */
/* */
/* CALLED BY */
/* */
@@ -69,9 +70,7 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* 06-02-2021 Scott Larson Added support for 8 MPU, */
/* resulting in verison 6.1.7 */
/* 10-15-2021 Scott Larson Initial Version 6.1.9 */
/* */
/**************************************************************************/
UINT _txm_module_manager_external_memory_enable(TXM_MODULE_INSTANCE *module_instance,
@@ -79,7 +78,7 @@ UINT _txm_module_manager_external_memory_enable(TXM_MODULE_INSTANCE *module_ins
ULONG length,
UINT attributes)
{
#ifndef TXM_MODULE_MANAGER_8_MPU
#ifdef TXM_MODULE_MANAGER_16_MPU
ULONG block_size;
ULONG region_size;
ULONG srd_bits;

6
ports_module/cortex_m7/ac6/module_manager/src/txm_module_manager_memory_fault_handler.c
View File

@@ -45,8 +45,8 @@ TXM_MODULE_MANAGER_FAULT_INFO
/* */
/* FUNCTION RELEASE */
/* */
/* _txm_module_manager_memory_fault_handler Cortex-M7/MPU/AC6 */
/* 6.1 */
/* _txm_module_manager_memory_fault_handler Cortex-M7 */
/* 6.1.9 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -76,7 +76,7 @@ TXM_MODULE_MANAGER_FAULT_INFO
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* 10-15-2021 Scott Larson Initial Version 6.1.9 */
/* */
/**************************************************************************/
VOID _txm_module_manager_memory_fault_handler(VOID)

6
ports_module/cortex_m7/ac6/module_manager/src/txm_module_manager_memory_fault_notify.c
View File

@@ -38,8 +38,8 @@ extern VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTA
/* */
/* FUNCTION RELEASE */
/* */
/* _txm_module_manager_memory_fault_notify Cortex-M7/MPU/AC6 */
/* 6.1 */
/* _txm_module_manager_memory_fault_notify Cortex-M7 */
/* 6.1.9 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -71,7 +71,7 @@ extern VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTA
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* 10-15-2021 Scott Larson Initial Version 6.1.9 */
/* */
/**************************************************************************/
UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *))

49
ports_module/cortex_m7/ac6/module_manager/src/txm_module_manager_mm_register_setup.c
View File

@@ -30,8 +30,8 @@
/* */
/* FUNCTION RELEASE */
/* */
/* _txm_module_manager_region_size_get Cortex-M7/MPU/AC6 */
/* 6.1 */
/* _txm_module_manager_region_size_get Cortex-M7 */
/* 6.1.9 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -61,7 +61,7 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* 10-15-2021 Scott Larson Initial Version 6.1.9 */
/* */
/**************************************************************************/
ULONG _txm_module_manager_region_size_get(ULONG block_size)
@@ -152,8 +152,8 @@ ULONG return_value;
/* */
/* FUNCTION RELEASE */
/* */
/* _txm_module_manager_calculate_srd_bits Cortex-M7/MPU/AC6 */
/* 6.1 */
/* _txm_module_manager_calculate_srd_bits Cortex-M7 */
/* 6.1.9 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -184,7 +184,7 @@ ULONG return_value;
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* 10-15-2021 Scott Larson Initial Version 6.1.9 */
/* */
/**************************************************************************/
ULONG _txm_module_manager_calculate_srd_bits(ULONG block_size, ULONG length)
@@ -230,8 +230,8 @@ UINT srd_bit_index;
/* */
/* FUNCTION RELEASE */
/* */
/* _txm_module_manager_mm_register_setup Cortex-M7/MPU/AC6 */
/* 6.1.7 */
/* _txm_module_manager_mm_register_setup Cortex-M7 */
/* 6.1.9 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -240,6 +240,19 @@ UINT srd_bit_index;
/* */
/* This function sets up the MPU register definitions based on the */
/* module's memory characteristics. */
/* */
/* Default MPU layout: */
/* Entry Description */
/* 0 Kernel mode entry */
/* 1 Module code region */
/* 2 Module code region */
/* 3 Module code region */
/* 4 Module code region */
/* 5 Module data region */
/* 6 Module data region */
/* 7 Module data region */
/* */
/* If TXM_MODULE_MANAGER_16_MPU is defined, there are 16 MPU slots. */
/* MPU layout for the Cortex-M7: */
/* Entry Description */
/* 0 Kernel mode entry */
@@ -259,7 +272,6 @@ UINT srd_bit_index;
/* 14 Unused region */
/* 15 Unused region */
/* */
/* If TXM_MODULE_MANAGER_8_MPU is defined, there are only 8 MPU slots. */
/* */
/* INPUT */
/* */
@@ -281,14 +293,12 @@ UINT srd_bit_index;
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* 06-02-2021 Scott Larson Added support for 8 MPU, */
/* resulting in version 6.1.7 */
/* 10-15-2021 Scott Larson Initial Version 6.1.9 */
/* */
/**************************************************************************/
VOID _txm_module_manager_mm_register_setup(TXM_MODULE_INSTANCE *module_instance)
{
#ifndef TXM_MODULE_MANAGER_8_MPU
#ifdef TXM_MODULE_MANAGER_16_MPU
ULONG code_address;
ULONG code_size;
@@ -574,7 +584,7 @@ UINT i;
for (i = 0; i < TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1; i++)
{
/* Build the base address register. */
base_address_register = code_address & ~(block_size - 1) | mpu_register | 0x10;
base_address_register = (code_address & ~(block_size - 1)) | mpu_register | 0x10;
/* Check if SRD bits need to be set. */
if (code_size < block_size)
@@ -705,13 +715,13 @@ UINT i;
#endif
}
#ifndef TXM_MODULE_MANAGER_8_MPU
#ifdef TXM_MODULE_MANAGER_16_MPU
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _txm_module_manager_inside_data_check Cortex-M7/MPU/AC6 */
/* 6.1.6 */
/* _txm_module_manager_inside_data_check Cortex-M7 */
/* 6.1.9 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -743,10 +753,7 @@ UINT i;
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* 04-02-2021 Scott Larson Modified comments, added */
/* check for overflow, */
/* resulting in version 6.1.6 */
/* 10-15-2021 Scott Larson Initial Version 6.1.9 */
/* */
/**************************************************************************/
UINT _txm_module_manager_inside_data_check(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE obj_ptr, UINT obj_size)

10
ports_module/cortex_m7/ac6/module_manager/src/txm_module_manager_thread_stack_build.S
View File

@@ -27,8 +27,8 @@
/* */
/* FUNCTION RELEASE */
/* */
/* _txm_module_manager_thread_stack_build Cortex-M7/MPU/AC6 */
/* 6.1.2 */
/* _txm_module_manager_thread_stack_build Cortex-M7/AC6 */
/* 6.1.9 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -60,9 +60,7 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* 11-09-2020 Scott Larson Modified comment(s), */
/* resulting in version 6.1.2 */
/* 10-15-2021 Scott Larson Initial Version 6.1.9 */
/* */
/**************************************************************************/
// VOID _txm_module_manager_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(TX_THREAD *, TXM_MODULE_INSTANCE *))
@@ -112,7 +110,7 @@ _txm_module_manager_thread_stack_build:
STR r3, [r2, #28] // Store initial r10
STR r3, [r2, #32] // Store initial r11
/* Hardware stack follows. */
/* Hardware stack follows. */
STR r0, [r2, #36] // Store initial r0, which is the thread control block

17
ports_module/cortex_m7/gnu/inc/tx_port.h
View File

@@ -26,7 +26,7 @@
/* PORT SPECIFIC C INFORMATION RELEASE */
/* */
/* tx_port.h Cortex-M7/GNU */
/* 6.1 */
/* 6.1.9 */
/* */
/* AUTHOR */
/* */
@@ -47,10 +47,7 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */
/* macro definition, */
/* resulting in version 6.1.6 */
/* 10-15-2021 Scott Larson Initial Version 6.1.9 */
/* */
/**************************************************************************/
@@ -142,7 +139,7 @@ typedef unsigned short USHORT;
/* Define the port specific options for the _tx_build_options variable. This variable indicates
how the ThreadX library was built. */
#define TX_PORT_SPECIFIC_BUILD_OPTIONS 0
#define TX_PORT_SPECIFIC_BUILD_OPTIONS (0)
/* Define the in-line initialization constant so that modules with in-line
@@ -405,6 +402,7 @@ ULONG _tx_misra_ipsr_get(VOID);
#define TX_THREAD_SYSTEM_RETURN_CHECK(c) (c) = ((ULONG) _tx_thread_preempt_disable);
#endif
/* Define the macro to ensure _tx_thread_preempt_disable is set early in initialization in order to
prevent early scheduling on Cortex-M parts. */
@@ -504,15 +502,10 @@ void tx_thread_fpu_disable(void);
#ifdef TX_THREAD_INIT
CHAR _tx_version_id[] =
"Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M7/GNU Version 6.1.6 *";
"Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M7/GNU Version 6.1.9 *";
#else
extern CHAR _tx_version_id[];
#endif
#endif

24
ports_module/cortex_m7/gnu/inc/txm_module_port.h
View File

@@ -25,8 +25,8 @@
/* */
/* APPLICATION INTERFACE DEFINITION RELEASE */
/* */
/* txm_module_port.h Cortex-M7/MPU/GNU */
/* 6.1.7 */
/* txm_module_port.h Cortex-M7/GNU */
/* 6.1.9 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -40,11 +40,7 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* 11-09-2020 Scott Larson Modified comment(s), */
/* resulting in version 6.1.2 */
/* 06-02-2021 Scott Larson Added support for 8 MPU, */
/* resulting in version 6.1.7 */
/* 10-15-2021 Scott Larson Initial Version 6.1.9 */
/* */
/**************************************************************************/
@@ -169,10 +165,10 @@ The following extensions must also be defined in tx_port.h:
#define INLINE_DECLARE inline
#ifndef TXM_MODULE_MANAGER_8_MPU
#ifdef TXM_MODULE_MANAGER_16_MPU
/* Define the number of MPU entries assigned to the code and data sections.
On Cortex-M7 parts, there are 16 total entries. ThreadX uses one for access
On some Cortex-M7 parts, there are 16 total entries. ThreadX uses one for access
to the kernel entry function, thus 15 remain for code and data protection. */
#define TXM_MODULE_MPU_TOTAL_ENTRIES 16
#define TXM_MODULE_MPU_CODE_ENTRIES 4
@@ -202,10 +198,10 @@ typedef struct TXM_MODULE_MPU_INFO_STRUCT
ULONG txm_module_instance_shared_memory_address[TXM_MODULE_MPU_SHARED_ENTRIES]; \
ULONG txm_module_instance_shared_memory_length[TXM_MODULE_MPU_SHARED_ENTRIES];
#else /* TXM_MODULE_MANAGER_8_MPU is defined */
#else /* TXM_MODULE_MANAGER_16_MPU is not defined */
/* Define the number of MPU entries assigned to the code and data sections.
On some Cortex-M7 parts, there are 8 total entries. ThreadX uses one for access
On Cortex-M3, M4, and some M7 parts, there are 8 total entries. ThreadX uses one for access
to the kernel entry function, thus 7 remain for code and data protection. */
#define TXM_MODULE_MANAGER_CODE_MPU_ENTRIES 4
#define TXM_MODULE_MANAGER_DATA_MPU_ENTRIES 3
@@ -223,7 +219,7 @@ typedef struct TXM_MODULE_MPU_INFO_STRUCT
ULONG txm_module_instance_shared_memory_address; \
ULONG txm_module_instance_shared_memory_length;
#endif /* TXM_MODULE_MANAGER_8_MPU */
#endif /* TXM_MODULE_MANAGER_16_MPU */
/* Define the memory fault information structure that is populated when a memory fault occurs. */
@@ -346,7 +342,7 @@ typedef struct TXM_MODULE_MANAGER_MEMORY_FAULT_INFO_STRUCT
/* Define the macros to perform port-specific checks when passing pointers to the kernel. */
/* Define macro to make sure object is inside the module's data. */
#ifndef TXM_MODULE_MANAGER_8_MPU
#ifdef TXM_MODULE_MANAGER_16_MPU
#define TXM_MODULE_MANAGER_CHECK_INSIDE_DATA(module_instance, obj_ptr, obj_size) \
_txm_module_manager_inside_data_check(module_instance, obj_ptr, obj_size)
#else
@@ -380,6 +376,6 @@ UINT _txm_module_manager_inside_data_check(TXM_MODULE_INSTANCE *module_instance
#define TXM_MODULE_MANAGER_VERSION_ID \
CHAR _txm_module_manager_version_id[] = \
"Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M7/MPU/GNU Version 6.1.7 *";
"Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M7/GNU Version 6.1.9 *";
#endif

15
ports_module/cortex_m7/gnu/module_lib/src/txm_module_thread_shell_entry.c
View File

@@ -44,7 +44,7 @@ TXM_MODULE_THREAD_ENTRY_INFO *_txm_module_entry_info;
ULONG (*_txm_module_kernel_call_dispatcher)(ULONG kernel_request, ULONG param_1, ULONG param_2, ULONG param3);
/* Define the GCC startup code that clears the uninitialized global data and sets up the
/* Define the startup code that clears the uninitialized global data and sets up the
preset global variables. */
extern VOID _gcc_setup(TXM_MODULE_INSTANCE *);
@@ -54,15 +54,15 @@ extern VOID _gcc_setup(TXM_MODULE_INSTANCE *);
/* */
/* FUNCTION RELEASE */
/* */
/* _txm_module_thread_shell_entry Cortex-M7/MPU/GNU */
/* 6.1 */
/* _txm_module_thread_shell_entry Cortex-M7/GNU */
/* 6.1.9 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
/* */
/* DESCRIPTION */
/* */
/* This function calls the specified entry function of the thread. It */
/* This function calls the specified entry function of the thread. It */
/* also provides a place for the thread's entry function to return. */
/* If the thread returns, this function places the thread in a */
/* "COMPLETED" state. */
@@ -78,7 +78,7 @@ extern VOID _gcc_setup(TXM_MODULE_INSTANCE *);
/* */
/* CALLS */
/* */
/* _gcc_setup GNU global init function */
/* _gcc_setup cstartup initialization */
/* thread_entry Thread's entry function */
/* tx_thread_resume Resume the module callback thread */
/* _txm_module_thread_system_suspend Module thread suspension routine */
@@ -91,7 +91,7 @@ extern VOID _gcc_setup(TXM_MODULE_INSTANCE *);
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* 10-15-2021 Scott Larson Initial Version 6.1.9 */
/* */
/**************************************************************************/
VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_ENTRY_INFO *thread_info)
@@ -106,7 +106,7 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN
execution. If not, simply skip the C startup code. */
if (thread_info -> txm_module_thread_entry_info_start_thread)
{
/* Initialize the GNU C environment. */
/* Initialize the C environment. */
_gcc_setup(thread_info -> txm_module_thread_entry_info_code_base_address);
/* Save the entry info pointer, for later use. */
@@ -171,4 +171,3 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN
TX_SAFETY_CRITICAL_EXCEPTION(__FILE__, __LINE__, 0);
#endif
}

6
ports_module/cortex_m7/gnu/module_manager/src/tx_thread_context_restore.S
View File

@@ -31,8 +31,8 @@
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_context_restore Cortex-Mx/GNU */
/* 6.1.8 */
/* _tx_thread_context_restore Cortex-M7/GNU */
/* 6.1.7 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -62,7 +62,7 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 08-02-2021 Scott Larson Initial Version 6.1.8 */
/* 06-02-2021 Scott Larson Initial Version 6.1.7 */
/* */
/**************************************************************************/
// VOID _tx_thread_context_restore(VOID)

6
ports_module/cortex_m7/gnu/module_manager/src/tx_thread_context_save.S
View File

@@ -27,8 +27,8 @@
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_context_save Cortex-Mx/GNU */
/* 6.1.8 */
/* _tx_thread_context_save Cortex-M7/GNU */
/* 6.1.7 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -58,7 +58,7 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 08-02-2021 Scott Larson Initial Version 6.1.8 */
/* 06-02-2021 Scott Larson Initial Version 6.1.7 */
/* */
/**************************************************************************/
// VOID _tx_thread_context_save(VOID)

6
ports_module/cortex_m7/gnu/module_manager/src/tx_thread_interrupt_control.S
View File

@@ -27,8 +27,8 @@
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_interrupt_control Cortex-Mx/GNU */
/* 6.1.8 */
/* _tx_thread_interrupt_control Cortex-M7/GNU */
/* 6.1.7 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -58,7 +58,7 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 08-02-2021 Scott Larson Initial Version 6.1.8 */
/* 06-02-2021 Scott Larson Initial Version 6.1.7 */
/* */
/**************************************************************************/
// UINT _tx_thread_interrupt_control(UINT new_posture)

79
ports_module/cortex_m7/gnu/module_manager/src/tx_thread_interrupt_disable.S Normal file
View File

@@ -0,0 +1,79 @@
/**************************************************************************/
/* */
/* Copyright (c) Microsoft Corporation. All rights reserved. */
/* */
/* This software is licensed under the Microsoft Software License */
/* Terms for Microsoft Azure RTOS. Full text of the license can be */
/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
/* and in the root directory of this software. */
/* */
/**************************************************************************/
/**************************************************************************/
/**************************************************************************/
/** */
/** ThreadX Component */
/** */
/** Thread */
/** */
/**************************************************************************/
/**************************************************************************/
.text 32
.align 4
.syntax unified
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_interrupt_disable Cortex-M7/GNU */
/* 6.1.7 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
/* */
/* DESCRIPTION */
/* */
/* This function is responsible for disabling interrupts and returning */
/* the previous interrupt lockout posture. */
/* */
/* INPUT */
/* */
/* None */
/* */
/* OUTPUT */
/* */
/* old_posture Old interrupt lockout posture */
/* */
/* CALLS */
/* */
/* None */
/* */
/* CALLED BY */
/* */
/* Application Code */
/* */
/* RELEASE HISTORY */
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 06-02-2021 Scott Larson Initial Version 6.1.7 */
/* */
/**************************************************************************/
// UINT _tx_thread_interrupt_disable(VOID)
// {
.global _tx_thread_interrupt_disable
.thumb_func
_tx_thread_interrupt_disable:
/* Return current interrupt lockout posture. */
#ifdef TX_PORT_USE_BASEPRI
MRS r0, BASEPRI
LDR r1, =TX_PORT_BASEPRI
MSR BASEPRI, r1
#else
MRS r0, PRIMASK
CPSID i
#endif
BX lr
// }

76
ports_module/cortex_m7/gnu/module_manager/src/tx_thread_interrupt_restore.S Normal file
View File

@@ -0,0 +1,76 @@
/**************************************************************************/
/* */
/* Copyright (c) Microsoft Corporation. All rights reserved. */
/* */
/* This software is licensed under the Microsoft Software License */
/* Terms for Microsoft Azure RTOS. Full text of the license can be */
/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
/* and in the root directory of this software. */
/* */
/**************************************************************************/
/**************************************************************************/
/**************************************************************************/
/** */
/** ThreadX Component */
/** */
/** Thread */
/** */
/**************************************************************************/
/**************************************************************************/
.text 32
.align 4
.syntax unified
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_interrupt_restore Cortex-M7/GNU */
/* 6.1.7 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
/* */
/* DESCRIPTION */
/* */
/* This function is responsible for restoring the previous */
/* interrupt lockout posture. */
/* */
/* INPUT */
/* */
/* previous_posture Previous interrupt posture */
/* */
/* OUTPUT */
/* */
/* None */
/* */
/* CALLS */
/* */
/* None */
/* */
/* CALLED BY */
/* */
/* Application Code */
/* */
/* RELEASE HISTORY */
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 06-02-2021 Scott Larson Initial Version 6.1.7 */
/* */
/**************************************************************************/
// VOID _tx_thread_interrupt_restore(UINT previous_posture)
// {
.global _tx_thread_interrupt_restore
.thumb_func
_tx_thread_interrupt_restore:
/* Restore previous interrupt lockout posture. */
#ifdef TX_PORT_USE_BASEPRI
MSR BASEPRI, r0
#else
MSR PRIMASK, r0
#endif
BX lr
// }

30
ports_module/cortex_m7/gnu/module_manager/src/tx_thread_schedule.S
View File

@@ -39,8 +39,8 @@
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_schedule Cortex-M7/MPU/GNU */
/* 6.1.7 */
/* _tx_thread_schedule Cortex-M7/GNU */
/* 6.1.9 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -73,15 +73,7 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* 11-09-2020 Scott Larson Modified comment(s), arrange */
/* code to fix link error when */
/* VFP is enabled, resulting */
/* in version 6.1.2 */
/* 06-02-2021 Scott Larson Fixed extended stack handling */
/* when calling kernel APIs, */
/* added support for 8 MPU, */
/* resulting in version 6.1.7 */
/* 10-15-2021 Scott Larson Initial Version 6.1.9 */
/* */
/**************************************************************************/
// VOID _tx_thread_schedule(VOID)
@@ -100,16 +92,14 @@ _tx_thread_schedule:
LDR r2, =_tx_thread_preempt_disable // Build address of preempt disable flag
STR r0, [r2, #0] // Clear preempt disable flag
/* Clear CONTROL.FPCA bit so VFP registers aren't unnecessarily stacked. */
#ifdef __ARM_PCS_VFP
/* Clear CONTROL.FPCA bit so VFP registers aren't unnecessarily stacked. */
MRS r0, CONTROL // Pickup current CONTROL register
BIC r0, r0, #4 // Clear the FPCA bit
MSR CONTROL, r0 // Setup new CONTROL register
#endif
/* Enable memory fault registers. */
LDR r0, =0xE000ED24 // Build SHCSR address
LDR r1, =0x70000 // Enable Usage, Bus, and MemManage faults
STR r1, [r0] //
@@ -373,7 +363,7 @@ __tx_ts_restore:
// Use alias registers to quickly load MPU
ADD r0, r0, #100 // Build address of MPU register start in thread control block
#ifndef TXM_MODULE_MANAGER_8_MPU
#ifdef TXM_MODULE_MANAGER_16_MPU
LDM r0!,{r2-r9} // Load MPU regions 0-3
STM r1,{r2-r9} // Store MPU regions 0-3
LDM r0!,{r2-r9} // Load MPU regions 4-7
@@ -458,12 +448,16 @@ __tx_SVCallHandler:
#endif
MRS r3, PSP // Pickup thread stack pointer
#ifdef __ARM_PCS_VFP
TST lr, #0x10 // Test for extended module stack
ITT EQ
ORREQ r3, r3, #1 // If so, set LSB in thread stack pointer to indicate extended frame
ORREQ lr, lr, #0x10 // Set bit, return with standard frame
#endif
STR r3, [r2, #0xB0] // Save thread stack pointer
#ifdef __ARM_PCS_VFP
BIC r3, #1 // Clear possibly OR'd bit
#endif
/* Build kernel stack by copying thread stack two registers at a time */
ADD r3, r3, #32 // Start at bottom of hardware stack
@@ -510,6 +504,7 @@ _tx_thread_user_return:
STR r3, [r2, #20] // Set stack size
#endif
#ifdef __ARM_PCS_VFP
/* If lazy stacking is pending, check if it can be cleared.
if(LSPACT && tx_thread_module_stack_start < FPCAR && FPCAR < tx_thread_module_stack_end)
then clear LSPACT. */
@@ -529,14 +524,17 @@ _tx_thread_user_return:
LDR r1, =0xE000EF34 // Address of FPCCR
STR r3, [r1] // Save updated FPCCR
_tx_no_lazy_clear:
#endif
LDR r0, [r2, #0xB0] // Load the module thread stack pointer
MRS r3, PSP // Pickup kernel stack pointer
#ifdef __ARM_PCS_VFP
TST r0, #1 // Is module stack extended?
ITTE NE // If so...
BICNE lr, #0x10 // Clear bit, return with extended frame
BICNE r0, #1 // Clear bit that indicates extended module frame
ORREQ lr, lr, #0x10 // Else set bit, return with standard frame
#endif
/* Copy kernel hardware stack to module thread stack. */
LDM r3!, {r1-r2}
@@ -561,7 +559,7 @@ _tx_skip_kernel_stack_exit:
BX lr // Return to thread
/* Kernel entry function from user mode. */
/* Kernel entry function from user mode. */
.global _txm_module_manager_kernel_dispatch
.align 5

6
ports_module/cortex_m7/gnu/module_manager/src/tx_thread_stack_build.S
View File

@@ -27,8 +27,8 @@
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_stack_build Cortex-Mx/GNU */
/* 6.1.8 */
/* _tx_thread_stack_build Cortex-M7/GNU */
/* 6.1.7 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -60,7 +60,7 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 08-02-2021 Scott Larson Initial Version 6.1.8 */
/* 06-02-2021 Scott Larson Initial Version 6.1.7 */
/* */
/**************************************************************************/
// VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID))

6
ports_module/cortex_m7/gnu/module_manager/src/tx_thread_system_return.S
View File

@@ -27,8 +27,8 @@
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_system_return Cortex-Mx/GNU */
/* 6.1.8 */
/* _tx_thread_system_return Cortex-M7/GNU */
/* 6.1.7 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -60,7 +60,7 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 08-02-2021 Scott Larson Initial Version 6.1.8 */
/* 06-02-2021 Scott Larson Initial Version 6.1.7 */
/* */
/**************************************************************************/
// VOID _tx_thread_system_return(VOID)

6
ports_module/cortex_m7/gnu/module_manager/src/tx_timer_interrupt.S
View File

@@ -37,8 +37,8 @@
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_timer_interrupt Cortex-Mx/GNU */
/* 6.1.8 */
/* _tx_timer_interrupt Cortex-M7/GNU */
/* 6.1.7 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -71,7 +71,7 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 08-02-2021 Scott Larson Initial Version 6.1.8 */
/* 06-02-2021 Scott Larson Initial Version 6.1.7 */
/* */
/**************************************************************************/
// VOID _tx_timer_interrupt(VOID)

16
ports_module/cortex_m7/gnu/module_manager/src/txm_module_manager_alignment_adjust.c
View File

@@ -30,8 +30,8 @@
/* */
/* FUNCTION RELEASE */
/* */
/* _txm_power_of_two_block_size Cortex-M7/MPU/GNU */
/* 6.1 */
/* _txm_power_of_two_block_size Cortex-M7 */
/* 6.1.9 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -61,7 +61,7 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* 10-15-2021 Scott Larson Initial Version 6.1.9 */
/* */
/**************************************************************************/
ULONG _txm_power_of_two_block_size(ULONG size)
@@ -93,8 +93,8 @@ ULONG _txm_power_of_two_block_size(ULONG size)
/* */
/* FUNCTION RELEASE */
/* */
/* _txm_module_manager_alignment_adjust Cortex-M7/MPU/GNU */
/* 6.1.7 */
/* _txm_module_manager_alignment_adjust Cortex-M7 */
/* 6.1.9 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -128,9 +128,7 @@ ULONG _txm_power_of_two_block_size(ULONG size)
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* 06-02-2021 Scott Larson Added support for 8 MPU, */
/* resulting in version 6.1.7 */
/* 10-15-2021 Scott Larson Initial Version 6.1.9 */
/* */
/**************************************************************************/
VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble,
@@ -139,7 +137,7 @@ VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble,
ULONG *data_size,
ULONG *data_alignment)
{
#ifndef TXM_MODULE_MANAGER_8_MPU
#ifdef TXM_MODULE_MANAGER_16_MPU
ULONG local_code_size;
ULONG local_code_alignment;
ULONG local_data_size;

11
ports_module/cortex_m7/gnu/module_manager/src/txm_module_manager_external_memory_enable.c
View File

@@ -33,8 +33,8 @@
/* */
/* FUNCTION RELEASE */
/* */
/* _txm_module_manager_external_memory_enable Cortex-M7/MPU/GNU */
/* 6.1.7 */
/* _txm_module_manager_external_memory_enable Cortex-M7 */
/* 6.1.9 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -60,6 +60,7 @@
/* _tx_mutex_get Get protection mutex */
/* _tx_mutex_put Release protection mutex */
/* _txm_power_of_two_block_size Round length to power of two */
/* _txm_module_manager_mm_register_setup Reconfigure MPU registers */
/* */
/* CALLED BY */
/* */
@@ -69,9 +70,7 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* 06-02-2021 Scott Larson Added support for 8 MPU, */
/* resulting in verison 6.1.7 */
/* 10-15-2021 Scott Larson Initial Version 6.1.9 */
/* */
/**************************************************************************/
UINT _txm_module_manager_external_memory_enable(TXM_MODULE_INSTANCE *module_instance,
@@ -79,7 +78,7 @@ UINT _txm_module_manager_external_memory_enable(TXM_MODULE_INSTANCE *module_ins
ULONG length,
UINT attributes)
{
#ifndef TXM_MODULE_MANAGER_8_MPU
#ifdef TXM_MODULE_MANAGER_16_MPU
ULONG block_size;
ULONG region_size;
ULONG srd_bits;

6
ports_module/cortex_m7/gnu/module_manager/src/txm_module_manager_memory_fault_handler.c
View File

@@ -45,8 +45,8 @@ TXM_MODULE_MANAGER_FAULT_INFO
/* */
/* FUNCTION RELEASE */
/* */
/* _txm_module_manager_memory_fault_handler Cortex-M7/MPU/GNU */
/* 6.1 */
/* _txm_module_manager_memory_fault_handler Cortex-M7 */
/* 6.1.9 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -76,7 +76,7 @@ TXM_MODULE_MANAGER_FAULT_INFO
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* 10-15-2021 Scott Larson Initial Version 6.1.9 */
/* */
/**************************************************************************/
VOID _txm_module_manager_memory_fault_handler(VOID)

6
ports_module/cortex_m7/gnu/module_manager/src/txm_module_manager_memory_fault_notify.c
View File

@@ -38,8 +38,8 @@ extern VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTA
/* */
/* FUNCTION RELEASE */
/* */
/* _txm_module_manager_memory_fault_notify Cortex-M7/MPU/GNU */
/* 6.1 */
/* _txm_module_manager_memory_fault_notify Cortex-M7 */
/* 6.1.9 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -71,7 +71,7 @@ extern VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTA
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* 10-15-2021 Scott Larson Initial Version 6.1.9 */
/* */
/**************************************************************************/
UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *))

49
ports_module/cortex_m7/gnu/module_manager/src/txm_module_manager_mm_register_setup.c
View File

@@ -30,8 +30,8 @@
/* */
/* FUNCTION RELEASE */
/* */
/* _txm_module_manager_region_size_get Cortex-M7/MPU/GNU */
/* 6.1 */
/* _txm_module_manager_region_size_get Cortex-M7 */
/* 6.1.9 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -61,7 +61,7 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* 10-15-2021 Scott Larson Initial Version 6.1.9 */
/* */
/**************************************************************************/
ULONG _txm_module_manager_region_size_get(ULONG block_size)
@@ -152,8 +152,8 @@ ULONG return_value;
/* */
/* FUNCTION RELEASE */
/* */
/* _txm_module_manager_calculate_srd_bits Cortex-M7/MPU/GNU */
/* 6.1 */
/* _txm_module_manager_calculate_srd_bits Cortex-M7 */
/* 6.1.9 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -184,7 +184,7 @@ ULONG return_value;
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* 10-15-2021 Scott Larson Initial Version 6.1.9 */
/* */
/**************************************************************************/
ULONG _txm_module_manager_calculate_srd_bits(ULONG block_size, ULONG length)
@@ -230,8 +230,8 @@ UINT srd_bit_index;
/* */
/* FUNCTION RELEASE */
/* */
/* _txm_module_manager_mm_register_setup Cortex-M7/MPU/GNU */
/* 6.1.7 */
/* _txm_module_manager_mm_register_setup Cortex-M7 */
/* 6.1.9 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -240,6 +240,19 @@ UINT srd_bit_index;
/* */
/* This function sets up the MPU register definitions based on the */
/* module's memory characteristics. */
/* */
/* Default MPU layout: */
/* Entry Description */
/* 0 Kernel mode entry */
/* 1 Module code region */
/* 2 Module code region */
/* 3 Module code region */
/* 4 Module code region */
/* 5 Module data region */
/* 6 Module data region */
/* 7 Module data region */
/* */
/* If TXM_MODULE_MANAGER_16_MPU is defined, there are 16 MPU slots. */
/* MPU layout for the Cortex-M7: */
/* Entry Description */
/* 0 Kernel mode entry */
@@ -259,7 +272,6 @@ UINT srd_bit_index;
/* 14 Unused region */
/* 15 Unused region */
/* */
/* If TXM_MODULE_MANAGER_8_MPU is defined, there are only 8 MPU slots. */
/* */
/* INPUT */
/* */
@@ -281,14 +293,12 @@ UINT srd_bit_index;
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* 06-02-2021 Scott Larson Added support for 8 MPU, */
/* resulting in version 6.1.7 */
/* 10-15-2021 Scott Larson Initial Version 6.1.9 */
/* */
/**************************************************************************/
VOID _txm_module_manager_mm_register_setup(TXM_MODULE_INSTANCE *module_instance)
{
#ifndef TXM_MODULE_MANAGER_8_MPU
#ifdef TXM_MODULE_MANAGER_16_MPU
ULONG code_address;
ULONG code_size;
@@ -574,7 +584,7 @@ UINT i;
for (i = 0; i < TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1; i++)
{
/* Build the base address register. */
base_address_register = code_address & ~(block_size - 1) | mpu_register | 0x10;
base_address_register = (code_address & ~(block_size - 1)) | mpu_register | 0x10;
/* Check if SRD bits need to be set. */
if (code_size < block_size)
@@ -705,13 +715,13 @@ UINT i;
#endif
}
#ifndef TXM_MODULE_MANAGER_8_MPU
#ifdef TXM_MODULE_MANAGER_16_MPU
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _txm_module_manager_inside_data_check Cortex-M7/MPU/GNU */
/* 6.1.6 */
/* _txm_module_manager_inside_data_check Cortex-M7 */
/* 6.1.9 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -743,10 +753,7 @@ UINT i;
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* 04-02-2021 Scott Larson Modified comments, added */
/* check for overflow, */
/* resulting in version 6.1.6 */
/* 10-15-2021 Scott Larson Initial Version 6.1.9 */
/* */
/**************************************************************************/
UINT _txm_module_manager_inside_data_check(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE obj_ptr, UINT obj_size)

8
ports_module/cortex_m7/gnu/module_manager/src/txm_module_manager_thread_stack_build.s
View File

@@ -27,8 +27,8 @@
/* */
/* FUNCTION RELEASE */
/* */
/* _txm_module_manager_thread_stack_build Cortex-M7/MPU/GNU */
/* 6.1.2 */
/* _txm_module_manager_thread_stack_build Cortex-M7/GNU */
/* 6.1.9 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -60,9 +60,7 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* 11-09-2020 Scott Larson Modified comment(s), */
/* resulting in version 6.1.2 */
/* 10-15-2021 Scott Larson Initial Version 6.1.9 */
/* */
/**************************************************************************/
// VOID _txm_module_manager_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(TX_THREAD *, TXM_MODULE_INSTANCE *))

28
ports_module/cortex_m7/iar/inc/tx_port.h
View File

@@ -26,7 +26,7 @@
/* PORT SPECIFIC C INFORMATION RELEASE */
/* */
/* tx_port.h Cortex-M7/IAR */
/* 6.1 */
/* 6.1.9 */
/* */
/* AUTHOR */
/* */
@@ -47,7 +47,7 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 10-15-2021 Scott Larson Initial Version 6.1.9 */
/* */
/**************************************************************************/
@@ -71,7 +71,7 @@
#include <stdlib.h>
#include <string.h>
#include <intrinsics.h>
#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT
#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT
#include <yvals.h>
#endif
@@ -117,7 +117,7 @@ typedef unsigned short USHORT;
#endif
/* Define various constants for the ThreadX Cortex-M3 port. */
/* Define various constants for the ThreadX Cortex-M7 port. */
#define TX_INT_DISABLE 1 /* Disable interrupts */
#define TX_INT_ENABLE 0 /* Enable interrupts */
@@ -180,8 +180,8 @@ ULONG _tx_misra_time_stamp_get(VOID);
for the multiple macros is so that backward compatibility can be maintained with
existing ThreadX kernel awareness modules. */
#define TX_THREAD_EXTENSION_0
#define TX_THREAD_EXTENSION_1
#define TX_THREAD_EXTENSION_0
#define TX_THREAD_EXTENSION_1
#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT
#define TX_THREAD_EXTENSION_2 VOID *tx_thread_module_instance_ptr; \
VOID *tx_thread_module_entry_info_ptr; \
@@ -224,13 +224,16 @@ ULONG _tx_misra_time_stamp_get(VOID);
#define TX_BLOCK_POOL_EXTENSION
#define TX_BYTE_POOL_EXTENSION
#define TX_MUTEX_EXTENSION
#define TX_EVENT_FLAGS_GROUP_EXTENSION VOID *tx_event_flags_group_module_instance; \
VOID (*tx_event_flags_group_set_module_notify)(struct TX_EVENT_FLAGS_GROUP_STRUCT *group_ptr);
#define TX_MUTEX_EXTENSION
#define TX_QUEUE_EXTENSION VOID *tx_queue_module_instance; \
VOID (*tx_queue_send_module_notify)(struct TX_QUEUE_STRUCT *queue_ptr);
#define TX_SEMAPHORE_EXTENSION VOID *tx_semaphore_module_instance; \
VOID (*tx_semaphore_put_module_notify)(struct TX_SEMAPHORE_STRUCT *semaphore_ptr);
#define TX_TIMER_EXTENSION VOID *tx_timer_module_instance; \
VOID (*tx_timer_module_expiration_function)(ULONG id);
@@ -449,12 +452,6 @@ ULONG _tx_misra_ipsr_get(VOID);
is used to define a local function save area for the disable and restore
macros. */
/* The embedded assembler blocks are design so as to be inlinable by the
armlink linker inlining. This requires them to consist of either a
single 32-bit instruction, or either one or two 16-bit instructions
followed by a "BX lr". Note that to reduce the critical region size, the
16-bit "CPSID i" instruction is preceeded by a 16-bit NOP */
#ifdef TX_DISABLE_INLINE
UINT _tx_thread_interrupt_disable(VOID);
@@ -512,7 +509,7 @@ void tx_thread_fpu_disable(void);
#ifdef TX_THREAD_INIT
CHAR _tx_version_id[] =
"Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M7/IAR Version 6.1 *";
"Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M7/IAR Version 6.x *";
#else
#ifdef TX_MISRA_ENABLE
extern CHAR _tx_version_id[100];
@@ -523,6 +520,3 @@ extern CHAR _tx_version_id[];
#endif

25
ports_module/cortex_m7/iar/inc/txm_module_port.h
View File

@@ -25,8 +25,8 @@
/* */
/* APPLICATION INTERFACE DEFINITION RELEASE */
/* */
/* txm_module_port.h Cortex-M7/MPU/IAR */
/* 6.1.7 */
/* txm_module_port.h Cortex-M7/IAR */
/* 6.1.9 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -40,12 +40,7 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* 11-09-2020 Scott Larson Modified comment(s), */
/* increase kernel stack size, */
/* resulting in version 6.1.2 */
/* 06-02-2021 Scott Larson Added support for 8 MPU, */
/* resulting in version 6.1.7 */
/* 10-15-2021 Scott Larson Initial Version 6.1.9 */
/* */
/**************************************************************************/
@@ -171,10 +166,10 @@ The following extensions must also be defined in tx_port.h:
#define INLINE_DECLARE inline
#ifndef TXM_MODULE_MANAGER_8_MPU
#ifdef TXM_MODULE_MANAGER_16_MPU
/* Define the number of MPU entries assigned to the code and data sections.
On Cortex-M7 parts, there are 16 total entries. ThreadX uses one for access
On some Cortex-M7 parts, there are 16 total entries. ThreadX uses one for access
to the kernel entry function, thus 15 remain for code and data protection. */
#define TXM_MODULE_MPU_TOTAL_ENTRIES 16
#define TXM_MODULE_MPU_CODE_ENTRIES 4
@@ -204,10 +199,10 @@ typedef struct TXM_MODULE_MPU_INFO_STRUCT
ULONG txm_module_instance_shared_memory_address[TXM_MODULE_MPU_SHARED_ENTRIES]; \
ULONG txm_module_instance_shared_memory_length[TXM_MODULE_MPU_SHARED_ENTRIES];
#else /* TXM_MODULE_MANAGER_8_MPU is defined */
#else /* TXM_MODULE_MANAGER_16_MPU is not defined */
/* Define the number of MPU entries assigned to the code and data sections.
On some Cortex-M7 parts, there are 8 total entries. ThreadX uses one for access
On Cortex-M3, M4, and some M7 parts, there are 8 total entries. ThreadX uses one for access
to the kernel entry function, thus 7 remain for code and data protection. */
#define TXM_MODULE_MANAGER_CODE_MPU_ENTRIES 4
#define TXM_MODULE_MANAGER_DATA_MPU_ENTRIES 3
@@ -225,7 +220,7 @@ typedef struct TXM_MODULE_MPU_INFO_STRUCT
ULONG txm_module_instance_shared_memory_address; \
ULONG txm_module_instance_shared_memory_length;
#endif /* TXM_MODULE_MANAGER_8_MPU */
#endif /* TXM_MODULE_MANAGER_16_MPU */
/* Define the memory fault information structure that is populated when a memory fault occurs. */
@@ -348,7 +343,7 @@ typedef struct TXM_MODULE_MANAGER_MEMORY_FAULT_INFO_STRUCT
/* Define the macros to perform port-specific checks when passing pointers to the kernel. */
/* Define macro to make sure object is inside the module's data. */
#ifndef TXM_MODULE_MANAGER_8_MPU
#ifdef TXM_MODULE_MANAGER_16_MPU
#define TXM_MODULE_MANAGER_CHECK_INSIDE_DATA(module_instance, obj_ptr, obj_size) \
_txm_module_manager_inside_data_check(module_instance, obj_ptr, obj_size)
#else
@@ -382,6 +377,6 @@ UINT _txm_module_manager_inside_data_check(TXM_MODULE_INSTANCE *module_instance
#define TXM_MODULE_MANAGER_VERSION_ID \
CHAR _txm_module_manager_version_id[] = \
"Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M7/MPU/IAR Version 6.1.7 *";
"Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M7/IAR Version 6.x *";
#endif

15
ports_module/cortex_m7/iar/module_lib/src/txm_module_thread_shell_entry.c
View File

@@ -44,7 +44,7 @@ TXM_MODULE_THREAD_ENTRY_INFO *_txm_module_entry_info;
ULONG (*_txm_module_kernel_call_dispatcher)(ULONG kernel_request, ULONG param_1, ULONG param_2, ULONG param3);
/* Define the IAR startup code that clears the uninitialized global data and sets up the
/* Define the startup code that clears the uninitialized global data and sets up the
preset global variables. */
extern VOID __iar_data_init3(VOID);
@@ -54,15 +54,15 @@ extern VOID __iar_data_init3(VOID);
/* */
/* FUNCTION RELEASE */
/* */
/* _txm_module_thread_shell_entry Cortex-M7/MPU/IAR */
/* 6.1 */
/* _txm_module_thread_shell_entry Cortex-M7/IAR */
/* 6.1.9 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
/* */
/* DESCRIPTION */
/* */
/* This function calls the specified entry function of the thread. It */
/* This function calls the specified entry function of the thread. It */
/* also provides a place for the thread's entry function to return. */
/* If the thread returns, this function places the thread in a */
/* "COMPLETED" state. */
@@ -78,7 +78,7 @@ extern VOID __iar_data_init3(VOID);
/* */
/* CALLS */
/* */
/* __iar_data_init3 IAR global initialization function*/
/* __iar_data_init3 cstartup initialization */
/* thread_entry Thread's entry function */
/* tx_thread_resume Resume the module callback thread */
/* _txm_module_thread_system_suspend Module thread suspension routine */
@@ -91,7 +91,7 @@ extern VOID __iar_data_init3(VOID);
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* 10-15-2021 Scott Larson Initial Version 6.1.9 */
/* */
/**************************************************************************/
VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_ENTRY_INFO *thread_info)
@@ -106,7 +106,7 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN
execution. If not, simply skip the C startup code. */
if (thread_info -> txm_module_thread_entry_info_start_thread)
{
/* Initialize the IAR C environment. */
/* Initialize the C environment. */
__iar_data_init3();
/* Save the entry info pointer, for later use. */
@@ -171,4 +171,3 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN
TX_SAFETY_CRITICAL_EXCEPTION(__FILE__, __LINE__, 0);
#endif
}

6
ports_module/cortex_m7/iar/module_manager/src/tx_thread_context_restore.s
View File

@@ -27,8 +27,8 @@
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_context_restore Cortex-Mx/IAR */
/* 6.1.8 */
/* _tx_thread_context_restore Cortex-M7/IAR */
/* 6.1.7 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -58,7 +58,7 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 08-02-2021 Scott Larson Initial Version 6.1.8 */
/* 06-02-2021 Scott Larson Initial Version 6.1.7 */
/* */
/**************************************************************************/
// VOID _tx_thread_context_restore(VOID)

6
ports_module/cortex_m7/iar/module_manager/src/tx_thread_context_save.s
View File

@@ -27,8 +27,8 @@
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_context_save Cortex-Mx/IAR */
/* 6.1.8 */
/* _tx_thread_context_save Cortex-M7/IAR */
/* 6.1.7 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -58,7 +58,7 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 08-02-2021 Scott Larson Initial Version 6.1.8 */
/* 06-02-2021 Scott Larson Initial Version 6.1.7 */
/* */
/**************************************************************************/
// VOID _tx_thread_context_save(VOID)

6
ports_module/cortex_m7/iar/module_manager/src/tx_thread_interrupt_control.s
View File

@@ -26,8 +26,8 @@
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_interrupt_control Cortex-Mx/IAR */
/* 6.1.8 */
/* _tx_thread_interrupt_control Cortex-M7/IAR */
/* 6.1.7 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -57,7 +57,7 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 08-02-2021 Scott Larson Initial Version 6.1.8 */
/* 06-02-2021 Scott Larson Initial Version 6.1.7 */
/* */
/**************************************************************************/
// UINT _tx_thread_interrupt_control(UINT new_posture)

6
ports_module/cortex_m7/iar/module_manager/src/tx_thread_interrupt_disable.s
View File

@@ -26,8 +26,8 @@
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_interrupt_disable Cortex-Mx/IAR */
/* 6.1.8 */
/* _tx_thread_interrupt_disable Cortex-M7/IAR */
/* 6.1.7 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -57,7 +57,7 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 08-02-2021 Scott Larson Initial Version 6.1.8 */
/* 06-02-2021 Scott Larson Initial Version 6.1.7 */
/* */
/**************************************************************************/
// UINT _tx_thread_interrupt_disable(VOID)

6
ports_module/cortex_m7/iar/module_manager/src/tx_thread_interrupt_restore.s
View File

@@ -26,8 +26,8 @@
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_interrupt_restore Cortex-Mx/IAR */
/* 6.1.8 */
/* _tx_thread_interrupt_restore Cortex-M7/IAR */
/* 6.1.7 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -57,7 +57,7 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 08-02-2021 Scott Larson Initial Version 6.1.8 */
/* 06-02-2021 Scott Larson Initial Version 6.1.7 */
/* */
/**************************************************************************/
// VOID _tx_thread_interrupt_restore(UINT previous_posture)

27
ports_module/cortex_m7/iar/module_manager/src/tx_thread_schedule.s
View File

@@ -35,8 +35,8 @@
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_schedule Cortex-M7/MPU/IAR */
/* 6.1.7 */
/* _tx_thread_schedule Cortex-M7/IAR */
/* 6.1.9 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -69,15 +69,7 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* 11-09-2020 Scott Larson Modified comment(s), arrange */
/* code to fix link error when */
/* VFP is enabled, resulting */
/* in version 6.1.2 */
/* 06-02-2021 Scott Larson Fixed extended stack handling */
/* when calling kernel APIs, */
/* added support for 8 MPU, */
/* resulting in version 6.1.7 */
/* 10-15-2021 Scott Larson Initial Version 6.1.9 */
/* */
/**************************************************************************/
// VOID _tx_thread_schedule(VOID)
@@ -103,7 +95,6 @@ _tx_thread_schedule:
#endif
/* Enable memory fault registers. */
LDR r0, =0xE000ED24 // Build SHCSR address
LDR r1, =0x70000 // Enable Usage, Bus, and MemManage faults
STR r1, [r0] //
@@ -362,7 +353,7 @@ __tx_ts_restore:
// Use alias registers to quickly load MPU
ADD r0, r0, #100 // Build address of MPU register start in thread control block
#ifndef TXM_MODULE_MANAGER_8_MPU
#ifdef TXM_MODULE_MANAGER_16_MPU
LDM r0!,{r2-r9} // Load MPU regions 0-3
STM r1,{r2-r9} // Store MPU regions 0-3
LDM r0!,{r2-r9} // Load MPU regions 4-7
@@ -445,13 +436,17 @@ __tx_SVCallHandler:
#endif
MRS r3, PSP // Pickup thread stack pointer
#ifdef __ARMVFP__
TST lr, #0x10 // Test for extended module stack
ITT EQ
ORREQ r3, r3, #1 // If so, set LSB in thread stack pointer to indicate extended frame
ORREQ lr, lr, #0x10 // Set bit, return with standard frame
#endif
STR r3, [r2, #0xB0] // Save thread stack pointer
#ifdef __ARMVFP__
BIC r3, #1 // Clear possibly OR'd bit
#endif
/* Build kernel stack by copying thread stack two registers at a time */
ADD r3, r3, #32 // Start at bottom of hardware stack
LDMDB r3!, {r1-r2}
@@ -498,6 +493,7 @@ _tx_thread_user_return:
STR r3, [r2, #20] // Set stack size
#endif
#ifdef __ARMVFP__
/* If lazy stacking is pending, check if it can be cleared.
if(LSPACT && tx_thread_module_stack_start < FPCAR && FPCAR < tx_thread_module_stack_end)
then clear LSPACT. */
@@ -517,14 +513,17 @@ _tx_thread_user_return:
LDR r1, =0xE000EF34 // Address of FPCCR
STR r3, [r1] // Save updated FPCCR
_tx_no_lazy_clear:
#endif
LDR r0, [r2, #0xB0] // Load the module thread stack pointer
MRS r3, PSP // Pickup kernel stack pointer
#ifdef __ARMVFP__
TST r0, #1 // Is module stack extended?
ITTE NE // If so...
BICNE lr, #0x10 // Clear bit, return with extended frame
BICNE r0, #1 // Clear bit that indicates extended module frame
ORREQ lr, lr, #0x10 // Else set bit, return with standard frame
#endif
/* Copy kernel hardware stack to module thread stack. */
LDM r3!, {r1-r2}

6
ports_module/cortex_m7/iar/module_manager/src/tx_thread_stack_build.s
View File

@@ -26,8 +26,8 @@
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_stack_build Cortex-Mx/IAR */
/* 6.1.8 */
/* _tx_thread_stack_build Cortex-M7/IAR */
/* 6.1.7 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -59,7 +59,7 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 08-02-2021 Scott Larson Initial Version 6.1.8 */
/* 06-02-2021 Scott Larson Initial Version 6.1.7 */
/* */
/**************************************************************************/
// VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID))

6
ports_module/cortex_m7/iar/module_manager/src/tx_thread_system_return.s
View File

@@ -26,8 +26,8 @@
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_system_return Cortex-Mx/IAR */
/* 6.1.8 */
/* _tx_thread_system_return Cortex-M7/IAR */
/* 6.1.7 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -59,7 +59,7 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 08-02-2021 Scott Larson Initial Version 6.1.8 */
/* 06-02-2021 Scott Larson Initial Version 6.1.7 */
/* */
/**************************************************************************/
// VOID _tx_thread_system_return(VOID)

6
ports_module/cortex_m7/iar/module_manager/src/tx_timer_interrupt.s
View File

@@ -39,8 +39,8 @@
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_timer_interrupt Cortex-Mx/IAR */
/* 6.1.8 */
/* _tx_timer_interrupt Cortex-M7/IAR */
/* 6.1.7 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -73,7 +73,7 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 08-02-2021 Scott Larson Initial Version 6.1.8 */
/* 06-02-2021 Scott Larson Initial Version 6.1.7 */
/* */
/**************************************************************************/
// VOID _tx_timer_interrupt(VOID)

16
ports_module/cortex_m7/iar/module_manager/src/txm_module_manager_alignment_adjust.c
View File

@@ -30,8 +30,8 @@
/* */
/* FUNCTION RELEASE */
/* */
/* _txm_power_of_two_block_size Cortex-M7/MPU/IAR */
/* 6.1 */
/* _txm_power_of_two_block_size Cortex-M7 */
/* 6.1.9 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -61,7 +61,7 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* 10-15-2021 Scott Larson Initial Version 6.1.9 */
/* */
/**************************************************************************/
ULONG _txm_power_of_two_block_size(ULONG size)
@@ -93,8 +93,8 @@ ULONG _txm_power_of_two_block_size(ULONG size)
/* */
/* FUNCTION RELEASE */
/* */
/* _txm_module_manager_alignment_adjust Cortex-M7/MPU/IAR */
/* 6.1.7 */
/* _txm_module_manager_alignment_adjust Cortex-M7 */
/* 6.1.9 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -128,9 +128,7 @@ ULONG _txm_power_of_two_block_size(ULONG size)
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* 06-02-2021 Scott Larson Added support for 8 MPU, */
/* resulting in version 6.1.7 */
/* 10-15-2021 Scott Larson Initial Version 6.1.9 */
/* */
/**************************************************************************/
VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble,
@@ -139,7 +137,7 @@ VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble,
ULONG *data_size,
ULONG *data_alignment)
{
#ifndef TXM_MODULE_MANAGER_8_MPU
#ifdef TXM_MODULE_MANAGER_16_MPU
ULONG local_code_size;
ULONG local_code_alignment;
ULONG local_data_size;

11
ports_module/cortex_m7/iar/module_manager/src/txm_module_manager_external_memory_enable.c
View File

@@ -33,8 +33,8 @@
/* */
/* FUNCTION RELEASE */
/* */
/* _txm_module_manager_external_memory_enable Cortex-M7/MPU/IAR */
/* 6.1.7 */
/* _txm_module_manager_external_memory_enable Cortex-M7 */
/* 6.1.9 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -60,6 +60,7 @@
/* _tx_mutex_get Get protection mutex */
/* _tx_mutex_put Release protection mutex */
/* _txm_power_of_two_block_size Round length to power of two */
/* _txm_module_manager_mm_register_setup Reconfigure MPU registers */
/* */
/* CALLED BY */
/* */
@@ -69,9 +70,7 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* 06-02-2021 Scott Larson Added support for 8 MPU, */
/* resulting in verison 6.1.7 */
/* 10-15-2021 Scott Larson Initial Version 6.1.9 */
/* */
/**************************************************************************/
UINT _txm_module_manager_external_memory_enable(TXM_MODULE_INSTANCE *module_instance,
@@ -79,7 +78,7 @@ UINT _txm_module_manager_external_memory_enable(TXM_MODULE_INSTANCE *module_ins
ULONG length,
UINT attributes)
{
#ifndef TXM_MODULE_MANAGER_8_MPU
#ifdef TXM_MODULE_MANAGER_16_MPU
ULONG block_size;
ULONG region_size;
ULONG srd_bits;

6
ports_module/cortex_m7/iar/module_manager/src/txm_module_manager_memory_fault_handler.c
View File

@@ -45,8 +45,8 @@ TXM_MODULE_MANAGER_FAULT_INFO
/* */
/* FUNCTION RELEASE */
/* */
/* _txm_module_manager_memory_fault_handler Cortex-M7/MPU/IAR */
/* 6.1 */
/* _txm_module_manager_memory_fault_handler Cortex-M7 */
/* 6.1.9 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -76,7 +76,7 @@ TXM_MODULE_MANAGER_FAULT_INFO
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* 10-15-2021 Scott Larson Initial Version 6.1.9 */
/* */
/**************************************************************************/
VOID _txm_module_manager_memory_fault_handler(VOID)

6
ports_module/cortex_m7/iar/module_manager/src/txm_module_manager_memory_fault_notify.c
View File

@@ -38,8 +38,8 @@ extern VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTA
/* */
/* FUNCTION RELEASE */
/* */
/* _txm_module_manager_memory_fault_notify Cortex-M7/MPU/IAR */
/* 6.1 */
/* _txm_module_manager_memory_fault_notify Cortex-M7 */
/* 6.1.9 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -71,7 +71,7 @@ extern VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTA
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* 10-15-2021 Scott Larson Initial Version 6.1.9 */
/* */
/**************************************************************************/
UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *))

53
ports_module/cortex_m7/iar/module_manager/src/txm_module_manager_mm_register_setup.c
View File

@@ -30,8 +30,8 @@
/* */
/* FUNCTION RELEASE */
/* */
/* _txm_module_manager_region_size_get Cortex-M7/MPU/IAR */
/* 6.1 */
/* _txm_module_manager_region_size_get Cortex-M7 */
/* 6.1.9 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -61,7 +61,7 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* 10-15-2021 Scott Larson Initial Version 6.1.9 */
/* */
/**************************************************************************/
ULONG _txm_module_manager_region_size_get(ULONG block_size)
@@ -152,8 +152,8 @@ ULONG return_value;
/* */
/* FUNCTION RELEASE */
/* */
/* _txm_module_manager_calculate_srd_bits Cortex-M7/MPU/IAR */
/* 6.1 */
/* _txm_module_manager_calculate_srd_bits Cortex-M7 */
/* 6.1.9 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -184,7 +184,7 @@ ULONG return_value;
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* 10-15-2021 Scott Larson Initial Version 6.1.9 */
/* */
/**************************************************************************/
ULONG _txm_module_manager_calculate_srd_bits(ULONG block_size, ULONG length)
@@ -230,16 +230,29 @@ UINT srd_bit_index;
/* */
/* FUNCTION RELEASE */
/* */
/* _txm_module_manager_mm_register_setup Cortex-M7/MPU/IAR */
/* 6.1.7 */
/* _txm_module_manager_mm_register_setup Cortex-M7 */
/* 6.1.9 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
/* */
/* DESCRIPTION */
/* */
/* This function sets up the Cortex-M7 MPU register definitions based */
/* on the module's memory characteristics. */
/* This function sets up the MPU register definitions based on the */
/* module's memory characteristics. */
/* */
/* Default MPU layout: */
/* Entry Description */
/* 0 Kernel mode entry */
/* 1 Module code region */
/* 2 Module code region */
/* 3 Module code region */
/* 4 Module code region */
/* 5 Module data region */
/* 6 Module data region */
/* 7 Module data region */
/* */
/* If TXM_MODULE_MANAGER_16_MPU is defined, there are 16 MPU slots. */
/* MPU layout for the Cortex-M7: */
/* Entry Description */
/* 0 Kernel mode entry */
@@ -259,7 +272,6 @@ UINT srd_bit_index;
/* 14 Unused region */
/* 15 Unused region */
/* */
/* If TXM_MODULE_MANAGER_8_MPU is defined, there are only 8 MPU slots. */
/* */
/* INPUT */
/* */
@@ -281,14 +293,12 @@ UINT srd_bit_index;
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* 06-02-2021 Scott Larson Added support for 8 MPU, */
/* resulting in version 6.1.7 */
/* 10-15-2021 Scott Larson Initial Version 6.1.9 */
/* */
/**************************************************************************/
VOID _txm_module_manager_mm_register_setup(TXM_MODULE_INSTANCE *module_instance)
{
#ifndef TXM_MODULE_MANAGER_8_MPU
#ifdef TXM_MODULE_MANAGER_16_MPU
ULONG code_address;
ULONG code_size;
@@ -574,7 +584,7 @@ UINT i;
for (i = 0; i < TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1; i++)
{
/* Build the base address register. */
base_address_register = code_address & ~(block_size - 1) | mpu_register | 0x10;
base_address_register = (code_address & ~(block_size - 1)) | mpu_register | 0x10;
/* Check if SRD bits need to be set. */
if (code_size < block_size)
@@ -705,13 +715,13 @@ UINT i;
#endif
}
#ifndef TXM_MODULE_MANAGER_8_MPU
#ifdef TXM_MODULE_MANAGER_16_MPU
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _txm_module_manager_inside_data_check Cortex-M7/MPU/IAR */
/* 6.1.6 */
/* _txm_module_manager_inside_data_check Cortex-M7 */
/* 6.1.9 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -743,10 +753,7 @@ UINT i;
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* 04-02-2021 Scott Larson Modified comments, added */
/* check for overflow, */
/* resulting in version 6.1.6 */
/* 10-15-2021 Scott Larson Initial Version 6.1.9 */
/* */
/**************************************************************************/
UINT _txm_module_manager_inside_data_check(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE obj_ptr, UINT obj_size)

8
ports_module/cortex_m7/iar/module_manager/src/txm_module_manager_thread_stack_build.s
View File

@@ -26,8 +26,8 @@
/* */
/* FUNCTION RELEASE */
/* */
/* _txm_module_manager_thread_stack_build Cortex-M7/MPU/IAR */
/* 6.1.2 */
/* _txm_module_manager_thread_stack_build Cortex-M7/IAR */
/* 6.1.9 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -59,9 +59,7 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* 11-09-2020 Scott Larson Modified comment(s), */
/* resulting in version 6.1.2 */
/* 10-15-2021 Scott Larson Initial Version 6.1.9 */
/* */
/**************************************************************************/
// VOID _txm_module_manager_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(TX_THREAD *, TXM_MODULE_INSTANCE *))