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6.1 minor release

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This commit is contained in:
Scott Larson
2020-09-30 15:42:41 -07:00
parent 7287542cc8
commit 1b5816a206
3038 changed files with 377204 additions and 8606 deletions
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10
ports_module/cortex-m4/iar/example_build/sample_threadx.ewp
View File

@@ -66,7 +66,7 @@
</option>
<option>
<name>OGLastSavedByProductVersion</name>
<state>8.50.1.24770</state>
<state>8.50.4.26131</state>
</option>
<option>
<name>GeneralEnableMisra</name>
@@ -349,8 +349,8 @@
</option>
<option>
<name>CCIncludePath2</name>
<state>../../../../common/inc</state>
<state>../inc</state>
<state>$PROJ_DIR$\..\inc</state>
<state>$PROJ_DIR$\..\..\..\..\common\inc</state>
</option>
<option>
<name>CCStdIncCheck</name>
@@ -1006,7 +1006,7 @@
</option>
<option>
<name>IlinkTrustzoneImportLibraryOut</name>
<state>sample_threadx_import_lib.o</state>
<state>###Unitialized###</state>
</option>
<option>
<name>OILinkExtraOption</name>
@@ -1173,7 +1173,7 @@
</option>
<option>
<name>RTConfigPath2</name>
<state>dl-stnl0.a</state>
<state></state>
</option>
<option>
<name>GBECoreSlave</name>

6
ports_module/cortex-m4/iar/example_build/sample_threadx_module.ewp
View File

@@ -66,7 +66,7 @@
</option>
<option>
<name>OGLastSavedByProductVersion</name>
<state>8.50.1.24770</state>
<state>8.50.4.26131</state>
</option>
<option>
<name>GeneralEnableMisra</name>
@@ -349,8 +349,8 @@
</option>
<option>
<name>CCIncludePath2</name>
<state>../inc</state>
<state>../../../../common/inc</state>
<state>$PROJ_DIR$\..\inc</state>
<state>$PROJ_DIR$\..\..\..\..\common\inc</state>
<state>$PROJ_DIR$\..\..\..\..\common_modules\inc</state>
</option>
<option>

2
ports_module/cortex-m4/iar/example_build/sample_threadx_module_manager.c
View File

@@ -40,7 +40,6 @@ VOID module_fault_handler(TX_THREAD *thread, TXM_MODULE_INSTANCE *module)
int main()
{
/* Enter the ThreadX kernel. */
tx_kernel_enter();
}
@@ -103,7 +102,6 @@ void module_manager_entry(ULONG thread_input)
/* Now just spin... */
while(1)
{
tx_thread_sleep(100);
}
}

2
ports_module/cortex-m4/iar/example_build/sample_threadx_module_manager.ewd
View File

@@ -88,7 +88,7 @@
</option>
<option>
<name>OCLastSavedByProductVersion</name>
<state>8.50.1.24770</state>
<state>8.50.4.26131</state>
</option>
<option>
<name>UseFlashLoader</name>

12
ports_module/cortex-m4/iar/example_build/sample_threadx_module_manager.ewp
View File

@@ -66,7 +66,7 @@
</option>
<option>
<name>OGLastSavedByProductVersion</name>
<state>8.50.1.24770</state>
<state>8.50.4.26131</state>
</option>
<option>
<name>GeneralEnableMisra</name>
@@ -349,11 +349,11 @@
</option>
<option>
<name>CCIncludePath2</name>
<state>../inc</state>
<state>../module_manager/inc</state>
<state>../../../../common/inc</state>
<state>../../../../common_modules/inc</state>
<state>../../../../common_modules/module_manager/inc</state>
<state>$PROJ_DIR$\..\inc</state>
<state>$PROJ_DIR$\..\module_manager\inc</state>
<state>$PROJ_DIR$\..\..\..\..\common\inc</state>
<state>$PROJ_DIR$\..\..\..\..\common_modules\inc</state>
<state>$PROJ_DIR$\..\..\..\..\common_modules\module_manager\inc</state>
</option>
<option>
<name>CCStdIncCheck</name>

24
ports_module/cortex-m4/iar/example_build/tx.ewp
View File

@@ -66,7 +66,7 @@
</option>
<option>
<name>OGLastSavedByProductVersion</name>
<state>8.50.1.24770</state>
<state>8.50.4.26131</state>
</option>
<option>
<name>GeneralEnableMisra</name>
@@ -349,11 +349,11 @@
</option>
<option>
<name>CCIncludePath2</name>
<state>../inc</state>
<state>../module_manager/inc</state>
<state>../../../../common/inc</state>
<state>../../../../common_modules/inc</state>
<state>../../../../common_modules/module_manager/inc</state>
<state>$PROJ_DIR$\..\inc</state>
<state>$PROJ_DIR$\..\module_manager\inc</state>
<state>$PROJ_DIR$\..\..\..\..\common\inc</state>
<state>$PROJ_DIR$\..\..\..\..\common_modules\inc</state>
<state>$PROJ_DIR$\..\..\..\..\common_modules\module_manager\inc</state>
</option>
<option>
<name>CCStdIncCheck</name>
@@ -1050,7 +1050,7 @@
</option>
<option>
<name>IarchiveOutput</name>
<state>C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports_module\cortex-m4\iar\example_build\Debug\Exe\tx.a</state>
<state></state>
</option>
</data>
</settings>
@@ -1176,7 +1176,7 @@
</option>
<option>
<name>RTConfigPath2</name>
<state>dl-stnl0.a</state>
<state></state>
</option>
<option>
<name>GBECoreSlave</name>
@@ -2146,7 +2146,7 @@
<name>$PROJ_DIR$\..\..\..\..\common\inc\tx_mutex.h</name>
</file>
<file>
<name>$PROJ_DIR$\..\module_common\inc\tx_port.h</name>
<name>$PROJ_DIR$\..\inc\tx_port.h</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\..\common\inc\tx_queue.h</name>
@@ -2167,7 +2167,7 @@
<name>$PROJ_DIR$\..\..\..\..\common\inc\tx_user_sample.h</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\..\common_modules\module_common\inc\txm_module.h</name>
<name>$PROJ_DIR$\..\..\..\..\common_modules\inc\txm_module.h</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\..\common_modules\module_manager\inc\txm_module_manager_dispatch.h</name>
@@ -2176,10 +2176,10 @@
<name>$PROJ_DIR$\..\..\..\..\common_modules\module_manager\inc\txm_module_manager_util.h</name>
</file>
<file>
<name>$PROJ_DIR$\..\module_common\inc\txm_module_port.h</name>
<name>$PROJ_DIR$\..\inc\txm_module_port.h</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\..\common_modules\module_common\inc\txm_module_user.h</name>
<name>$PROJ_DIR$\..\..\..\..\common_modules\inc\txm_module_user.h</name>
</file>
</group>
<group>

4
ports_module/cortex-m4/iar/example_build/tx_initialize_low_level.s
View File

@@ -55,7 +55,7 @@ __tx_free_memory_start
;/* FUNCTION RELEASE */
;/* */
;/* _tx_initialize_low_level Cortex-M4/IAR */
;/* 6.0.1 */
;/* 6.1 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
@@ -88,7 +88,7 @@ __tx_free_memory_start
;/* */
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* 09-30-2020 William E. Lamie Initial Version 6.1 */
;/* */
;/**************************************************************************/
;VOID _tx_initialize_low_level(VOID)

16
ports_module/cortex-m4/iar/example_build/txm.ewp
View File

@@ -66,7 +66,7 @@
</option>
<option>
<name>OGLastSavedByProductVersion</name>
<state>8.50.1.24770</state>
<state>8.50.4.26131</state>
</option>
<option>
<name>GeneralEnableMisra</name>
@@ -349,9 +349,9 @@
</option>
<option>
<name>CCIncludePath2</name>
<state>../inc</state>
<state>../../../../common/inc</state>
<state>../../../../common_modules/inc</state>
<state>$PROJ_DIR$\..\inc</state>
<state>$PROJ_DIR$\..\..\..\..\common\inc</state>
<state>$PROJ_DIR$\..\..\..\..\common_modules\inc</state>
</option>
<option>
<name>CCStdIncCheck</name>
@@ -1048,7 +1048,7 @@
</option>
<option>
<name>IarchiveOutput</name>
<state>C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports_module\cortex-m4\iar\example_build\Debug\Exe\txm.a</state>
<state></state>
</option>
</data>
</settings>
@@ -2165,13 +2165,13 @@
<name>$PROJ_DIR$\..\..\..\..\common\inc\tx_user_sample.h</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\..\common_modules\module_common\inc\txm_module.h</name>
<name>$PROJ_DIR$\..\..\..\..\common_modules\inc\txm_module.h</name>
</file>
<file>
<name>$PROJ_DIR$\..\module_common\inc\txm_module_port.h</name>
<name>$PROJ_DIR$\..\inc\txm_module_port.h</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\..\common_modules\module_common\inc\txm_module_user.h</name>
<name>$PROJ_DIR$\..\..\..\..\common_modules\inc\txm_module_user.h</name>
</file>
</group>
<group>

103
ports_module/cortex-m4/iar/example_build/txm_module_preamble.s
View File

@@ -1,7 +1,7 @@
SECTION .text:CODE
AAPCS INTERWORK, ROPI, RWPI_COMPATIBLE, VFP_COMPATIBLE
PRESERVE8
AAPCS INTERWORK, ROPI, RWPI_COMPATIBLE, VFP_COMPATIBLE
PRESERVE8
/* Define public symbols. */
@@ -15,56 +15,55 @@
/* Define common external refrences. */
EXTERN _txm_module_thread_shell_entry
EXTERN _txm_module_callback_request_thread_entry
EXTERN ROPI$$Length
EXTERN RWPI$$Length
EXTERN _txm_module_thread_shell_entry
EXTERN _txm_module_callback_request_thread_entry
EXTERN ROPI$$Length
EXTERN RWPI$$Length
DATA
DATA
__txm_module_preamble:
DC32 0x4D4F4455 ; Module ID
DC32 0x5 ; Module Major Version
DC32 0x6 ; Module Minor Version
DC32 32 ; Module Preamble Size in 32-bit words
DC32 0x12345678 ; Module ID (application defined)
DC32 0x00000007 ; Module Properties where:
; Bits 31-24: Compiler ID
; 0 -> IAR
; 1 -> RVDS
; 2 -> GNU
; Bit 0: 0 -> Privileged mode execution
; 1 -> User mode execution
; Bit 1: 0 -> No MPU protection
; 1 -> MPU protection (must have user mode selected)
; Bit 2: 0 -> Disable shared/external memory access
; 1 -> Enable shared/external memory access
DC32 _txm_module_thread_shell_entry - . - 0 ; Module Shell Entry Point
DC32 demo_module_start - . - 0 ; Module Start Thread Entry Point
DC32 0 ; Module Stop Thread Entry Point
DC32 1 ; Module Start/Stop Thread Priority
DC32 1022 ; Module Start/Stop Thread Stack Size
DC32 _txm_module_callback_request_thread_entry - . - 0 ; Module Callback Thread Entry
DC32 1 ; Module Callback Thread Priority
DC32 1022 ; Module Callback Thread Stack Size
DC32 ROPI$$Length ; Module Code Size
DC32 RWPI$$Length ; Module Data Size
DC32 0 ; Reserved 0
DC32 0 ; Reserved 1
DC32 0 ; Reserved 2
DC32 0 ; Reserved 3
DC32 0 ; Reserved 4
DC32 0 ; Reserved 5
DC32 0 ; Reserved 6
DC32 0 ; Reserved 7
DC32 0 ; Reserved 8
DC32 0 ; Reserved 9
DC32 0 ; Reserved 10
DC32 0 ; Reserved 11
DC32 0 ; Reserved 12
DC32 0 ; Reserved 13
DC32 0 ; Reserved 14
DC32 0 ; Reserved 15
END
DC32 0x4D4F4455 ; Module ID
DC32 0x6 ; Module Major Version
DC32 0x1 ; Module Minor Version
DC32 32 ; Module Preamble Size in 32-bit words
DC32 0x12345678 ; Module ID (application defined)
DC32 0x00000007 ; Module Properties where:
; Bits 31-24: Compiler ID
; 0 -> IAR
; 1 -> RVDS
; 2 -> GNU
; Bits 23-3: Reserved
; Bit 2: 0 -> Disable shared/external memory access
; 1 -> Enable shared/external memory access
; Bit 1: 0 -> No MPU protection
; 1 -> MPU protection (must have user mode selected - bit 0 set)
; Bit 0: 0 -> Privileged mode execution
; 1 -> User mode execution
DC32 _txm_module_thread_shell_entry - . - 0 ; Module Shell Entry Point
DC32 demo_module_start - . - 0 ; Module Start Thread Entry Point
DC32 0 ; Module Stop Thread Entry Point
DC32 1 ; Module Start/Stop Thread Priority
DC32 1024 ; Module Start/Stop Thread Stack Size
DC32 _txm_module_callback_request_thread_entry - . - 0 ; Module Callback Thread Entry
DC32 1 ; Module Callback Thread Priority
DC32 1024 ; Module Callback Thread Stack Size
DC32 ROPI$$Length ; Module Code Size
DC32 RWPI$$Length ; Module Data Size
DC32 0 ; Reserved 0
DC32 0 ; Reserved 1
DC32 0 ; Reserved 2
DC32 0 ; Reserved 3
DC32 0 ; Reserved 4
DC32 0 ; Reserved 5
DC32 0 ; Reserved 6
DC32 0 ; Reserved 7
DC32 0 ; Reserved 8
DC32 0 ; Reserved 9
DC32 0 ; Reserved 10
DC32 0 ; Reserved 11
DC32 0 ; Reserved 12
DC32 0 ; Reserved 13
DC32 0 ; Reserved 14
DC32 0 ; Reserved 15
END

10
ports_module/cortex-m4/iar/inc/tx_port.h
View File

@@ -26,7 +26,7 @@
/* PORT SPECIFIC C INFORMATION RELEASE */
/* */
/* tx_port.h Cortex-M4/IAR */
/* 6.0.1 */
/* 6.1 */
/* */
/* AUTHOR */
/* */
@@ -47,7 +47,7 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* */
/**************************************************************************/
@@ -117,7 +117,7 @@ typedef unsigned short USHORT;
#endif
/* Define various constants for the ThreadX Cortex-M3 port. */
/* Define various constants for the ThreadX ARM Cortex-M port. */
#define TX_INT_DISABLE 1 /* Disable interrupts */
#define TX_INT_ENABLE 0 /* Enable interrupts */
@@ -376,7 +376,7 @@ void _tx_misra_vfp_touch(void);
#else
#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr)
#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr)
#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr)
#endif
@@ -506,7 +506,7 @@ void tx_thread_fpu_disable(void);
#ifdef TX_THREAD_INIT
CHAR _tx_version_id[] =
"Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M4/IAR Version 6.0.1 *";
"Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M4/IAR Version 6.1 *";
#else
#ifdef TX_MISRA_ENABLE
extern CHAR _tx_version_id[100];

93
ports_module/cortex-m4/iar/inc/txm_module_port.h
View File

@@ -10,37 +10,37 @@
/**************************************************************************/
/**************************************************************************/
/**************************************************************************/
/** */
/** ThreadX Component */
/** */
/** Module */
/** */
/**************************************************************************/
/**************************************************************************/
/**************************************************************************/
/**************************************************************************/
/** */
/** ThreadX Component */
/** */
/** Module */
/** */
/**************************************************************************/
/**************************************************************************/
/**************************************************************************/
/* */
/* APPLICATION INTERFACE DEFINITION RELEASE */
/* */
/* txm_module_port.h Cortex-M4/MPU/IAR */
/* 6.0.1 */
/**************************************************************************/
/* */
/* APPLICATION INTERFACE DEFINITION RELEASE */
/* */
/* txm_module_port.h Cortex-M4/MPU/IAR */
/* 6.1 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
/* */
/* DESCRIPTION */
/* */
/* This file defines the basic module constants, interface structures, */
/* and function prototypes. */
/* */
/* RELEASE HISTORY */
/* */
/* DESCRIPTION */
/* */
/* This file defines the basic module constants, interface structures, */
/* and function prototypes. */
/* */
/* RELEASE HISTORY */
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 06-30-2020 Scott Larson Initial Version 6.0.1 */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* */
/**************************************************************************/
@@ -52,13 +52,13 @@
#ifdef TXM_MODULE_INCLUDE_USER_DEFINE_FILE
/* Yes, include the user defines in txm_module_user.h. The defines in this file may
/* Yes, include the user defines in txm_module_user.h. The defines in this file may
alternately be defined on the command line. */
#include "txm_module_user.h"
#endif
/* It is assumed that the base ThreadX tx_port.h file has been modified to add the
/* It is assumed that the base ThreadX tx_port.h file has been modified to add the
following extensions to the ThreadX thread control block (this code should replace
the corresponding macro define in tx_port.h):
@@ -151,7 +151,7 @@ The following extensions must also be defined in tx_port.h:
#define INLINE_DECLARE inline
/* Define the number of MPU entries assigned to the code and data sections. On Cortex-M parts, there can only be 7 total
/* Define the number of MPU entries assigned to the code and data sections. On Cortex-M parts, there can only be 7 total
entries, since ThreadX uses one for access to the kernel dispatch function. */
#define TXM_MODULE_MANAGER_CODE_MPU_ENTRIES 4
@@ -205,9 +205,6 @@ typedef struct TXM_MODULE_MANAGER_MEMORY_FAULT_INFO_STRUCT
#define TXM_MODULE_MANAGER_FAULT_INFO \
TXM_MODULE_MANAGER_MEMORY_FAULT_INFO _txm_module_manager_memory_fault_info;
/* Define the macro to check the stack available in dispatch. */
#define TXM_MODULE_MANAGER_CHECK_STACK_AVAILABLE
/* Define the macro to check the code alignment. */
#define TXM_MODULE_MANAGER_CHECK_CODE_ALIGNMENT(module_location, code_alignment) \
@@ -292,16 +289,16 @@ typedef struct TXM_MODULE_MANAGER_MEMORY_FAULT_INFO_STRUCT
#define TXM_MODULE_MANAGER_MODULE_UNLOAD(module_instance)
/* Define the macro to perform port-specific functions when passing function pointer to kernel. */
/* Determine if the pointer is within the module's code memory. */
#define TXM_MODULE_MANAGER_CHECK_FUNCTION_POINTER(module_instance, pointer) \
if (((pointer < sizeof(TXM_MODULE_PREAMBLE) + (ULONG) module_instance -> txm_module_instance_code_start) || \
((pointer+sizeof(pointer)) > (ULONG) module_instance -> txm_module_instance_code_end)) \
&& (pointer != (ULONG) TX_NULL)) \
{ \
return(TX_PTR_ERROR); \
}
/* Define the macros to perform port-specific checks when passing pointers to the kernel. */
/* Define macro to make sure object is inside the module's data. */
#define TXM_MODULE_MANAGER_CHECK_INSIDE_DATA(module_instance, obj_ptr, obj_size) \
/* Check if it's inside module data. */ \
((((obj_ptr) >= (ALIGN_TYPE) module_instance -> txm_module_instance_data_start) && \
(((obj_ptr) + (obj_size)) <= ((ALIGN_TYPE) module_instance -> txm_module_instance_data_end + 1))) || \
/* Check if it's inside shared memory. */ \
(((obj_ptr) >= (ALIGN_TYPE) module_instance -> txm_module_instance_shared_memory_address) && \
(((obj_ptr) + (obj_size)) <= (ALIGN_TYPE) (module_instance -> txm_module_instance_shared_memory_address + module_instance -> txm_module_instance_shared_memory_length))))
/* Define some internal prototypes to this module port. */
@@ -311,21 +308,17 @@ typedef struct TXM_MODULE_MANAGER_MEMORY_FAULT_INFO_STRUCT
#endif
#define TXM_MODULE_MANAGER_ADDITIONAL_PROTOTYPES \
#define TXM_MODULE_MANAGER_ADDITIONAL_PROTOTYPES \
VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble, ULONG *code_size, ULONG *code_alignment, ULONG *data_size, ULONG *data_alignment); \
VOID _txm_module_manager_memory_fault_handler(VOID); \
UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *)); \
VOID _txm_module_manager_mm_register_setup(TXM_MODULE_INSTANCE *module_instance); \
ULONG _txm_power_of_two_block_size(ULONG size); \
ULONG _txm_module_manager_calculate_srd_bits(ULONG block_size, ULONG length); \
ULONG _txm_module_manager_region_size_get(ULONG block_size); \
UCHAR _txm_module_manager_shared_memory_check_outside(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE obj_ptr, UINT obj_size); \
UCHAR _txm_module_manager_shared_memory_check_inside(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE obj_ptr, UINT obj_size); \
UCHAR _txm_module_manager_shared_memory_check_inside_byte(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE obj_ptr);
VOID _txm_module_manager_memory_fault_handler(VOID); \
UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *)); \
VOID _txm_module_manager_mm_register_setup(TXM_MODULE_INSTANCE *module_instance); \
ULONG _txm_power_of_two_block_size(ULONG size); \
ULONG _txm_module_manager_calculate_srd_bits(ULONG block_size, ULONG length); \
ULONG _txm_module_manager_region_size_get(ULONG block_size);
#define TXM_MODULE_MANAGER_VERSION_ID \
CHAR _txm_module_manager_version_id[] = \
"Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M4/MPU/IAR Version 6.0.1 *";
"Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M4/MPU/IAR Version 6.1 *";
#endif

106
ports_module/cortex-m4/iar/module_lib/src/txm_module_thread_shell_entry.c
View File

@@ -10,15 +10,15 @@
/**************************************************************************/
/**************************************************************************/
/**************************************************************************/
/** */
/** ThreadX Component */
/** */
/** Module */
/** */
/**************************************************************************/
/**************************************************************************/
/**************************************************************************/
/**************************************************************************/
/** */
/** ThreadX Component */
/** */
/** Module */
/** */
/**************************************************************************/
/**************************************************************************/
#ifndef TXM_MODULE
#define TXM_MODULE
@@ -44,54 +44,54 @@ TXM_MODULE_THREAD_ENTRY_INFO *_txm_module_entry_info;
ULONG (*_txm_module_kernel_call_dispatcher)(ULONG kernel_request, ULONG param_1, ULONG param_2, ULONG param3);
/* Define the IAR startup code that clears the uninitialized global data and sets up the
/* Define the IAR startup code that clears the uninitialized global data and sets up the
preset global variables. */
extern VOID __iar_data_init3(VOID);
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _txm_module_thread_shell_entry Cortex-M4/MPU/IAR */
/* 6.0.1 */
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _txm_module_thread_shell_entry Cortex-M4/MPU/IAR */
/* 6.1 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
/* */
/* DESCRIPTION */
/* */
/* This function calls the specified entry function of the thread. It */
/* also provides a place for the thread's entry function to return. */
/* If the thread returns, this function places the thread in a */
/* "COMPLETED" state. */
/* */
/* INPUT */
/* */
/* thread_ptr Pointer to current thread */
/* thread_info Pointer to thread entry info */
/* */
/* OUTPUT */
/* */
/* None */
/* */
/* CALLS */
/* */
/* __iar_data_init3 IAR global initialization function*/
/* thread_entry Thread's entry function */
/* tx_thread_resume Resume the module callback thread */
/* _txm_module_thread_system_suspend Module thread suspension routine */
/* */
/* CALLED BY */
/* */
/* Initial thread stack frame */
/* */
/* RELEASE HISTORY */
/* */
/* DESCRIPTION */
/* */
/* This function calls the specified entry function of the thread. It */
/* also provides a place for the thread's entry function to return. */
/* If the thread returns, this function places the thread in a */
/* "COMPLETED" state. */
/* */
/* INPUT */
/* */
/* thread_ptr Pointer to current thread */
/* thread_info Pointer to thread entry info */
/* */
/* OUTPUT */
/* */
/* None */
/* */
/* CALLS */
/* */
/* __iar_data_init3 IAR global initialization function*/
/* thread_entry Thread's entry function */
/* tx_thread_resume Resume the module callback thread */
/* _txm_module_thread_system_suspend Module thread suspension routine */
/* */
/* CALLED BY */
/* */
/* Initial thread stack frame */
/* */
/* RELEASE HISTORY */
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 06-30-2020 Scott Larson Initial Version 6.0.1 */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* */
/**************************************************************************/
VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_ENTRY_INFO *thread_info)
@@ -102,25 +102,23 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN
#endif
/* Determine if this is the start thread. If so, we must prepare the module for
/* Determine if this is the start thread. If so, we must prepare the module for
execution. If not, simply skip the C startup code. */
if (thread_info -> txm_module_thread_entry_info_start_thread)
{
/* Initialize the IAR C environment. */
__iar_data_init3();
/* Save the entry info pointer, for later use. */
_txm_module_entry_info = thread_info;
/* Save the kernel function dispatch address. This is used to make all resident calls from
/* Save the kernel function dispatch address. This is used to make all resident calls from
the module. */
_txm_module_kernel_call_dispatcher = thread_info -> txm_module_thread_entry_info_kernel_call_dispatcher;
/* Ensure that we have a valid pointer. */
while (!_txm_module_kernel_call_dispatcher)
{
/* Loop here, if an error is present getting the dispatch function pointer!
An error here typically indicates the resident portion of _tx_thread_schedule
is not supporting the trap to obtain the function pointer. */
@@ -165,7 +163,7 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN
#endif
/* Call actual thread suspension routine. */
_txm_module_thread_system_suspend(thread_ptr);
_txm_module_thread_system_suspend(thread_ptr);
#ifdef TX_SAFETY_CRITICAL

2
ports_module/cortex-m4/iar/module_manager/src/tx_misra.s
View File

@@ -107,7 +107,7 @@
SECTION `.data`:DATA:REORDER:NOROOT(2)
DATA
// 51 CHAR _tx_version_id[100] = "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX 6.0.1 MISRA C Compliant *";
// 51 CHAR _tx_version_id[100] = "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX 6.1 MISRA C Compliant *";
_tx_version_id:
DC8 43H, 6FH, 70H, 79H, 72H, 69H, 67H, 68H
DC8 74H, 20H, 28H, 63H, 29H, 20H, 31H, 39H

25
ports_module/cortex-m4/iar/module_manager/src/tx_thread_context_restore.s
View File

@@ -21,33 +21,25 @@
;/**************************************************************************/
;
;
;#define TX_SOURCE_CODE
EXTERN _tx_execution_isr_exit
;
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_thread.h"
;#include "tx_timer.h"
;
;
EXTERN _tx_execution_isr_exit
;
;
SECTION `.text`:CODE:NOROOT(2)
THUMB
SECTION `.text`:CODE:NOROOT(2)
THUMB
;/**************************************************************************/
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_context_restore Cortex-M4/IAR */
;/* 6.0.1 */
;/* 6.1 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
;/* */
;/* DESCRIPTION */
;/* */
;/* This function is only needed for legacy applications and it should */
;/* not be called in any new development on a Cortex-M. */
;/* This function restores the interrupt context if it is processing a */
;/* nested interrupt. If not, it returns to the interrupt thread if no */
;/* preemption is necessary. Otherwise, if preemption is necessary or */
@@ -73,7 +65,7 @@
;/* */
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* 09-30-2020 William E. Lamie Initial Version 6.1 */
;/* */
;/**************************************************************************/
;VOID _tx_thread_context_restore(VOID)
@@ -94,5 +86,4 @@ _tx_thread_context_restore:
BX lr
;
;}
END
END

24
ports_module/cortex-m4/iar/module_manager/src/tx_thread_context_save.s
View File

@@ -21,33 +21,25 @@
;/**************************************************************************/
;
;
;#define TX_SOURCE_CODE
EXTERN _tx_execution_isr_enter
;
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_thread.h"
;#include "tx_timer.h"
;
;
EXTERN _tx_execution_isr_enter
;
;
SECTION `.text`:CODE:NOROOT(2)
THUMB
SECTION `.text`:CODE:NOROOT(2)
THUMB
;/**************************************************************************/
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_context_save Cortex-M4/IAR */
;/* 6.0.1 */
;/* 6.1 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
;/* */
;/* DESCRIPTION */
;/* */
;/* This function is only needed for legacy applications and it should */
;/* not be called in any new development on a Cortex-M. */
;/* This function saves the context of an executing thread in the */
;/* beginning of interrupt processing. The function also ensures that */
;/* the system stack is used upon return to the calling ISR. */
@@ -72,7 +64,7 @@
;/* */
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* 09-30-2020 William E. Lamie Initial Version 6.1 */
;/* */
;/**************************************************************************/
;VOID _tx_thread_context_save(VOID)
@@ -82,7 +74,7 @@ _tx_thread_context_save:
#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
;
; /* Call the ISR enter function to indicate an ISR is starting. */
;
;
PUSH {r0, lr} ; Save return address
BL _tx_execution_isr_enter ; Call the ISR enter function
POP {r0, lr} ; Recover return address

28
ports_module/cortex-m4/iar/module_manager/src/tx_thread_interrupt_control.s
View File

@@ -20,23 +20,15 @@
;/**************************************************************************/
;/**************************************************************************/
;
;#define TX_SOURCE_CODE
;
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_thread.h"
;
;
SECTION `.text`:CODE:NOROOT(2)
THUMB
SECTION `.text`:CODE:NOROOT(2)
THUMB
;/**************************************************************************/
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_interrupt_control Cortex-M4/IAR */
;/* 6.0.1 */
;/* 6.1 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
@@ -66,21 +58,17 @@
;/* */
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* 09-30-2020 William E. Lamie Initial Version 6.1 */
;/* */
;/**************************************************************************/
;UINT _tx_thread_interrupt_control(UINT new_posture)
;{
PUBLIC _tx_thread_interrupt_control
_tx_thread_interrupt_control:
;
; /* Pickup current interrupt lockout posture. */
;
MRS r1, PRIMASK
MSR PRIMASK, r0
MOV r0, r1
BX lr
MRS r1, PRIMASK ; Pickup current interrupt lockout
MSR PRIMASK, r0 ; Apply the new interrupt lockout
MOV r0, r1 ; Transfer old to return register
BX lr ; Return to caller
;
;}
END

16
ports_module/cortex-m4/iar/module_manager/src/tx_thread_interrupt_disable.s
View File

@@ -20,23 +20,15 @@
;/**************************************************************************/
;/**************************************************************************/
;
;#define TX_SOURCE_CODE
;
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_thread.h"
;
;
SECTION `.text`:CODE:NOROOT(2)
THUMB
SECTION `.text`:CODE:NOROOT(2)
THUMB
;/**************************************************************************/
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_interrupt_restore Cortex-M4/IAR */
;/* 6.0.1 */
;/* 6.1 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
@@ -66,7 +58,7 @@
;/* */
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* 09-30-2020 William E. Lamie Initial Version 6.1 */
;/* */
;/**************************************************************************/
;UINT _tx_thread_interrupt_disable(UINT new_posture)

16
ports_module/cortex-m4/iar/module_manager/src/tx_thread_interrupt_restore.s
View File

@@ -20,23 +20,15 @@
;/**************************************************************************/
;/**************************************************************************/
;
;#define TX_SOURCE_CODE
;
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_thread.h"
;
;
SECTION `.text`:CODE:NOROOT(2)
THUMB
SECTION `.text`:CODE:NOROOT(2)
THUMB
;/**************************************************************************/
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_interrupt_restore Cortex-M4/IAR */
;/* 6.0.1 */
;/* 6.1 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
@@ -66,7 +58,7 @@
;/* */
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* 09-30-2020 William E. Lamie Initial Version 6.1 */
;/* */
;/**************************************************************************/
;VOID _tx_thread_interrupt_restore(UINT new_posture)

249
ports_module/cortex-m4/iar/module_manager/src/tx_thread_schedule.s
View File

@@ -12,8 +12,8 @@
;
;/**************************************************************************/
;/**************************************************************************/
;/** */
;/** ThreadX Component */
;/** */
;/** ThreadX Component */
;/** */
;/** Thread */
;/** */
@@ -21,68 +21,58 @@
;/**************************************************************************/
;
;
;#define TX_SOURCE_CODE
;
#define TXM_MODULE_KERNEL_STACK_MAINTENANCE_DISABLE
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_thread.h"
;#include "tx_timer.h"
;
EXTERN _tx_thread_current_ptr
EXTERN _tx_thread_execute_ptr
EXTERN _tx_timer_time_slice
EXTERN _tx_thread_system_stack_ptr
EXTERN _tx_execution_thread_enter
EXTERN _tx_execution_thread_exit
EXTERN _tx_thread_preempt_disable
EXTERN _txm_module_manager_memory_fault_handler
EXTERN _txm_module_manager_memory_fault_info
EXTERN _tx_thread_current_ptr
EXTERN _tx_thread_execute_ptr
EXTERN _tx_timer_time_slice
EXTERN _tx_thread_system_stack_ptr
EXTERN _tx_execution_thread_enter
EXTERN _tx_execution_thread_exit
EXTERN _tx_thread_preempt_disable
EXTERN _txm_module_manager_memory_fault_handler
EXTERN _txm_module_manager_memory_fault_info
;
;
SECTION `.text`:CODE:NOROOT(2)
THUMB
;/**************************************************************************/
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_schedule Cortex-M4/MPU/IAR */
;/* 6.0.1 */
SECTION `.text`:CODE:NOROOT(2)
THUMB
;/**************************************************************************/
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_schedule Cortex-M4/MPU/IAR */
;/* 6.1 */
;/* AUTHOR */
;/* */
;/* Scott Larson, Microsoft Corporation */
;/* */
;/* DESCRIPTION */
;/* */
;/* This function waits for a thread control block pointer to appear in */
;/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */
;/* in the variable, the corresponding thread is resumed. */
;/* */
;/* INPUT */
;/* */
;/* None */
;/* */
;/* OUTPUT */
;/* */
;/* DESCRIPTION */
;/* */
;/* This function waits for a thread control block pointer to appear in */
;/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */
;/* in the variable, the corresponding thread is resumed. */
;/* */
;/* INPUT */
;/* */
;/* None */
;/* */
;/* CALLS */
;/* */
;/* */
;/* OUTPUT */
;/* */
;/* None */
;/* */
;/* CALLED BY */
;/* */
;/* _tx_initialize_kernel_enter ThreadX entry function */
;/* _tx_thread_system_return Return to system from thread */
;/* _tx_thread_context_restore Restore thread's context */
;/* */
;/* RELEASE HISTORY */
;/* */
;/* */
;/* CALLS */
;/* */
;/* None */
;/* */
;/* CALLED BY */
;/* */
;/* _tx_initialize_kernel_enter ThreadX entry function */
;/* _tx_thread_system_return Return to system from thread */
;/* _tx_thread_context_restore Restore thread's context */
;/* */
;/* RELEASE HISTORY */
;/* */
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 Scott Larson Initial Version 6.0.1 */
;/* 09-30-2020 Scott Larson Initial Version 6.1 */
;/* */
;/**************************************************************************/
;VOID _tx_thread_schedule(VOID)
@@ -95,7 +85,7 @@ _tx_thread_schedule:
; from the PendSV handling routines below. */
;
; /* Clear the preempt-disable flag to enable rescheduling after initialization on Cortex-M targets. */
;
;
MOV r0, #0 ; Build value for TX_FALSE
LDR r2, =_tx_thread_preempt_disable ; Build address of preempt disable flag
STR r0, [r2, #0] ; Clear preempt disable flag
@@ -104,7 +94,7 @@ _tx_thread_schedule:
;
#ifdef __ARMVFP__
MRS r0, CONTROL ; Pickup current CONTROL register
BIC r0, r0, #4 ; Clear the FPCA bit
BIC r0, r0, #4 ; Clear the FPCA bit
MSR CONTROL, r0 ; Setup new CONTROL register
#endif
;
@@ -112,26 +102,24 @@ _tx_thread_schedule:
;
LDR r0, =0xE000ED24 ; Build SHCSR address
LDR r1, =0x70000 ; Enable Usage, Bus, and MemManage faults
STR r1, [r0] ;
STR r1, [r0] ;
;
; /* Enable interrupts */
;
CPSIE i
;
;
; /* Enter the scheduler for the first time. */
;
MOV r0, #0x10000000 ; Load PENDSVSET bit
MOV r1, #0xE000E000 ; Load NVIC base
STR r0, [r1, #0xD04] ; Set PENDSVBIT in ICSR
NOP ;
NOP ;
NOP ;
NOP ;
;
; /* We should never get here - ever! */
;
BKPT 0xEF ; Setup error conditions
BX lr ;
DSB ; Complete all memory accesses
ISB ; Flush pipeline
; /* Wait here for the PendSV to take place. */
__tx_wait_here:
B __tx_wait_here ; Wait for the PendSV to happen
;}
;
@@ -193,7 +181,7 @@ UsageFault_Handler:
STR r0, [r12, #88] ; Save xPSR
MRS r0, CONTROL ; Pickup current CONTROL register
BIC r0, r0, #1 ; Clear the UNPRIV bit
BIC r0, r0, #1 ; Clear the UNPRIV bit
MSR CONTROL, r0 ; Setup new CONTROL register
LDR r0, =0xE000ED28 ; Build the Memory Management Fault Status Register (MMFSR)
@@ -209,7 +197,7 @@ UsageFault_Handler:
BIC r1, r1, #1 ; Clear the lazy preservation active bit
STR r1, [r0] ; Store the value
#endif
BL _txm_module_manager_memory_fault_handler ; Call memory manager fault handler
#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
@@ -237,15 +225,15 @@ UsageFault_Handler:
;
; /* Generic context PendSV handler. */
;
;
PUBLIC PendSV_Handler
PUBLIC __tx_PendSVHandler
PendSV_Handler:
__tx_PendSVHandler:
;
; /* Get current thread value and new thread pointer. */
;
__tx_ts_handler:
;
__tx_ts_handler:
#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
;
@@ -263,7 +251,7 @@ __tx_ts_handler:
LDR r1, [r0] ; Pickup current thread pointer
;
; /* Determine if there is a current thread to finish preserving. */
;
;
CBZ r1, __tx_ts_new ; If NULL, skip preservation
;
; /* Recover PSP and preserve current thread context. */
@@ -338,7 +326,7 @@ __tx_ts_restore:
MRS r5, CONTROL ; Pickup current CONTROL register
LDR r4, [r1, #0x98] ; Pickup current user mode flag
BIC r5, r5, #1 ; Clear the UNPRIV bit
BIC r5, r5, #1 ; Clear the UNPRIV bit
ORR r4, r4, r5 ; Build new CONTROL register
MSR CONTROL, r4 ; Setup new CONTROL register
@@ -347,7 +335,7 @@ __tx_ts_restore:
STR r3, [r0] ; Disable MPU
LDR r0, [r1, #0x90] ; Pickup the module instance pointer
CBZ r0, skip_mpu_setup ; Is this thread owned by a module? No, skip MPU setup
LDR r1, [r0, #0x64] ; Pickup MPU register[0]
LDR r1, [r0, #0x64] ; Pickup MPU register[0]
CBZ r1, skip_mpu_setup ; Is protection required for this module? No, skip MPU setup
LDR r1, =0xE000ED9C ; Build address of MPU base register
@@ -358,13 +346,13 @@ __tx_ts_restore:
LDM r0,{r2-r9} ; Load second four MPU regions
STM r1,{r2-r9} ; Store second four MPU regions
LDR r0, =0xE000ED94 ; Build MPU control reg address
MOV r1, #5 ; Build enable value
MOV r1, #5 ; Build enable value with background region enabled
STR r1, [r0] ; Enable MPU
skip_mpu_setup:
LDMIA r12!, {LR} ; Pickup LR
#ifdef __ARMVFP__
TST LR, #0x10 ; Determine if the VFP extended frame is present
BNE _skip_vfp_restore ; If not, skip VFP restore
BNE _skip_vfp_restore ; If not, skip VFP restore
VLDMIA r12!, {s16-s31} ; Yes, restore additional VFP registers
_skip_vfp_restore:
#endif
@@ -372,11 +360,11 @@ _skip_vfp_restore:
MSR PSP, r12 ; Setup the thread's stack pointer
;
; /* Return to thread. */
;
;
BX lr ; Return to thread!
;
; /* The following is the idle wait processing... in this case, no threads are ready for execution and the
; system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts
; system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts
; are disabled to allow use of WFI for waiting for a thread to arrive. */
;
__tx_ts_wait:
@@ -392,16 +380,16 @@ __tx_ts_wait:
CPSIE i ; Enable interrupts
B __tx_ts_wait ; Loop to continue waiting
;
; /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are
; /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are
; already in the handler! */
;
__tx_ts_ready:
MOV r7, #0x08000000 ; Build clear PendSV value
MOV r8, #0xE000E000 ; Build base NVIC address
STR r7, [r8, #0xD04] ; Clear any PendSV
STR r7, [r8, #0xD04] ; Clear any PendSV
;
; /* Re-enable interrupts and restore new thread. */
;
;
CPSIE i ; Enable interrupts
B __tx_ts_restore ; Restore the thread
;}
@@ -429,7 +417,7 @@ __tx_SVCallHandler:
CMP r1, r2 ; Did we come from user_mode_entry?
IT NE ; If no (not equal), then...
BXNE lr ; return from where we came.
LDR r3, [r0, #20] ; This is the saved LR
LDR r1, =_tx_thread_current_ptr ; Build current thread pointer address
LDR r2, [r1] ; Pickup current thread pointer
@@ -438,73 +426,72 @@ __tx_SVCallHandler:
STR r3, [r2, #0xA0] ; Save the original LR in thread control block
; If there is memory protection, use kernel stack
LDR r0, [r2, #0x90] ; Load the module instance ptr
LDR r0, [r0, #0x0C] ; Load the module property flags
TST r0, #2 ; Check if memory protected
LDR r0, [r2, #0x90] ; Load the module instance ptr
LDR r0, [r0, #0x0C] ; Load the module property flags
TST r0, #2 ; Check if memory protected
BEQ _tx_skip_kernel_stack_enter
; Switch to the module thread's kernel stack
LDR r0, [r2, #0xA8] ; Load the module kernel stack end
LDR r0, [r2, #0xA8] ; Load the module kernel stack end
#ifndef TXM_MODULE_KERNEL_STACK_MAINTENANCE_DISABLE
LDR r1, [r2, #0xA4] ; Load the module kernel stack start
LDR r3, [r2, #0xAC] ; Load the module kernel stack size
STR r1, [r2, #12] ; Set stack start
STR r0, [r2, #16] ; Set stack end
STR r3, [r2, #20] ; Set stack size
LDR r1, [r2, #0xA4] ; Load the module kernel stack start
LDR r3, [r2, #0xAC] ; Load the module kernel stack size
STR r1, [r2, #12] ; Set stack start
STR r0, [r2, #16] ; Set stack end
STR r3, [r2, #20] ; Set stack size
#endif
MRS r3, PSP ; Pickup thread stack pointer
STR r3, [r2, #0xB0] ; Save thread stack pointer
MRS r3, PSP ; Pickup thread stack pointer
STR r3, [r2, #0xB0] ; Save thread stack pointer
; Build kernel stack by copying thread stack two registers at a time
ADD r3, r3, #32 ; start at bottom of hardware stack
LDMDB r3!,{r1-r2} ;
STMDB r0!,{r1-r2} ;
LDMDB r3!,{r1-r2} ;
STMDB r0!,{r1-r2} ;
LDMDB r3!,{r1-r2} ;
STMDB r0!,{r1-r2} ;
LDMDB r3!,{r1-r2} ;
STMDB r0!,{r1-r2} ;
ADD r3, r3, #32 ; start at bottom of hardware stack
LDMDB r3!,{r1-r2}
STMDB r0!,{r1-r2}
LDMDB r3!,{r1-r2}
STMDB r0!,{r1-r2}
LDMDB r3!,{r1-r2}
STMDB r0!,{r1-r2}
LDMDB r3!,{r1-r2}
STMDB r0!,{r1-r2}
MSR PSP, r0 ; Set kernel stack pointer
_tx_skip_kernel_stack_enter:
MSR PSP, r0 ; Set kernel stack pointer
_tx_skip_kernel_stack_enter:
MRS r0, CONTROL ; Pickup current CONTROL register
BIC r0, r0, #1 ; Clear the UNPRIV bit
BIC r0, r0, #1 ; Clear the UNPRIV bit
MSR CONTROL, r0 ; Setup new CONTROL register
BX lr ; Return to thread
_tx_thread_user_return:
LDR r2, =_txm_module_user_mode_exit-1 ; Subtract 1 because of THUMB mode.
CMP r1, r2 ; Did we come from user_mode_exit?
IT NE ; If no (not equal), then...
BXNE lr ; return from where we came
LDR r1, =_tx_thread_current_ptr ; Build current thread pointer address
LDR r2, [r1] ; Pickup current thread pointer
LDR r1, [r2, #0x9C] ; Pick up user mode
STR r1, [r2, #0x98] ; Set the current user mode selection for thread
; If there is memory protection, use kernel stack
LDR r0, [r2, #0x90] ; Load the module instance ptr
LDR r0, [r0, #0x0C] ; Load the module property flags
TST r0, #2 ; Check if memory protected
LDR r0, [r2, #0x90] ; Load the module instance ptr
LDR r0, [r0, #0x0C] ; Load the module property flags
TST r0, #2 ; Check if memory protected
BEQ _tx_skip_kernel_stack_exit
#ifndef TXM_MODULE_KERNEL_STACK_MAINTENANCE_DISABLE
LDR r0, [r2, #0xB4] ; Load the module thread stack start
LDR r1, [r2, #0xB8] ; Load the module thread stack end
LDR r3, [r2, #0xBC] ; Load the module thread stack size
STR r0, [r2, #12] ; Set stack start
STR r1, [r2, #16] ; Set stack end
STR r3, [r2, #20] ; Set stack size
#endif
LDR r0, [r2, #0xB0] ; Load the module thread stack pointer
MRS r3, PSP ; Pickup kernel stack pointer
; Copy kernel hardware stack to module thread stack.
#ifndef TXM_MODULE_KERNEL_STACK_MAINTENANCE_DISABLE
LDR r0, [r2, #0xB4] ; Load the module thread stack start
LDR r1, [r2, #0xB8] ; Load the module thread stack end
LDR r3, [r2, #0xBC] ; Load the module thread stack size
STR r0, [r2, #12] ; Set stack start
STR r1, [r2, #16] ; Set stack end
STR r3, [r2, #20] ; Set stack size
#endif
LDR r0, [r2, #0xB0] ; Load the module thread stack pointer
MRS r3, PSP ; Pickup kernel stack pointer
; Copy kernel hardware stack to module thread stack.
LDM r3!,{r1-r2}
STM r0!,{r1-r2}
LDM r3!,{r1-r2}
@@ -513,13 +500,13 @@ _tx_thread_user_return:
STM r0!,{r1-r2}
LDM r3!,{r1-r2}
STM r0!,{r1-r2}
SUB r0, r0, #32 ; Subtract 32 to get back to top of stack
MSR PSP, r0 ; Set thread stack pointer
SUB r0, r0, #32 ; Subtract 32 to get back to top of stack
MSR PSP, r0 ; Set thread stack pointer
LDR r1, =_tx_thread_current_ptr ; Build current thread pointer address
LDR r2, [r1] ; Pickup current thread pointer
LDR r1, [r2, #0x9C] ; Pick up user mode
_tx_skip_kernel_stack_exit:
MRS r0, CONTROL ; Pickup current CONTROL register
ORR r0, r0, r1 ; OR in the user mode bit
@@ -544,7 +531,7 @@ _txm_module_priv:
; At this point, we are out of user mode. The original LR has been saved in the
; thread control block. Simply call the kernel dispatch function.
BL _txm_module_manager_kernel_dispatch
; Pickup the original LR value while still in privileged mode
LDR r2, =_tx_thread_current_ptr ; Build current thread pointer address
LDR r3, [r2] ; Pickup current thread pointer
@@ -552,7 +539,7 @@ _txm_module_priv:
SVC 2 ; Exit kernel and return to user mode
_txm_module_user_mode_exit:
BX lr ; Return to the caller
BX lr ; Return to the caller
NOP
NOP
NOP
@@ -565,7 +552,7 @@ _txm_module_user_mode_exit:
PUBLIC tx_thread_fpu_enable
tx_thread_fpu_enable:
;
; /* Automatic VPF logic is supported, this function is present only for
; /* Automatic VPF logic is supported, this function is present only for
; backward compatibility purposes and therefore simply returns. */
;
BX LR ; Return to caller
@@ -573,7 +560,7 @@ tx_thread_fpu_enable:
PUBLIC tx_thread_fpu_disable
tx_thread_fpu_disable:
;
; /* Automatic VPF logic is supported, this function is present only for
; /* Automatic VPF logic is supported, this function is present only for
; backward compatibility purposes and therefore simply returns. */
;
BX LR ; Return to caller

15
ports_module/cortex-m4/iar/module_manager/src/tx_thread_stack_build.s
View File

@@ -21,14 +21,14 @@
;/**************************************************************************/
;
;
SECTION `.text`:CODE:NOROOT(2)
THUMB
SECTION `.text`:CODE:NOROOT(2)
THUMB
;/**************************************************************************/
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_stack_build Cortex-M4/IAR */
;/* 6.0.1 */
;/* 6.1 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
@@ -60,7 +60,7 @@
;/* */
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* 09-30-2020 William E. Lamie Initial Version 6.1 */
;/* */
;/**************************************************************************/
;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID))
@@ -68,11 +68,11 @@
PUBLIC _tx_thread_stack_build
_tx_thread_stack_build:
;
;
;
; /* Build a fake interrupt frame. The form of the fake interrupt stack
; on the Cortex-M should look like the following after it is built:
;
; Stack Top:
;
; Stack Top:
; LR Interrupted LR (LR at time of PENDSV)
; r4 Initial value for r4
; r5 Initial value for r5
@@ -132,4 +132,3 @@ _tx_thread_stack_build:
BX lr ; Return to caller
;}
END

27
ports_module/cortex-m4/iar/module_manager/src/tx_thread_system_return.s
View File

@@ -20,25 +20,15 @@
;/**************************************************************************/
;/**************************************************************************/
;
;#define TX_SOURCE_CODE
;
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_thread.h"
;#include "tx_timer.h"
;
;
;
SECTION `.text`:CODE:NOROOT(2)
THUMB
SECTION `.text`:CODE:NOROOT(2)
THUMB
;/**************************************************************************/
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_system_return Cortex-M4/IAR */
;/* 6.0.1 */
;/* 6.1 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
@@ -70,7 +60,7 @@
;/* */
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* 09-30-2020 William E. Lamie Initial Version 6.1 */
;/* */
;/**************************************************************************/
;VOID _tx_thread_system_return(VOID)
@@ -79,9 +69,9 @@
_tx_thread_system_return??rA:
_tx_thread_system_return:
;
; /* Return to real scheduler via PendSV. Note that this routine is often
; /* Return to real scheduler via PendSV. Note that this routine is often
; replaced with in-line assembly in tx_port.h to improved performance. */
;
;
MOV r0, #0x10000000 ; Load PENDSVSET bit
MOV r1, #0xE000E000 ; Load NVIC base
STR r0, [r1, #0xD04] ; Set PENDSVBIT in ICSR
@@ -92,7 +82,6 @@ _tx_thread_system_return:
CPSIE i ; Enable interrupts
MSR PRIMASK, r1 ; Restore original interrupt posture
_isr_context:
BX lr ; Return to caller
BX lr ; Return to caller
;}
END
END

26
ports_module/cortex-m4/iar/module_manager/src/tx_timer_interrupt.s
View File

@@ -20,17 +20,6 @@
;/**************************************************************************/
;/**************************************************************************/
;
;#define TX_SOURCE_CODE
;
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_timer.h"
;#include "tx_thread.h"
;
;
;Define Assembly language external references...
;
EXTERN _tx_timer_time_slice
EXTERN _tx_timer_system_clock
@@ -46,14 +35,14 @@
EXTERN _tx_thread_preempt_disable
;
;
SECTION `.text`:CODE:NOROOT(2)
THUMB
SECTION `.text`:CODE:NOROOT(2)
THUMB
;/**************************************************************************/
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* _tx_timer_interrupt Cortex-M4/IAR */
;/* 6.0.1 */
;/* 6.1 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
@@ -86,7 +75,7 @@
;/* */
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* 09-30-2020 William E. Lamie Initial Version 6.1 */
;/* */
;/**************************************************************************/
;VOID _tx_timer_interrupt(VOID)
@@ -109,7 +98,7 @@ _tx_timer_interrupt:
; if (_tx_timer_time_slice)
; {
;
MOV32 r3, _tx_timer_time_slice ; Pickup address of time-slice
MOV32 r3, _tx_timer_time_slice ; Pickup address of time-slice
LDR r2, [r3, #0] ; Pickup time-slice
CBZ r2, __tx_timer_no_time_slice ; Is it non-active?
; Yes, skip time-slice processing
@@ -226,13 +215,13 @@ __tx_timer_dont_activate:
; if (_tx_timer_expired_time_slice)
; {
;
MOV32 r3, _tx_timer_expired_time_slice ; Pickup addr of time-slice expired
MOV32 r3, _tx_timer_expired_time_slice ; Pickup addr of time-slice expired
LDR r2, [r3, #0] ; Pickup the actual flag
CBZ r2, __tx_timer_not_ts_expiration ; See if the flag is set
; No, skip time-slice processing
;
; /* Time slice interrupted thread. */
; _tx_thread_time_slice();
; _tx_thread_time_slice();
BL _tx_thread_time_slice ; Call time-slice processing
MOV32 r0, _tx_thread_preempt_disable ; Build address of preempt disable flag
@@ -265,4 +254,3 @@ __tx_timer_nothing_expired:
;
;}
END

33
ports_module/cortex-m4/iar/module_manager/src/txm_module_manager_alignment_adjust.c
View File

@@ -31,7 +31,7 @@
/* FUNCTION RELEASE */
/* */
/* _txm_power_of_two_block_size Cortex-M4/MPU/IAR */
/* 6.0.1 */
/* 6.1 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -61,7 +61,7 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 06-30-2020 Scott Larson Initial Version 6.0.1 */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* */
/**************************************************************************/
ULONG _txm_power_of_two_block_size(ULONG size)
@@ -69,11 +69,11 @@ ULONG _txm_power_of_two_block_size(ULONG size)
/* Check for 0 size. */
if(size == 0)
return 0;
/* Minimum MPU block size is 32. */
if(size <= 32)
return 32;
/* Bit twiddling trick to round to next high power of 2
(if original size is power of 2, it will return original size. Perfect!) */
size--;
@@ -83,7 +83,7 @@ ULONG _txm_power_of_two_block_size(ULONG size)
size |= size >> 8;
size |= size >> 16;
size++;
/* Return a power of 2 size at or above the input size. */
return(size);
}
@@ -94,15 +94,15 @@ ULONG _txm_power_of_two_block_size(ULONG size)
/* FUNCTION RELEASE */
/* */
/* _txm_module_manager_alignment_adjust Cortex-M4/MPU/IAR */
/* 6.0.1 */
/* 6.1 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
/* */
/* DESCRIPTION */
/* */
/* This function adjusts the alignment and size of the code and data */
/* section for a given module implementation. */
/* This function adjusts the alignment and size of the code and data */
/* section for a given module implementation. */
/* */
/* INPUT */
/* */
@@ -128,7 +128,7 @@ ULONG _txm_power_of_two_block_size(ULONG size)
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 06-30-2020 Scott Larson Initial Version 6.0.1 */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* */
/**************************************************************************/
VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble,
@@ -253,19 +253,18 @@ ULONG data_size_accum;
/* Just set block size to 32MB just to create an allocation error! */
code_block_size = 33554432;
}
/* Calculate the new code size. */
local_code_size = code_block_size*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1);
/* Determine if the code block size is greater than the current alignment. If so, use block size
as the alignment. */
if (code_block_size > local_code_alignment)
local_code_alignment = code_block_size;
}
else
{
/* Determine code block sizes. Minimize the alignment requirement.
There are 4 MPU code entries available. The following is how the code size
will be distributed:
@@ -279,11 +278,10 @@ ULONG data_size_accum;
code_size_accum = code_size_accum + _txm_power_of_two_block_size(local_code_size - code_size_accum);
local_code_size = code_size_accum;
}
/* Determine the best data block size, which in our case is the minimal alignment. */
if (local_data_size <= (32*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES))
{
/* Block size of 32 is best. */
data_block_size = 32;
}
@@ -374,7 +372,6 @@ ULONG data_size_accum;
}
else
{
/* Just set data block size to 32MB just to create an allocation error! */
data_block_size = 33554432;
}
@@ -386,11 +383,13 @@ ULONG data_size_accum;
data_size_accum += data_block_size;
}
local_data_size = data_size_accum;
/* Determine if the data block size is greater than the current alignment. If so, use block size
as the alignment. */
if (data_block_size > local_data_alignment)
{
local_data_alignment = data_block_size;
}
/* Return all the information to the caller. */
*code_size = local_code_size;

104
ports_module/cortex-m4/iar/module_manager/src/txm_module_manager_external_memory_enable.c
View File

@@ -10,15 +10,15 @@
/**************************************************************************/
/**************************************************************************/
/**************************************************************************/
/** */
/** ThreadX Component */
/** */
/** Module Manager */
/** */
/**************************************************************************/
/**************************************************************************/
/**************************************************************************/
/**************************************************************************/
/** */
/** ThreadX Component */
/** */
/** Module Manager */
/** */
/**************************************************************************/
/**************************************************************************/
#define TX_SOURCE_CODE
@@ -29,52 +29,53 @@
#include "txm_module.h"
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _txm_module_manager_external_memory_enable Cortex-M4/MPU/IAR */
/* 6.0.1 */
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _txm_module_manager_external_memory_enable Cortex-M4/MPU/IAR */
/* 6.1 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
/* */
/* DESCRIPTION */
/* */
/* This function creates an entry in the MPU table for a shared */
/* memory space. */
/* */
/* INPUT */
/* */
/* module_instance Module instance pointer */
/* start_address Start address of memory */
/* length Length of external memory */
/* attributes Memory attributes (r/w) */
/* */
/* OUTPUT */
/* */
/* status Completion status */
/* */
/* CALLS */
/* */
/* _tx_mutex_get Get protection mutex */
/* _tx_mutex_put Release protection mutex */
/* _txm_power_of_two_block_size Round length to power of two */
/* */
/* CALLED BY */
/* */
/* Application code */
/* */
/* RELEASE HISTORY */
/* */
/* DESCRIPTION */
/* */
/* This function creates an entry in the MPU table for a shared */
/* memory space. */
/* */
/* INPUT */
/* */
/* module_instance Module instance pointer */
/* start_address Start address of memory */
/* length Length of external memory */
/* attributes Memory attributes (r/w) */
/* */
/* OUTPUT */
/* */
/* status Completion status */
/* */
/* CALLS */
/* */
/* _tx_mutex_get Get protection mutex */
/* _tx_mutex_put Release protection mutex */
/* _txm_power_of_two_block_size Round length to power of two */
/* _txm_module_manager_mm_register_setup Reconfigure MPU registers */
/* */
/* CALLED BY */
/* */
/* Application code */
/* */
/* RELEASE HISTORY */
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 06-30-2020 Scott Larson Initial Version 6.0.1 */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* */
/**************************************************************************/
UINT _txm_module_manager_external_memory_enable(TXM_MODULE_INSTANCE *module_instance,
VOID *start_address,
ULONG length,
UINT _txm_module_manager_external_memory_enable(TXM_MODULE_INSTANCE *module_instance,
VOID *start_address,
ULONG length,
UINT attributes)
{
@@ -88,15 +89,13 @@ TXM_MODULE_PREAMBLE *module_preamble;
/* Determine if the module manager has not been initialized yet. */
if (_txm_module_manager_ready != TX_TRUE)
{
/* Module manager has not been initialized. */
return(TX_NOT_AVAILABLE);
return(TX_NOT_AVAILABLE);
}
/* Determine if the module is valid. */
if (module_instance == TX_NULL)
{
/* Invalid module pointer. */
return(TX_PTR_ERROR);
}
@@ -107,7 +106,6 @@ TXM_MODULE_PREAMBLE *module_preamble;
/* Determine if the module instance is valid. */
if (module_instance -> txm_module_instance_id != TXM_MODULE_ID)
{
/* Release the protection mutex. */
_tx_mutex_put(&_txm_module_manager_mutex);
@@ -118,7 +116,6 @@ TXM_MODULE_PREAMBLE *module_preamble;
/* Determine if the module instance is in the loaded state. */
if (module_instance -> txm_module_instance_state != TXM_MODULE_LOADED)
{
/* Release the protection mutex. */
_tx_mutex_put(&_txm_module_manager_mutex);
@@ -138,7 +135,7 @@ TXM_MODULE_PREAMBLE *module_preamble;
return(TXM_MODULE_INVALID_PROPERTIES);
}
/* Start address and length must adhere to Cortex-M MPU.
/* Start address and length must adhere to Cortex-M MPU.
The address must align with the block size. */
block_size = _txm_power_of_two_block_size(length);
@@ -183,4 +180,3 @@ TXM_MODULE_PREAMBLE *module_preamble;
/* Return success. */
return(TX_SUCCESS);
}

86
ports_module/cortex-m4/iar/module_manager/src/txm_module_manager_memory_fault_handler.c
View File

@@ -10,15 +10,15 @@
/**************************************************************************/
/**************************************************************************/
/**************************************************************************/
/** */
/** ThreadX Component */
/** */
/** Module Manager */
/** */
/**************************************************************************/
/**************************************************************************/
/**************************************************************************/
/**************************************************************************/
/** */
/** ThreadX Component */
/** */
/** Module Manager */
/** */
/**************************************************************************/
/**************************************************************************/
#define TX_SOURCE_CODE
@@ -33,50 +33,50 @@
VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTANCE *);
/* Define a macro that can be used to allocate global variables useful to
store information about the last fault. This macro is defined in
/* Define a macro that can be used to allocate global variables useful to
store information about the last fault. This macro is defined in
txm_module_port.h and is usually populated in the assembly language
fault handling prior to the code calling _txm_module_manager_memory_fault_handler. */
TXM_MODULE_MANAGER_FAULT_INFO
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _txm_module_manager_memory_fault_handler Cortex-M4/MPU/IAR */
/* 6.0.1 */
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _txm_module_manager_memory_fault_handler Cortex-M4/MPU/IAR */
/* 6.1 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
/* */
/* DESCRIPTION */
/* */
/* This function handles a fault associated with a memory protected */
/* module. */
/* */
/* INPUT */
/* */
/* None */
/* */
/* OUTPUT */
/* */
/* None */
/* */
/* CALLS */
/* */
/* _tx_thread_terminate Terminate thread */
/* */
/* CALLED BY */
/* */
/* Fault handler */
/* */
/* RELEASE HISTORY */
/* */
/* DESCRIPTION */
/* */
/* This function handles a fault associated with a memory protected */
/* module. */
/* */
/* INPUT */
/* */
/* None */
/* */
/* OUTPUT */
/* */
/* None */
/* */
/* CALLS */
/* */
/* _tx_thread_terminate Terminate thread */
/* */
/* CALLED BY */
/* */
/* Fault handler */
/* */
/* RELEASE HISTORY */
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 06-30-2020 Scott Larson Initial Version 6.0.1 */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* */
/**************************************************************************/
VOID _txm_module_manager_memory_fault_handler(VOID)
@@ -85,7 +85,6 @@ VOID _txm_module_manager_memory_fault_handler(VOID)
TXM_MODULE_INSTANCE *module_instance_ptr;
TX_THREAD *thread_ptr;
/* Pickup the current thread. */
thread_ptr = _tx_thread_current_ptr;
@@ -95,7 +94,6 @@ TX_THREAD *thread_ptr;
/* Is there a thread? */
if (thread_ptr)
{
/* Pickup the module instance. */
module_instance_ptr = thread_ptr -> tx_thread_module_instance_ptr;
@@ -106,9 +104,7 @@ TX_THREAD *thread_ptr;
/* Determine if there is a user memory fault notification callback. */
if (_txm_module_manager_fault_notify)
{
/* Yes, call the user's notification memory fault callback. */
(_txm_module_manager_fault_notify)(thread_ptr, module_instance_ptr);
}
}

84
ports_module/cortex-m4/iar/module_manager/src/txm_module_manager_memory_fault_notify.c
View File

@@ -10,15 +10,15 @@
/**************************************************************************/
/**************************************************************************/
/**************************************************************************/
/** */
/** ThreadX Component */
/** */
/** Module Manager */
/** */
/**************************************************************************/
/**************************************************************************/
/**************************************************************************/
/**************************************************************************/
/** */
/** ThreadX Component */
/** */
/** Module Manager */
/** */
/**************************************************************************/
/**************************************************************************/
#define TX_SOURCE_CODE
@@ -34,53 +34,51 @@ extern VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTA
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _txm_module_manager_memory_fault_notify Cortex-M4/MPU/IAR */
/* 6.0.1 */
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _txm_module_manager_memory_fault_notify Cortex-M4/MPU/IAR */
/* 6.1 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
/* */
/* DESCRIPTION */
/* */
/* This function registers an application callback when/if a memory */
/* fault occurs. The supplied thread is automatically terminated, but */
/* any other threads in the same module may still execute. */
/* */
/* INPUT */
/* */
/* notify_function Memory fault notification */
/* function, NULL disables. */
/* */
/* OUTPUT */
/* */
/* status Completion status */
/* */
/* CALLS */
/* */
/* None */
/* */
/* CALLED BY */
/* */
/* Application Code */
/* */
/* RELEASE HISTORY */
/* */
/* DESCRIPTION */
/* */
/* This function registers an application callback when/if a memory */
/* fault occurs. The supplied thread is automatically terminated, but */
/* any other threads in the same module may still execute. */
/* */
/* INPUT */
/* */
/* notify_function Memory fault notification */
/* function, NULL disables. */
/* */
/* OUTPUT */
/* */
/* status Completion status */
/* */
/* CALLS */
/* */
/* None */
/* */
/* CALLED BY */
/* */
/* Application Code */
/* */
/* RELEASE HISTORY */
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 06-30-2020 Scott Larson Initial Version 6.0.1 */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* */
/**************************************************************************/
UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *))
{
/* Setup notification function. */
_txm_module_manager_fault_notify = notify_function;
/* Return success. */
return(TX_SUCCESS);
}

411
ports_module/cortex-m4/iar/module_manager/src/txm_module_manager_mm_register_setup.c
View File

@@ -10,59 +10,58 @@
/**************************************************************************/
/**************************************************************************/
/**************************************************************************/
/** */
/** ThreadX Component */
/** */
/** Module Manager */
/** */
/**************************************************************************/
/**************************************************************************/
/**************************************************************************/
/**************************************************************************/
/** */
/** ThreadX Component */
/** */
/** Module Manager */
/** */
/**************************************************************************/
/**************************************************************************/
#define TX_SOURCE_CODE
#include "tx_api.h"
#include "txm_module.h"
#include "txm_module_manager_util.h"
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _txm_module_manager_region_size_get Cortex-M4/MPU/IAR */
/* 6.0.1 */
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _txm_module_manager_region_size_get Cortex-M4/MPU/IAR */
/* 6.1 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
/* */
/* DESCRIPTION */
/* */
/* This function converts the region size in bytes to the block size */
/* for the Cortex-M4 MPU specification. */
/* */
/* INPUT */
/* */
/* block_size Size of the block in bytes */
/* */
/* OUTPUT */
/* */
/* MPU size specification */
/* */
/* CALLS */
/* */
/* None */
/* */
/* CALLED BY */
/* */
/* _txm_module_manager_mm_register_setup */
/* */
/* RELEASE HISTORY */
/* */
/* DESCRIPTION */
/* */
/* This function converts the region size in bytes to the block size */
/* for the Cortex-M4 MPU specification. */
/* */
/* INPUT */
/* */
/* block_size Size of the block in bytes */
/* */
/* OUTPUT */
/* */
/* MPU size specification */
/* */
/* CALLS */
/* */
/* None */
/* */
/* CALLED BY */
/* */
/* _txm_module_manager_mm_register_setup */
/* */
/* RELEASE HISTORY */
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 06-30-2020 Scott Larson Initial Version 6.0.1 */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* */
/**************************************************************************/
ULONG _txm_module_manager_region_size_get(ULONG block_size)
@@ -70,7 +69,6 @@ ULONG _txm_module_manager_region_size_get(ULONG block_size)
ULONG return_value;
/* Process relative to the input block size. */
if (block_size == 32)
{
@@ -140,7 +138,7 @@ ULONG return_value;
{
return_value = 0x14;
}
else
else
{
/* Max 4MB MPU pages for modules. */
return_value = 0x15;
@@ -150,45 +148,43 @@ ULONG return_value;
}
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _txm_module_manager_calculate_srd_bits Cortex-M4/MPU/IAR */
/* 6.0.1 */
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _txm_module_manager_calculate_srd_bits Cortex-M4/MPU/IAR */
/* 6.1 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
/* */
/* DESCRIPTION */
/* */
/* This function calculates the SRD bits that need to be set to */
/* protect "length" bytes in a block. */
/* */
/* INPUT */
/* */
/* block_size Size of the block in bytes */
/* length Actual length in bytes */
/* */
/* OUTPUT */
/* */
/* SRD bits to be OR'ed with region attribute register. */
/* */
/* CALLS */
/* */
/* None */
/* */
/* CALLED BY */
/* */
/* _txm_module_manager_mm_register_setup */
/* */
/* RELEASE HISTORY */
/* */
/* DESCRIPTION */
/* */
/* This function calculates the SRD bits that need to be set to */
/* protect "length" bytes in a block. */
/* */
/* INPUT */
/* */
/* block_size Size of the block in bytes */
/* length Actual length in bytes */
/* */
/* OUTPUT */
/* */
/* SRD bits to be OR'ed with region attribute register. */
/* */
/* CALLS */
/* */
/* None */
/* */
/* CALLED BY */
/* */
/* _txm_module_manager_mm_register_setup */
/* */
/* RELEASE HISTORY */
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 06-30-2020 Scott Larson Initial Version 6.0.1 */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* */
/**************************************************************************/
ULONG _txm_module_manager_calculate_srd_bits(ULONG block_size, ULONG length)
@@ -230,43 +226,42 @@ UINT srd_bit_index;
}
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _txm_module_manager_mm_register_setup Cortex-M4/MPU/IAR */
/* 6.0.1 */
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _txm_module_manager_mm_register_setup Cortex-M4/MPU/IAR */
/* 6.1 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
/* */
/* DESCRIPTION */
/* */
/* This function sets up the Cortex-M4 MPU register definitions based */
/* on the module's memory characteristics. */
/* */
/* INPUT */
/* */
/* module_instance Pointer to module instance */
/* */
/* OUTPUT */
/* */
/* MPU specifications for module in module_instance */
/* */
/* CALLS */
/* */
/* _txm_module_manager_region_size_get */
/* */
/* CALLED BY */
/* */
/* _txm_module_manager_thread_create */
/* */
/* RELEASE HISTORY */
/* */
/* DESCRIPTION */
/* */
/* This function sets up the Cortex-M4 MPU register definitions based */
/* on the module's memory characteristics. */
/* */
/* INPUT */
/* */
/* module_instance Pointer to module instance */
/* */
/* OUTPUT */
/* */
/* MPU specifications for module in module_instance */
/* */
/* CALLS */
/* */
/* _txm_module_manager_region_size_get */
/* */
/* CALLED BY */
/* */
/* _txm_module_manager_thread_create */
/* */
/* RELEASE HISTORY */
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 06-30-2020 Scott Larson Initial Version 6.0.1 */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* */
/**************************************************************************/
VOID _txm_module_manager_mm_register_setup(TXM_MODULE_INSTANCE *module_instance)
@@ -291,9 +286,11 @@ UINT i;
/* Setup the first region for the ThreadX trampoline code. */
/* Set base register to user mode entry, which is guaranteed to be at least 32-byte aligned. */
base_address_register = (ULONG) _txm_module_manager_user_mode_entry;
/* Mask address to proper range, region 0, set Valid bit. */
base_address_register = (base_address_register & 0xFFFFFFE0) | mpu_register | 0x10;
module_instance -> txm_module_instance_mpu_registers[0] = base_address_register;
/* Attributes: read only, write-back, shareable, size 32 bytes, region enabled. */
module_instance -> txm_module_instance_mpu_registers[1] = 0x06070009;
@@ -304,11 +301,10 @@ UINT i;
mpu_table_index = 2;
/* Setup values for code area. */
code_address = (ULONG) module_instance -> txm_module_instance_code_start;
code_address = (ULONG) module_instance -> txm_module_instance_code_start;
code_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_code_size;
/* Check if shared memory was set up. If so, only 3 entries are available for
/* Check if shared memory was set up. If so, only 3 entries are available for
code protection. If not set up, 4 code entries are available. */
if(module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_INDEX] == 0)
{
@@ -352,7 +348,7 @@ UINT i;
/* Calculate the region size information. */
region_size = (_txm_module_manager_region_size_get(block_size) << 1);
/* Build the base attribute register. */
base_attribute_register = region_size | srd_bits | 0x06070001;
@@ -385,7 +381,6 @@ UINT i;
/* Now loop through to setup MPU protection for the code area. */
for (i = 0; i < TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1; i++)
{
/* Build the base address register. */
base_address_register = code_address & ~(block_size - 1) | mpu_register | 0x10;
@@ -405,7 +400,7 @@ UINT i;
base_attribute_register = base_attribute_register | 0x1;
}
/* Setup the MPU Base Address Register. */
module_instance -> txm_module_instance_mpu_registers[mpu_table_index] = base_address_register;
module_instance -> txm_module_instance_mpu_registers[mpu_table_index] = base_address_register;
/* Setup the MPU Base Attribute Register. */
module_instance -> txm_module_instance_mpu_registers[mpu_table_index+1] = base_attribute_register;
@@ -415,9 +410,13 @@ UINT i;
/* Decrement the code size. */
if (code_size > block_size)
{
code_size = code_size - block_size;
}
else
{
code_size = 0;
}
/* Move MPU table index. */
mpu_table_index = mpu_table_index + 2;
@@ -435,7 +434,7 @@ UINT i;
}
/* Setup values for data area. */
data_address = (ULONG) module_instance -> txm_module_instance_data_start;
data_address = (ULONG) module_instance -> txm_module_instance_data_start;
/* Adjust the size of the module elements to be aligned to the default alignment. We do this
so that when we partition the allocated memory, we can simply place these regions right beside
@@ -455,8 +454,7 @@ UINT i;
/* Update the data size to include thread stacks. */
data_size = data_size + start_stop_stack_size + callback_stack_size;
block_size = _txm_power_of_two_block_size(data_size / TXM_MODULE_MANAGER_DATA_MPU_ENTRIES);
block_size = _txm_power_of_two_block_size(data_size / TXM_MODULE_MANAGER_DATA_MPU_ENTRIES);
/* Reset SRD bitfield. */
srd_bits = 0;
@@ -467,7 +465,6 @@ UINT i;
/* Now loop through to setup MPU protection for the data area. */
for (i = 0; i < TXM_MODULE_MANAGER_DATA_MPU_ENTRIES; i++)
{
/* Build the base address register. */
base_address_register = (data_address & ~(block_size - 1)) | mpu_register | 0x10;
@@ -475,11 +472,11 @@ UINT i;
if (data_size < block_size)
{
srd_bits = _txm_module_manager_calculate_srd_bits(block_size, data_size);
}
}
/* Build the base attribute register. */
base_attribute_register = region_size | srd_bits | 0x13070000;
/* Is there still some data? If so set the region enable bit. */
if (data_size)
{
@@ -488,7 +485,7 @@ UINT i;
}
/* Setup the MPU Base Address Register. */
module_instance -> txm_module_instance_mpu_registers[mpu_table_index] = base_address_register;
module_instance -> txm_module_instance_mpu_registers[mpu_table_index] = base_address_register;
/* Setup the MPU Base Attribute Register. */
module_instance -> txm_module_instance_mpu_registers[mpu_table_index+1] = base_attribute_register;
@@ -498,9 +495,13 @@ UINT i;
/* Decrement the data size. */
if (data_size > block_size)
{
data_size = data_size - block_size;
}
else
{
data_size = 0;
}
/* Move MPU table index. */
mpu_table_index = mpu_table_index + 2;
@@ -508,176 +509,4 @@ UINT i;
/* Increment the MPU register index. */
mpu_register++;
}
}
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _txm_module_manager_shared_memory_check_outside */
/* Cortex-M4/MPU/IAR */
/* 6.0.1 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
/* */
/* DESCRIPTION */
/* */
/* This function checks if the specified object is outside shared */
/* memory. */
/* */
/* INPUT */
/* */
/* module_instance Pointer to module instance */
/* obj_ptr Pointer to the object */
/* obj_size Size of the object */
/* */
/* OUTPUT */
/* */
/* Whether the object is outside the shared memory region. */
/* */
/* CALLS */
/* */
/* N/A */
/* */
/* CALLED BY */
/* */
/* Module dispatch check functions */
/* */
/* RELEASE HISTORY */
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 06-30-2020 Scott Larson Initial Version 6.0.1 */
/* */
/**************************************************************************/
UCHAR _txm_module_manager_shared_memory_check_outside(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE obj_ptr, UINT obj_size)
{
ALIGN_TYPE shared_memory_start;
ALIGN_TYPE shared_memory_end;
shared_memory_start = (ALIGN_TYPE) module_instance -> txm_module_instance_shared_memory_address;
shared_memory_end = shared_memory_start + module_instance -> txm_module_instance_shared_memory_length;
if (TXM_MODULE_MANAGER_CHECK_OUTSIDE_RANGE_EXCLUSIVE(shared_memory_start, shared_memory_end,
obj_ptr, obj_size))
{
return(TX_TRUE);
}
return(TX_FALSE);
}
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _txm_module_manager_shared_memory_check_inside Cortex-M4/MPU/IAR */
/* 6.0.1 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
/* */
/* DESCRIPTION */
/* */
/* This function checks if the specified object is inside shared */
/* memory. */
/* */
/* INPUT */
/* */
/* module_instance Pointer to module instance */
/* obj_ptr Pointer to the object */
/* obj_size Size of the object */
/* */
/* OUTPUT */
/* */
/* Whether the object is inside the shared memory region. */
/* */
/* CALLS */
/* */
/* N/A */
/* */
/* CALLED BY */
/* */
/* Module dispatch check functions */
/* */
/* RELEASE HISTORY */
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 06-30-2020 Scott Larson Initial Version 6.0.1 */
/* */
/**************************************************************************/
UCHAR _txm_module_manager_shared_memory_check_inside(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE obj_ptr, UINT obj_size)
{
ALIGN_TYPE shared_memory_start;
ALIGN_TYPE shared_memory_end;
shared_memory_start = (ALIGN_TYPE) module_instance -> txm_module_instance_shared_memory_address;
shared_memory_end = shared_memory_start + module_instance -> txm_module_instance_shared_memory_length;
if (TXM_MODULE_MANAGER_CHECK_INSIDE_RANGE_EXCLUSIVE(shared_memory_start, shared_memory_end,
obj_ptr, obj_size))
{
return(TX_TRUE);
}
return(TX_FALSE);
}
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _txm_module_manager_shared_memory_check_inside_byte */
/* Cortex-M4/MPU/IAR */
/* 6.0.1 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
/* */
/* DESCRIPTION */
/* */
/* This function checks if the specified byte is inside shared memory. */
/* */
/* INPUT */
/* */
/* module_instance Pointer to module instance */
/* byte_ptr Pointer to the byte */
/* */
/* OUTPUT */
/* */
/* Whether the byte is inside the shared memory region. */
/* */
/* CALLS */
/* */
/* N/A */
/* */
/* CALLED BY */
/* */
/* Module dispatch check functions */
/* */
/* RELEASE HISTORY */
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 06-30-2020 Scott Larson Initial Version 6.0.1 */
/* */
/**************************************************************************/
UCHAR _txm_module_manager_shared_memory_check_inside_byte(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE byte_ptr)
{
ALIGN_TYPE shared_memory_start;
ALIGN_TYPE shared_memory_end;
shared_memory_start = (ALIGN_TYPE) module_instance -> txm_module_instance_shared_memory_address;
shared_memory_end = shared_memory_start + module_instance -> txm_module_instance_shared_memory_length;
if (TXM_MODULE_MANAGER_CHECK_INSIDE_RANGE_EXCLUSIVE_BYTE(shared_memory_start, shared_memory_end,
byte_ptr))
{
return(TX_TRUE);
}
return(TX_FALSE);
}

114
ports_module/cortex-m4/iar/module_manager/src/txm_module_manager_thread_stack_build.s
View File

@@ -10,66 +10,57 @@
;/**************************************************************************/
;
;
;/**************************************************************************/
;/**************************************************************************/
;/** */
;/** ThreadX Component */
;/** */
;/** Module Manager */
;/** */
;/**************************************************************************/
;/**************************************************************************/
;/**************************************************************************/
;/**************************************************************************/
;/** */
;/** ThreadX Component */
;/** */
;/** Module Manager */
;/** */
;/**************************************************************************/
;/**************************************************************************/
;
;
;#define TX_SOURCE_CODE
;
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_thread.h"
;
;
SECTION `.text`:CODE:NOROOT(2)
THUMB
;/**************************************************************************/
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* _txm_module_manager_thread_stack_build Cortex-M4/MPU/IAR */
;/* 6.0.1 */
SECTION `.text`:CODE:NOROOT(2)
THUMB
;/**************************************************************************/
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* _txm_module_manager_thread_stack_build Cortex-M4/MPU/IAR */
;/* 6.1 */
;/* AUTHOR */
;/* */
;/* Scott Larson, Microsoft Corporation */
;/* */
;/* DESCRIPTION */
;/* */
;/* This function builds a stack frame on the supplied thread's stack. */
;/* The stack frame results in a fake interrupt return to the supplied */
;/* function pointer. */
;/* */
;/* INPUT */
;/* */
;/* thread_ptr Pointer to thread */
;/* function_ptr Pointer to shell function */
;/* */
;/* OUTPUT */
;/* */
;/* None */
;/* */
;/* CALLS */
;/* */
;/* None */
;/* */
;/* CALLED BY */
;/* */
;/* _tx_thread_create Create thread service */
;/* */
;/* RELEASE HISTORY */
;/* */
;/* DESCRIPTION */
;/* */
;/* This function builds a stack frame on the supplied thread's stack. */
;/* The stack frame results in a fake interrupt return to the supplied */
;/* function pointer. */
;/* */
;/* INPUT */
;/* */
;/* thread_ptr Pointer to thread */
;/* function_ptr Pointer to shell function */
;/* */
;/* OUTPUT */
;/* */
;/* None */
;/* */
;/* CALLS */
;/* */
;/* None */
;/* */
;/* CALLED BY */
;/* */
;/* _tx_thread_create Create thread service */
;/* */
;/* RELEASE HISTORY */
;/* */
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 Scott Larson Initial Version 6.0.1 */
;/* 09-30-2020 Scott Larson Initial Version 6.1 */
;/* */
;/**************************************************************************/
;VOID _txm_module_manager_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(TX_THREAD *, TXM_MODULE_INSTANCE *))
@@ -77,11 +68,11 @@
PUBLIC _txm_module_manager_thread_stack_build
_txm_module_manager_thread_stack_build:
;
;
;
; /* Build a fake interrupt frame. The form of the fake interrupt stack
; on the Cortex-M should look like the following after it is built:
;
; Stack Top:
;
; Stack Top:
; LR Interrupted LR (LR at time of PENDSV)
; r4 Initial value for r4
; r5 Initial value for r5
@@ -89,7 +80,7 @@ _txm_module_manager_thread_stack_build:
; r7 Initial value for r7
; r8 Initial value for r8
; r9 Initial value for r9
; r10 (sl) Initial value for r10 (sl)
; r10 Initial value for r10
; r11 Initial value for r11
; r0 Initial value for r0 (Hardware stack starts here!!)
; r1 Initial value for r1
@@ -116,17 +107,15 @@ _txm_module_manager_thread_stack_build:
STR r3, [r2, #12] ; Store initial r6
STR r3, [r2, #16] ; Store initial r7
STR r3, [r2, #20] ; Store initial r8
LDR r3, [r0, #12] ; Pickup stack starting address
STR r3, [r2, #28] ; Store initial r10 (sl)
MOV r3, #0 ; Build initial register value
STR r3, [r2, #28] ; Store initial r10
STR r3, [r2, #32] ; Store initial r11
;
; /* Hardware stack follows. /
; /* Hardware stack follows. */
;
STR r0, [r2, #36] ; Store initial r0, which is the thread control block
LDR r3, [r0, #8] ; Pickup thread entry info pointer,which is in the stack pointer position of the thread control block.
; It was setup in the txm_module_manager_thread_create function. It will be overwritten later in this
; It was setup in the txm_module_manager_thread_create function. It will be overwritten later in this
; function with the actual, initial stack pointer.
STR r3, [r2, #40] ; Store initial r1, which is the module entry information.
LDR r3, [r3, #8] ; Pickup data base register from the module information
@@ -145,8 +134,7 @@ _txm_module_manager_thread_stack_build:
; /* Setup stack pointer. */
; thread_ptr -> tx_thread_stack_ptr = r2;
;
STR r2, [r0, #8] ; Save stack pointer in thread's
; control block
STR r2, [r0, #8] ; Save stack pointer in thread's control block
BX lr ; Return to caller
;}
END