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Release ARMv7-M and ARMv8-M architecture ports (#249)

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* Release ARMv7-M and ARMv8-M architecture ports

* Add a pipeline to check ports_arch
This commit is contained in:
TiejunZhou
2023-04-18 18:11:20 +08:00
committed by GitHub
parent d64ef2ab06
commit 23680f5e5f
179 changed files with 47913 additions and 0 deletions
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ports_arch/ARMv7-M/threadx_modules/inc/tx_port.h Normal file
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/**************************************************************************/
/* */
/* Copyright (c) Microsoft Corporation. All rights reserved. */
/* */
/* This software is licensed under the Microsoft Software License */
/* Terms for Microsoft Azure RTOS. Full text of the license can be */
/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
/* and in the root directory of this software. */
/* */
/**************************************************************************/
/**************************************************************************/
/**************************************************************************/
/** */
/** ThreadX Component */
/** */
/** Port Specific */
/** */
/**************************************************************************/
/**************************************************************************/
/**************************************************************************/
/* */
/* PORT SPECIFIC C INFORMATION RELEASE */
/* */
/* tx_port.h Cortex-Mx */
/* 6.2.0 */
/* */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
/* */
/* DESCRIPTION */
/* */
/* This file contains data type definitions that make the ThreadX */
/* real-time kernel function identically on a variety of different */
/* processor architectures. For example, the size or number of bits */
/* in an "int" data type vary between microprocessor architectures and */
/* even C compilers for the same microprocessor. ThreadX does not */
/* directly use native C data types. Instead, ThreadX creates its */
/* own special types that can be mapped to actual data types by this */
/* file to guarantee consistency in the interface and functionality. */
/* */
/* This file replaces the previous Cortex-M3/M4/M7 files. It unifies */
/* the ARMv7-M architecture and compilers into one common file. */
/* */
/* RELEASE HISTORY */
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 10-15-2021 Scott Larson Initial Version 6.1.9 */
/* 04-25-2022 Scott Larson Modified comments and added */
/* volatile to registers, */
/* resulting in version 6.1.11 */
/* */
/**************************************************************************/
#ifndef TX_PORT_H
#define TX_PORT_H
/* Determine if the optional ThreadX user define file should be used. */
#ifdef TX_INCLUDE_USER_DEFINE_FILE
/* Yes, include the user defines in tx_user.h. The defines in this file may
alternately be defined on the command line. */
#include "tx_user.h"
#endif /* TX_INCLUDE_USER_DEFINE_FILE */
/* Define compiler library include files. */
#include <stdlib.h>
#include <string.h>
#ifdef __ICCARM__
#include <intrinsics.h> /* IAR Intrinsics */
#define __asm__ __asm /* Define to make all inline asm look similar */
#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT
#include <yvals.h>
#endif /* TX_ENABLE_IAR_LIBRARY_SUPPORT */
#endif /* __ICCARM__ */
#ifdef __ghs__
#include <arm_ghs.h>
#include "tx_ghs.h"
#endif /* __ghs__ */
#if !defined(__GNUC__) && !defined(__CC_ARM)
#define __get_control_value __get_CONTROL
#define __set_control_value __set_CONTROL
#endif
#ifndef __GNUC__
#define __get_ipsr_value __get_IPSR
#endif
/* Define ThreadX basic types for this port. */
#define VOID void
typedef char CHAR;
typedef unsigned char UCHAR;
typedef int INT;
typedef unsigned int UINT;
typedef long LONG;
typedef unsigned long ULONG;
typedef unsigned long long ULONG64;
typedef short SHORT;
typedef unsigned short USHORT;
#define ULONG64_DEFINED
/* Define the priority levels for ThreadX. Legal values range
from 32 to 1024 and MUST be evenly divisible by 32. */
#ifndef TX_MAX_PRIORITIES
#define TX_MAX_PRIORITIES 32
#endif
/* Define the minimum stack for a ThreadX thread on this processor. If the size supplied during
thread creation is less than this value, the thread create call will return an error. */
#ifndef TX_MINIMUM_STACK
#define TX_MINIMUM_STACK 200 /* Minimum stack size for this port */
#endif
/* Define the system timer thread's default stack size and priority. These are only applicable
if TX_TIMER_PROCESS_IN_ISR is not defined. */
#ifndef TX_TIMER_THREAD_STACK_SIZE
#define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */
#endif
#ifndef TX_TIMER_THREAD_PRIORITY
#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */
#endif
/* By default, ThreadX for Cortex-M uses the PRIMASK register to enable/disable interrupts.
If using BASEPRI is desired, define the following two symbols for both c and assembly files:
TX_PORT_USE_BASEPRI - This tells ThreadX to use BASEPRI instead of PRIMASK.
TX_PORT_BASEPRI = (priority_mask << (8 - number_priority_bits)) - this defines the maximum priority level to mask.
Any interrupt with a higher priority than priority_mask will not be masked, thus the interrupt will run.
*/
/* Define various constants for the ThreadX Cortex-M port. */
#define TX_INT_DISABLE 1 /* Disable interrupts */
#define TX_INT_ENABLE 0 /* Enable interrupts */
/* Define the clock source for trace event entry time stamp. The following two item are port specific.
For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock
source constants would be:
#define TX_TRACE_TIME_SOURCE *((volatile ULONG *) 0x0a800024)
#define TX_TRACE_TIME_MASK 0x0000FFFFUL
*/
#ifndef TX_MISRA_ENABLE
#ifndef TX_TRACE_TIME_SOURCE
#define TX_TRACE_TIME_SOURCE *((volatile ULONG *) 0xE0001004)
#endif
#else
ULONG _tx_misra_time_stamp_get(VOID);
#define TX_TRACE_TIME_SOURCE _tx_misra_time_stamp_get()
#endif
#ifndef TX_TRACE_TIME_MASK
#define TX_TRACE_TIME_MASK 0xFFFFFFFFUL
#endif
/* Define the port specific options for the _tx_build_options variable. This variable indicates
how the ThreadX library was built. */
#define TX_PORT_SPECIFIC_BUILD_OPTIONS (0)
/* Define the in-line initialization constant so that modules with in-line
initialization capabilities can prevent their initialization from being
a function call. */
#ifdef TX_MISRA_ENABLE
#define TX_DISABLE_INLINE
#else
#define TX_INLINE_INITIALIZATION
#endif
/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is
disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack
checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING
define is negated, thereby forcing the stack fill which is necessary for the stack checking
logic. */
#ifndef TX_MISRA_ENABLE
#ifdef TX_ENABLE_STACK_CHECKING
#undef TX_DISABLE_STACK_FILLING
#endif
#endif
/* Define the TX_THREAD control block extensions for this port. The main reason
for the multiple macros is so that backward compatibility can be maintained with
existing ThreadX kernel awareness modules. */
#define TX_THREAD_EXTENSION_0
#define TX_THREAD_EXTENSION_1
#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT
#define TX_THREAD_EXTENSION_2 VOID *tx_thread_module_instance_ptr; \
VOID *tx_thread_module_entry_info_ptr; \
ULONG tx_thread_module_current_user_mode; \
ULONG tx_thread_module_user_mode; \
ULONG tx_thread_module_saved_lr; \
VOID *tx_thread_module_kernel_stack_start; \
VOID *tx_thread_module_kernel_stack_end; \
ULONG tx_thread_module_kernel_stack_size; \
VOID *tx_thread_module_stack_ptr; \
VOID *tx_thread_module_stack_start; \
VOID *tx_thread_module_stack_end; \
ULONG tx_thread_module_stack_size; \
VOID *tx_thread_module_reserved; \
VOID *tx_thread_iar_tls_pointer;
#else
#define TX_THREAD_EXTENSION_2 VOID *tx_thread_module_instance_ptr; \
VOID *tx_thread_module_entry_info_ptr; \
ULONG tx_thread_module_current_user_mode; \
ULONG tx_thread_module_user_mode; \
ULONG tx_thread_module_saved_lr; \
VOID *tx_thread_module_kernel_stack_start; \
VOID *tx_thread_module_kernel_stack_end; \
ULONG tx_thread_module_kernel_stack_size; \
VOID *tx_thread_module_stack_ptr; \
VOID *tx_thread_module_stack_start; \
VOID *tx_thread_module_stack_end; \
ULONG tx_thread_module_stack_size; \
VOID *tx_thread_module_reserved;
#endif
#ifndef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
#define TX_THREAD_EXTENSION_3
#else
#define TX_THREAD_EXTENSION_3 unsigned long long tx_thread_execution_time_total; \
unsigned long long tx_thread_execution_time_last_start;
#endif
/* Define the port extensions of the remaining ThreadX objects. */
#define TX_BLOCK_POOL_EXTENSION
#define TX_BYTE_POOL_EXTENSION
#define TX_MUTEX_EXTENSION
#define TX_EVENT_FLAGS_GROUP_EXTENSION VOID *tx_event_flags_group_module_instance; \
VOID (*tx_event_flags_group_set_module_notify)(struct TX_EVENT_FLAGS_GROUP_STRUCT *group_ptr);
#define TX_QUEUE_EXTENSION VOID *tx_queue_module_instance; \
VOID (*tx_queue_send_module_notify)(struct TX_QUEUE_STRUCT *queue_ptr);
#define TX_SEMAPHORE_EXTENSION VOID *tx_semaphore_module_instance; \
VOID (*tx_semaphore_put_module_notify)(struct TX_SEMAPHORE_STRUCT *semaphore_ptr);
#define TX_TIMER_EXTENSION VOID *tx_timer_module_instance; \
VOID (*tx_timer_module_expiration_function)(ULONG id);
/* Define the user extension field of the thread control block. Nothing
additional is needed for this port so it is defined as white space. */
#ifndef TX_THREAD_USER_EXTENSION
#define TX_THREAD_USER_EXTENSION
#endif
/* Define the macros for processing extensions in tx_thread_create, tx_thread_delete,
tx_thread_shell_entry, and tx_thread_terminate. */
#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT
#if (__VER__ < 8000000)
#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate();
#define TX_THREAD_DELETE_EXTENSION(thread_ptr) __iar_dlib_perthread_deallocate(thread_ptr -> tx_thread_iar_tls_pointer); \
thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL;
#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION __iar_dlib_perthread_access(0);
#else
void *_tx_iar_create_per_thread_tls_area(void);
void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr);
void __iar_Initlocks(void);
#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = _tx_iar_create_per_thread_tls_area();
#define TX_THREAD_DELETE_EXTENSION(thread_ptr) do {_tx_iar_destroy_per_thread_tls_area(thread_ptr -> tx_thread_iar_tls_pointer); \
thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; } while(0);
#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION do {__iar_Initlocks();} while(0);
#endif
#else
#define TX_THREAD_CREATE_EXTENSION(thread_ptr)
#define TX_THREAD_DELETE_EXTENSION(thread_ptr)
#endif
#if defined(__ARMVFP__) || defined(__ARM_PCS_VFP) || defined(__ARM_FP) || defined(__TARGET_FPU_VFP) || defined(__VFP__)
#ifdef TX_MISRA_ENABLE
ULONG _tx_misra_control_get(void);
void _tx_misra_control_set(ULONG value);
ULONG _tx_misra_fpccr_get(void);
void _tx_misra_vfp_touch(void);
#else /* TX_MISRA_ENABLE not defined */
/* Define some helper functions (these are intrinsics in some compilers). */
#ifdef __GNUC__ /* GCC and ARM Compiler 6 */
__attribute__( ( always_inline ) ) static inline ULONG __get_control_value(void)
{
ULONG control_value;
__asm__ volatile (" MRS %0,CONTROL ": "=r" (control_value) );
return(control_value);
}
__attribute__( ( always_inline ) ) static inline void __set_control_value(ULONG control_value)
{
__asm__ volatile (" MSR CONTROL,%0": : "r" (control_value): "memory" );
}
#define TX_VFP_TOUCH() __asm__ volatile ("VMOV.F32 s0, s0");
#elif defined(__CC_ARM) /* ARM Compiler 5 */
__attribute__( ( always_inline ) ) ULONG __get_control_value(void)
{
ULONG control_value;
__asm volatile ("MRS control_value,CONTROL");
return(control_value);
}
__attribute__( ( always_inline ) ) void __set_control_value(ULONG control_value)
{
__asm__ volatile ("MSR CONTROL,control_value");
}
/* Can't access VFP registers with inline asm, so define this in tx_thread_schedule. */
void _tx_vfp_access(void);
#define TX_VFP_TOUCH() _tx_vfp_access();
#elif defined(__ICCARM__) /* IAR */
#define TX_VFP_TOUCH() __asm__ volatile ("VMOV.F32 s0, s0");
#endif /* Helper functions for different compilers */
#endif /* TX_MISRA_ENABLE */
/* A completed thread falls into _thread_shell_entry and we can simply deactivate the FPU via CONTROL.FPCA
in order to ensure no lazy stacking will occur. */
#ifndef TX_MISRA_ENABLE
#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) { \
ULONG _tx_vfp_state; \
_tx_vfp_state = __get_control_value(); \
_tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \
__set_control_value(_tx_vfp_state); \
}
#else
#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) { \
ULONG _tx_vfp_state; \
_tx_vfp_state = _tx_misra_control_get(); \
_tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \
_tx_misra_control_set(_tx_vfp_state); \
}
#endif
/* A thread can be terminated by another thread, so we first check if it's self-terminating and not in an ISR.
If so, deactivate the FPU via CONTROL.FPCA. Otherwise we are in an interrupt or another thread is terminating
this one, so if the FPCCR.LSPACT bit is set, we need to save the CONTROL.FPCA state, touch the FPU to flush
the lazy FPU save, then restore the CONTROL.FPCA state. */
#ifndef TX_MISRA_ENABLE
#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) { \
ULONG _tx_system_state; \
_tx_system_state = TX_THREAD_GET_SYSTEM_STATE(); \
if ((_tx_system_state == ((ULONG) 0)) && ((thread_ptr) == _tx_thread_current_ptr)) \
{ \
ULONG _tx_vfp_state; \
_tx_vfp_state = __get_control_value(); \
_tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \
__set_control_value(_tx_vfp_state); \
} \
else \
{ \
ULONG _tx_fpccr; \
_tx_fpccr = *((volatile ULONG *) 0xE000EF34); \
_tx_fpccr = _tx_fpccr & ((ULONG) 0x01); \
if (_tx_fpccr == ((ULONG) 0x01)) \
{ \
ULONG _tx_vfp_state; \
_tx_vfp_state = __get_control_value(); \
_tx_vfp_state = _tx_vfp_state & ((ULONG) 0x4); \
TX_VFP_TOUCH(); \
if (_tx_vfp_state == ((ULONG) 0)) \
{ \
_tx_vfp_state = __get_control_value(); \
_tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \
__set_control_value(_tx_vfp_state); \
} \
} \
} \
}
#else
#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) { \
ULONG _tx_system_state; \
_tx_system_state = TX_THREAD_GET_SYSTEM_STATE(); \
if ((_tx_system_state == ((ULONG) 0)) && ((thread_ptr) == _tx_thread_current_ptr)) \
{ \
ULONG _tx_vfp_state; \
_tx_vfp_state = _tx_misra_control_get(); \
_tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \
_tx_misra_control_set(_tx_vfp_state); \
} \
else \
{ \
ULONG _tx_fpccr; \
_tx_fpccr = _tx_misra_fpccr_get(); \
_tx_fpccr = _tx_fpccr & ((ULONG) 0x01); \
if (_tx_fpccr == ((ULONG) 0x01)) \
{ \
ULONG _tx_vfp_state; \
_tx_vfp_state = _tx_misra_control_get(); \
_tx_vfp_state = _tx_vfp_state & ((ULONG) 0x4); \
_tx_misra_vfp_touch(); \
if (_tx_vfp_state == ((ULONG) 0)) \
{ \
_tx_vfp_state = _tx_misra_control_get(); \
_tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \
_tx_misra_control_set(_tx_vfp_state); \
} \
} \
} \
}
#endif
#else /* No VFP in use */
#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr)
#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr)
#endif /* defined(__ARMVFP__) || defined(__ARM_PCS_VFP) || defined(__ARM_FP) || defined(__TARGET_FPU_VFP) || defined(__VFP__) */
/* Define the ThreadX object creation extensions for the remaining objects. */
#define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr)
#define TX_BYTE_POOL_CREATE_EXTENSION(pool_ptr)
#define TX_EVENT_FLAGS_GROUP_CREATE_EXTENSION(group_ptr)
#define TX_MUTEX_CREATE_EXTENSION(mutex_ptr)
#define TX_QUEUE_CREATE_EXTENSION(queue_ptr)
#define TX_SEMAPHORE_CREATE_EXTENSION(semaphore_ptr)
#define TX_TIMER_CREATE_EXTENSION(timer_ptr)
/* Define the ThreadX object deletion extensions for the remaining objects. */
#define TX_BLOCK_POOL_DELETE_EXTENSION(pool_ptr)
#define TX_BYTE_POOL_DELETE_EXTENSION(pool_ptr)
#define TX_EVENT_FLAGS_GROUP_DELETE_EXTENSION(group_ptr)
#define TX_MUTEX_DELETE_EXTENSION(mutex_ptr)
#define TX_QUEUE_DELETE_EXTENSION(queue_ptr)
#define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr)
#define TX_TIMER_DELETE_EXTENSION(timer_ptr)
/* Define the get system state macro. */
#ifndef TX_THREAD_GET_SYSTEM_STATE
#ifndef TX_MISRA_ENABLE
#ifdef __CC_ARM /* ARM Compiler 5 */
register unsigned int _ipsr __asm("ipsr");
#define TX_THREAD_GET_SYSTEM_STATE() (_tx_thread_system_state | _ipsr)
#elif defined(__GNUC__) /* GCC and ARM Compiler 6 */
__attribute__( ( always_inline ) ) static inline unsigned int __get_ipsr_value(void)
{
unsigned int ipsr_value;
__asm__ volatile (" MRS %0,IPSR ": "=r" (ipsr_value) );
return(ipsr_value);
}
#define TX_THREAD_GET_SYSTEM_STATE() (_tx_thread_system_state | __get_ipsr_value())
#elif defined(__ICCARM__) /* IAR */
#define TX_THREAD_GET_SYSTEM_STATE() (_tx_thread_system_state | __get_IPSR())
#endif /* TX_THREAD_GET_SYSTEM_STATE for different compilers */
#else /* TX_MISRA_ENABLE is defined, use MISRA function. */
ULONG _tx_misra_ipsr_get(VOID);
#define TX_THREAD_GET_SYSTEM_STATE() (_tx_thread_system_state | _tx_misra_ipsr_get())
#endif /* TX_MISRA_ENABLE */
#endif /* TX_THREAD_GET_SYSTEM_STATE */
/* Define the check for whether or not to call the _tx_thread_system_return function. A non-zero value
indicates that _tx_thread_system_return should not be called. This overrides the definition in tx_thread.h
for Cortex-M since so we don't waste time checking the _tx_thread_system_state variable that is always
zero after initialization for Cortex-M ports. */
#ifndef TX_THREAD_SYSTEM_RETURN_CHECK
#define TX_THREAD_SYSTEM_RETURN_CHECK(c) (c) = ((ULONG) _tx_thread_preempt_disable);
#endif
/* Define the macro to ensure _tx_thread_preempt_disable is set early in initialization in order to
prevent early scheduling on Cortex-M parts. */
#define TX_PORT_SPECIFIC_POST_INITIALIZATION _tx_thread_preempt_disable++;
#ifndef TX_DISABLE_INLINE
/* Define the TX_LOWEST_SET_BIT_CALCULATE macro for each compiler. */
#ifdef __ICCARM__ /* IAR Compiler */
#define TX_LOWEST_SET_BIT_CALCULATE(m, b) (b) = (UINT) __CLZ(__RBIT((m)));
#elif defined(__CC_ARM) /* AC5 Compiler */
#define TX_LOWEST_SET_BIT_CALCULATE(m, b) (b) = (UINT) __clz(__rbit((m)));
#elif defined(__GNUC__) /* GCC and AC6 Compiler */
#define TX_LOWEST_SET_BIT_CALCULATE(m, b) __asm__ volatile (" RBIT %0,%1 ": "=r" (m) : "r" (m) ); \
__asm__ volatile (" CLZ %0,%1 ": "=r" (b) : "r" (m) );
#else
#error "Compiler not supported."
#endif
/* Define the interrupt disable/restore macros for each compiler. */
#if defined(__GNUC__) || defined(__ICCARM__)
/*** GCC/AC6 and IAR ***/
__attribute__( ( always_inline ) ) static inline UINT __get_interrupt_posture(void)
{
UINT posture;
#ifdef TX_PORT_USE_BASEPRI
__asm__ volatile ("MRS %0, BASEPRI ": "=r" (posture));
#else
__asm__ volatile ("MRS %0, PRIMASK ": "=r" (posture));
#endif
return(posture);
}
#ifdef TX_PORT_USE_BASEPRI
__attribute__( ( always_inline ) ) static inline void __set_basepri_value(UINT basepri_value)
{
__asm__ volatile ("MSR BASEPRI,%0 ": : "r" (basepri_value));
}
#else
__attribute__( ( always_inline ) ) static inline void __enable_interrupts(void)
{
__asm__ volatile ("CPSIE i": : : "memory");
}
#endif
__attribute__( ( always_inline ) ) static inline void __restore_interrupt(UINT int_posture)
{
#ifdef TX_PORT_USE_BASEPRI
__set_basepri_value(int_posture);
#else
__asm__ volatile ("MSR PRIMASK,%0": : "r" (int_posture): "memory");
#endif
}
__attribute__( ( always_inline ) ) static inline UINT __disable_interrupts(void)
{
UINT int_posture;
int_posture = __get_interrupt_posture();
#ifdef TX_PORT_USE_BASEPRI
__set_basepri_value(TX_PORT_BASEPRI);
#else
__asm__ volatile ("CPSID i" : : : "memory");
#endif
return(int_posture);
}
__attribute__( ( always_inline ) ) static inline void _tx_thread_system_return_inline(void)
{
UINT interrupt_save;
/* Set PendSV to invoke ThreadX scheduler. */
*((volatile ULONG *) 0xE000ED04) = ((ULONG) 0x10000000);
if (__get_ipsr_value() == 0)
{
interrupt_save = __get_interrupt_posture();
#ifdef TX_PORT_USE_BASEPRI
__set_basepri_value(0);
#else
__enable_interrupts();
#endif
__restore_interrupt(interrupt_save);
}
}
#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save;
#define TX_DISABLE interrupt_save = __disable_interrupts();
#define TX_RESTORE __restore_interrupt(interrupt_save);
/*** End GCC/AC6 and IAR ***/
#elif defined(__CC_ARM)
/*** AC5 ***/
static __inline unsigned int __get_interrupt_posture(void)
{
unsigned int posture;
#ifdef TX_PORT_USE_BASEPRI
__asm__ volatile ("MRS #posture, BASEPRI");
#else
__asm__ volatile ("MRS #posture, PRIMASK");
#endif
return(posture);
}
#ifdef TX_PORT_USE_BASEPRI
static __inline void __set_basepri_value(unsigned int basepri_value)
{
__asm__ volatile ("MSR BASEPRI, #basepri_value");
}
#endif
static __inline unsigned int __disable_interrupts(void)
{
unsigned int int_posture;
int_posture = __get_interrupt_posture();
#ifdef TX_PORT_USE_BASEPRI
__set_basepri_value(TX_PORT_BASEPRI);
#else
__asm__ volatile ("CPSID i");
#endif
return(int_posture);
}
static __inline void __restore_interrupt(unsigned int int_posture)
{
#ifdef TX_PORT_USE_BASEPRI
__set_basepri_value(int_posture);
#else
__asm__ volatile ("MSR PRIMASK, #int_posture");
#endif
}
static void _tx_thread_system_return_inline(void)
{
unsigned int interrupt_save;
/* Set PendSV to invoke ThreadX scheduler. */
*((volatile ULONG *) 0xE000ED04) = ((ULONG) 0x10000000);
if (_ipsr == 0)
{
#ifdef TX_PORT_USE_BASEPRI
interrupt_save = __get_interrupt_posture();
__set_basepri_value(0);
__set_basepri_value(interrupt_save);
#else
interrupt_save = __disable_irq();
__enable_irq();
if (interrupt_save != 0)
__disable_irq();
#endif
}
}
#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save;
#define TX_DISABLE interrupt_save = __disable_interrupts();
#define TX_RESTORE __restore_interrupt(interrupt_save);
/*** End AC5 ***/
#endif /* Interrupt disable/restore macros for each compiler. */
/* Redefine _tx_thread_system_return for improved performance. */
#define _tx_thread_system_return _tx_thread_system_return_inline
#else /* TX_DISABLE_INLINE is defined */
UINT _tx_thread_interrupt_disable(VOID);
VOID _tx_thread_interrupt_restore(UINT previous_posture);
#define TX_INTERRUPT_SAVE_AREA register UINT interrupt_save;
#define TX_DISABLE interrupt_save = _tx_thread_interrupt_disable();
#define TX_RESTORE _tx_thread_interrupt_restore(interrupt_save);
#endif /* TX_DISABLE_INLINE */
/* Define FPU extension for the Cortex-M. Each is assumed to be called in the context of the executing
thread. These are no longer needed, but are preserved for backward compatibility only. */
void tx_thread_fpu_enable(void);
void tx_thread_fpu_disable(void);
/* Define the version ID of ThreadX. This may be utilized by the application. */
#ifdef TX_THREAD_INIT
CHAR _tx_version_id[] =
"Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-Mx Version 6.2.1 *";
#else
#ifdef TX_MISRA_ENABLE
extern CHAR _tx_version_id[100];
#else
extern CHAR _tx_version_id[];
#endif
#endif
#endif

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ports_arch/ARMv7-M/threadx_modules/inc/txm_module_port.h Normal file
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@@ -0,0 +1,469 @@
/**************************************************************************/
/* */
/* Copyright (c) Microsoft Corporation. All rights reserved. */
/* */
/* This software is licensed under the Microsoft Software License */
/* Terms for Microsoft Azure RTOS. Full text of the license can be */
/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
/* and in the root directory of this software. */
/* */
/**************************************************************************/
/**************************************************************************/
/**************************************************************************/
/** */
/** ThreadX Component */
/** */
/** Module */
/** */
/**************************************************************************/
/**************************************************************************/
/**************************************************************************/
/* */
/* APPLICATION INTERFACE DEFINITION RELEASE */
/* */
/* txm_module_port.h Cortex-Mx */
/* 6.2.1 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
/* */
/* DESCRIPTION */
/* */
/* This file defines the basic module constants, interface structures, */
/* and function prototypes. */
/* */
/* RELEASE HISTORY */
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 10-15-2021 Scott Larson Initial Version 6.1.9 */
/* 01-31-2022 Scott Larson Modified comments and made */
/* heap user-configurable, */
/* resulting in version 6.1.10 */
/* 07-29-2022 Scott Larson Enabled user-defined and */
/* default MPU settings, */
/* resulting in version 6.1.12 */
/* 10-31-2022 Scott Larson Configure heap size, */
/* resulting in version 6.2.0 */
/* 03-08-2023 Scott Larson Set default values for RBAR, */
/* unify this file for all */
/* compilers, */
/* resulting in version 6.2.1 */
/* */
/**************************************************************************/
#ifndef TXM_MODULE_PORT_H
#define TXM_MODULE_PORT_H
/* Determine if the optional Modules user define file should be used. */
#ifdef TXM_MODULE_INCLUDE_USER_DEFINE_FILE
/* Yes, include the user defines in txm_module_user.h. The defines in this file may
alternately be defined on the command line. */
#include "txm_module_user.h"
#endif
/* It is assumed that the base ThreadX tx_port.h file has been modified to add the
following extensions to the ThreadX thread control block (this code should replace
the corresponding macro define in tx_port.h):
#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT
#define TX_THREAD_EXTENSION_2 VOID *tx_thread_module_instance_ptr; \
VOID *tx_thread_module_entry_info_ptr; \
ULONG tx_thread_module_current_user_mode; \
ULONG tx_thread_module_user_mode; \
ULONG tx_thread_module_saved_lr; \
VOID *tx_thread_module_kernel_stack_start; \
VOID *tx_thread_module_kernel_stack_end; \
ULONG tx_thread_module_kernel_stack_size; \
VOID *tx_thread_module_stack_ptr; \
VOID *tx_thread_module_stack_start; \
VOID *tx_thread_module_stack_end; \
ULONG tx_thread_module_stack_size; \
VOID *tx_thread_module_reserved; \
VOID *tx_thread_iar_tls_pointer;
#else
#define TX_THREAD_EXTENSION_2 VOID *tx_thread_module_instance_ptr; \
VOID *tx_thread_module_entry_info_ptr; \
ULONG tx_thread_module_current_user_mode; \
ULONG tx_thread_module_user_mode; \
ULONG tx_thread_module_saved_lr; \
VOID *tx_thread_module_kernel_stack_start; \
VOID *tx_thread_module_kernel_stack_end; \
ULONG tx_thread_module_kernel_stack_size; \
VOID *tx_thread_module_stack_ptr; \
VOID *tx_thread_module_stack_start; \
VOID *tx_thread_module_stack_end; \
ULONG tx_thread_module_stack_size; \
VOID *tx_thread_module_reserved;
#endif
The following extensions must also be defined in tx_port.h:
#define TX_EVENT_FLAGS_GROUP_EXTENSION VOID *tx_event_flags_group_module_instance; \
VOID (*tx_event_flags_group_set_module_notify)(struct TX_EVENT_FLAGS_GROUP_STRUCT *group_ptr);
#define TX_QUEUE_EXTENSION VOID *tx_queue_module_instance; \
VOID (*tx_queue_send_module_notify)(struct TX_QUEUE_STRUCT *queue_ptr);
#define TX_SEMAPHORE_EXTENSION VOID *tx_semaphore_module_instance; \
VOID (*tx_semaphore_put_module_notify)(struct TX_SEMAPHORE_STRUCT *semaphore_ptr);
#define TX_TIMER_EXTENSION VOID *tx_timer_module_instance; \
VOID (*tx_timer_module_expiration_function)(ULONG id);
*/
/* Users can define the module heap size. */
#ifndef TXM_MODULE_HEAP_SIZE
#define TXM_MODULE_HEAP_SIZE 512
#endif
/* Define the kernel stack size for a module thread. */
#ifndef TXM_MODULE_KERNEL_STACK_SIZE
#define TXM_MODULE_KERNEL_STACK_SIZE 768
#endif
/* For the following 3 access control settings, change TEX and C, B, S (bits 21 through 16 of MPU_RASR)
* to reflect your system memory attributes (cache, shareable, memory type). */
/* Code region access control: privileged read-only, outer & inner write-back, normal memory, shareable. */
#ifndef TXM_MODULE_MPU_CODE_ACCESS_CONTROL
#define TXM_MODULE_MPU_CODE_ACCESS_CONTROL 0x06070000
#endif
/* Data region access control: execute never, read/write, outer & inner write-back, normal memory, shareable. */
#ifndef TXM_MODULE_MPU_DATA_ACCESS_CONTROL
#define TXM_MODULE_MPU_DATA_ACCESS_CONTROL 0x13070000
#endif
/* Shared region access control: execute never, read-only, outer & inner write-back, normal memory, shareable. */
#ifndef TXM_MODULE_MPU_SHARED_ACCESS_CONTROL
#define TXM_MODULE_MPU_SHARED_ACCESS_CONTROL 0x12070000
#endif
/* For Cortex-M devices with 16 MPU regions, the last four regions (12-15)
are not used by ThreadX. These may be defined by the user.
RBAR needs the valid bit and region number set, as MPU alias registers are used. */
#define TXM_MODULE_MPU_USER_DEFINED_RBAR_12 0x1C
#define TXM_MODULE_MPU_USER_DEFINED_RASR_12 0
#define TXM_MODULE_MPU_USER_DEFINED_RBAR_13 0x1D
#define TXM_MODULE_MPU_USER_DEFINED_RASR_13 0
#define TXM_MODULE_MPU_USER_DEFINED_RBAR_14 0x1E
#define TXM_MODULE_MPU_USER_DEFINED_RASR_14 0
#define TXM_MODULE_MPU_USER_DEFINED_RBAR_15 0x1F
#define TXM_MODULE_MPU_USER_DEFINED_RASR_15 0
/* Users can define these default MPU configuration values.
If TXM_MODULE_MPU_DEFAULT is *not* defined, the MPU is disabled
when a thread that is not owned by a module is running
and the defines below are not used.
If TXM_MODULE_MPU_DEFAULT is defined, the MPU is configured to the
below values when a thread that is not owned by a module is running.
RBAR needs the valid bit and region number set, as MPU alias registers are used. */
#define TXM_MODULE_MPU_DEFAULT_RBAR_0 0x10
#define TXM_MODULE_MPU_DEFAULT_RASR_0 0
#define TXM_MODULE_MPU_DEFAULT_RBAR_1 0x11
#define TXM_MODULE_MPU_DEFAULT_RASR_1 0
#define TXM_MODULE_MPU_DEFAULT_RBAR_2 0x12
#define TXM_MODULE_MPU_DEFAULT_RASR_2 0
#define TXM_MODULE_MPU_DEFAULT_RBAR_3 0x13
#define TXM_MODULE_MPU_DEFAULT_RASR_3 0
#define TXM_MODULE_MPU_DEFAULT_RBAR_4 0x14
#define TXM_MODULE_MPU_DEFAULT_RASR_4 0
#define TXM_MODULE_MPU_DEFAULT_RBAR_5 0x15
#define TXM_MODULE_MPU_DEFAULT_RASR_5 0
#define TXM_MODULE_MPU_DEFAULT_RBAR_6 0x16
#define TXM_MODULE_MPU_DEFAULT_RASR_6 0
#define TXM_MODULE_MPU_DEFAULT_RBAR_7 0x17
#define TXM_MODULE_MPU_DEFAULT_RASR_7 0
#define TXM_MODULE_MPU_DEFAULT_RBAR_8 0x18
#define TXM_MODULE_MPU_DEFAULT_RASR_8 0
#define TXM_MODULE_MPU_DEFAULT_RBAR_9 0x19
#define TXM_MODULE_MPU_DEFAULT_RASR_9 0
#define TXM_MODULE_MPU_DEFAULT_RBAR_10 0x1A
#define TXM_MODULE_MPU_DEFAULT_RASR_10 0
#define TXM_MODULE_MPU_DEFAULT_RBAR_11 0x1B
#define TXM_MODULE_MPU_DEFAULT_RASR_11 0
#define TXM_MODULE_MPU_DEFAULT_RBAR_12 0x1C
#define TXM_MODULE_MPU_DEFAULT_RASR_12 0
#define TXM_MODULE_MPU_DEFAULT_RBAR_13 0x1D
#define TXM_MODULE_MPU_DEFAULT_RASR_13 0
#define TXM_MODULE_MPU_DEFAULT_RBAR_14 0x1E
#define TXM_MODULE_MPU_DEFAULT_RASR_14 0
#define TXM_MODULE_MPU_DEFAULT_RBAR_15 0x1F
#define TXM_MODULE_MPU_DEFAULT_RASR_15 0
/* Define constants specific to the tools the module can be built with for this particular modules port. */
#define TXM_MODULE_IAR_COMPILER 0x00000000
#define TXM_MODULE_RVDS_COMPILER 0x01000000
#define TXM_MODULE_GNU_COMPILER 0x02000000
#define TXM_MODULE_COMPILER_MASK 0xFF000000
#define TXM_MODULE_OPTIONS_MASK 0x000000FF
/* Define the properties for this particular module port. */
#define TXM_MODULE_MEMORY_PROTECTION_ENABLED
#ifdef TXM_MODULE_MEMORY_PROTECTION_ENABLED
#define TXM_MODULE_REQUIRE_ALLOCATED_OBJECT_MEMORY
#else
#define TXM_MODULE_REQUIRE_LOCAL_OBJECT_MEMORY
#endif
#define TXM_MODULE_USER_MODE 0x00000001
#define TXM_MODULE_MEMORY_PROTECTION 0x00000002
#define TXM_MODULE_SHARED_EXTERNAL_MEMORY_ACCESS 0x00000004
/* Define the supported options for this module. */
#define TXM_MODULE_MANAGER_SUPPORTED_OPTIONS (TXM_MODULE_USER_MODE | TXM_MODULE_MEMORY_PROTECTION | TXM_MODULE_SHARED_EXTERNAL_MEMORY_ACCESS)
#define TXM_MODULE_MANAGER_REQUIRED_OPTIONS 0
/* Define offset adjustments according to the compiler used to build the module. */
#define TXM_MODULE_IAR_SHELL_ADJUST 24
#define TXM_MODULE_IAR_START_ADJUST 28
#define TXM_MODULE_IAR_STOP_ADJUST 32
#define TXM_MODULE_IAR_CALLBACK_ADJUST 44
#define TXM_MODULE_RVDS_SHELL_ADJUST 0
#define TXM_MODULE_RVDS_START_ADJUST 0
#define TXM_MODULE_RVDS_STOP_ADJUST 0
#define TXM_MODULE_RVDS_CALLBACK_ADJUST 0
#define TXM_MODULE_GNU_SHELL_ADJUST 24
#define TXM_MODULE_GNU_START_ADJUST 28
#define TXM_MODULE_GNU_STOP_ADJUST 32
#define TXM_MODULE_GNU_CALLBACK_ADJUST 44
/* Define other module port-specific constants. */
/* Define INLINE_DECLARE to inline for this compiler. */
#define INLINE_DECLARE inline
#define TXM_MPU_VALID_BIT 0x10
#define TXM_ENABLE_REGION 0x01
#define TXM_MODULE_MANAGER_MPU_KERNEL_ENTRY_INDEX 0
/* Shared memory region attributes. */
#define TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE 1
#define TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT 0x01000000
/* There are 2 registers to set up each MPU region: MPU_RBAR, MPU_RASR. */
typedef struct TXM_MODULE_MPU_INFO_STRUCT
{
ULONG txm_module_mpu_region_address;
ULONG txm_module_mpu_region_attribute_size;
} TXM_MODULE_MPU_INFO;
#ifdef TXM_MODULE_MANAGER_16_MPU
/* Define the number of MPU entries assigned to the code and data sections.
On some Cortex-M7 parts, there are 16 total entries. ThreadX uses one for access
to the kernel entry function, thus 15 remain for code and data protection. */
#define TXM_MODULE_MANAGER_MPU_TOTAL_ENTRIES 16
#define TXM_MODULE_MANAGER_MPU_CODE_ENTRIES 4
#define TXM_MODULE_MANAGER_MPU_DATA_ENTRIES 4
#define TXM_MODULE_MANAGER_MPU_SHARED_ENTRIES 3
#define TXM_MODULE_MANAGER_MPU_SHARED_INDEX 9
#define TXM_MODULE_MANAGER_MPU_USER_REGION_INDEX 12
/* Define the port-extensions to the module manager instance structure. */
#define TXM_MODULE_MANAGER_PORT_EXTENSION \
TXM_MODULE_MPU_INFO txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_MPU_TOTAL_ENTRIES]; \
ULONG txm_module_instance_shared_memory_count; \
ULONG txm_module_instance_shared_memory_address[TXM_MODULE_MANAGER_MPU_SHARED_ENTRIES]; \
ULONG txm_module_instance_shared_memory_length[TXM_MODULE_MANAGER_MPU_SHARED_ENTRIES];
#else /* TXM_MODULE_MANAGER_16_MPU is not defined */
/* Define the number of MPU entries assigned to the code and data sections.
On Cortex-M3, M4, and some M7 parts, there are 8 total entries. ThreadX uses one for access
to the kernel entry function, thus 7 remain for code and data protection. */
#define TXM_MODULE_MANAGER_MPU_TOTAL_ENTRIES 8
#define TXM_MODULE_MANAGER_CODE_MPU_ENTRIES 4
#define TXM_MODULE_MANAGER_DATA_MPU_ENTRIES 3
#define TXM_MODULE_MANAGER_SHARED_MPU_REGION 4
/* Define the port-extensions to the module manager instance structure. */
#define TXM_MODULE_MANAGER_PORT_EXTENSION \
TXM_MODULE_MPU_INFO txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_MPU_TOTAL_ENTRIES]; \
ULONG txm_module_instance_shared_memory_address; \
ULONG txm_module_instance_shared_memory_length;
#endif /* TXM_MODULE_MANAGER_16_MPU */
/* Define the memory fault information structure that is populated when a memory fault occurs. */
typedef struct TXM_MODULE_MANAGER_MEMORY_FAULT_INFO_STRUCT
{
TX_THREAD *txm_module_manager_memory_fault_info_thread_ptr;
VOID *txm_module_manager_memory_fault_info_code_location;
ULONG txm_module_manager_memory_fault_info_shcsr;
ULONG txm_module_manager_memory_fault_info_cfsr;
ULONG txm_module_manager_memory_fault_info_mmfar;
ULONG txm_module_manager_memory_fault_info_bfar;
ULONG txm_module_manager_memory_fault_info_control;
ULONG txm_module_manager_memory_fault_info_sp;
ULONG txm_module_manager_memory_fault_info_r0;
ULONG txm_module_manager_memory_fault_info_r1;
ULONG txm_module_manager_memory_fault_info_r2;
ULONG txm_module_manager_memory_fault_info_r3;
ULONG txm_module_manager_memory_fault_info_r4;
ULONG txm_module_manager_memory_fault_info_r5;
ULONG txm_module_manager_memory_fault_info_r6;
ULONG txm_module_manager_memory_fault_info_r7;
ULONG txm_module_manager_memory_fault_info_r8;
ULONG txm_module_manager_memory_fault_info_r9;
ULONG txm_module_manager_memory_fault_info_r10;
ULONG txm_module_manager_memory_fault_info_r11;
ULONG txm_module_manager_memory_fault_info_r12;
ULONG txm_module_manager_memory_fault_info_lr;
ULONG txm_module_manager_memory_fault_info_xpsr;
} TXM_MODULE_MANAGER_MEMORY_FAULT_INFO;
#define TXM_MODULE_MANAGER_FAULT_INFO \
TXM_MODULE_MANAGER_MEMORY_FAULT_INFO _txm_module_manager_memory_fault_info;
/* Define the macro to check the code alignment. */
#define TXM_MODULE_MANAGER_CHECK_CODE_ALIGNMENT(module_location, code_alignment) \
{ \
ULONG temp; \
temp = (ULONG) module_location; \
temp = temp & (code_alignment - 1); \
if (temp) \
{ \
_tx_mutex_put(&_txm_module_manager_mutex); \
return(TXM_MODULE_ALIGNMENT_ERROR); \
} \
}
/* Define the macro to adjust the alignment and size for code/data areas. */
#define TXM_MODULE_MANAGER_ALIGNMENT_ADJUST(module_preamble, code_size, code_alignment, data_size, data_alignment) _txm_module_manager_alignment_adjust(module_preamble, &code_size, &code_alignment, &data_size, &data_alignment);
/* Define the macro to adjust the symbols in the module preamble. */
#define TXM_MODULE_MANAGER_CALCULATE_ADJUSTMENTS(properties, shell_function_adjust, start_function_adjust, stop_function_adjust, callback_function_adjust) \
if ((properties & TXM_MODULE_COMPILER_MASK) == TXM_MODULE_IAR_COMPILER) \
{ \
shell_function_adjust = TXM_MODULE_IAR_SHELL_ADJUST; \
start_function_adjust = TXM_MODULE_IAR_START_ADJUST; \
stop_function_adjust = TXM_MODULE_IAR_STOP_ADJUST; \
callback_function_adjust = TXM_MODULE_IAR_CALLBACK_ADJUST; \
} \
else if ((properties & TXM_MODULE_COMPILER_MASK) == TXM_MODULE_RVDS_COMPILER) \
{ \
shell_function_adjust = TXM_MODULE_RVDS_SHELL_ADJUST; \
start_function_adjust = TXM_MODULE_RVDS_START_ADJUST; \
stop_function_adjust = TXM_MODULE_RVDS_STOP_ADJUST; \
callback_function_adjust = TXM_MODULE_RVDS_CALLBACK_ADJUST; \
} \
else \
{ \
shell_function_adjust = TXM_MODULE_GNU_SHELL_ADJUST; \
start_function_adjust = TXM_MODULE_GNU_START_ADJUST; \
stop_function_adjust = TXM_MODULE_GNU_STOP_ADJUST; \
callback_function_adjust = TXM_MODULE_GNU_CALLBACK_ADJUST; \
}
/* Define the macro to populate the thread control block with module port-specific information.
Check if the module is in user mode and set up txm_module_thread_entry_info_kernel_call_dispatcher accordingly.
*/
#define TXM_MODULE_MANAGER_THREAD_SETUP(thread_ptr, module_instance) \
thread_ptr -> tx_thread_module_current_user_mode = module_instance -> txm_module_instance_property_flags & TXM_MODULE_USER_MODE; \
thread_ptr -> tx_thread_module_user_mode = module_instance -> txm_module_instance_property_flags & TXM_MODULE_USER_MODE; \
if (thread_ptr -> tx_thread_module_user_mode) \
{ \
thread_entry_info -> txm_module_thread_entry_info_kernel_call_dispatcher = _txm_module_manager_user_mode_entry; \
} \
else \
{ \
thread_entry_info -> txm_module_thread_entry_info_kernel_call_dispatcher = _txm_module_manager_kernel_dispatch; \
}
/* Define the macro to populate the module control block with module port-specific information.
If memory protection is enabled, set up the MPU registers.
*/
#define TXM_MODULE_MANAGER_MODULE_SETUP(module_instance) \
if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_USER_MODE) \
{ \
if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION) \
{ \
_txm_module_manager_mm_register_setup(module_instance); \
} \
} \
else \
{ \
/* Do nothing. */ \
}
/* Define the macro to perform port-specific functions when unloading the module. */
/* Nothing needs to be done for this port. */
#define TXM_MODULE_MANAGER_MODULE_UNLOAD(module_instance)
/* Define the macros to perform port-specific checks when passing pointers to the kernel. */
/* Define macro to make sure object is inside the module's data. */
#ifdef TXM_MODULE_MANAGER_16_MPU
#define TXM_MODULE_MANAGER_CHECK_INSIDE_DATA(module_instance, obj_ptr, obj_size) \
_txm_module_manager_inside_data_check(module_instance, obj_ptr, obj_size)
#else
#define TXM_MODULE_MANAGER_CHECK_INSIDE_DATA(module_instance, obj_ptr, obj_size) \
/* Check for overflow. */ \
(((obj_ptr) < ((obj_ptr) + (obj_size))) && \
/* Check if it's inside module data. */ \
((((obj_ptr) >= (ALIGN_TYPE) module_instance -> txm_module_instance_data_start) && \
(((obj_ptr) + (obj_size)) <= ((ALIGN_TYPE) module_instance -> txm_module_instance_data_end + 1))) || \
/* Check if it's inside shared memory. */ \
(((obj_ptr) >= (ALIGN_TYPE) module_instance -> txm_module_instance_shared_memory_address) && \
(((obj_ptr) + (obj_size)) <= (ALIGN_TYPE) (module_instance -> txm_module_instance_shared_memory_address + module_instance -> txm_module_instance_shared_memory_length)))))
#endif
/* Define some internal prototypes to this module port. */
#ifndef TX_SOURCE_CODE
#define txm_module_manager_memory_fault_notify _txm_module_manager_memory_fault_notify
#endif
#define TXM_MODULE_MANAGER_ADDITIONAL_PROTOTYPES \
VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble, ULONG *code_size, ULONG *code_alignment, ULONG *data_size, ULONG *data_alignment); \
VOID _txm_module_manager_memory_fault_handler(VOID); \
UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *)); \
VOID _txm_module_manager_mm_register_setup(TXM_MODULE_INSTANCE *module_instance); \
ULONG _txm_power_of_two_block_size(ULONG size); \
ULONG _txm_module_manager_calculate_srd_bits(ULONG block_size, ULONG length); \
ULONG _txm_module_manager_region_size_get(ULONG block_size); \
UINT _txm_module_manager_inside_data_check(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE obj_ptr, UINT obj_size);
#define TXM_MODULE_MANAGER_VERSION_ID \
CHAR _txm_module_manager_version_id[] = \
"Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-Mx Version 6.2.1 *";
#endif