Release 6.2.1 on 08 Mar 2023. Expand to see details.
cee19603d Include tx_user.h conditionally. e40e08007 Update owners d69641273 Update release date and version 394aee52f Add tx_user.h to GNU port assembly files 5cca2ddd0 RISC-V 64 bit port for Microchip e0f2c373c Link Winmm.lib that required by the high-resolution timer. 6af472a68 Update Win32 port with high resolution timer. aea7b556a Add DMB ISH barrier inst in ARMv8-A SMP scheduler 19091a262 Add .section .preamble to m3 m4 m7 module ports ced60e1b7 Add missing parenthesis in ports assembly file 309dc77ca Modules Cortex-A7 IAR new port c752a4063 Modules Cortex-A7 GNU new port dc224b90f Fix race condition in tx_thread_wait_abort and update regression test 6e261f5b7 create threadx cmsis-pack
This commit is contained in:
Tiejun Zhou
284
ports/risc-v64/gnu/src/tx_thread_context_save.S
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284
ports/risc-v64/gnu/src/tx_thread_context_save.S
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/**************************************************************************/
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/* */
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/* Copyright (c) Microsoft Corporation. All rights reserved. */
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/* */
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/* This software is licensed under the Microsoft Software License */
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/* Terms for Microsoft Azure RTOS. Full text of the license can be */
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/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
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/* and in the root directory of this software. */
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/* */
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/**************************************************************************/
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/**************************************************************************/
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/**************************************************************************/
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/** */
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/** ThreadX Component */
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/** */
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/** Thread */
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/** */
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/**************************************************************************/
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/**************************************************************************/
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#include "tx_port.h"
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.section .text
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/**************************************************************************/
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/* */
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/* FUNCTION RELEASE */
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/* */
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/* _tx_thread_context_save RISC-V64/GNU */
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/* 6.2.1 */
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/* AUTHOR */
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/* */
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/* Scott Larson, Microsoft Corporation */
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/* */
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/* DESCRIPTION */
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/* */
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/* This function saves the context of an executing thread in the */
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/* beginning of interrupt processing. The function also ensures that */
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/* the system stack is used upon return to the calling ISR. */
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/* */
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/* INPUT */
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/* */
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/* None */
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/* */
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/* OUTPUT */
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/* */
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/* None */
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/* */
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/* CALLS */
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/* */
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/* None */
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/* */
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/* CALLED BY */
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/* */
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/* ISRs */
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/* */
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/* RELEASE HISTORY */
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/* */
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/* DATE NAME DESCRIPTION */
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/* */
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/* 03-08-2023 Scott Larson Initial Version 6.2.1 */
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/* */
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/**************************************************************************/
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/* VOID _tx_thread_context_save(VOID)
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{ */
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.global _tx_thread_context_save
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_tx_thread_context_save:
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/* Upon entry to this routine, it is assumed that interrupts are locked
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out and the interrupt stack fame has been allocated and x1 (ra) has
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been saved on the stack. */
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STORE x5, 19*REGBYTES(sp) // First store t0 and t1
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STORE x6, 18*REGBYTES(sp)
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la x5, _tx_thread_system_state // Pickup address of system state
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LOAD x6, 0(x5) // Pickup system state
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/* Check for a nested interrupt condition. */
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/* if (_tx_thread_system_state++)
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{ */
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beqz x6, _tx_thread_not_nested_save // If 0, first interrupt condition
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addi x6, x6, 1 // Increment the interrupt counter
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STORE x6, 0(x5) // Store the interrupt counter
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/* Nested interrupt condition.
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Save the reset of the scratch registers on the stack and return to the
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calling ISR. */
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STORE x7, 17*REGBYTES(sp) // Store t2
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STORE x8, 12*REGBYTES(sp) // Store s0
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STORE x10, 27*REGBYTES(sp) // Store a0
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STORE x11, 26*REGBYTES(sp) // Store a1
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STORE x12, 25*REGBYTES(sp) // Store a2
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STORE x13, 24*REGBYTES(sp) // Store a3
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STORE x14, 23*REGBYTES(sp) // Store a4
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STORE x15, 22*REGBYTES(sp) // Store a5
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STORE x16, 21*REGBYTES(sp) // Store a6
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STORE x17, 20*REGBYTES(sp) // Store a7
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STORE x28, 16*REGBYTES(sp) // Store t3
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STORE x29, 15*REGBYTES(sp) // Store t4
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STORE x30, 14*REGBYTES(sp) // Store t5
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STORE x31, 13*REGBYTES(sp) // Store t6
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csrr t0, mepc // Load exception program counter
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STORE t0, 30*REGBYTES(sp) // Save it on the stack
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/* Save floating point scratch registers. */
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#if defined(__riscv_float_abi_single)
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fsw f0, 31*REGBYTES(sp) // Store ft0
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fsw f1, 32*REGBYTES(sp) // Store ft1
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fsw f2, 33*REGBYTES(sp) // Store ft2
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fsw f3, 34*REGBYTES(sp) // Store ft3
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fsw f4, 35*REGBYTES(sp) // Store ft4
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fsw f5, 36*REGBYTES(sp) // Store ft5
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fsw f6, 37*REGBYTES(sp) // Store ft6
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fsw f7, 38*REGBYTES(sp) // Store ft7
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fsw f10,41*REGBYTES(sp) // Store fa0
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fsw f11,42*REGBYTES(sp) // Store fa1
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fsw f12,43*REGBYTES(sp) // Store fa2
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fsw f13,44*REGBYTES(sp) // Store fa3
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fsw f14,45*REGBYTES(sp) // Store fa4
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fsw f15,46*REGBYTES(sp) // Store fa5
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fsw f16,47*REGBYTES(sp) // Store fa6
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fsw f17,48*REGBYTES(sp) // Store fa7
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fsw f28,59*REGBYTES(sp) // Store ft8
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fsw f29,60*REGBYTES(sp) // Store ft9
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fsw f30,61*REGBYTES(sp) // Store ft10
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fsw f31,62*REGBYTES(sp) // Store ft11
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csrr t0, fcsr
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STORE t0, 63*REGBYTES(sp) // Store fcsr
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#elif defined(__riscv_float_abi_double)
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fsd f0, 31*REGBYTES(sp) // Store ft0
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fsd f1, 32*REGBYTES(sp) // Store ft1
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fsd f2, 33*REGBYTES(sp) // Store ft2
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fsd f3, 34*REGBYTES(sp) // Store ft3
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fsd f4, 35*REGBYTES(sp) // Store ft4
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fsd f5, 36*REGBYTES(sp) // Store ft5
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fsd f6, 37*REGBYTES(sp) // Store ft6
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fsd f7, 38*REGBYTES(sp) // Store ft7
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fsd f10,41*REGBYTES(sp) // Store fa0
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fsd f11,42*REGBYTES(sp) // Store fa1
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fsd f12,43*REGBYTES(sp) // Store fa2
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fsd f13,44*REGBYTES(sp) // Store fa3
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fsd f14,45*REGBYTES(sp) // Store fa4
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fsd f15,46*REGBYTES(sp) // Store fa5
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fsd f16,47*REGBYTES(sp) // Store fa6
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fsd f17,48*REGBYTES(sp) // Store fa7
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fsd f28,59*REGBYTES(sp) // Store ft8
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fsd f29,60*REGBYTES(sp) // Store ft9
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fsd f30,61*REGBYTES(sp) // Store ft10
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fsd f31,62*REGBYTES(sp) // Store ft11
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csrr t0, fcsr
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STORE t0, 63*REGBYTES(sp) // Store fcsr
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#endif
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#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
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call _tx_execution_isr_enter // Call the ISR execution enter function
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#endif
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ret // Return to calling ISR
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_tx_thread_not_nested_save:
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/* } */
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/* Otherwise, not nested, check to see if a thread was running. */
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/* else if (_tx_thread_current_ptr)
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{ */
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addi x6, x6, 1 // Increment the interrupt counter
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STORE x6, 0(x5) // Store the interrupt counter
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/* Not nested: Find the user thread that was running and load our SP */
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LOAD x5, _tx_thread_current_ptr // Pickup current thread pointer
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beqz x5, _tx_thread_idle_system_save // If NULL, idle system was interrupted
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/* Save the standard scratch registers. */
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STORE x7, 17*REGBYTES(sp) // Store t2
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STORE x8, 12*REGBYTES(sp) // Store s0
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STORE x10, 27*REGBYTES(sp) // Store a0
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STORE x11, 26*REGBYTES(sp) // Store a1
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STORE x12, 25*REGBYTES(sp) // Store a2
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STORE x13, 24*REGBYTES(sp) // Store a3
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STORE x14, 23*REGBYTES(sp) // Store a4
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STORE x15, 22*REGBYTES(sp) // Store a5
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STORE x16, 21*REGBYTES(sp) // Store a6
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STORE x17, 20*REGBYTES(sp) // Store a7
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STORE x28, 16*REGBYTES(sp) // Store t3
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STORE x29, 15*REGBYTES(sp) // Store t4
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STORE x30, 14*REGBYTES(sp) // Store t5
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STORE x31, 13*REGBYTES(sp) // Store t6
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csrr t0, mepc // Load exception program counter
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STORE t0, 30*REGBYTES(sp) // Save it on the stack
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/* Save floating point scratch registers. */
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#if defined(__riscv_float_abi_single)
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fsw f0, 31*REGBYTES(sp) // Store ft0
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fsw f1, 32*REGBYTES(sp) // Store ft1
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fsw f2, 33*REGBYTES(sp) // Store ft2
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fsw f3, 34*REGBYTES(sp) // Store ft3
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fsw f4, 35*REGBYTES(sp) // Store ft4
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fsw f5, 36*REGBYTES(sp) // Store ft5
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fsw f6, 37*REGBYTES(sp) // Store ft6
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fsw f7, 38*REGBYTES(sp) // Store ft7
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fsw f10,41*REGBYTES(sp) // Store fa0
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fsw f11,42*REGBYTES(sp) // Store fa1
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fsw f12,43*REGBYTES(sp) // Store fa2
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fsw f13,44*REGBYTES(sp) // Store fa3
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fsw f14,45*REGBYTES(sp) // Store fa4
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fsw f15,46*REGBYTES(sp) // Store fa5
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fsw f16,47*REGBYTES(sp) // Store fa6
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fsw f17,48*REGBYTES(sp) // Store fa7
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fsw f28,59*REGBYTES(sp) // Store ft8
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fsw f29,60*REGBYTES(sp) // Store ft9
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fsw f30,61*REGBYTES(sp) // Store ft10
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fsw f31,62*REGBYTES(sp) // Store ft11
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csrr t0, fcsr
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STORE t0, 63*REGBYTES(sp) // Store fcsr
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#elif defined(__riscv_float_abi_double)
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fsd f0, 31*REGBYTES(sp) // Store ft0
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fsd f1, 32*REGBYTES(sp) // Store ft1
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fsd f2, 33*REGBYTES(sp) // Store ft2
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fsd f3, 34*REGBYTES(sp) // Store ft3
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fsd f4, 35*REGBYTES(sp) // Store ft4
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fsd f5, 36*REGBYTES(sp) // Store ft5
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fsd f6, 37*REGBYTES(sp) // Store ft6
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fsd f7, 38*REGBYTES(sp) // Store ft7
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fsd f10,41*REGBYTES(sp) // Store fa0
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fsd f11,42*REGBYTES(sp) // Store fa1
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fsd f12,43*REGBYTES(sp) // Store fa2
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fsd f13,44*REGBYTES(sp) // Store fa3
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fsd f14,45*REGBYTES(sp) // Store fa4
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fsd f15,46*REGBYTES(sp) // Store fa5
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fsd f16,47*REGBYTES(sp) // Store fa6
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fsd f17,48*REGBYTES(sp) // Store fa7
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fsd f28,59*REGBYTES(sp) // Store ft8
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fsd f29,60*REGBYTES(sp) // Store ft9
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fsd f30,61*REGBYTES(sp) // Store ft10
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fsd f31,62*REGBYTES(sp) // Store ft11
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csrr t0, fcsr
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STORE t0, 63*REGBYTES(sp) // Store fcsr
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#endif
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/* Save the current stack pointer in the thread's control block. */
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/* _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; */
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/* Switch to the system stack. */
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/* sp = _tx_thread_system_stack_ptr; */
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LOAD t1, _tx_thread_current_ptr // Pickup current thread pointer
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STORE sp, 2*REGBYTES(t1) // Save stack pointer
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#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
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/* _tx_execution_isr_enter is called with thread stack pointer */
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call _tx_execution_isr_enter // Call the ISR execution enter function
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#endif
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LOAD sp, _tx_thread_system_stack_ptr // Switch to system stack
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ret // Return to calling ISR
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/* }
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else
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{ */
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_tx_thread_idle_system_save:
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#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
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call _tx_execution_isr_enter // Call the ISR execution enter function
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#endif
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/* Interrupt occurred in the scheduling loop. */
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/* }
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} */
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#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double)
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addi sp, sp, 65*REGBYTES // Recover stack frame - with floating point enabled
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#else
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addi sp, sp, 32*REGBYTES // Recover the reserved stack space
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#endif
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ret // Return to calling ISR
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