7iwind/threadx
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Release 6.2.1 on 08 Mar 2023. Expand to see details.

Browse Source 
cee19603d Include tx_user.h conditionally.
e40e08007 Update owners
d69641273 Update release date and version
394aee52f Add tx_user.h to GNU port assembly files
5cca2ddd0 RISC-V 64 bit port for Microchip
e0f2c373c Link Winmm.lib that required by the high-resolution timer.
6af472a68 Update Win32 port with high resolution timer.
aea7b556a Add DMB ISH barrier inst in ARMv8-A SMP scheduler
19091a262 Add .section .preamble to m3 m4 m7 module ports
ced60e1b7 Add missing parenthesis in ports assembly file
309dc77ca Modules Cortex-A7 IAR new port
c752a4063 Modules Cortex-A7 GNU new port
dc224b90f Fix race condition in tx_thread_wait_abort and update regression test
6e261f5b7 create threadx cmsis-pack
This commit is contained in:
Tiejun Zhou
2023-03-08 08:26:22 +00:00
parent 745395d6a2
commit 2aa19f3de0
1026 changed files with 53474 additions and 5969 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
ports_module/cortex_m4/ac6/inc/tx_port.h
View File

@@ -720,7 +720,7 @@ void tx_thread_fpu_disable(void);
#ifdef TX_THREAD_INIT
CHAR _tx_version_id[] =
"Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M4 Version 6.2.0 *";
"Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M4 Version 6.2.1 *";
#else
#ifdef TX_MISRA_ENABLE
extern CHAR _tx_version_id[100];

147
ports_module/cortex_m4/ac6/inc/txm_module_port.h
View File

@@ -25,8 +25,8 @@
/* */
/* APPLICATION INTERFACE DEFINITION RELEASE */
/* */
/* txm_module_port.h Cortex-M4/AC6 */
/* 6.1.12 */
/* txm_module_port.h Cortex-M4 */
/* 6.2.1 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -47,6 +47,12 @@
/* 07-29-2022 Scott Larson Enabled user-defined and */
/* default MPU settings, */
/* resulting in version 6.1.12 */
/* 10-31-2022 Scott Larson Configure heap size, */
/* resulting in version 6.2.0 */
/* 03-08-2023 Scott Larson Set default values for RBAR, */
/* unify this file for all */
/* compilers, */
/* resulting in version 6.2.1 */
/* */
/**************************************************************************/
@@ -68,6 +74,22 @@
following extensions to the ThreadX thread control block (this code should replace
the corresponding macro define in tx_port.h):
#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT
#define TX_THREAD_EXTENSION_2 VOID *tx_thread_module_instance_ptr; \
VOID *tx_thread_module_entry_info_ptr; \
ULONG tx_thread_module_current_user_mode; \
ULONG tx_thread_module_user_mode; \
ULONG tx_thread_module_saved_lr; \
VOID *tx_thread_module_kernel_stack_start; \
VOID *tx_thread_module_kernel_stack_end; \
ULONG tx_thread_module_kernel_stack_size; \
VOID *tx_thread_module_stack_ptr; \
VOID *tx_thread_module_stack_start; \
VOID *tx_thread_module_stack_end; \
ULONG tx_thread_module_stack_size; \
VOID *tx_thread_module_reserved; \
VOID *tx_thread_iar_tls_pointer;
#else
#define TX_THREAD_EXTENSION_2 VOID *tx_thread_module_instance_ptr; \
VOID *tx_thread_module_entry_info_ptr; \
ULONG tx_thread_module_current_user_mode; \
@@ -81,6 +103,7 @@
VOID *tx_thread_module_stack_end; \
ULONG tx_thread_module_stack_size; \
VOID *tx_thread_module_reserved;
#endif
The following extensions must also be defined in tx_port.h:
@@ -123,14 +146,15 @@ The following extensions must also be defined in tx_port.h:
#endif
/* For Cortex-M devices with 16 MPU regions, the last four regions (12-15)
are not used by ThreadX. These may be defined by the user. */
#define TXM_MODULE_MPU_USER_DEFINED_RBAR_12 0
are not used by ThreadX. These may be defined by the user.
RBAR needs the valid bit and region number set, as MPU alias registers are used. */
#define TXM_MODULE_MPU_USER_DEFINED_RBAR_12 0x1C
#define TXM_MODULE_MPU_USER_DEFINED_RASR_12 0
#define TXM_MODULE_MPU_USER_DEFINED_RBAR_13 0
#define TXM_MODULE_MPU_USER_DEFINED_RBAR_13 0x1D
#define TXM_MODULE_MPU_USER_DEFINED_RASR_13 0
#define TXM_MODULE_MPU_USER_DEFINED_RBAR_14 0
#define TXM_MODULE_MPU_USER_DEFINED_RBAR_14 0x1E
#define TXM_MODULE_MPU_USER_DEFINED_RASR_14 0
#define TXM_MODULE_MPU_USER_DEFINED_RBAR_15 0
#define TXM_MODULE_MPU_USER_DEFINED_RBAR_15 0x1F
#define TXM_MODULE_MPU_USER_DEFINED_RASR_15 0
@@ -141,38 +165,39 @@ The following extensions must also be defined in tx_port.h:
and the defines below are not used.
If TXM_MODULE_MPU_DEFAULT is defined, the MPU is configured to the
below values when a thread that is not owned by a module is running. */
#define TXM_MODULE_MPU_DEFAULT_RBAR_0 0
below values when a thread that is not owned by a module is running.
RBAR needs the valid bit and region number set, as MPU alias registers are used. */
#define TXM_MODULE_MPU_DEFAULT_RBAR_0 0x10
#define TXM_MODULE_MPU_DEFAULT_RASR_0 0
#define TXM_MODULE_MPU_DEFAULT_RBAR_1 0
#define TXM_MODULE_MPU_DEFAULT_RBAR_1 0x11
#define TXM_MODULE_MPU_DEFAULT_RASR_1 0
#define TXM_MODULE_MPU_DEFAULT_RBAR_2 0
#define TXM_MODULE_MPU_DEFAULT_RBAR_2 0x12
#define TXM_MODULE_MPU_DEFAULT_RASR_2 0
#define TXM_MODULE_MPU_DEFAULT_RBAR_3 0
#define TXM_MODULE_MPU_DEFAULT_RBAR_3 0x13
#define TXM_MODULE_MPU_DEFAULT_RASR_3 0
#define TXM_MODULE_MPU_DEFAULT_RBAR_4 0
#define TXM_MODULE_MPU_DEFAULT_RBAR_4 0x14
#define TXM_MODULE_MPU_DEFAULT_RASR_4 0
#define TXM_MODULE_MPU_DEFAULT_RBAR_5 0
#define TXM_MODULE_MPU_DEFAULT_RBAR_5 0x15
#define TXM_MODULE_MPU_DEFAULT_RASR_5 0
#define TXM_MODULE_MPU_DEFAULT_RBAR_6 0
#define TXM_MODULE_MPU_DEFAULT_RBAR_6 0x16
#define TXM_MODULE_MPU_DEFAULT_RASR_6 0
#define TXM_MODULE_MPU_DEFAULT_RBAR_7 0
#define TXM_MODULE_MPU_DEFAULT_RBAR_7 0x17
#define TXM_MODULE_MPU_DEFAULT_RASR_7 0
#define TXM_MODULE_MPU_DEFAULT_RBAR_8 0
#define TXM_MODULE_MPU_DEFAULT_RBAR_8 0x18
#define TXM_MODULE_MPU_DEFAULT_RASR_8 0
#define TXM_MODULE_MPU_DEFAULT_RBAR_9 0
#define TXM_MODULE_MPU_DEFAULT_RBAR_9 0x19
#define TXM_MODULE_MPU_DEFAULT_RASR_9 0
#define TXM_MODULE_MPU_DEFAULT_RBAR_10 0
#define TXM_MODULE_MPU_DEFAULT_RBAR_10 0x1A
#define TXM_MODULE_MPU_DEFAULT_RASR_10 0
#define TXM_MODULE_MPU_DEFAULT_RBAR_11 0
#define TXM_MODULE_MPU_DEFAULT_RBAR_11 0x1B
#define TXM_MODULE_MPU_DEFAULT_RASR_11 0
#define TXM_MODULE_MPU_DEFAULT_RBAR_12 0
#define TXM_MODULE_MPU_DEFAULT_RBAR_12 0x1C
#define TXM_MODULE_MPU_DEFAULT_RASR_12 0
#define TXM_MODULE_MPU_DEFAULT_RBAR_13 0
#define TXM_MODULE_MPU_DEFAULT_RBAR_13 0x1D
#define TXM_MODULE_MPU_DEFAULT_RASR_13 0
#define TXM_MODULE_MPU_DEFAULT_RBAR_14 0
#define TXM_MODULE_MPU_DEFAULT_RBAR_14 0x1E
#define TXM_MODULE_MPU_DEFAULT_RASR_14 0
#define TXM_MODULE_MPU_DEFAULT_RBAR_15 0
#define TXM_MODULE_MPU_DEFAULT_RBAR_15 0x1F
#define TXM_MODULE_MPU_DEFAULT_RASR_15 0
@@ -226,24 +251,16 @@ The following extensions must also be defined in tx_port.h:
/* Define other module port-specific constants. */
/* Define INLINE_DECLARE to inline for ARM compiler. */
/* Define INLINE_DECLARE to inline for this compiler. */
#define INLINE_DECLARE inline
#ifdef TXM_MODULE_MANAGER_16_MPU
#define TXM_MPU_VALID_BIT 0x10
#define TXM_ENABLE_REGION 0x01
#define TXM_MODULE_MANAGER_MPU_KERNEL_ENTRY_INDEX 0
/* Define the number of MPU entries assigned to the code and data sections.
On some Cortex-M7 parts, there are 16 total entries. ThreadX uses one for access
to the kernel entry function, thus 15 remain for code and data protection. */
#define TXM_MODULE_MPU_TOTAL_ENTRIES 16
#define TXM_MODULE_MPU_CODE_ENTRIES 4
#define TXM_MODULE_MPU_DATA_ENTRIES 4
#define TXM_MODULE_MPU_SHARED_ENTRIES 3
#define TXM_MODULE_MPU_KERNEL_ENTRY_INDEX 0
#define TXM_MODULE_MPU_SHARED_INDEX 9
#define TXM_ENABLE_REGION 0x01
/* Shared memory region attributes. */
#define TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE 1
#define TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT 0x01000000
/* There are 2 registers to set up each MPU region: MPU_RBAR, MPU_RASR. */
typedef struct TXM_MODULE_MPU_INFO_STRUCT
@@ -251,44 +268,50 @@ typedef struct TXM_MODULE_MPU_INFO_STRUCT
ULONG txm_module_mpu_region_address;
ULONG txm_module_mpu_region_attribute_size;
} TXM_MODULE_MPU_INFO;
/* Shared memory region attributes. */
#define TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE 1
#define TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT 0x01000000
#ifdef TXM_MODULE_MANAGER_16_MPU
/* Define the number of MPU entries assigned to the code and data sections.
On some Cortex-M7 parts, there are 16 total entries. ThreadX uses one for access
to the kernel entry function, thus 15 remain for code and data protection. */
#define TXM_MODULE_MANAGER_MPU_TOTAL_ENTRIES 16
#define TXM_MODULE_MANAGER_MPU_CODE_ENTRIES 4
#define TXM_MODULE_MANAGER_MPU_DATA_ENTRIES 4
#define TXM_MODULE_MANAGER_MPU_SHARED_ENTRIES 3
#define TXM_MODULE_MANAGER_MPU_SHARED_INDEX 9
#define TXM_MODULE_MANAGER_MPU_USER_REGION_INDEX 12
/* Define the port-extensions to the module manager instance structure. */
#define TXM_MODULE_MANAGER_PORT_EXTENSION \
TXM_MODULE_MPU_INFO txm_module_instance_mpu_registers[TXM_MODULE_MPU_TOTAL_ENTRIES]; \
ULONG txm_module_instance_shared_memory_count; \
ULONG txm_module_instance_shared_memory_address[TXM_MODULE_MPU_SHARED_ENTRIES]; \
ULONG txm_module_instance_shared_memory_length[TXM_MODULE_MPU_SHARED_ENTRIES];
#define TXM_MODULE_MANAGER_PORT_EXTENSION \
TXM_MODULE_MPU_INFO txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_MPU_TOTAL_ENTRIES]; \
ULONG txm_module_instance_shared_memory_count; \
ULONG txm_module_instance_shared_memory_address[TXM_MODULE_MANAGER_MPU_SHARED_ENTRIES]; \
ULONG txm_module_instance_shared_memory_length[TXM_MODULE_MANAGER_MPU_SHARED_ENTRIES];
#else /* TXM_MODULE_MANAGER_16_MPU is not defined */
/* Define the number of MPU entries assigned to the code and data sections.
On Cortex-M3, M4, and some M7 parts, there are 8 total entries. ThreadX uses one for access
to the kernel entry function, thus 7 remain for code and data protection. */
#define TXM_MODULE_MANAGER_CODE_MPU_ENTRIES 4
#define TXM_MODULE_MANAGER_DATA_MPU_ENTRIES 3
#define TXM_MODULE_MANAGER_SHARED_MPU_INDEX 8
#define TXM_MODULE_MANAGER_SHARED_MPU_REGION 4
/* Shared memory region attributes. */
#define TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE 1
#define TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT 0x01000000
#define TXM_MODULE_MANAGER_MPU_TOTAL_ENTRIES 8
#define TXM_MODULE_MANAGER_CODE_MPU_ENTRIES 4
#define TXM_MODULE_MANAGER_DATA_MPU_ENTRIES 3
#define TXM_MODULE_MANAGER_SHARED_MPU_REGION 4
/* Define the port-extensions to the module manager instance structure. */
#define TXM_MODULE_MANAGER_PORT_EXTENSION \
ULONG txm_module_instance_mpu_registers[16]; \
ULONG txm_module_instance_shared_memory_address; \
ULONG txm_module_instance_shared_memory_length;
#define TXM_MODULE_MANAGER_PORT_EXTENSION \
TXM_MODULE_MPU_INFO txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_MPU_TOTAL_ENTRIES]; \
ULONG txm_module_instance_shared_memory_address; \
ULONG txm_module_instance_shared_memory_length;
#endif /* TXM_MODULE_MANAGER_16_MPU */
/* Define the memory fault information structure that is populated when a memory fault occurs. */
typedef struct TXM_MODULE_MANAGER_MEMORY_FAULT_INFO_STRUCT
{
TX_THREAD *txm_module_manager_memory_fault_info_thread_ptr;
@@ -441,6 +464,6 @@ UINT _txm_module_manager_inside_data_check(TXM_MODULE_INSTANCE *module_instance
#define TXM_MODULE_MANAGER_VERSION_ID \
CHAR _txm_module_manager_version_id[] = \
"Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M4/AC6 Version 6.1.12 *";
"Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M4 Version 6.2.1 *";
#endif

6
ports_module/cortex_m4/ac6/module_manager/src/tx_thread_context_restore.S
View File

@@ -20,6 +20,8 @@
/**************************************************************************/
/**************************************************************************/
#include "tx_user.h"
#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE))
.global _tx_execution_isr_exit
#endif
@@ -32,7 +34,7 @@
/* FUNCTION RELEASE */
/* */
/* _tx_thread_context_restore Cortex-M4/AC6 */
/* 6.1.7 */
/* 6.2.1 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -63,6 +65,8 @@
/* DATE NAME DESCRIPTION */
/* */
/* 06-02-2021 Scott Larson Initial Version 6.1.7 */
/* 03-08-2023 Scott Larson Include tx_user.h, */
/* resulting in version 6.2.1 */
/* */
/**************************************************************************/
// VOID _tx_thread_context_restore(VOID)

6
ports_module/cortex_m4/ac6/module_manager/src/tx_thread_context_save.S
View File

@@ -20,6 +20,8 @@
/**************************************************************************/
/**************************************************************************/
#include "tx_user.h"
.text
.align 4
.syntax unified
@@ -31,7 +33,7 @@
/* FUNCTION RELEASE */
/* */
/* _tx_thread_context_save Cortex-M4/AC6 */
/* 6.1.7 */
/* 6.2.1 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -62,6 +64,8 @@
/* DATE NAME DESCRIPTION */
/* */
/* 06-02-2021 Scott Larson Initial Version 6.1.7 */
/* 03-08-2023 Scott Larson Include tx_user.h, */
/* resulting in version 6.2.1 */
/* */
/**************************************************************************/
// VOID _tx_thread_context_save(VOID)

6
ports_module/cortex_m4/ac6/module_manager/src/tx_thread_interrupt_control.S
View File

@@ -20,6 +20,8 @@
/**************************************************************************/
/**************************************************************************/
#include "tx_user.h"
.text 32
.align 4
.syntax unified
@@ -28,7 +30,7 @@
/* FUNCTION RELEASE */
/* */
/* _tx_thread_interrupt_control Cortex-M4/AC6 */
/* 6.1.7 */
/* 6.2.1 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -59,6 +61,8 @@
/* DATE NAME DESCRIPTION */
/* */
/* 06-02-2021 Scott Larson Initial Version 6.1.7 */
/* 03-08-2023 Scott Larson Include tx_user.h, */
/* resulting in version 6.2.1 */
/* */
/**************************************************************************/
// UINT _tx_thread_interrupt_control(UINT new_posture)

6
ports_module/cortex_m4/ac6/module_manager/src/tx_thread_interrupt_disable.S
View File

@@ -20,6 +20,8 @@
/**************************************************************************/
/**************************************************************************/
#include "tx_user.h"
.text 32
.align 4
.syntax unified
@@ -28,7 +30,7 @@
/* FUNCTION RELEASE */
/* */
/* _tx_thread_interrupt_disable Cortex-M4/AC6 */
/* 6.1.7 */
/* 6.2.1 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -59,6 +61,8 @@
/* DATE NAME DESCRIPTION */
/* */
/* 06-02-2021 Scott Larson Initial Version 6.1.7 */
/* 03-08-2023 Scott Larson Include tx_user.h, */
/* resulting in version 6.2.1 */
/* */
/**************************************************************************/
// UINT _tx_thread_interrupt_disable(VOID)

6
ports_module/cortex_m4/ac6/module_manager/src/tx_thread_interrupt_restore.S
View File

@@ -20,6 +20,8 @@
/**************************************************************************/
/**************************************************************************/
#include "tx_user.h"
.text 32
.align 4
.syntax unified
@@ -28,7 +30,7 @@
/* FUNCTION RELEASE */
/* */
/* _tx_thread_interrupt_restore Cortex-M4/AC6 */
/* 6.1.7 */
/* 6.2.1 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -59,6 +61,8 @@
/* DATE NAME DESCRIPTION */
/* */
/* 06-02-2021 Scott Larson Initial Version 6.1.7 */
/* 03-08-2023 Scott Larson Include tx_user.h, */
/* resulting in version 6.2.1 */
/* */
/**************************************************************************/
// VOID _tx_thread_interrupt_restore(UINT previous_posture)

6
ports_module/cortex_m4/ac6/module_manager/src/tx_thread_stack_build.S
View File

@@ -20,6 +20,8 @@
/**************************************************************************/
/**************************************************************************/
#include "tx_user.h"
.text
.align 4
.syntax unified
@@ -28,7 +30,7 @@
/* FUNCTION RELEASE */
/* */
/* _tx_thread_stack_build Cortex-M4/AC6 */
/* 6.1.7 */
/* 6.2.1 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -61,6 +63,8 @@
/* DATE NAME DESCRIPTION */
/* */
/* 06-02-2021 Scott Larson Initial Version 6.1.7 */
/* 03-08-2023 Scott Larson Include tx_user.h, */
/* resulting in version 6.2.1 */
/* */
/**************************************************************************/
// VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID))

6
ports_module/cortex_m4/ac6/module_manager/src/tx_thread_system_return.S
View File

@@ -20,6 +20,8 @@
/**************************************************************************/
/**************************************************************************/
#include "tx_user.h"
.text 32
.align 4
.syntax unified
@@ -28,7 +30,7 @@
/* FUNCTION RELEASE */
/* */
/* _tx_thread_system_return Cortex-M4/AC6 */
/* 6.1.7 */
/* 6.2.1 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -61,6 +63,8 @@
/* DATE NAME DESCRIPTION */
/* */
/* 06-02-2021 Scott Larson Initial Version 6.1.7 */
/* 03-08-2023 Scott Larson Include tx_user.h, */
/* resulting in version 6.2.1 */
/* */
/**************************************************************************/
// VOID _tx_thread_system_return(VOID)

6
ports_module/cortex_m4/ac6/module_manager/src/tx_timer_interrupt.S
View File

@@ -20,6 +20,8 @@
/**************************************************************************/
/**************************************************************************/
#include "tx_user.h"
.global _tx_timer_time_slice
.global _tx_timer_system_clock
.global _tx_timer_current_ptr
@@ -38,7 +40,7 @@
/* FUNCTION RELEASE */
/* */
/* _tx_timer_interrupt Cortex-M4/AC6 */
/* 6.1.10 */
/* 6.2.1 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -75,6 +77,8 @@
/* 01-31-2022 Scott Larson Modified comment(s), added */
/* TX_NO_TIMER support, */
/* resulting in version 6.1.10 */
/* 03-08-2023 Scott Larson Include tx_user.h, */
/* resulting in version 6.2.1 */
/* */
/**************************************************************************/
// VOID _tx_timer_interrupt(VOID)

20
ports_module/cortex_m4/ac6/module_manager/src/txm_module_manager_external_memory_enable.c
View File

@@ -34,7 +34,7 @@
/* FUNCTION RELEASE */
/* */
/* _txm_module_manager_external_memory_enable Cortex-M4 */
/* 6.1.9 */
/* 6.2.1 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -71,6 +71,8 @@
/* DATE NAME DESCRIPTION */
/* */
/* 10-15-2021 Scott Larson Initial Version 6.1.9 */
/* 03-08-2023 Scott Larson Update defines, */
/* resulting in version 6.2.1 */
/* */
/**************************************************************************/
UINT _txm_module_manager_external_memory_enable(TXM_MODULE_INSTANCE *module_instance,
@@ -125,7 +127,7 @@ ULONG attributes_check = 0;
}
/* Determine if there are shared memory entries available. */
if(module_instance -> txm_module_instance_shared_memory_count >= TXM_MODULE_MPU_SHARED_ENTRIES)
if(module_instance -> txm_module_instance_shared_memory_count >= TXM_MODULE_MANAGER_MPU_SHARED_ENTRIES)
{
/* Release the protection mutex. */
_tx_mutex_put(&_txm_module_manager_mutex);
@@ -152,19 +154,19 @@ ULONG attributes_check = 0;
Set up MPU registers. */
/* Pick up index into shared memory entries. */
shared_index = TXM_MODULE_MPU_SHARED_INDEX + module_instance -> txm_module_instance_shared_memory_count;
shared_index = TXM_MODULE_MANAGER_MPU_SHARED_INDEX + module_instance -> txm_module_instance_shared_memory_count;
/* Save address register with address, MPU region, set Valid bit. */
module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_address = address | shared_index | 0x10;
module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_address = address | shared_index | TXM_MPU_VALID_BIT;
/* Calculate the region size. */
region_size = (_txm_module_manager_region_size_get(block_size) << 1);
region_size = _txm_module_manager_region_size_get(block_size);
/* Calculate the subregion bits. */
srd_bits = _txm_module_manager_calculate_srd_bits(block_size, length);
/* Generate SRD, size, and enable attributes. */
size_register = srd_bits | region_size | TXM_ENABLE_REGION | TXM_MODULE_MPU_SHARED_ACCESS_CONTROL;
size_register = srd_bits | (region_size << 1) | TXM_ENABLE_REGION | TXM_MODULE_MPU_SHARED_ACCESS_CONTROL;
/* Check for optional write attribute. */
if(attributes & TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE)
@@ -262,10 +264,10 @@ TXM_MODULE_PREAMBLE *module_preamble;
/* At this point, we have a valid address and block size.
Set up MPU registers. */
module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_INDEX] = address | TXM_MODULE_MANAGER_SHARED_MPU_REGION | 0x10;
module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_REGION].txm_module_mpu_region_address = address | TXM_MODULE_MANAGER_SHARED_MPU_REGION | TXM_MPU_VALID_BIT;
/* Calculate the region size. */
region_size = (_txm_module_manager_region_size_get(block_size) << 1);
region_size = _txm_module_manager_region_size_get(block_size);
/* Calculate the subregion bits. */
subregion_bits = _txm_module_manager_calculate_srd_bits(block_size, length);
@@ -276,7 +278,7 @@ TXM_MODULE_PREAMBLE *module_preamble;
}
/* Build register with attributes. */
module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_INDEX+1] = region_size | subregion_bits | attributes_check | 0x12070001;
module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_REGION].txm_module_mpu_region_attribute_size = (region_size << 1) | subregion_bits | attributes_check | TXM_MODULE_MPU_SHARED_ACCESS_CONTROL | TXM_ENABLE_REGION;
/* Keep track of shared memory address and length in module instance. */
module_instance -> txm_module_instance_shared_memory_address = address;

574
ports_module/cortex_m4/ac6/module_manager/src/txm_module_manager_mm_register_setup.c
View File

@@ -68,7 +68,7 @@ const ULONG txm_module_default_mpu_registers[32] =
/* FUNCTION RELEASE */
/* */
/* _txm_module_manager_region_size_get Cortex-M4 */
/* 6.1.9 */
/* 6.2.1 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -81,6 +81,7 @@ const ULONG txm_module_default_mpu_registers[32] =
/* INPUT */
/* */
/* block_size Size of the block in bytes */
/* Must be a power of two */
/* */
/* OUTPUT */
/* */
@@ -99,86 +100,32 @@ const ULONG txm_module_default_mpu_registers[32] =
/* DATE NAME DESCRIPTION */
/* */
/* 10-15-2021 Scott Larson Initial Version 6.1.9 */
/* 03-08-2023 Scott Larson Changed from lookup table to */
/* calculation and check for */
/* minumum block size, */
/* resulting in version 6.2.1 */
/* */
/**************************************************************************/
ULONG _txm_module_manager_region_size_get(ULONG block_size)
{
ULONG return_value;
ULONG return_value = 5; /* 5 is the region size for 64 byte block. */
/* Process relative to the input block size. */
if (block_size == 32)
/* Check if at or below minumum block size. */
if (block_size <= 32)
{
return_value = 0x04;
/* Return minimum region size. */
return 0x04;
}
else if (block_size == 64)
/* Remove some trailing zeros from block_size. */
block_size = block_size >> 6;
/* Increment return_value until block_size lsb is set. */
while((block_size & 1) == 0)
{
return_value = 0x05;
}
else if (block_size == 128)
{
return_value = 0x06;
}
else if (block_size == 256)
{
return_value = 0x07;
}
else if (block_size == 512)
{
return_value = 0x08;
}
else if (block_size == 1024)
{
return_value = 0x09;
}
else if (block_size == 2048)
{
return_value = 0x0A;
}
else if (block_size == 4096)
{
return_value = 0x0B;
}
else if (block_size == 8192)
{
return_value = 0x0C;
}
else if (block_size == 16384)
{
return_value = 0x0D;
}
else if (block_size == 32768)
{
return_value = 0x0E;
}
else if (block_size == 65536)
{
return_value = 0x0F;
}
else if (block_size == 131072)
{
return_value = 0x10;
}
else if (block_size == 262144)
{
return_value = 0x11;
}
else if (block_size == 524288)
{
return_value = 0x12;
}
else if (block_size == 1048576)
{
return_value = 0x13;
}
else if (block_size == 2097152)
{
return_value = 0x14;
}
else
{
/* Max 4MB MPU pages for modules. */
return_value = 0x15;
block_size = block_size >> 1;
return_value++;
}
return(return_value);
@@ -235,10 +182,10 @@ UINT srd_bit_index;
{
/* Divide block_size by 8 by shifting right 3. Result is size of subregion. */
block_size = block_size >> 3;
/* Set SRD index into attribute register. */
srd_bit_index = 8;
/* If subregion overlaps length, move to the next subregion. */
while(length > block_size)
{
@@ -250,7 +197,7 @@ UINT srd_bit_index;
{
srd_bit_index++;
}
/* Set unused subregion bits. */
while(srd_bit_index < 16)
{
@@ -258,7 +205,7 @@ UINT srd_bit_index;
srd_bit_index++;
}
}
return(srd_bits);
}
@@ -268,7 +215,7 @@ UINT srd_bit_index;
/* FUNCTION RELEASE */
/* */
/* _txm_module_manager_mm_register_setup Cortex-M4 */
/* 6.1.12 */
/* 6.2.1 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -284,7 +231,7 @@ UINT srd_bit_index;
/* 1 Module code region */
/* 2 Module code region */
/* 3 Module code region */
/* 4 Module code region */
/* 4 Module code region [optional shared memory region] */
/* 5 Module data region */
/* 6 Module data region */
/* 7 Module data region */
@@ -333,6 +280,10 @@ UINT srd_bit_index;
/* 10-15-2021 Scott Larson Initial Version 6.1.9 */
/* 07-29-2022 Scott Larson Enable user defined regions, */
/* resulting in version 6.1.12 */
/* 03-08-2023 Scott Larson Initialize unused MPU region, */
/* fix MPU settings for region */
/* size less than 32 bytes, */
/* resulting in version 6.2.1 */
/* */
/**************************************************************************/
VOID _txm_module_manager_mm_register_setup(TXM_MODULE_INSTANCE *module_instance)
@@ -348,27 +299,24 @@ ULONG callback_stack_size;
ULONG block_size;
ULONG region_size;
ULONG srd_bits = 0;
UINT mpu_table_index;
UINT mpu_table_index = 1;
UINT i;
/* Setup the first MPU region for kernel mode entry. */
/* Set address register to user mode entry function address, which is guaranteed to be at least 32-byte aligned.
Mask address to proper range, region 0, set Valid bit. */
module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MPU_KERNEL_ENTRY_INDEX].txm_module_mpu_region_address = ((ULONG) _txm_module_manager_user_mode_entry & 0xFFFFFFE0) | 0x10;
/* Set the attributes, size (32 bytes) and enable bit. */
module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MPU_KERNEL_ENTRY_INDEX].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_CODE_ACCESS_CONTROL | (_txm_module_manager_region_size_get(32) << 1) | TXM_ENABLE_REGION;
module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_MPU_KERNEL_ENTRY_INDEX].txm_module_mpu_region_address = ((ULONG) _txm_module_manager_user_mode_entry & 0xFFFFFFE0) | TXM_MPU_VALID_BIT;
/* Set the attributes, region size (32 bytes), and enable bit. */
module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_MPU_KERNEL_ENTRY_INDEX].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_CODE_ACCESS_CONTROL | 0x08 | TXM_ENABLE_REGION;
/* End of kernel mode entry setup. */
/* Setup code protection. */
/* Initialize the MPU table index. */
mpu_table_index = 1;
/* Pickup code starting address and actual size. */
code_address = (ULONG) module_instance -> txm_module_instance_code_start;
code_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_code_size;
/* Determine code block sizes. Minimize the alignment requirement.
There are 4 MPU code entries available. The following is how the code size
will be distributed:
@@ -376,67 +324,100 @@ UINT i;
2. 1/4 of the largest power of two that is greater than or equal to code size.
3. Largest power of 2 that fits in the remaining space.
4. Smallest power of 2 that exceeds the remaining space, minimum 32. */
/* Now loop through to setup MPU protection for the code area. */
for (i = 0; i < TXM_MODULE_MPU_CODE_ENTRIES; i++)
for (i = 0; i < TXM_MODULE_MANAGER_MPU_CODE_ENTRIES; i++)
{
/* First two MPU blocks are 1/4 of the largest power of two
that is greater than or equal to code size. */
if (i < 2)
switch(i)
{
block_size = _txm_power_of_two_block_size(code_size) >> 2;
/* First two MPU blocks are 1/4 of the largest power of two
that is greater than or equal to code size. */
case 0:
{
block_size = _txm_power_of_two_block_size(code_size) >> 2;
break;
}
case 2:
{
/* Third MPU block is the largest power of 2 that fits within the remaining space. */
/* Subtract (block_size*2) from code_size to calculate remaining space. */
code_size = code_size - (block_size << 1);
block_size = _txm_power_of_two_block_size(code_size);
/* Minimum block size is 32. */
if(block_size > 32)
{
/* POW2 function result is divided by two to fit in the remaining space. */
block_size = block_size >> 1;
}
break;
}
case 3:
{
/* Last MPU block is the smallest power of 2 that exceeds the remaining space, minimum 32. */
/* Calculate remaining space. */
if(code_size - block_size > code_size)
{
/* Case 2 covered the remaining code size. This region will not be used. */
block_size = 0;
}
else
{
code_size = code_size - block_size;
block_size = _txm_power_of_two_block_size(code_size);
srd_bits = _txm_module_manager_calculate_srd_bits(block_size, code_size);
}
break;
}
default:
{
/* Case 1 is the same as 0 - the block size was already calculated. */
break;
}
}
/* Third MPU block is the largest power of 2 that fits in the remaining space. */
else if (i == 2)
/* Build the base address register with address, MPU region, set Valid bit. */
module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = (code_address & ~(block_size - 1)) | mpu_table_index | TXM_MPU_VALID_BIT;
/* Only configure attribute register if the block is valid. */
if(block_size)
{
/* Subtract (block_size*2) from code_size to calculate remaining space. */
code_size = code_size - (block_size << 1);
block_size = _txm_power_of_two_block_size(code_size) >> 1;
/* Calculate the region size information. */
region_size = _txm_module_manager_region_size_get(block_size);
/* Build the attribute-size register with permissions, SRD, size, enable. */
module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_CODE_ACCESS_CONTROL | srd_bits | (region_size << 1) | TXM_ENABLE_REGION;
/* Adjust the code address. */
code_address = code_address + block_size;
}
/* Last MPU block is the smallest power of 2 that exceeds the remaining space, minimum 32. */
else
{
/* Calculate remaining space. */
code_size = code_size - block_size;
block_size = _txm_power_of_two_block_size(code_size);
srd_bits = _txm_module_manager_calculate_srd_bits(block_size, code_size);
module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = 0;
}
/* Calculate the region size information. */
region_size = (_txm_module_manager_region_size_get(block_size) << 1);
/* Build the base address register with address, MPU region, set Valid bit. */
module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = (code_address & ~(block_size - 1)) | mpu_table_index | 0x10;
/* Build the attribute-size register with permissions, SRD, size, enable. */
module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_CODE_ACCESS_CONTROL | srd_bits | region_size | TXM_ENABLE_REGION;
/* Adjust the code address. */
code_address = code_address + block_size;
/* Increment MPU table index. */
mpu_table_index++;
}
/* End of code protection. */
/* Setup data protection. */
/* Reset SRD bitfield. */
srd_bits = 0;
/* Pickup data starting address and actual size. */
data_address = (ULONG) module_instance -> txm_module_instance_data_start;
/* Adjust the size of the module elements to be aligned to the default alignment. We do this
so that when we partition the allocated memory, we can simply place these regions right beside
each other without having to align their pointers. Note this only works when they all have
the same alignment. */
data_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_data_size;
start_stop_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_start_stop_stack_size;
callback_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_callback_stack_size;
data_size = ((data_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT;
start_stop_stack_size = ((start_stop_stack_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT;
@@ -445,7 +426,7 @@ UINT i;
/* Update the data size to include thread stacks. */
data_size = data_size + start_stop_stack_size + callback_stack_size;
/* Determine data block sizes. Minimize the alignment requirement.
There are 4 MPU data entries available. The following is how the data size
will be distributed:
@@ -453,45 +434,89 @@ UINT i;
2. 1/4 of the largest power of two that is greater than or equal to data size.
3. Largest power of 2 that fits in the remaining space.
4. Smallest power of 2 that exceeds the remaining space, minimum 32. */
/* Now loop through to setup MPU protection for the data area. */
for (i = 0; i < TXM_MODULE_MPU_DATA_ENTRIES; i++)
for (i = 0; i < TXM_MODULE_MANAGER_MPU_DATA_ENTRIES; i++)
{
/* First two MPU blocks are 1/4 of the largest power of two
that is greater than or equal to data size. */
if (i < 2)
switch(i)
{
block_size = _txm_power_of_two_block_size(data_size) >> 2;
/* First two MPU blocks are 1/4 of the largest power of two
that is greater than or equal to data size. */
case 0:
{
block_size = _txm_power_of_two_block_size(data_size) >> 2;
break;
}
case 2:
{
/* Third MPU block is the largest power of 2 that fits within the remaining space. */
/* Subtract (block_size*2) from data_size to calculate remaining space. */
data_size = data_size - (block_size << 1);
block_size = _txm_power_of_two_block_size(data_size);
/* Minimum block size is 32. */
if(block_size > 32)
{
/* POW2 function result is divided by two to fit in the remaining space. */
block_size = block_size >> 1;
}
break;
}
case 3:
{
/* Last MPU block is the smallest power of 2 that exceeds the remaining space, minimum 32. */
/* Calculate remaining space. */
if(data_size - block_size > data_size)
{
/* Case 2 covered the remaining data size. This region will not be used. */
block_size = 0;
}
else
{
data_size = data_size - block_size;
block_size = _txm_power_of_two_block_size(data_size);
srd_bits = _txm_module_manager_calculate_srd_bits(block_size, data_size);
}
break;
}
default:
{
/* Case 1 is the same as 0 - the block size was already calculated. */
break;
}
}
/* Third MPU block is the largest power of 2 that fits in the remaining space. */
else if (i == 2)
/* Build the base address register with address, MPU region, set Valid bit. */
module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = (data_address & ~(block_size - 1)) | mpu_table_index | TXM_MPU_VALID_BIT;
/* Only configure attribute register if the block is valid. */
if(block_size)
{
/* Subtract (block_size*2) from data_size to calculate remaining space. */
data_size = data_size - (block_size << 1);
block_size = _txm_power_of_two_block_size(data_size) >> 1;
/* Calculate the region size information. */
region_size = _txm_module_manager_region_size_get(block_size);
/* Build the attribute-size register with permissions, SRD, size, enable. */
module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_DATA_ACCESS_CONTROL | srd_bits | (region_size << 1) | TXM_ENABLE_REGION;
/* Adjust the data address. */
data_address = data_address + block_size;
}
/* Last MPU block is the smallest power of 2 that exceeds the remaining space, minimum 32. */
else
{
/* Calculate remaining space. */
data_size = data_size - block_size;
block_size = _txm_power_of_two_block_size(data_size);
srd_bits = _txm_module_manager_calculate_srd_bits(block_size, data_size);
module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = 0;
}
/* Calculate the region size information. */
region_size = (_txm_module_manager_region_size_get(block_size) << 1);
/* Build the base address register with address, MPU region, set Valid bit. */
module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = (data_address & ~(block_size - 1)) | mpu_table_index | 0x10;
/* Build the attribute-size register with permissions, SRD, size, enable. */
module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_DATA_ACCESS_CONTROL | srd_bits | region_size | TXM_ENABLE_REGION;
/* Adjust the data address. */
data_address = data_address + block_size;
/* Increment MPU table index. */
mpu_table_index++;
}
/* End of data protection. */
/* Setup MPU for the shared regions. */
while (mpu_table_index < TXM_MODULE_MANAGER_MPU_USER_REGION_INDEX)
{
/* Build the base address register with address, MPU region, set Valid bit. */
module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = mpu_table_index | TXM_MPU_VALID_BIT;
/* Increment MPU table index. */
mpu_table_index++;
}
@@ -515,39 +540,30 @@ ULONG data_size;
ULONG start_stop_stack_size;
ULONG callback_stack_size;
ULONG block_size;
ULONG base_address_register;
ULONG base_attribute_register;
ULONG region_size;
ULONG srd_bits = 0;
UINT mpu_register = 0;
UINT mpu_table_index;
UINT mpu_table_index = 1;
UINT i;
/* Setup the first region for the ThreadX trampoline code. */
/* Set base register to user mode entry, which is guaranteed to be at least 32-byte aligned. */
base_address_register = (ULONG) _txm_module_manager_user_mode_entry;
/* Mask address to proper range, region 0, set Valid bit. */
base_address_register = (base_address_register & 0xFFFFFFE0) | mpu_register | 0x10;
module_instance -> txm_module_instance_mpu_registers[0] = base_address_register;
/* Attributes: read only, write-back, shareable, size 32 bytes, region enabled. */
module_instance -> txm_module_instance_mpu_registers[1] = 0x06070009;
/* Setup the first MPU region for kernel mode entry. */
/* Set address register to user mode entry function address, which is guaranteed to be at least 32-byte aligned.
Mask address to proper range, region 0, set Valid bit. */
module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_MPU_KERNEL_ENTRY_INDEX].txm_module_mpu_region_address = ((ULONG) _txm_module_manager_user_mode_entry & 0xFFFFFFE0) | TXM_MPU_VALID_BIT;
/* Set the attributes, region size (32 bytes), and enable bit. */
module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_MPU_KERNEL_ENTRY_INDEX].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_CODE_ACCESS_CONTROL | 0x08 | TXM_ENABLE_REGION;
/* End of kernel mode entry setup. */
/* Initialize the MPU register. */
mpu_register = 1;
/* Setup code protection. */
/* Initialize the MPU table index. */
mpu_table_index = 2;
/* Setup values for code area. */
/* Pickup code starting address and actual size. */
code_address = (ULONG) module_instance -> txm_module_instance_code_start;
code_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_code_size;
/* Check if shared memory was set up. If so, only 3 entries are available for
code protection. If not set up, 4 code entries are available. */
if(module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_INDEX] == 0)
if(module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_REGION].txm_module_mpu_region_address == 0)
{
/* Determine code block sizes. Minimize the alignment requirement.
There are 4 MPU code entries available. The following is how the code size
@@ -556,99 +572,120 @@ UINT i;
2. 1/4 of the largest power of two that is greater than or equal to code size.
3. Largest power of 2 that fits in the remaining space.
4. Smallest power of 2 that exceeds the remaining space, minimum 32. */
/* Now loop through to setup MPU protection for the code area. */
for (i = 0; i < TXM_MODULE_MANAGER_CODE_MPU_ENTRIES; i++)
{
/* First two MPU blocks are 1/4 of the largest power of two
that is greater than or equal to code size. */
if (i < 2)
switch(i)
{
block_size = _txm_power_of_two_block_size(code_size) >> 2;
/* First two MPU blocks are 1/4 of the largest power of two
that is greater than or equal to code size. */
case 0:
{
block_size = _txm_power_of_two_block_size(code_size) >> 2;
break;
}
case 2:
{
/* Third MPU block is the largest power of 2 that fits within the remaining space. */
/* Subtract (block_size*2) from code_size to calculate remaining space. */
code_size = code_size - (block_size << 1);
block_size = _txm_power_of_two_block_size(code_size);
/* Minimum block size is 32. */
if(block_size > 32)
{
/* POW2 function result is divided by two to fit in the remaining space. */
block_size = block_size >> 1;
}
break;
}
case 3:
{
/* Last MPU block is the smallest power of 2 that exceeds the remaining space, minimum 32. */
/* Calculate remaining space. */
if(code_size - block_size > code_size)
{
/* Case 2 covered the remaining code size. This region will not be used. */
block_size = 0;
}
else
{
code_size = code_size - block_size;
block_size = _txm_power_of_two_block_size(code_size);
srd_bits = _txm_module_manager_calculate_srd_bits(block_size, code_size);
}
break;
}
default:
{
/* Case 1 is the same as 0 - the block size was already calculated. */
break;
}
}
/* Third MPU block is the largest power of 2 that fits in the remaining space. */
else if (i == 2)
/* Build the base address register with address, MPU region, set Valid bit. */
module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = (code_address & ~(block_size - 1)) | mpu_table_index | TXM_MPU_VALID_BIT;
/* Only configure attribute register if the block is valid. */
if(block_size)
{
/* Subtract (block_size*2) from code_size to calculate remaining space. */
code_size = code_size - (block_size << 1);
block_size = _txm_power_of_two_block_size(code_size) >> 1;
/* Calculate the region size information. */
region_size = _txm_module_manager_region_size_get(block_size);
/* Build the attribute-size register with permissions, SRD, size, enable. */
module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_CODE_ACCESS_CONTROL | srd_bits | (region_size << 1) | TXM_ENABLE_REGION;
/* Adjust the code address. */
code_address = code_address + block_size;
}
/* Last MPU block is the smallest power of 2 that exceeds the remaining space, minimum 32. */
else
{
/* Calculate remaining space. */
code_size = code_size - block_size;
block_size = _txm_power_of_two_block_size(code_size);
srd_bits = _txm_module_manager_calculate_srd_bits(block_size, code_size);
module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = 0;
}
/* Build the base address register. */
base_address_register = (code_address & ~(block_size - 1)) | mpu_register | 0x10;
/* Calculate the region size information. */
region_size = (_txm_module_manager_region_size_get(block_size) << 1);
/* Build the base attribute register. */
base_attribute_register = region_size | srd_bits | 0x06070001;
/* Setup the MPU Base Address Register. */
module_instance -> txm_module_instance_mpu_registers[mpu_table_index] = base_address_register;
/* Setup the MPU Base Attribute Register. */
module_instance -> txm_module_instance_mpu_registers[mpu_table_index+1] = base_attribute_register;
/* Adjust the code address. */
code_address = code_address + block_size;
/* Move MPU table index. */
mpu_table_index = mpu_table_index + 2;
/* Increment the MPU register index. */
mpu_register++;
/* Increment MPU table index. */
mpu_table_index++;
}
}
/* Only 3 code entries available. */
else
{
/* Calculate block size, one code entry taken up by shared memory. */
block_size = _txm_power_of_two_block_size(code_size / (TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1));
/* Calculate the region size information. */
region_size = (_txm_module_manager_region_size_get(block_size) << 1);
/* Calculate the region size and pre-shift it so we don't need to shift it multiple times in the for loop. */
region_size = _txm_module_manager_region_size_get(block_size) << 1;
/* Now loop through to setup MPU protection for the code area. */
for (i = 0; i < TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1; i++)
{
/* Build the base address register. */
base_address_register = (code_address & ~(block_size - 1)) | mpu_register | 0x10;
/* Build the base address register with address, MPU region, set Valid bit. */
module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = (code_address & ~(block_size - 1)) | mpu_table_index | TXM_MPU_VALID_BIT;
/* Check if SRD bits need to be set. */
if (code_size < block_size)
{
srd_bits = _txm_module_manager_calculate_srd_bits(block_size, code_size);
}
/* Build the base attribute register. */
base_attribute_register = region_size | srd_bits | 0x06070000;
base_attribute_register = region_size | srd_bits | TXM_MODULE_MPU_CODE_ACCESS_CONTROL;
/* Is there still some code? If so set the region enable bit. */
if (code_size)
{
/* Set the region enable bit. */
base_attribute_register = base_attribute_register | 0x1;
base_attribute_register |= TXM_ENABLE_REGION;
}
/* Setup the MPU Base Address Register. */
module_instance -> txm_module_instance_mpu_registers[mpu_table_index] = base_address_register;
/* Setup the MPU Base Attribute Register. */
module_instance -> txm_module_instance_mpu_registers[mpu_table_index+1] = base_attribute_register;
module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = base_attribute_register;
/* Adjust the code address. */
code_address = code_address + block_size;
/* Decrement the code size. */
if (code_size > block_size)
{
@@ -658,34 +695,27 @@ UINT i;
{
code_size = 0;
}
/* Move MPU table index. */
mpu_table_index = mpu_table_index + 2;
/* Increment the MPU register index. */
mpu_register++;
/* Increment MPU table index. */
mpu_table_index++;
}
/* Adjust indeces to pass over the shared memory entry. */
/* Move MPU table index. */
mpu_table_index = mpu_table_index + 2;
/* Increment the MPU register index. */
mpu_register++;
/* Data protection is already set up so we can simply return here. */
return;
}
/* Setup values for data area. */
data_address = (ULONG) module_instance -> txm_module_instance_data_start;
/* Adjust the size of the module elements to be aligned to the default alignment. We do this
so that when we partition the allocated memory, we can simply place these regions right beside
each other without having to align their pointers. Note this only works when they all have
the same alignment. */
data_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_data_size;
start_stop_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_start_stop_stack_size;
callback_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_callback_stack_size;
data_size = ((data_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT;
start_stop_stack_size = ((start_stop_stack_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT;
@@ -694,46 +724,43 @@ UINT i;
/* Update the data size to include thread stacks. */
data_size = data_size + start_stop_stack_size + callback_stack_size;
block_size = _txm_power_of_two_block_size(data_size / TXM_MODULE_MANAGER_DATA_MPU_ENTRIES);
/* Reset SRD bitfield. */
srd_bits = 0;
/* Calculate the region size information. */
region_size = (_txm_module_manager_region_size_get(block_size) << 1);
/* Calculate the region size and pre-shift it so we don't need to shift it multiple times in the for loop. */
region_size = _txm_module_manager_region_size_get(block_size) << 1;
/* Now loop through to setup MPU protection for the data area. */
for (i = 0; i < TXM_MODULE_MANAGER_DATA_MPU_ENTRIES; i++)
{
/* Build the base address register. */
base_address_register = (data_address & ~(block_size - 1)) | mpu_register | 0x10;
/* Build the base address register with address, MPU region, set Valid bit. */
module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = (data_address & ~(block_size - 1)) | mpu_table_index | TXM_MPU_VALID_BIT;
/* Check if SRD bits need to be set. */
if (data_size < block_size)
{
srd_bits = _txm_module_manager_calculate_srd_bits(block_size, data_size);
}
/* Build the base attribute register. */
base_attribute_register = region_size | srd_bits | 0x13070000;
/* Build the attribute-size register with permissions, SRD, size. */
base_attribute_register = region_size | srd_bits | TXM_MODULE_MPU_DATA_ACCESS_CONTROL;
/* Is there still some data? If so set the region enable bit. */
if (data_size)
{
/* Set the region enable bit. */
base_attribute_register = base_attribute_register | 0x1;
base_attribute_register |= TXM_ENABLE_REGION;
}
/* Setup the MPU Base Address Register. */
module_instance -> txm_module_instance_mpu_registers[mpu_table_index] = base_address_register;
/* Setup the MPU Base Attribute Register. */
module_instance -> txm_module_instance_mpu_registers[mpu_table_index+1] = base_attribute_register;
module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = base_attribute_register;
/* Adjust the data address. */
data_address = data_address + block_size;
/* Decrement the data size. */
if (data_size > block_size)
{
@@ -743,12 +770,9 @@ UINT i;
{
data_size = 0;
}
/* Move MPU table index. */
mpu_table_index = mpu_table_index + 2;
/* Increment the MPU register index. */
mpu_register++;
/* Increment MPU table index. */
mpu_table_index++;
}
#endif
@@ -808,7 +832,7 @@ ALIGN_TYPE shared_memory_address_end;
{
return(TX_FALSE);
}
/* Check if the object is inside the module data. */
if ((obj_ptr >= (ALIGN_TYPE) module_instance -> txm_module_instance_data_start) &&
((obj_ptr + obj_size) <= ((ALIGN_TYPE) module_instance -> txm_module_instance_data_end + 1)))