updated to 6.0.1 and added additional processors/toolchains
This commit is contained in:
tameraw
360
ports/arc_em/metaware/src/tx_initialize_low_level.s
Normal file
360
ports/arc_em/metaware/src/tx_initialize_low_level.s
Normal file
@@ -0,0 +1,360 @@
|
||||
;/**************************************************************************/
|
||||
;/* */
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||||
;/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
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;/* */
|
||||
;/* This software is licensed under the Microsoft Software License */
|
||||
;/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
;/* and in the root directory of this software. */
|
||||
;/* */
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||||
;/**************************************************************************/
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||||
;
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||||
;
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||||
;/**************************************************************************/
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;/**************************************************************************/
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||||
;/** */
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;/** ThreadX Component */
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;/** */
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;/** Initialize */
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;/** */
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;/**************************************************************************/
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;/**************************************************************************/
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;
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.equ IRQ_SELECT, 0x40B
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.equ KSTACK_TOP, 0x264
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.equ KSTACK_BASE, 0x265
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.equ STATUS32_SC, 0x4000
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;
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;
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; /* Define section for placement after all linker allocated RAM memory. This
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; is used to calculate the first free address that is passed to
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; tx_appication_define, soley for the ThreadX application's use. */
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;
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.section ".free_memory","aw"
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.align 4
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.global _tx_first_free_address
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_tx_first_free_address:
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.space 4
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;
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; /* Define section for placement before the main stack area for setting
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; up the STACK_TOP address for hardware stack checking. */
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;
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.section ".stack_top","aw"
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.align 4
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.global _tx_system_stack_top_address
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_tx_system_stack_top_address:
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.space 4
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;
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; /* Define section for placement after the main stack area for setting
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; up the STACK_BASE address for hardware stack checking. */
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;
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.section ".stack_base","aw"
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.align 4
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.global _tx_system_stack_base_address
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_tx_system_stack_base_address:
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.space 4
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;
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;
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.text
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;/**************************************************************************/
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;/* */
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;/* FUNCTION RELEASE */
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;/* */
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;/* _tx_initialize_low_level ARCv2_EM/MetaWare */
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;/* 6.0.1 */
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;/* AUTHOR */
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;/* */
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;/* William E. Lamie, Microsoft Corporation */
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;/* */
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;/* DESCRIPTION */
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;/* */
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;/* This function is responsible for any low-level processor */
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;/* initialization, including setting up interrupt vectors, setting */
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;/* up a periodic timer interrupt source, saving the system stack */
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;/* pointer for use in ISR processing later, and finding the first */
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;/* available RAM memory address for tx_application_define. */
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;/* */
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;/* INPUT */
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;/* */
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;/* None */
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;/* */
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||||
;/* OUTPUT */
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;/* */
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||||
;/* None */
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||||
;/* */
|
||||
;/* CALLS */
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||||
;/* */
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||||
;/* None */
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||||
;/* */
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;/* CALLED BY */
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;/* */
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;/* _tx_initialize_kernel_enter ThreadX entry function */
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;/* */
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;/* RELEASE HISTORY */
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;/* */
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;/* DATE NAME DESCRIPTION */
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;/* */
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;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
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;/* */
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;/**************************************************************************/
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;VOID _tx_initialize_low_level(VOID)
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;{
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.global _tx_initialize_low_level
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.type _tx_initialize_low_level, @function
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_tx_initialize_low_level:
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.ifdef TX_ENABLE_HW_STACK_CHECKING
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mov r0, _tx_system_stack_top_address ; Pickup top of system stack (lowest memory address)
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sr r0, [KSTACK_TOP] ; Setup KSTACK_TOP
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mov r0, _tx_system_stack_base_address ; Pickup base of system stack (highest memory address)
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sr r0, [KSTACK_BASE] ; Setup KSTACK_BASE
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lr r0, [status32] ; Pickup current STATUS32
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or r0, r0, STATUS32_SC ; Or in hardware stack checking enable bit (SC)
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kflag r0 ; Enable hardware stack checking
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.endif
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;
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; /* Save the system stack pointer. */
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; _tx_thread_system_stack_ptr = (VOID_PTR) (sp);
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;
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st sp, [gp, _tx_thread_system_stack_ptr@sda] ; Save system stack pointer
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;
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;
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; /* Pickup the first available memory address. */
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;
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mov r0, _tx_first_free_address ; Pickup first free memory address
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;
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; /* Save the first available memory address. */
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; _tx_initialize_unused_memory = (VOID_PTR) _end;
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;
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st r0, [gp, _tx_initialize_unused_memory@sda]
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;
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;
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; /* Setup Timer 0 for periodic interrupts at interrupt vector 16. */
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;
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mov r0, 0 ; Disable additional ISR reg saving/restoring
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sr r0, [AUX_IRQ_CTRL] ;
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mov r0, 16 ; Select timer 0
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sr r0, [IRQ_SELECT] ;
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mov r0, 15 ; Set timer 0 to priority 15
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sr r0, [IRQ_PRIORITY] ;
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mov r0, 1 ; Enable this interrupt
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sr r0, [IRQ_ENABLE] ;
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mov r0, 0x10000 ; Setup timer period
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sr r0, [LIMIT0] ;
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mov r0, 0 ; Clear timer 0 current count
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sr r0, [COUNT0] ;
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mov r0, 3 ; Enable timer 0
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sr r0, [CONTROL0] ;
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.ifdef TX_TIMER_1_SETUP
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mov r0, 17 ; Select timer 1
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sr r0, [IRQ_SELECT] ;
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mov r0, 2 ; Set timer 1 to priority 14
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sr r0, [IRQ_PRIORITY] ;
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mov r0, 1 ; Enable this interrupt
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sr r0, [IRQ_ENABLE] ;
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mov r0, 0x10020 ; Setup timer period
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sr r0, [LIMIT1] ;
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mov r0, 0 ; Clear timer 0 current count
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sr r0, [COUNT1] ;
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mov r0, 3 ; Enable timer 0
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sr r0, [CONTROL1] ;
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.endif
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;
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; /* Done, return to caller. */
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;
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j_s.d [blink] ; Return to caller
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nop
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;}
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;
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;
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; /* Define default vector table entries. */
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;
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.global _tx_memory_error
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_tx_memory_error:
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flag 1
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nop
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nop
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nop
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b _tx_memory_error
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.global _tx_instruction_error
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_tx_instruction_error:
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flag 1
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nop
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nop
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nop
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b _tx_instruction_error
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.global _tx_ev_machine_check
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_tx_ev_machine_check:
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flag 1
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nop
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nop
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nop
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b _tx_ev_machine_check
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.global _tx_ev_tblmiss_inst
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_tx_ev_tblmiss_inst:
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flag 1
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nop
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nop
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nop
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b _tx_ev_tblmiss_inst
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.global _tx_ev_tblmiss_data
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_tx_ev_tblmiss_data:
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flag 1
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nop
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nop
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nop
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b _tx_ev_tblmiss_data
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.global _tx_ev_protection_viol
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_tx_ev_protection_viol:
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flag 1
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nop
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nop
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nop
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b _tx_ev_protection_viol
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.global _tx_ev_privilege_viol
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_tx_ev_privilege_viol:
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flag 1
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nop
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nop
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nop
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b _tx_ev_privilege_viol
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.global _tx_ev_software_int
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_tx_ev_software_int:
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flag 1
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nop
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nop
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nop
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b _tx_ev_software_int
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.global _tx_ev_trap
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_tx_ev_trap:
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flag 1
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nop
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nop
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nop
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b _tx_ev_trap
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.global _tx_ev_extension
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_tx_ev_extension:
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flag 1
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nop
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nop
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nop
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b _tx_ev_extension
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.global _tx_ev_divide_by_zero
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_tx_ev_divide_by_zero:
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flag 1
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nop
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nop
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nop
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b _tx_ev_divide_by_zero
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.global _tx_ev_dc_error
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_tx_ev_dc_error:
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flag 1
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nop
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nop
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nop
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b _tx_ev_dc_error
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.global _tx_ev_maligned
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_tx_ev_maligned:
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flag 1
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nop
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nop
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nop
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b _tx_ev_maligned
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.global _tx_unsued_0
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_tx_unsued_0:
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flag 1
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nop
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nop
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nop
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b _tx_unsued_0
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.global _tx_unused_1
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_tx_unused_1:
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flag 1
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nop
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nop
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nop
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b _tx_unused_1
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.global _tx_timer_0
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_tx_timer_0:
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;
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; /* By default, setup Timer 0 as the ThreadX timer interrupt. */
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;
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sub sp, sp, 160 ; Allocate an interrupt stack frame
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st r0, [sp, 0] ; Save r0
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st r1, [sp, 4] ; Save r1
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st r2, [sp, 8] ; Save r2
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mov r0, 3
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sr r0, [CONTROL0]
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b _tx_timer_interrupt ; Jump to generic ThreadX timer interrupt
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; handler
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; flag 1
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; nop
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||||
; nop
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||||
; nop
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||||
; b _tx_timer_0
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.global _tx_timer_1
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_tx_timer_1:
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sub sp, sp, 160 ; Allocate an interrupt stack frame
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st blink, [sp, 16] ; Save blink
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bl _tx_thread_context_save ; Call context save
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;
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||||
; /* ISR processing goes here. If the applications wishes to re-enable
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; interrupts, the SETI instruction can be used here. Also note that
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; register usage in assembly code must be confined to the compiler
|
||||
; scratch registers. */
|
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;
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mov r0, 3
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sr r0, [CONTROL1]
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;
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b _tx_thread_context_restore ; Call context restore
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||||
|
||||
; flag 1
|
||||
; nop
|
||||
; nop
|
||||
; nop
|
||||
; b _tx_timer_1
|
||||
|
||||
.global _tx_undefined_0
|
||||
_tx_undefined_0:
|
||||
flag 1
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
b _tx_undefined_0
|
||||
|
||||
.global _tx_undefined_1
|
||||
_tx_undefined_1:
|
||||
flag 1
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
b _tx_undefined_1
|
||||
|
||||
.global _tx_undefined_2
|
||||
_tx_undefined_2:
|
||||
flag 1
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
b _tx_undefined_2
|
||||
|
||||
.end
|
||||
302
ports/arc_em/metaware/src/tx_thread_context_restore.s
Normal file
302
ports/arc_em/metaware/src/tx_thread_context_restore.s
Normal file
@@ -0,0 +1,302 @@
|
||||
;/**************************************************************************/
|
||||
;/* */
|
||||
;/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
;/* */
|
||||
;/* This software is licensed under the Microsoft Software License */
|
||||
;/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
;/* and in the root directory of this software. */
|
||||
;/* */
|
||||
;/**************************************************************************/
|
||||
;
|
||||
;
|
||||
;/**************************************************************************/
|
||||
;/**************************************************************************/
|
||||
;/** */
|
||||
;/** ThreadX Component */
|
||||
;/** */
|
||||
;/** Thread */
|
||||
;/** */
|
||||
;/**************************************************************************/
|
||||
;/**************************************************************************/
|
||||
;
|
||||
;
|
||||
;#define TX_SOURCE_CODE
|
||||
;
|
||||
.equ BTA, 0x412
|
||||
.equ KSTACK_TOP, 0x264
|
||||
.equ KSTACK_BASE, 0x265
|
||||
.equ STATUS32_SC, 0x4000
|
||||
;
|
||||
;/* Include necessary system files. */
|
||||
;
|
||||
;#include "tx_api.h"
|
||||
;#include "tx_thread.h"
|
||||
;#include "tx_timer.h"
|
||||
;
|
||||
;
|
||||
;/**************************************************************************/
|
||||
;/* */
|
||||
;/* FUNCTION RELEASE */
|
||||
;/* */
|
||||
;/* _tx_thread_context_restore ARCv2_EM/MetaWare */
|
||||
;/* 6.0.1 */
|
||||
;/* AUTHOR */
|
||||
;/* */
|
||||
;/* William E. Lamie, Microsoft Corporation */
|
||||
;/* */
|
||||
;/* DESCRIPTION */
|
||||
;/* */
|
||||
;/* This function restores the interrupt context if it is processing a */
|
||||
;/* nested interrupt. If not, it returns to the interrupt thread if no */
|
||||
;/* preemption is necessary. Otherwise, if preemption is necessary or */
|
||||
;/* if no thread was running, the function returns to the scheduler. */
|
||||
;/* */
|
||||
;/* INPUT */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* OUTPUT */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* CALLS */
|
||||
;/* */
|
||||
;/* _tx_thread_schedule Thread scheduling routine */
|
||||
;/* */
|
||||
;/* CALLED BY */
|
||||
;/* */
|
||||
;/* ISRs Interrupt Service Routines */
|
||||
;/* */
|
||||
;/* RELEASE HISTORY */
|
||||
;/* */
|
||||
;/* DATE NAME DESCRIPTION */
|
||||
;/* */
|
||||
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
|
||||
;/* */
|
||||
;/**************************************************************************/
|
||||
;VOID _tx_thread_context_restore(VOID)
|
||||
;{
|
||||
.global _tx_thread_context_restore
|
||||
.type _tx_thread_context_restore, @function
|
||||
_tx_thread_context_restore:
|
||||
;
|
||||
; /* Note: it is assumed that the stack pointer is in the same position now as
|
||||
; it was after the last context save call. */
|
||||
;
|
||||
; /* Lockout interrupts. */
|
||||
;
|
||||
clri ; Disable interrupts
|
||||
nop ; Delay for interrupts to really be disabled
|
||||
|
||||
.ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
|
||||
;
|
||||
; /* Call the ISR exit function to indicate an ISR is complete. */
|
||||
;
|
||||
bl.d _tx_execution_isr_exit ; Call the ISR exit function
|
||||
sub sp, sp, 16 ; ..allocating some space on the stack
|
||||
add sp, sp, 16 ; Recover the stack space
|
||||
.endif
|
||||
;
|
||||
; /* Determine if interrupts are nested. */
|
||||
; if (--_tx_thread_system_state)
|
||||
; {
|
||||
;
|
||||
ld r0, [gp, _tx_thread_system_state@sda] ; Pickup system state contents
|
||||
sub r0, r0, 1 ; Decrement the system state
|
||||
st r0, [gp, _tx_thread_system_state@sda] ; Store the new system state
|
||||
breq r0, 0, __tx_thread_not_nested_restore ; If zero, not a nested interrupt
|
||||
;
|
||||
; /* Interrupts are nested. */
|
||||
;
|
||||
; /* Just recover the saved registers and return to the point of
|
||||
; interrupt. */
|
||||
;
|
||||
|
||||
__tx_thread_nested_restore:
|
||||
|
||||
ld r0, [sp, 4] ; Recover LP_START
|
||||
sr r0, [LP_START] ; Restore LP_START
|
||||
ld r1, [sp, 8] ; Recover LP_END
|
||||
sr r1, [LP_END] ; Restore LP_END
|
||||
ld r2, [sp, 12] ; Recover LP_COUNT
|
||||
mov LP_COUNT, r2
|
||||
ld r2, [sp, 156] ; Pickup BTA
|
||||
sr r2, [BTA] ; Recover BTA
|
||||
.ifdef TX_ENABLE_ACC
|
||||
ld r58, [sp, 140] ; Recover r58
|
||||
ld r59, [sp, 144] ; Recover r59
|
||||
.endif
|
||||
ld blink, [sp, 16] ; Recover blink
|
||||
ld r12, [sp, 84] ; Recover r12
|
||||
ld r11, [sp, 88] ; Recover r11
|
||||
ld r10, [sp, 92] ; Recover r10
|
||||
ld r9, [sp, 96] ; Recover r9
|
||||
ld r8, [sp, 100] ; Recover r8
|
||||
ld r7, [sp, 104] ; Recover r7
|
||||
ld r6, [sp, 108] ; Recover r6
|
||||
ld r5, [sp, 112] ; Recover r5
|
||||
ld r4, [sp, 116] ; Recover r4
|
||||
ld r3, [sp, 120] ; Recover r3
|
||||
ld r2, [sp, 124] ; Recover r2
|
||||
ld r1, [sp, 128] ; Recover r1
|
||||
ld r0, [sp, 132] ; Recover r0
|
||||
add sp, sp, 160 ; Recover interrupt stack frame
|
||||
rtie ; Return from interrupt
|
||||
;
|
||||
;
|
||||
; }
|
||||
__tx_thread_not_nested_restore:
|
||||
;
|
||||
; /* Determine if a thread was interrupted and no preemption is required. */
|
||||
; else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr)
|
||||
; || (_tx_thread_preempt_disable))
|
||||
; {
|
||||
;
|
||||
ld r0, [gp, _tx_thread_current_ptr@sda] ; Pickup current thread pointer
|
||||
ld r2, [gp, _tx_thread_preempt_disable@sda] ; Pickup preempt disable flag
|
||||
sub.f 0, r0, 0 ; Set condition codes
|
||||
beq.d __tx_thread_idle_system_restore ; If NULL, idle system was interrupted
|
||||
lr r4, [AUX_IRQ_ACT] ; Pickup the interrupt active register
|
||||
neg r5, r4 ; Negate
|
||||
and r5, r4, r5 ; See if there are any other interrupts present
|
||||
brne.d r4, r5, __tx_thread_no_preempt_restore ; If more interrupts, just return to the point of interrupt
|
||||
ld r4, [gp, _tx_thread_execute_ptr@sda] ; Pickup next thread to execute
|
||||
brne r2, 0, __tx_thread_no_preempt_restore ; If set, don't preempt executing thread
|
||||
brne r0, r4, __tx_thread_preempt_restore ; Not equal, preempt executing thread
|
||||
;
|
||||
;
|
||||
__tx_thread_no_preempt_restore:
|
||||
;
|
||||
; /* Restore interrupted thread or ISR. */
|
||||
;
|
||||
; /* Pickup the saved stack pointer. */
|
||||
; sp = _tx_thread_current_ptr -> tx_thread_stack_ptr;
|
||||
;
|
||||
|
||||
; /* Recover the saved context and return to the point of interrupt. */
|
||||
;
|
||||
|
||||
.ifdef TX_ENABLE_HW_STACK_CHECKING
|
||||
lr r2, [status32] ; Pickup current STATUS32
|
||||
and r2, r2, ~STATUS32_SC ; Clear the hardware stack checking enable bit (SC)
|
||||
kflag r2 ; Disable hardware stack checking
|
||||
ld r3, [r0, 12] ; Pickup the top of the thread's stack (lowest address)
|
||||
sr r3, [KSTACK_TOP] ; Setup KSTACK_TOP
|
||||
ld r3, [r0, 16] ; Pickup the base of the thread's stack (highest address)
|
||||
sr r3, [KSTACK_BASE] ; Setup KSTACK_BASE
|
||||
.endif
|
||||
|
||||
ld sp, [r0, 8] ; Switch back to thread's stack
|
||||
|
||||
.ifdef TX_ENABLE_HW_STACK_CHECKING
|
||||
or r2, r2, STATUS32_SC ; Or in hardware stack checking enable bit (SC)
|
||||
kflag r2 ; Enable hardware stack checking
|
||||
.endif
|
||||
|
||||
ld r0, [sp, 4] ; Recover LP_START
|
||||
sr r0, [LP_START] ; Restore LP_START
|
||||
ld r1, [sp, 8] ; Recover LP_END
|
||||
sr r1, [LP_END] ; Restore LP_END
|
||||
ld r2, [sp, 12] ; Recover LP_COUNT
|
||||
mov LP_COUNT, r2
|
||||
ld r2, [sp, 156] ; Pickup BTA
|
||||
sr r2, [BTA] ; Recover BTA
|
||||
.ifdef TX_ENABLE_ACC
|
||||
ld r58, [sp, 140] ; Recover r58
|
||||
ld r59, [sp, 144] ; Recover r59
|
||||
.endif
|
||||
ld blink, [sp, 16] ; Recover blink
|
||||
ld r12, [sp, 84] ; Recover r12
|
||||
ld r11, [sp, 88] ; Recover r11
|
||||
ld r10, [sp, 92] ; Recover r10
|
||||
ld r9, [sp, 96] ; Recover r9
|
||||
ld r8, [sp, 100] ; Recover r8
|
||||
ld r7, [sp, 104] ; Recover r7
|
||||
ld r6, [sp, 108] ; Recover r6
|
||||
ld r5, [sp, 112] ; Recover r5
|
||||
ld r4, [sp, 116] ; Recover r4
|
||||
ld r3, [sp, 120] ; Recover r3
|
||||
ld r2, [sp, 124] ; Recover r2
|
||||
ld r1, [sp, 128] ; Recover r1
|
||||
ld r0, [sp, 132] ; Recover r0
|
||||
add sp, sp, 160 ; Recover interrupt stack frame
|
||||
rtie ; Return from interrupt
|
||||
;
|
||||
; }
|
||||
; else
|
||||
; {
|
||||
__tx_thread_preempt_restore:
|
||||
;
|
||||
ld r7, [r0, 8] ; Pickup stack pointer
|
||||
mov r6, 1 ; Build interrupt stack type
|
||||
st r6, [r7, 0] ; Setup interrupt stack type
|
||||
st fp, [r7, 24] ; Save fp
|
||||
st gp, [r7, 28] ; Save gp
|
||||
st r25, [r7, 32] ; Save r25
|
||||
st r24, [r7, 36] ; Save r24
|
||||
st r23, [r7, 40] ; Save r23
|
||||
st r22, [r7, 44] ; Save r22
|
||||
st r21, [r7, 48] ; Save r21
|
||||
st r20, [r7, 52] ; Save r20
|
||||
st r19, [r7, 56] ; Save r19
|
||||
st r18, [r7, 60] ; Save r18
|
||||
st r17, [r7, 64] ; Save r17
|
||||
st r16, [r7, 68] ; Save r16
|
||||
st r15, [r7, 72] ; Save r15
|
||||
st r14, [r7, 76] ; Save r14
|
||||
st r13, [r7, 80] ; Save r13
|
||||
st r30, [r7, 136] ; Save r30
|
||||
;
|
||||
; /* Save the remaining time-slice and disable it. */
|
||||
; if (_tx_timer_time_slice)
|
||||
; {
|
||||
;
|
||||
ld r2, [gp, _tx_timer_time_slice@sda] ; Pickup time-slice contents
|
||||
mov r7, 0 ; Build clear/NULL value
|
||||
breq r2, 0, __tx_thread_dont_save_ts ; No time-slice, don't need to save it
|
||||
;
|
||||
; _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice;
|
||||
; _tx_timer_time_slice = 0;
|
||||
;
|
||||
st r2, [r0, 24] ; If set, save remaining time-slice
|
||||
st r7, [gp, _tx_timer_time_slice@sda] ; If set, clear time slice
|
||||
;
|
||||
; }
|
||||
__tx_thread_dont_save_ts:
|
||||
;
|
||||
;
|
||||
; /* Clear the current thread pointer. */
|
||||
; _tx_thread_current_ptr = TX_NULL;
|
||||
;
|
||||
st r7, [gp, _tx_thread_current_ptr@sda] ; Set current thread ptr to NULL
|
||||
|
||||
sub sp, sp, 8 ; Allocate a small stack frame on the system stack
|
||||
lr r0, [STATUS32] ; Pickup STATUS32
|
||||
st r0, [sp, 4] ; Place on stack
|
||||
mov r0, _tx_thread_schedule ; Build address of scheduler
|
||||
st r0, [sp, 0] ; Write over the point of interrupt
|
||||
rtie ; Return from interrupt to scheduler
|
||||
;
|
||||
; }
|
||||
;
|
||||
; /* Return to the scheduler. */
|
||||
; _tx_thread_schedule();
|
||||
;
|
||||
__tx_thread_idle_system_restore:
|
||||
|
||||
lr r4, [AUX_IRQ_ACT] ; Pickup the interrupt active register
|
||||
neg r5, r4 ; Negate
|
||||
and r5, r4, r5 ; See if there are any other interrupts present
|
||||
sub.f 0, r4, r5 ; Set condition codes
|
||||
bne __tx_thread_nested_restore ; If more interrupts, just return to the point of interrupt
|
||||
|
||||
lr r0, [STATUS32] ; Pickup STATUS32
|
||||
st r0, [sp, 4] ; Place on stack
|
||||
mov r0, _tx_thread_schedule ; Build address of scheduler
|
||||
st r0, [sp, 0] ; Write over the point of interrupt
|
||||
rtie ; Return from interrupt to scheduler
|
||||
;
|
||||
;}
|
||||
.end
|
||||
|
||||
260
ports/arc_em/metaware/src/tx_thread_context_save.s
Normal file
260
ports/arc_em/metaware/src/tx_thread_context_save.s
Normal file
@@ -0,0 +1,260 @@
|
||||
;/**************************************************************************/
|
||||
;/* */
|
||||
;/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
;/* */
|
||||
;/* This software is licensed under the Microsoft Software License */
|
||||
;/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
;/* and in the root directory of this software. */
|
||||
;/* */
|
||||
;/**************************************************************************/
|
||||
;
|
||||
;
|
||||
;/**************************************************************************/
|
||||
;/**************************************************************************/
|
||||
;/** */
|
||||
;/** ThreadX Component */
|
||||
;/** */
|
||||
;/** Thread */
|
||||
;/** */
|
||||
;/**************************************************************************/
|
||||
;/**************************************************************************/
|
||||
;
|
||||
;
|
||||
;#define TX_SOURCE_CODE
|
||||
;
|
||||
.equ BTA, 0x412
|
||||
.equ KSTACK_TOP, 0x264
|
||||
.equ KSTACK_BASE, 0x265
|
||||
.equ STATUS32_SC, 0x4000
|
||||
;
|
||||
;/* Include necessary system files. */
|
||||
;
|
||||
;#include "tx_api.h"
|
||||
;#include "tx_thread.h"
|
||||
;#include "tx_timer.h"
|
||||
;
|
||||
;
|
||||
;/**************************************************************************/
|
||||
;/* */
|
||||
;/* FUNCTION RELEASE */
|
||||
;/* */
|
||||
;/* _tx_thread_context_save ARCv2_EM/MetaWare */
|
||||
;/* 6.0.1 */
|
||||
;/* AUTHOR */
|
||||
;/* */
|
||||
;/* William E. Lamie, Microsoft Corporation */
|
||||
;/* */
|
||||
;/* DESCRIPTION */
|
||||
;/* */
|
||||
;/* This function saves the context of an executing thread in the */
|
||||
;/* beginning of interrupt processing. The function also ensures that */
|
||||
;/* the system stack is used upon return to the calling ISR. */
|
||||
;/* */
|
||||
;/* INPUT */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* OUTPUT */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* CALLS */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* CALLED BY */
|
||||
;/* */
|
||||
;/* ISRs */
|
||||
;/* */
|
||||
;/* RELEASE HISTORY */
|
||||
;/* */
|
||||
;/* DATE NAME DESCRIPTION */
|
||||
;/* */
|
||||
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
|
||||
;/* */
|
||||
;/**************************************************************************/
|
||||
;VOID _tx_thread_context_save(VOID)
|
||||
;{
|
||||
.global _tx_thread_context_save
|
||||
.type _tx_thread_context_save, @function
|
||||
_tx_thread_context_save:
|
||||
;
|
||||
; /* Upon entry to this routine, it is assumed that an interrupt stack frame
|
||||
; has already been allocated, and the interrupted blink register is already saved. */
|
||||
;
|
||||
clri ; Disable interrupts
|
||||
st r1, [sp, 128] ; Save r1
|
||||
st r0, [sp, 132] ; Save r0
|
||||
;
|
||||
; /* Check for a nested interrupt condition. */
|
||||
; if (_tx_thread_system_state++)
|
||||
; {
|
||||
;
|
||||
ld r0, [gp, _tx_thread_system_state@sda] ; Pickup system state
|
||||
st r3, [sp, 120] ; Save r3
|
||||
st r2, [sp, 124] ; Save r2
|
||||
breq r0, 0, __tx_thread_not_nested_save ; If 0, we are not in a nested
|
||||
; condition
|
||||
;
|
||||
; /* Nested interrupt condition. */
|
||||
;
|
||||
add r0, r0, 1 ; Increment the nested interrupt count
|
||||
st r0, [gp, _tx_thread_system_state@sda] ; Update system state
|
||||
;
|
||||
; /* Save the rest of the scratch registers on the stack and return to the
|
||||
; calling ISR. */
|
||||
;
|
||||
__tx_thread_nested_save: ; Label is for special nested interrupt case from idle system save below
|
||||
st r12, [sp, 84] ; Save r12
|
||||
st r11, [sp, 88] ; Save r11
|
||||
st r10, [sp, 92] ; Save r10
|
||||
st r9, [sp, 96] ; Save r9
|
||||
st r8, [sp, 100] ; Save r8
|
||||
st r7, [sp, 104] ; Save r7
|
||||
st r6, [sp, 108] ; Save r6
|
||||
st r5, [sp, 112] ; Save r5
|
||||
st r4, [sp, 116] ; Save r6
|
||||
lr r10, [LP_START] ; Pickup LP_START
|
||||
lr r9, [LP_END] ; Pickup LP_END
|
||||
st LP_COUNT, [sp, 12] ; Save LP_COUNT
|
||||
st r10, [sp, 4] ; Save LP_START
|
||||
st r9, [sp, 8] ; Save LP_END
|
||||
.ifdef TX_ENABLE_ACC
|
||||
st r58, [sp, 140] ; Save r58
|
||||
st r59, [sp, 144] ; Save r59
|
||||
.endif
|
||||
lr r0, [BTA] ; Pickup BTA
|
||||
st r0, [sp, 156] ; Save BTA
|
||||
|
||||
;
|
||||
; /* Return to the ISR. */
|
||||
;
|
||||
.ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
|
||||
;
|
||||
; /* Call the ISR enter function to indicate an ISR is executing. */
|
||||
;
|
||||
sub sp, sp, 32 ; Allocating some space on the stack
|
||||
st blink, [sp, 16] ; Save blink
|
||||
bl.d _tx_execution_isr_enter ; Call the ISR enter function
|
||||
nop ; Delay slot
|
||||
ld blink, [sp, 16] ; Recover blink
|
||||
add sp, sp, 32 ; Recover the stack space
|
||||
.endif
|
||||
;
|
||||
|
||||
j.d [blink] ; Return to Level 1 ISR
|
||||
st ilink, [sp, 20] ; Save ilink
|
||||
;
|
||||
__tx_thread_not_nested_save:
|
||||
; }
|
||||
;
|
||||
; /* Otherwise, not nested, check to see if a thread was running. */
|
||||
; else if (_tx_thread_current_ptr)
|
||||
; {
|
||||
;
|
||||
add r0, r0, 1 ; Increment the nested interrupt count
|
||||
st r0, [gp, _tx_thread_system_state@sda] ; Update system state
|
||||
ld r1, [gp, _tx_thread_current_ptr@sda] ; Pickup current thread pointer
|
||||
st r12, [sp, 84] ; Save r12
|
||||
st r11, [sp, 88] ; Save r11
|
||||
breq r1, 0, __tx_thread_idle_system_save ; If no thread is running, idle system was
|
||||
; interrupted.
|
||||
;
|
||||
; /* Save minimal context of interrupted thread. */
|
||||
;
|
||||
st r10, [sp, 92] ; Save r10
|
||||
st r9, [sp, 96] ; Save r9
|
||||
st r8, [sp, 100] ; Save r8
|
||||
st r7, [sp, 104] ; Save r7
|
||||
st r6, [sp, 108] ; Save r6
|
||||
st r5, [sp, 112] ; Save r5
|
||||
st r4, [sp, 116] ; Save r4
|
||||
lr r10, [LP_START] ; Pickup LP_START
|
||||
lr r9, [LP_END] ; Pickup LP_END
|
||||
st LP_COUNT, [sp, 12] ; Save LP_COUNT
|
||||
st r10, [sp, 4] ; Save LP_START
|
||||
st r9, [sp, 8] ; Save LP_END
|
||||
st ilink, [sp, 20] ; Save ilink
|
||||
.ifdef TX_ENABLE_ACC
|
||||
st r58, [sp, 140] ; Save r58
|
||||
st r59, [sp, 144] ; Save r59
|
||||
.endif
|
||||
lr r0, [BTA] ; Pickup BTA
|
||||
st r0, [sp, 156] ; Save BTA
|
||||
;
|
||||
; /* Save the current stack pointer in the thread's control block. */
|
||||
; _tx_thread_current_ptr -> tx_thread_stack_ptr = sp;
|
||||
;
|
||||
st sp, [r1, 8] ; Save thread's stack pointer
|
||||
|
||||
.ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
|
||||
;
|
||||
; /* Call the ISR enter function to indicate an ISR is executing. */
|
||||
;
|
||||
sub sp, sp, 32 ; Allocating some space on the stack
|
||||
st blink, [sp, 16] ; Save blink
|
||||
bl.d _tx_execution_isr_enter ; Call the ISR enter function
|
||||
nop ; Delay slot
|
||||
ld blink, [sp, 16] ; Recover blink
|
||||
add sp, sp, 32 ; Recover the stack space
|
||||
.endif
|
||||
|
||||
.ifdef TX_ENABLE_HW_STACK_CHECKING
|
||||
lr r2, [status32] ; Pickup current STATUS32
|
||||
and r2, r2, ~STATUS32_SC ; Clear the hardware stack checking enable bit (SC)
|
||||
kflag r2 ; Disable hardware stack checking
|
||||
mov r1, _tx_system_stack_top_address ; Pickup top of system stack (lowest memory address)
|
||||
sr r1, [KSTACK_TOP] ; Setup KSTACK_TOP
|
||||
mov r1, _tx_system_stack_base_address ; Pickup base of system stack (highest memory address)
|
||||
sr r1, [KSTACK_BASE] ; Setup KSTACK_BASE
|
||||
ld sp, [gp, _tx_thread_system_stack_ptr@sda] ; Switch to system stack
|
||||
or r2, r2, STATUS32_SC ; Or in hardware stack checking enable bit (SC)
|
||||
j_s.d [blink] ; Return to calling ISR
|
||||
kflag r2 ; Enable hardware stack checking
|
||||
.else
|
||||
;
|
||||
; /* Switch to the system stack. */
|
||||
; sp = _tx_thread_system_stack_ptr;
|
||||
;
|
||||
j_s.d [blink] ; Return to calling ISR
|
||||
ld sp, [gp, _tx_thread_system_stack_ptr@sda] ; Switch to system stack
|
||||
.endif
|
||||
;
|
||||
; }
|
||||
; else
|
||||
; {
|
||||
;
|
||||
__tx_thread_idle_system_save:
|
||||
;
|
||||
; /* Interrupt occurred in the scheduling loop. */
|
||||
;
|
||||
.ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
|
||||
;
|
||||
; /* Call the ISR enter function to indicate an ISR is executing. */
|
||||
;
|
||||
sub sp, sp, 32 ; Allocating some space on the stack
|
||||
st blink, [sp, 16] ; Save blink
|
||||
bl.d _tx_execution_isr_enter ; Call the ISR enter function
|
||||
nop ; Delay slot
|
||||
ld blink, [sp, 16] ; Recover blink
|
||||
add sp, sp, 32 ; Recover the stack space
|
||||
.endif
|
||||
;
|
||||
; /* See if we have a special nesting condition. This happens when the higher priority
|
||||
; interrupt occurs before the nested interrupt logic is valid. */
|
||||
;
|
||||
lr r0, [AUX_IRQ_ACT] ; Pickup the interrupt active register
|
||||
neg r1, r0 ; Negate
|
||||
and r1, r0, r1 ; See if there are any other interrupts present
|
||||
brne r0, r1, __tx_thread_nested_save ; If more interrupts, go into the nested interrupt save logic
|
||||
;
|
||||
; /* Not much to do here, just adjust the stack pointer, and return to
|
||||
; ISR processing. */
|
||||
;
|
||||
j_s.d [blink] ; Return to ISR
|
||||
add sp, sp, 160 ; Recover stack space
|
||||
;
|
||||
; }
|
||||
;}
|
||||
.end
|
||||
87
ports/arc_em/metaware/src/tx_thread_interrupt_control.s
Normal file
87
ports/arc_em/metaware/src/tx_thread_interrupt_control.s
Normal file
@@ -0,0 +1,87 @@
|
||||
;/**************************************************************************/
|
||||
;/* */
|
||||
;/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
;/* */
|
||||
;/* This software is licensed under the Microsoft Software License */
|
||||
;/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
;/* and in the root directory of this software. */
|
||||
;/* */
|
||||
;/**************************************************************************/
|
||||
;
|
||||
;
|
||||
;/**************************************************************************/
|
||||
;/**************************************************************************/
|
||||
;/** */
|
||||
;/** ThreadX Component */
|
||||
;/** */
|
||||
;/** Thread */
|
||||
;/** */
|
||||
;/**************************************************************************/
|
||||
;/**************************************************************************/
|
||||
;
|
||||
;#define TX_SOURCE_CODE
|
||||
;
|
||||
;
|
||||
;/* Include necessary system files. */
|
||||
;
|
||||
;#include "tx_api.h"
|
||||
;#include "tx_thread.h"
|
||||
;
|
||||
;
|
||||
;/**************************************************************************/
|
||||
;/* */
|
||||
;/* FUNCTION RELEASE */
|
||||
;/* */
|
||||
;/* _tx_thread_interrupt_control ARCv2_EM/MetaWare */
|
||||
;/* 6.0.1 */
|
||||
;/* AUTHOR */
|
||||
;/* */
|
||||
;/* William E. Lamie, Microsoft Corporation */
|
||||
;/* */
|
||||
;/* DESCRIPTION */
|
||||
;/* */
|
||||
;/* This function is responsible for changing the interrupt lockout */
|
||||
;/* posture of the system. */
|
||||
;/* */
|
||||
;/* INPUT */
|
||||
;/* */
|
||||
;/* new_posture New interrupt lockout posture */
|
||||
;/* */
|
||||
;/* OUTPUT */
|
||||
;/* */
|
||||
;/* old_posture Old interrupt lockout posture */
|
||||
;/* */
|
||||
;/* CALLS */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* CALLED BY */
|
||||
;/* */
|
||||
;/* Application Code */
|
||||
;/* */
|
||||
;/* RELEASE HISTORY */
|
||||
;/* */
|
||||
;/* DATE NAME DESCRIPTION */
|
||||
;/* */
|
||||
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
|
||||
;/* */
|
||||
;/**************************************************************************/
|
||||
;UINT _tx_thread_interrupt_control(UINT new_posture)
|
||||
;{
|
||||
.global _tx_thread_interrupt_control
|
||||
.type _tx_thread_interrupt_control, @function
|
||||
_tx_thread_interrupt_control:
|
||||
;
|
||||
; /* Pickup current interrupt lockout posture. */
|
||||
;
|
||||
clri r1 ; Get current interrupt state
|
||||
;
|
||||
; /* Apply the new interrupt posture. */
|
||||
;
|
||||
seti r0 ; Set desired interrupt state
|
||||
j_s.d [blink] ; Return to caller with delay slot
|
||||
mov r0, r1 ; Return previous mask value. Return value is TX_INT_DISABLE or TX_INT_ENABLE.
|
||||
;
|
||||
;}
|
||||
.end
|
||||
238
ports/arc_em/metaware/src/tx_thread_schedule.s
Normal file
238
ports/arc_em/metaware/src/tx_thread_schedule.s
Normal file
@@ -0,0 +1,238 @@
|
||||
;/**************************************************************************/
|
||||
;/* */
|
||||
;/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
;/* */
|
||||
;/* This software is licensed under the Microsoft Software License */
|
||||
;/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
;/* and in the root directory of this software. */
|
||||
;/* */
|
||||
;/**************************************************************************/
|
||||
;
|
||||
;
|
||||
;/**************************************************************************/
|
||||
;/**************************************************************************/
|
||||
;/** */
|
||||
;/** ThreadX Component */
|
||||
;/** */
|
||||
;/** Thread */
|
||||
;/** */
|
||||
;/**************************************************************************/
|
||||
;/**************************************************************************/
|
||||
;
|
||||
;
|
||||
;#define TX_SOURCE_CODE
|
||||
;
|
||||
;
|
||||
.equ BTA, 0x412
|
||||
.equ KSTACK_TOP, 0x264
|
||||
.equ KSTACK_BASE, 0x265
|
||||
.equ STATUS32_SC, 0x4000
|
||||
;
|
||||
;/* Include necessary system files. */
|
||||
;
|
||||
;#include "tx_api.h"
|
||||
;#include "tx_thread.h"
|
||||
;#include "tx_timer.h"
|
||||
;
|
||||
;
|
||||
;/**************************************************************************/
|
||||
;/* */
|
||||
;/* FUNCTION RELEASE */
|
||||
;/* */
|
||||
;/* _tx_thread_schedule ARCv2_EM/MetaWare */
|
||||
;/* 6.0.1 */
|
||||
;/* AUTHOR */
|
||||
;/* */
|
||||
;/* William E. Lamie, Microsoft Corporation */
|
||||
;/* */
|
||||
;/* DESCRIPTION */
|
||||
;/* */
|
||||
;/* This function waits for a thread control block pointer to appear in */
|
||||
;/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */
|
||||
;/* in the variable, the corresponding thread is resumed. */
|
||||
;/* */
|
||||
;/* INPUT */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* OUTPUT */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* CALLS */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* CALLED BY */
|
||||
;/* */
|
||||
;/* _tx_initialize_kernel_enter ThreadX entry function */
|
||||
;/* _tx_thread_system_return Return to system from thread */
|
||||
;/* _tx_thread_context_restore Restore thread's context */
|
||||
;/* */
|
||||
;/* RELEASE HISTORY */
|
||||
;/* */
|
||||
;/* DATE NAME DESCRIPTION */
|
||||
;/* */
|
||||
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
|
||||
;/* */
|
||||
;/**************************************************************************/
|
||||
;VOID _tx_thread_schedule(VOID)
|
||||
;{
|
||||
.global _tx_thread_schedule
|
||||
.type _tx_thread_schedule, @function
|
||||
_tx_thread_schedule:
|
||||
;
|
||||
; /* Enable interrupts. */
|
||||
;
|
||||
mov r0, 0x1F ; Build enable interrupt value
|
||||
seti r0 ; Enable interrupts
|
||||
;
|
||||
; /* Wait for a thread to execute. */
|
||||
; do
|
||||
; {
|
||||
;
|
||||
__tx_thread_schedule_loop:
|
||||
;
|
||||
ld r0, [gp, _tx_thread_execute_ptr@sda] ; Pickup next thread to execute
|
||||
breq r0, 0, __tx_thread_schedule_loop ; If NULL, keep looking
|
||||
;
|
||||
; }
|
||||
; while(_tx_thread_execute_ptr == TX_NULL);
|
||||
;
|
||||
; /* Yes! We have a thread to execute. Lockout interrupts and
|
||||
; transfer control to it. */
|
||||
;
|
||||
clri ; Lockout interrupts
|
||||
nop ; Delay for interrupts to really be disabled
|
||||
;
|
||||
; /* Setup the current thread pointer. */
|
||||
; _tx_thread_current_ptr = _tx_thread_execute_ptr;
|
||||
;
|
||||
st r0, [gp, _tx_thread_current_ptr@sda] ; Setup current thread pointer
|
||||
;
|
||||
; /* Increment the run count for this thread. */
|
||||
; _tx_thread_current_ptr -> tx_thread_run_count++;
|
||||
;
|
||||
ld r3, [r0, 4] ; Pickup run counter
|
||||
ld r4, [r0, 24] ; Pickup time-slice for this thread
|
||||
add r3, r3, 1 ; Increment run counter
|
||||
st r3, [r0, 4] ; Store the new run counter
|
||||
|
||||
.ifdef TX_ENABLE_HW_STACK_CHECKING
|
||||
lr r2, [status32] ; Pickup current STATUS32
|
||||
and r2, r2, ~STATUS32_SC ; Clear the hardware stack checking enable bit (SC)
|
||||
kflag r2 ; Disable hardware stack checking
|
||||
ld r3, [r0, 12] ; Pickup the top of the thread's stack (lowest address)
|
||||
sr r3, [KSTACK_TOP] ; Setup KSTACK_TOP
|
||||
ld r3, [r0, 16] ; Pickup the base of the thread's stack (highest address)
|
||||
sr r3, [KSTACK_BASE] ; Setup KSTACK_BASE
|
||||
.endif
|
||||
;
|
||||
; /* Setup time-slice, if present. */
|
||||
; _tx_timer_time_slice = _tx_thread_current_ptr -> tx_thread_time_slice;
|
||||
;
|
||||
ld sp, [r0, 8] ; Switch to thread's stack
|
||||
|
||||
.ifdef TX_ENABLE_HW_STACK_CHECKING
|
||||
or r2, r2, STATUS32_SC ; Or in hardware stack checking enable bit (SC)
|
||||
kflag r2 ; Enable hardware stack checking
|
||||
.endif
|
||||
|
||||
st r4, [gp, _tx_timer_time_slice@sda] ; Setup time-slice
|
||||
;
|
||||
; /* Switch to the thread's stack. */
|
||||
; sp = _tx_thread_execute_ptr -> tx_thread_stack_ptr;
|
||||
;
|
||||
.ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
|
||||
;
|
||||
; /* Call the thread entry function to indicate the thread is executing. */
|
||||
;
|
||||
bl.d _tx_execution_thread_enter ; Call the thread execution enter function
|
||||
sub sp, sp, 16 ; ..allocating some space on the stack
|
||||
add sp, sp, 16 ; Recover the stack space
|
||||
.endif
|
||||
;
|
||||
; /* Determine if an interrupt frame or a synchronous task suspension frame
|
||||
; is present. */
|
||||
;
|
||||
ld r1, [sp, 0] ; Pickup the stack type
|
||||
brne r1, 0, __tx_thread_schedule_int_ret ; Compare to solicited stack type. If not, thread was interrupted
|
||||
ld blink, [sp, 4] ; Recover blink
|
||||
ld fp, [sp, 8] ; Recover fp
|
||||
ld gp, [sp, 12] ; Recover gp
|
||||
ld r25, [sp, 16] ; Recover r25
|
||||
ld r24, [sp, 20] ; Recover r24
|
||||
ld r23, [sp, 24] ; Recover r23
|
||||
ld r22, [sp, 28] ; Recover r22
|
||||
ld r21, [sp, 32] ; Recover r21
|
||||
ld r20, [sp, 36] ; Recover r20
|
||||
ld r19, [sp, 40] ; Recover r19
|
||||
ld r18, [sp, 44] ; Recover r18
|
||||
ld r17, [sp, 48] ; Recover r17
|
||||
ld r16, [sp, 52] ; Recover r16
|
||||
ld r15, [sp, 56] ; Recover r15
|
||||
ld r14, [sp, 60] ; Recover r14
|
||||
ld r13, [sp, 64] ; Recover r13
|
||||
ld r1, [sp, 68] ; Pickup status32
|
||||
ld r30, [sp, 72] ; Recover r30
|
||||
add sp, sp, 76 ; Recover solicited stack frame
|
||||
j_s.d [blink] ; Return to thread and restore flags
|
||||
seti r1 ; Recover STATUS32
|
||||
;
|
||||
__tx_thread_schedule_int_ret:
|
||||
;
|
||||
mov r0, 0x2 ; Pretend level 1 interrupt is returning
|
||||
sr r0, [AUX_IRQ_ACT] ;
|
||||
|
||||
ld r0, [sp, 4] ; Recover LP_START
|
||||
sr r0, [LP_START] ; Restore LP_START
|
||||
ld r1, [sp, 8] ; Recover LP_END
|
||||
sr r1, [LP_END] ; Restore LP_END
|
||||
ld r2, [sp, 12] ; Recover LP_COUNT
|
||||
mov LP_COUNT, r2
|
||||
ld r0, [sp, 156] ; Pickup saved BTA
|
||||
sr r0, [BTA] ; Recover BTA
|
||||
ld blink, [sp, 16] ; Recover blink
|
||||
ld ilink, [sp, 20] ; Recover ilink
|
||||
ld fp, [sp, 24] ; Recover fp
|
||||
ld gp, [sp, 28] ; Recover gp
|
||||
ld r25, [sp, 32] ; Recover r25
|
||||
ld r24, [sp, 36] ; Recover r24
|
||||
ld r23, [sp, 40] ; Recover r23
|
||||
ld r22, [sp, 44] ; Recover r22
|
||||
ld r21, [sp, 48] ; Recover r21
|
||||
ld r20, [sp, 52] ; Recover r20
|
||||
ld r19, [sp, 56] ; Recover r19
|
||||
ld r18, [sp, 60] ; Recover r18
|
||||
ld r17, [sp, 64] ; Recover r17
|
||||
ld r16, [sp, 68] ; Recover r16
|
||||
ld r15, [sp, 72] ; Recover r15
|
||||
ld r14, [sp, 76] ; Recover r14
|
||||
ld r13, [sp, 80] ; Recover r13
|
||||
ld r12, [sp, 84] ; Recover r12
|
||||
ld r11, [sp, 88] ; Recover r11
|
||||
ld r10, [sp, 92] ; Recover r10
|
||||
ld r9, [sp, 96] ; Recover r9
|
||||
ld r8, [sp, 100] ; Recover r8
|
||||
ld r7, [sp, 104] ; Recover r7
|
||||
ld r6, [sp, 108] ; Recover r6
|
||||
ld r5, [sp, 112] ; Recover r5
|
||||
ld r4, [sp, 116] ; Recover r4
|
||||
ld r3, [sp, 120] ; Recover r3
|
||||
ld r2, [sp, 124] ; Recover r2
|
||||
ld r1, [sp, 128] ; Recover r1
|
||||
ld r0, [sp, 132] ; Recover r0
|
||||
ld r30, [sp, 136] ; Recover r30
|
||||
.ifdef TX_ENABLE_ACC
|
||||
ld r58, [sp, 140] ; Recover r58
|
||||
ld r59, [sp, 144] ; Recover r59
|
||||
.endif
|
||||
add sp, sp, 160 ; Recover interrupt stack frame
|
||||
rtie ; Return to point of interrupt
|
||||
|
||||
;
|
||||
;}
|
||||
;
|
||||
.end
|
||||
|
||||
205
ports/arc_em/metaware/src/tx_thread_stack_build.s
Normal file
205
ports/arc_em/metaware/src/tx_thread_stack_build.s
Normal file
@@ -0,0 +1,205 @@
|
||||
;/**************************************************************************/
|
||||
;/* */
|
||||
;/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
;/* */
|
||||
;/* This software is licensed under the Microsoft Software License */
|
||||
;/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
;/* and in the root directory of this software. */
|
||||
;/* */
|
||||
;/**************************************************************************/
|
||||
;
|
||||
;
|
||||
;/**************************************************************************/
|
||||
;/**************************************************************************/
|
||||
;/** */
|
||||
;/** ThreadX Component */
|
||||
;/** */
|
||||
;/** Thread */
|
||||
;/** */
|
||||
;/**************************************************************************/
|
||||
;/**************************************************************************/
|
||||
;
|
||||
;
|
||||
;#define TX_SOURCE_CODE
|
||||
;
|
||||
;
|
||||
;/* Include necessary system files. */
|
||||
;
|
||||
;#include "tx_api.h"
|
||||
;#include "tx_thread.h"
|
||||
;
|
||||
;
|
||||
.equ LONG_ALIGN_MASK, 0xFFFFFFFC
|
||||
.equ INT_ENABLE_BITS, 0x8000001E
|
||||
;
|
||||
;
|
||||
;/**************************************************************************/
|
||||
;/* */
|
||||
;/* FUNCTION RELEASE */
|
||||
;/* */
|
||||
;/* _tx_thread_stack_build ARCv2_EM/MetaWare */
|
||||
;/* 6.0.1 */
|
||||
;/* AUTHOR */
|
||||
;/* */
|
||||
;/* William E. Lamie, Microsoft Corporation */
|
||||
;/* */
|
||||
;/* DESCRIPTION */
|
||||
;/* */
|
||||
;/* This function builds a stack frame on the supplied thread's stack. */
|
||||
;/* The stack frame results in a fake interrupt return to the supplied */
|
||||
;/* function pointer. */
|
||||
;/* */
|
||||
;/* INPUT */
|
||||
;/* */
|
||||
;/* thread_ptr Pointer to thread control blk */
|
||||
;/* function_ptr Pointer to return function */
|
||||
;/* */
|
||||
;/* OUTPUT */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* CALLS */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* CALLED BY */
|
||||
;/* */
|
||||
;/* _tx_thread_create Create thread service */
|
||||
;/* */
|
||||
;/* RELEASE HISTORY */
|
||||
;/* */
|
||||
;/* DATE NAME DESCRIPTION */
|
||||
;/* */
|
||||
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
|
||||
;/* */
|
||||
;/**************************************************************************/
|
||||
;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID))
|
||||
;{
|
||||
.global _tx_thread_stack_build
|
||||
.type _tx_thread_stack_build, @function
|
||||
_tx_thread_stack_build:
|
||||
;
|
||||
;
|
||||
; /* Build a fake interrupt frame. The form of the fake interrupt stack
|
||||
; on the ARCv2 EM should look like the following after it is built.
|
||||
; Note that the extension registers are always assigned space here.
|
||||
;
|
||||
; Stack Top: 1 Interrupt stack frame type
|
||||
; LP_START Initial loop start
|
||||
; LP_END Initial loop end
|
||||
; LP_COUNT Initial loop count
|
||||
; blink Initial blink value
|
||||
; ilink Initial ilink (point of interrupt)
|
||||
; fp (r27) Initial fp (0)
|
||||
; gp Initial gp
|
||||
; r25 Initial r25
|
||||
; r24 Initial r24
|
||||
; r23 Initial r23
|
||||
; r22 Initial r22
|
||||
; r21 Initial r21
|
||||
; r20 Initial r20
|
||||
; r19 Initial r19
|
||||
; r18 Initial r18
|
||||
; r17 Initial r17
|
||||
; r16 Initial r16
|
||||
; r15 Initial r15
|
||||
; r14 Initial r14
|
||||
; r13 Initial r13
|
||||
; r12 Initial r12
|
||||
; r11 Initial r11
|
||||
; r10 Initial r10
|
||||
; r9 Initial r9
|
||||
; r8 Initial r8
|
||||
; r7 Initial r7
|
||||
; r6 Initial r6
|
||||
; r5 Initial r5
|
||||
; r4 Initial r4
|
||||
; r3 Initial r3
|
||||
; r2 Initial r2
|
||||
; r1 Initial r1
|
||||
; r0 Initial r0
|
||||
; r30 Initial r30
|
||||
; r58 Initial r58
|
||||
; r59 Initial r59
|
||||
; 0 Reserved
|
||||
; 0 Reserved
|
||||
; 0 Initial BTA
|
||||
; 0 Point of Interrupt (thread entry point)
|
||||
; 0 Initial STATUS32
|
||||
; 0 Backtrace
|
||||
; 0 Backtrace
|
||||
; 0 Backtrace
|
||||
; 0 Backtrace
|
||||
;
|
||||
; *: these registers will only be saved and restored if flag -Xxmac_d16 is passed to hcac
|
||||
;
|
||||
; Stack Bottom: (higher memory address) */
|
||||
;
|
||||
ld r3, [r0, 16] ; Pickup end of stack area
|
||||
and r3, r3, LONG_ALIGN_MASK ; Ensure long-word alignment
|
||||
sub r3, r3, 196 ; Allocate an interrupt stack frame (ARCv2 EM)
|
||||
;
|
||||
; /* Actually build the stack frame. */
|
||||
;
|
||||
st 1, [r3, 0] ; Store interrupt stack type on the
|
||||
; top of the stack
|
||||
mov r5, 0 ; Build initial clear value
|
||||
st r5, [r3, 4] ; Store initial LP_START
|
||||
st r5, [r3, 8] ; Store initial LP_END
|
||||
st r5, [r3, 12] ; Store initial LP_COUNT
|
||||
st r5, [r3, 16] ; Store initial blink
|
||||
st r1, [r3, 20] ; Store initial ilink
|
||||
st r5, [r3, 24] ; Store initial fp (0 for backtrace)
|
||||
st gp, [r3, 28] ; Store current gp
|
||||
st r5, [r3, 32] ; Store initial r25
|
||||
st r5, [r3, 36] ; Store initial r24
|
||||
st r5, [r3, 40] ; Store initial r23
|
||||
st r5, [r3, 44] ; Store initial r22
|
||||
st r5, [r3, 48] ; Store initial r21
|
||||
st r5, [r3, 52] ; Store initial r20
|
||||
st r5, [r3, 56] ; Store initial r19
|
||||
st r5, [r3, 60] ; Store initial r18
|
||||
st r5, [r3, 64] ; Store initial r17
|
||||
st r5, [r3, 68] ; Store initial r16
|
||||
st r5, [r3, 72] ; Store initial r15
|
||||
st r5, [r3, 76] ; Store initial r14
|
||||
st r5, [r3, 80] ; Store initial r13
|
||||
st r5, [r3, 84] ; Store initial r12
|
||||
st r5, [r3, 88] ; Store initial r11
|
||||
st r5, [r3, 92] ; Store initial r10
|
||||
st r5, [r3, 96] ; Store initial r9
|
||||
st r5, [r3, 100] ; Store initial r8
|
||||
st r5, [r3, 104] ; Store initial r7
|
||||
st r5, [r3, 108] ; Store initial r6
|
||||
st r5, [r3, 112] ; Store initial r5
|
||||
st r5, [r3, 116] ; Store initial r4
|
||||
st r5, [r3, 120] ; Store initial r3
|
||||
st r5, [r3, 124] ; Store initial r2
|
||||
st r5, [r3, 128] ; Store initial r1
|
||||
st r5, [r3, 132] ; Store initial r0
|
||||
st r5, [r3, 136] ; Store initial r30
|
||||
st r5, [r3, 140] ; Store initial r58
|
||||
st r5, [r3, 144] ; Store initial r59
|
||||
st r5, [r3, 148] ; Reserved
|
||||
st r5, [r3, 152] ; Reserved
|
||||
st r5, [r3, 156] ; Store initial BTA
|
||||
st r1, [r3, 160] ; Store initial point of entry
|
||||
lr r6, [status32] ; Pickup STATUS32
|
||||
or r6, r6, INT_ENABLE_BITS ; Make sure interrupts are enabled
|
||||
st r6, [r3, 164] ; Store initial STATUS32
|
||||
st r5, [r3, 168] ; Backtrace 0
|
||||
st r5, [r3, 172] ; Backtrace 0
|
||||
st r5, [r3, 176] ; Backtrace 0
|
||||
st r5, [r3, 180] ; Backtrace 0
|
||||
;
|
||||
; /* Setup stack pointer. */
|
||||
; thread_ptr -> tx_thread_stack_ptr = r3;
|
||||
;
|
||||
j_s.d [blink] ; Return to caller
|
||||
st r3, [r0, 8] ; Save stack pointer in thread's
|
||||
; control block
|
||||
;}
|
||||
.end
|
||||
|
||||
|
||||
169
ports/arc_em/metaware/src/tx_thread_system_return.s
Normal file
169
ports/arc_em/metaware/src/tx_thread_system_return.s
Normal file
@@ -0,0 +1,169 @@
|
||||
;/**************************************************************************/
|
||||
;/* */
|
||||
;/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
;/* */
|
||||
;/* This software is licensed under the Microsoft Software License */
|
||||
;/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
;/* and in the root directory of this software. */
|
||||
;/* */
|
||||
;/**************************************************************************/
|
||||
;
|
||||
;
|
||||
;/**************************************************************************/
|
||||
;/**************************************************************************/
|
||||
;/** */
|
||||
;/** ThreadX Component */
|
||||
;/** */
|
||||
;/** Thread */
|
||||
;/** */
|
||||
;/**************************************************************************/
|
||||
;/**************************************************************************/
|
||||
;
|
||||
;#define TX_SOURCE_CODE
|
||||
;
|
||||
.equ KSTACK_TOP, 0x264
|
||||
.equ KSTACK_BASE, 0x265
|
||||
.equ STATUS32_SC, 0x4000
|
||||
;
|
||||
;/* Include necessary system files. */
|
||||
;
|
||||
;#include "tx_api.h"
|
||||
;#include "tx_thread.h"
|
||||
;#include "tx_timer.h"
|
||||
;
|
||||
;
|
||||
;/**************************************************************************/
|
||||
;/* */
|
||||
;/* FUNCTION RELEASE */
|
||||
;/* */
|
||||
;/* _tx_thread_system_return ARCv2_EM/MetaWare */
|
||||
;/* 6.0.1 */
|
||||
;/* AUTHOR */
|
||||
;/* */
|
||||
;/* William E. Lamie, Microsoft Corporation */
|
||||
;/* */
|
||||
;/* DESCRIPTION */
|
||||
;/* */
|
||||
;/* This function is target processor specific. It is used to transfer */
|
||||
;/* control from a thread back to the ThreadX system. Only a */
|
||||
;/* minimal context is saved since the compiler assumes temp registers */
|
||||
;/* are going to get slicked by a function call anyway. */
|
||||
;/* */
|
||||
;/* INPUT */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* OUTPUT */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* CALLS */
|
||||
;/* */
|
||||
;/* _tx_thread_schedule Thread scheduling loop */
|
||||
;/* */
|
||||
;/* CALLED BY */
|
||||
;/* */
|
||||
;/* ThreadX components */
|
||||
;/* */
|
||||
;/* RELEASE HISTORY */
|
||||
;/* */
|
||||
;/* DATE NAME DESCRIPTION */
|
||||
;/* */
|
||||
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
|
||||
;/* */
|
||||
;/**************************************************************************/
|
||||
;VOID _tx_thread_system_return(VOID)
|
||||
;{
|
||||
.global _tx_thread_system_return
|
||||
.type _tx_thread_system_return, @function
|
||||
_tx_thread_system_return:
|
||||
;
|
||||
; /* Save minimal context on the stack. */
|
||||
;
|
||||
; /* Lockout interrupts. */
|
||||
;
|
||||
clri r2 ; Disable interrupts
|
||||
sub sp, sp, 76 ; Allocate a solicited stack frame
|
||||
mov r3, 0 ; Build a solicited stack type
|
||||
st r3, [sp, 0] ; Store stack type on the top
|
||||
st blink, [sp, 4] ; Save return address and flags
|
||||
st fp, [sp, 8] ; Save fp
|
||||
st r26, [sp, 12] ; Save r26
|
||||
st r25, [sp, 16] ; Save r25
|
||||
st r24, [sp, 20] ; Save r24
|
||||
st r23, [sp, 24] ; Save r23
|
||||
st r22, [sp, 28] ; Save r22
|
||||
st r21, [sp, 32] ; Save r21
|
||||
st r20, [sp, 36] ; Save r20
|
||||
st r19, [sp, 40] ; Save r19
|
||||
st r18, [sp, 44] ; Save r18
|
||||
st r17, [sp, 48] ; Save r17
|
||||
st r16, [sp, 52] ; Save r16
|
||||
st r15, [sp, 56] ; Save r15
|
||||
st r14, [sp, 60] ; Save r14
|
||||
st r13, [sp, 64] ; Save r13
|
||||
st r2, [sp, 68] ; Save status32
|
||||
st r30, [sp, 72] ; Save r30
|
||||
;
|
||||
.ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
|
||||
;
|
||||
; /* Call the thread exit function to indicate the thread is no longer executing. */
|
||||
;
|
||||
bl.d _tx_execution_thread_exit ; Call the thread exit function
|
||||
sub sp, sp, 16 ; ..allocating some space on the stack
|
||||
add sp, sp, 16 ; Recover the stack space
|
||||
mov r3, 0 ; Build clear value
|
||||
.endif
|
||||
;
|
||||
; /* Save current stack and switch to system stack. */
|
||||
; _tx_thread_current_ptr -> tx_thread_stack_ptr = sp;
|
||||
; sp = _tx_thread_system_stack_ptr;
|
||||
;
|
||||
ld r0, [gp, _tx_thread_current_ptr@sda] ; Pickup current thread ptr
|
||||
st sp, [r0, 8] ; Save thread's stack pointer
|
||||
ld r5, [gp, _tx_timer_time_slice@sda] ; Pickup current time-slice
|
||||
|
||||
.ifdef TX_ENABLE_HW_STACK_CHECKING
|
||||
lr r2, [status32] ; Pickup current STATUS32
|
||||
and r2, r2, ~STATUS32_SC ; Clear the hardware stack checking enable bit (SC)
|
||||
kflag r2 ; Disable hardware stack checking
|
||||
mov r1, _tx_system_stack_top_address ; Pickup top of system stack (lowest memory address)
|
||||
sr r1, [KSTACK_TOP] ; Setup KSTACK_TOP
|
||||
mov r1, _tx_system_stack_base_address ; Pickup base of system stack (highest memory address)
|
||||
sr r1, [KSTACK_BASE] ; Setup KSTACK_BASE
|
||||
.endif
|
||||
|
||||
ld sp, [gp, _tx_thread_system_stack_ptr@sda] ; Switch to system stack
|
||||
|
||||
.ifdef TX_ENABLE_HW_STACK_CHECKING
|
||||
or r2, r2, STATUS32_SC ; Or in hardware stack checking enable bit (SC)
|
||||
kflag r2 ; Enable hardware stack checking
|
||||
.endif
|
||||
;
|
||||
; /* Determine if the time-slice is active. */
|
||||
; if (_tx_timer_time_slice)
|
||||
; {
|
||||
;
|
||||
breq r5, 0, __tx_thread_dont_save_ts ; If not, skip save processing
|
||||
;
|
||||
; /* Save time-slice for the thread and clear the current time-slice. */
|
||||
; _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice;
|
||||
; _tx_timer_time_slice = 0;
|
||||
;
|
||||
st r3, [gp, _tx_timer_time_slice@sda] ; Clear time-slice variable
|
||||
st r5, [r0, 24] ; Save current time-slice
|
||||
;
|
||||
; }
|
||||
__tx_thread_dont_save_ts:
|
||||
;
|
||||
; /* Clear the current thread pointer. */
|
||||
; _tx_thread_current_ptr = TX_NULL;
|
||||
;
|
||||
b.d _tx_thread_schedule ; Return to scheduler..
|
||||
st r3, [gp, _tx_thread_current_ptr@sda] ; ..clearing current thread pointer
|
||||
;
|
||||
;}
|
||||
.end
|
||||
|
||||
|
||||
238
ports/arc_em/metaware/src/tx_timer_interrupt.s
Normal file
238
ports/arc_em/metaware/src/tx_timer_interrupt.s
Normal file
@@ -0,0 +1,238 @@
|
||||
;/**************************************************************************/
|
||||
;/* */
|
||||
;/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
;/* */
|
||||
;/* This software is licensed under the Microsoft Software License */
|
||||
;/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
;/* and in the root directory of this software. */
|
||||
;/* */
|
||||
;/**************************************************************************/
|
||||
;
|
||||
;
|
||||
;/**************************************************************************/
|
||||
;/**************************************************************************/
|
||||
;/** */
|
||||
;/** ThreadX Component */
|
||||
;/** */
|
||||
;/** Timer */
|
||||
;/** */
|
||||
;/**************************************************************************/
|
||||
;/**************************************************************************/
|
||||
;
|
||||
;#define TX_SOURCE_CODE
|
||||
;
|
||||
;
|
||||
;/* Include necessary system files. */
|
||||
;
|
||||
;#include "tx_api.h"
|
||||
;#include "tx_timer.h"
|
||||
;#include "tx_thread.h"
|
||||
;
|
||||
;
|
||||
;/**************************************************************************/
|
||||
;/* */
|
||||
;/* FUNCTION RELEASE */
|
||||
;/* */
|
||||
;/* _tx_timer_interrupt ARCv2_EM/MetaWare */
|
||||
;/* 6.0.1 */
|
||||
;/* AUTHOR */
|
||||
;/* */
|
||||
;/* William E. Lamie, Microsoft Corporation */
|
||||
;/* */
|
||||
;/* DESCRIPTION */
|
||||
;/* */
|
||||
;/* This function processes the hardware timer interrupt. This */
|
||||
;/* processing includes incrementing the system clock and checking for */
|
||||
;/* time slice and/or timer expiration. If either is found, the */
|
||||
;/* interrupt context save/restore functions are called along with the */
|
||||
;/* expiration functions. */
|
||||
;/* */
|
||||
;/* INPUT */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* OUTPUT */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* CALLS */
|
||||
;/* */
|
||||
;/* _tx_timer_expiration_process Process timer expiration */
|
||||
;/* _tx_thread_time_slice Time slice interrupted thread */
|
||||
;/* _tx_thread_context_save Save interrupt context */
|
||||
;/* _tx_thread_context_restore Restore interrupt context */
|
||||
;/* */
|
||||
;/* CALLED BY */
|
||||
;/* */
|
||||
;/* interrupt vector */
|
||||
;/* */
|
||||
;/* RELEASE HISTORY */
|
||||
;/* */
|
||||
;/* DATE NAME DESCRIPTION */
|
||||
;/* */
|
||||
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
|
||||
;/* */
|
||||
;/**************************************************************************/
|
||||
;VOID _tx_timer_interrupt(VOID)
|
||||
;{
|
||||
.global _tx_timer_interrupt
|
||||
.type _tx_timer_interrupt, @function
|
||||
_tx_timer_interrupt:
|
||||
;
|
||||
; /* Upon entry to this routine, it is assumed the interrupt stack frame has
|
||||
; already been allocated and registers r0, r1, and r2 have already been saved
|
||||
; at offsets 0, 4, and 8 respectively. */
|
||||
;
|
||||
; /* Increment the system clock. */
|
||||
; _tx_timer_system_clock++;
|
||||
;
|
||||
clri ; Lockout interrupts
|
||||
ld r0, [gp,_tx_timer_system_clock@sda] ; Pickup current system clock
|
||||
ld r2, [gp, _tx_timer_time_slice@sda] ; Pickup current time-slice
|
||||
add r0, r0, 1 ; Increment the system clock
|
||||
st r0, [gp,_tx_timer_system_clock@sda] ; Store system clock back in memory
|
||||
|
||||
; /* Test for time-slice expiration. */
|
||||
; if (_tx_timer_time_slice)
|
||||
; {
|
||||
;
|
||||
mov r1, 0 ; Clear expiration flag
|
||||
breq r2, 0, __tx_timer_no_time_slice ; If zero, no time-slice is active
|
||||
;
|
||||
; /* Decrement the time_slice. */
|
||||
; _tx_timer_time_slice--;
|
||||
;
|
||||
sub r2, r2, 1 ; Decrement time-slice
|
||||
st r2, [gp, _tx_timer_time_slice@sda] ; Store new time-slice value
|
||||
;
|
||||
; /* Check for expiration. */
|
||||
; if (__tx_timer_time_slice == 0)
|
||||
;
|
||||
brne r2, 0, __tx_timer_no_time_slice ; If non-zero, skip over expiration
|
||||
;
|
||||
; /* Set the time-slice expired flag. */
|
||||
; _tx_timer_expired_time_slice = TX_TRUE;
|
||||
;
|
||||
mov r1, 1 ; Set register flag
|
||||
st r1, [gp, _tx_timer_expired_time_slice@sda] ; Set the time-slice expired flag
|
||||
|
||||
;
|
||||
; }
|
||||
;
|
||||
__tx_timer_no_time_slice:
|
||||
;
|
||||
; /* Test for timer expiration. */
|
||||
; if (*_tx_timer_current_ptr)
|
||||
; {
|
||||
;
|
||||
ld r0, [gp, _tx_timer_current_ptr@sda] ; Pickup current timer pointer
|
||||
ld r2, [r0, 0] ; Pickup examine actual list entry
|
||||
breq r2, 0, __tx_timer_no_timer ;
|
||||
; If NULL, no timer has expired, just move to the next entry
|
||||
;
|
||||
; /* Set expiration flag. */
|
||||
; _tx_timer_expired = TX_TRUE;
|
||||
;
|
||||
mov r1, 1 ; Build expiration value
|
||||
b.d __tx_timer_done ; Skip moving the timer pointer
|
||||
st r1, [gp, _tx_timer_expired@sda] ; Set the expired value
|
||||
;
|
||||
; }
|
||||
; else
|
||||
; {
|
||||
__tx_timer_no_timer:
|
||||
;
|
||||
; /* No timer expired, increment the timer pointer. */
|
||||
; _tx_timer_current_ptr++;
|
||||
;
|
||||
ld r2, [gp, _tx_timer_list_end@sda] ; Pickup end of list
|
||||
add r0, r0, 4 ; Move to next timer entry
|
||||
;
|
||||
; /* Check for wrap-around. */
|
||||
; if (_tx_timer_current_ptr == _tx_timer_list_end)
|
||||
;
|
||||
st r0, [gp, _tx_timer_current_ptr@sda] ; Store the current timer
|
||||
brne r0, r2, __tx_timer_skip_wrap ; If not equal, don't wrap the list
|
||||
;
|
||||
; /* Wrap to beginning of list. */
|
||||
; _tx_timer_current_ptr = _tx_timer_list_start;
|
||||
;
|
||||
ld r2, [gp, _tx_timer_list_start@sda] ; Pickup start of timer list
|
||||
st r2, [gp, _tx_timer_current_ptr@sda] ; Set current timer to the start
|
||||
;
|
||||
__tx_timer_skip_wrap:
|
||||
;
|
||||
; }
|
||||
;
|
||||
__tx_timer_done:
|
||||
;
|
||||
;
|
||||
; /* See if anything has expired. */
|
||||
; if ((_tx_timer_expired_time_slice) || (_tx_timer_expired))
|
||||
; {
|
||||
;
|
||||
breq r1, 0, __tx_timer_nothing_expired ; If 0, nothing has expired
|
||||
;
|
||||
__tx_something_expired:
|
||||
;
|
||||
ld r0, [sp, 0] ; Recover r0
|
||||
ld r1, [sp, 4] ; Recover r1
|
||||
ld r2, [sp, 8] ; Recover r2
|
||||
st blink, [sp, 16] ; Save blink
|
||||
bl _tx_thread_context_save ; Save interrupted context
|
||||
;
|
||||
; /* Did a timer expire? */
|
||||
; if (_tx_timer_expired)
|
||||
; {
|
||||
;
|
||||
ld r2, [gp, _tx_timer_expired@sda] ; Pickup timer expired flag
|
||||
ld r4, [gp, _tx_thread_preempt_disable@sda] ; Pickup preempt disable
|
||||
breq r2, 0, __tx_timer_dont_activate ; If not set, skip expiration processing
|
||||
;
|
||||
; /* Process the timer expiration. */
|
||||
; /* _tx_timer_expiration_process(); */
|
||||
bl.d _tx_timer_expiration_process ; Call the timer expiration handling routine
|
||||
sub sp, sp, 16 ; ..allocating some space on the stack
|
||||
add sp, sp, 16 ; Recover the stack space
|
||||
;
|
||||
; }
|
||||
__tx_timer_dont_activate:
|
||||
;
|
||||
; /* Did time slice expire? */
|
||||
; if (_tx_timer_expired_time_slice)
|
||||
; {
|
||||
;
|
||||
ld r2, [gp, _tx_timer_expired_time_slice@sda] ; Pickup expired time-slice flag
|
||||
breq r2, 0, __tx_timer_not_ts_expiration ; If not set, skip time-slice
|
||||
;
|
||||
; /* Time slice interrupted thread. */
|
||||
; /* _tx_thread_time_slice(); */
|
||||
|
||||
bl.d _tx_thread_time_slice ; Call time-slice processing
|
||||
sub sp, sp, 16 ; ..allocating some stack space
|
||||
add sp, sp, 16 ; Recover stack space
|
||||
;
|
||||
; }
|
||||
;
|
||||
__tx_timer_not_ts_expiration:
|
||||
;
|
||||
st 0, [gp, _tx_timer_expired_time_slice@sda]
|
||||
b _tx_thread_context_restore ; Go restore interrupt context..
|
||||
; ..clearing time-slice expired flag
|
||||
; Note that we don't return from
|
||||
; this function.
|
||||
;
|
||||
; }
|
||||
;
|
||||
__tx_timer_nothing_expired:
|
||||
;
|
||||
ld r0, [sp, 0] ; Recover r0
|
||||
ld r1, [sp, 4] ; Recover r1
|
||||
ld r2, [sp, 8] ; Recover r2
|
||||
add sp, sp, 160 ; Recover interrupt stack frame
|
||||
rtie ; Return to point of interrupt
|
||||
;
|
||||
;}
|
||||
.end
|
||||
|
||||
Reference in New Issue
Block a user