updated to 6.0.1 and added additional processors/toolchains
This commit is contained in:
tameraw
343
ports/c667x/ccs/src/tx_thread_context_restore.asm
Normal file
343
ports/c667x/ccs/src/tx_thread_context_restore.asm
Normal file
@@ -0,0 +1,343 @@
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;/**************************************************************************/
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;/* */
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;/* Copyright (c) Microsoft Corporation. All rights reserved. */
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;/* */
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;/* This software is licensed under the Microsoft Software License */
|
||||
;/* Terms for Microsoft Azure RTOS. Full text of the license can be */
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||||
;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
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||||
;/* and in the root directory of this software. */
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||||
;/* */
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;/**************************************************************************/
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;
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;
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;/**************************************************************************/
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;/**************************************************************************/
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;/** */
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;/** ThreadX Component */
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;/** */
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;/** Thread */
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;/** */
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;/**************************************************************************/
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;/**************************************************************************/
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;
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;
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;#define TX_SOURCE_CODE
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;
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;
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;/* Include necessary system files. */
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;
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;#include "tx_api.h"
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;#include "tx_thread.h"
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;#include "tx_timer.h"
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;
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FP .set A15
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DP .set B14
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SP .set B15
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;
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.global _tx_thread_system_state
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.global _tx_thread_current_ptr
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.global _tx_thread_system_stack_ptr
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.global _tx_thread_execute_ptr
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.global _tx_timer_time_slice
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.global _tx_thread_schedule
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.global _tx_thread_preempt_disable
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;
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;
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.sect ".text"
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;/**************************************************************************/
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;/* */
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;/* FUNCTION RELEASE */
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;/* */
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;/* _tx_thread_context_restore C667x/TI */
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;/* 6.0 */
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;/* AUTHOR */
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;/* */
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;/* William E. Lamie, Microsoft Corporation */
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;/* */
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;/* DESCRIPTION */
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;/* */
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;/* This function restores the interrupt context if it is processing a */
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;/* nested interrupt. If not, it returns to the interrupt thread if no */
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;/* preemption is necessary. Otherwise, if preemption is necessary or */
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;/* if no thread was running, the function returns to the scheduler. */
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;/* */
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;/* INPUT */
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;/* */
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;/* None */
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;/* */
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;/* OUTPUT */
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;/* */
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;/* None */
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;/* */
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;/* CALLS */
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;/* */
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;/* _tx_thread_schedule Thread scheduling routine */
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;/* */
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;/* CALLED BY */
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;/* */
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;/* ISRs Interrupt Service Routines */
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;/* */
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;/* RELEASE HISTORY */
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||||
;/* */
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||||
;/* DATE NAME DESCRIPTION */
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||||
;/* */
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||||
;/* 05-19-2020 William E. Lamie Initial Version 6.0 */
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;/* */
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;/**************************************************************************/
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;VOID _tx_thread_context_restore(VOID)
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;{
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.global _tx_thread_context_restore
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_tx_thread_context_restore:
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;
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; /* Lockout interrupts. */
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;
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MVC CSR,B0 ; Pickup CSR
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AND -2,B0,B0 ; Build interrupt lockout value
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MVC B0,CSR ; Lockout interrupts
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;
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; /* Determine if interrupts are nested. */
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; if (--_tx_thread_system_state)
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; {
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;
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MVKL _tx_thread_system_state,A0 ; Build address of system state
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MVKH _tx_thread_system_state,A0 ;
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LDW *A0,A1 ; Pickup system state variable
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MVKL _tx_thread_current_ptr,A2 ; Build address of current thread ptr
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NOP 3 ; Delay slots
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SUB A1,1,A1 ; Decrement system state
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[!A1] B _tx_thread_not_nested_restore ; If 0, not a nested restore
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MVKH _tx_thread_current_ptr,A2 ;
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LDW *A2,A3 ; Pickup current thread pointer
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STW A1,*A0 ; Store system state
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NOP 2 ; Delay slots
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;
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; /* Interrupts are nested. */
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;
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; /* Just recover the saved registers and return to the point of
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; interrupt. */
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;
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LDW *+SP(8),B0 ; Recover saved CSR
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LDW *+SP(12),B1 ; Recover saved IRP
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LDW *+SP(16),B2 ; Recover saved AMR
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LDW *+SP(20),A0 ; Recover A0
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LDW *+SP(24),A1 ; Recover A1
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LDW *+SP(28),A2 ; Recover A2
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LDW *+SP(32),A3 ; Recover A3
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LDW *+SP(36),A4 ; Recover A4
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LDW *+SP(40),A5 ; Recover A5
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LDW *+SP(44),A6 ; Recover A6
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LDW *+SP(48),A7 ; Recover A7
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LDW *+SP(52),A8 ; Recover A8
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LDW *+SP(56),A9 ; Recover A9
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MVC B0,CSR ; Setup CSR
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MVC B1,IRP ; Setup IRP
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MVC B2,AMR ; Setup AMR
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LDW *+SP(268),B0 ; Recover saved ILC
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LDW *+SP(272),B1 ; Recover saved RILC
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LDW *+SP(276),B2 ; Recover saved ITSR
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NOP 4
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MVC B0,ILC ; Setup ILC
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MVC B1,RILC ; Setup RILC
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MVC B2,ITSR ; Setup ITSR
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LDW *+SP(84),B0 ; Recover B0
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LDW *+SP(88),B1 ; Recover B1
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LDW *+SP(92),B2 ; Recover B2
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LDW *+SP(100),B4 ; Recover B4
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LDW *+SP(104),B5 ; Recover B5
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LDW *+SP(108),B6 ; Recover B6
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LDW *+SP(112),B7 ; Recover B7
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LDW *+SP(116),B8 ; Recover B8
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LDW *+SP(140),A16 ; Recover A16
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LDW *+SP(144),A17 ; Recover A17
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LDW *+SP(148),A18 ; Recover A18
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LDW *+SP(152),A19 ; Recover A19
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LDW *+SP(156),A20 ; Recover A20
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LDW *+SP(160),A21 ; Recover A21
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LDW *+SP(164),A22 ; Recover A22
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LDW *+SP(168),A23 ; Recover A23
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LDW *+SP(172),A24 ; Recover A24
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LDW *+SP(176),A25 ; Recover A25
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LDW *+SP(180),A26 ; Recover A26
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LDW *+SP(184),A27 ; Recover A27
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LDW *+SP(188),A28 ; Recover A28
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LDW *+SP(192),A29 ; Recover A29
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LDW *+SP(196),A30 ; Recover A30
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LDW *+SP(200),A31 ; Recover A31
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LDW *+SP(204),B16 ; Recover B16
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LDW *+SP(208),B17 ; Recover B17
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LDW *+SP(212),B18 ; Recover B18
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LDW *+SP(216),B19 ; Recover B19
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LDW *+SP(220),B20 ; Recover B20
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LDW *+SP(224),B21 ; Recover B21
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LDW *+SP(228),B22 ; Recover B22
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LDW *+SP(232),B23 ; Recover B23
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LDW *+SP(236),B24 ; Recover B24
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LDW *+SP(240),B25 ; Recover B25
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LDW *+SP(244),B26 ; Recover B26
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||||
LDW *+SP(248),B27 ; Recover B27
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||||
LDW *+SP(252),B28 ; Recover B28
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LDW *+SP(256),B29 ; Recover B29
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LDW *+SP(260),B30 ; Recover B30
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LDW *+SP(264),B31 ; Recover B31
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B IRP ; Return to point of interrupt
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|| LDW *+SP(120),B9 ; Recover B9
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LDW *+SP(96),B3 ; Recover B3
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ADDK.S2 288,SP ; Recover stack space
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NOP 3 ; Delay slots
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;
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; }
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_tx_thread_not_nested_restore:
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;
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; /* Determine if a thread was interrupted and no preemption is required. */
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; else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr)
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; || (_tx_thread_preempt_disable))
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; {
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;
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NOP ; Delay
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MV A3,A1 ; Move thread pointer into A1
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[!A1] B _tx_thread_schedule ; If null, idle system restore
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MVKL _tx_thread_preempt_disable,A0 ; Build preempt disable flag address
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MVKH _tx_thread_preempt_disable,A0 ;
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MVKL _tx_thread_execute_ptr,A4 ; Build execute thread pointer
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MVKH _tx_thread_execute_ptr,A4 ;
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LDW *A0,B1 ; Pickup preempt disable flag
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LDW *A4,A6 ; Pickup next thread to execute
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NOP 4 ; Delay slot
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CMPEQ A6,A1,A7 ; Determine if threads are the same?
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ADD A7,B1,B1 ; Add results together
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[B1] B _tx_thread_no_preempt_restore ; If set, skip preeemption
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LDW *+A1(8),A6 ; Recover thread's stack pointer
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MVKL _tx_timer_time_slice,A5 ; Build time slice address
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MVKH _tx_timer_time_slice,A5 ;
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LDW *A5,B1 ; Pickup current time-slice
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NOP ; Delay slot
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;
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;
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_tx_thread_preempt_restore:
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;
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;
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MVKL 1,A0 ; Build the interrupt stack type
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STW A0,*+A6(4) ; Save stack type
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;
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; /* Store the remaining registers on the thread's stack. */
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;
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STW A10,*+A6(60) ; Save A10
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STW A11,*+A6(64) ; Save A11
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STW A12,*+A6(68) ; Save A12
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STW A13,*+A6(72) ; Save A13
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STW A14,*+A6(76) ; Save A14
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STW A15,*+A6(80) ; Save A15 (FP)
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STW B10,*+A6(124) ; Save B10
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ADDK 128,A6 ; Move stack pointer
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STW B11,*+A6(0) ; Save B11
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STW B12,*+A6(4) ; Save B12
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STW B13,*+A6(8) ; Save B13
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;
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; /* Save the remaining time-slice and disable it. */
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; if (_tx_timer_time_slice)
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; {
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;
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; _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice;
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; _tx_timer_time_slice = 0;
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;
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; }
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_tx_thread_dont_save_ts:
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;
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;
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; /* Clear the current task pointer. */
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; _tx_thread_current_ptr = TX_NULL;
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;
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; /* Return to the scheduler. */
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; _tx_thread_schedule();
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;
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B _tx_thread_schedule ; Return to scheduler
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STW B1,*+A1(24) ; Store current time-slice
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ZERO A3 ; Clear value
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STW A3,*A2 ; Set current thread pointer to NULL
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STW A3,*A5 ; Set time slice to 0
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NOP ; Delay
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;
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;
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_tx_thread_no_preempt_restore:
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;
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; /* Restore interrupted thread. */
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;
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; /* Pickup the saved stack pointer. */
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; SP = _tx_thread_current_ptr -> tx_thread_stack_ptr;
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;
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; /* Recover the saved context and return to the point of interrupt. */
|
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;
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||||
MV A6,SP ; Setup real stack pointer
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LDW *+SP(8),B0 ; Recover saved CSR
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||||
LDW *+SP(12),B1 ; Recover saved IRP
|
||||
LDW *+SP(16),B2 ; Recover saved AMR
|
||||
LDW *+SP(20),A0 ; Recover A0
|
||||
LDW *+SP(24),A1 ; Recover A1
|
||||
LDW *+SP(28),A2 ; Recover A2
|
||||
LDW *+SP(32),A3 ; Recover A3
|
||||
LDW *+SP(36),A4 ; Recover A4
|
||||
LDW *+SP(40),A5 ; Recover A5
|
||||
LDW *+SP(44),A6 ; Recover A6
|
||||
LDW *+SP(48),A7 ; Recover A7
|
||||
LDW *+SP(52),A8 ; Recover A8
|
||||
LDW *+SP(56),A9 ; Recover A9
|
||||
MVC B0,CSR ; Setup CSR
|
||||
MVC B1,IRP ; Setup IRP
|
||||
MVC B2,AMR ; Setup AMR
|
||||
LDW *+SP(268),B0 ; Recover saved ILC
|
||||
LDW *+SP(272),B1 ; Recover saved RILC
|
||||
LDW *+SP(276),B2 ; Recover saved ITSR
|
||||
NOP 4 ; Delay
|
||||
MVC B0,ILC ; Setup ILC
|
||||
MVC B1,RILC ; Setup RILC
|
||||
MVC B2,ITSR ; Setup ITSR
|
||||
LDW *+SP(84),B0 ; Recover B0
|
||||
LDW *+SP(88),B1 ; Recover B1
|
||||
LDW *+SP(92),B2 ; Recover B2
|
||||
LDW *+SP(100),B4 ; Recover B4
|
||||
LDW *+SP(104),B5 ; Recover B5
|
||||
LDW *+SP(108),B6 ; Recover B6
|
||||
LDW *+SP(112),B7 ; Recover B7
|
||||
LDW *+SP(116),B8 ; Recover B8
|
||||
LDW *+SP(140),A16 ; Recover A16
|
||||
LDW *+SP(144),A17 ; Recover A17
|
||||
LDW *+SP(148),A18 ; Recover A18
|
||||
LDW *+SP(152),A19 ; Recover A19
|
||||
LDW *+SP(156),A20 ; Recover A20
|
||||
LDW *+SP(160),A21 ; Recover A21
|
||||
LDW *+SP(164),A22 ; Recover A22
|
||||
LDW *+SP(168),A23 ; Recover A23
|
||||
LDW *+SP(172),A24 ; Recover A24
|
||||
LDW *+SP(176),A25 ; Recover A25
|
||||
LDW *+SP(180),A26 ; Recover A26
|
||||
LDW *+SP(184),A27 ; Recover A27
|
||||
LDW *+SP(188),A28 ; Recover A28
|
||||
LDW *+SP(192),A29 ; Recover A29
|
||||
LDW *+SP(196),A30 ; Recover A30
|
||||
LDW *+SP(200),A31 ; Recover A31
|
||||
LDW *+SP(204),B16 ; Recover B16
|
||||
LDW *+SP(208),B17 ; Recover B17
|
||||
LDW *+SP(212),B18 ; Recover B18
|
||||
LDW *+SP(216),B19 ; Recover B19
|
||||
LDW *+SP(220),B20 ; Recover B20
|
||||
LDW *+SP(224),B21 ; Recover B21
|
||||
LDW *+SP(228),B22 ; Recover B22
|
||||
LDW *+SP(232),B23 ; Recover B23
|
||||
LDW *+SP(236),B24 ; Recover B24
|
||||
LDW *+SP(240),B25 ; Recover B25
|
||||
LDW *+SP(244),B26 ; Recover B26
|
||||
LDW *+SP(248),B27 ; Recover B27
|
||||
LDW *+SP(252),B28 ; Recover B28
|
||||
LDW *+SP(256),B29 ; Recover B29
|
||||
LDW *+SP(260),B30 ; Recover B30
|
||||
LDW *+SP(264),B31 ; Recover B31
|
||||
B IRP ; Return to point of interrupt
|
||||
|| LDW *+SP(120),B9 ; Recover B9
|
||||
LDW *+SP(96),B3 ; Recover B3
|
||||
ADDK.S2 288,SP ; Recover stack space
|
||||
NOP 3 ; Delay slots
|
||||
;
|
||||
; }
|
||||
;}
|
||||
|
||||
274
ports/c667x/ccs/src/tx_thread_context_save.asm
Normal file
274
ports/c667x/ccs/src/tx_thread_context_save.asm
Normal file
@@ -0,0 +1,274 @@
|
||||
;/**************************************************************************/
|
||||
;/* */
|
||||
;/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
;/* */
|
||||
;/* This software is licensed under the Microsoft Software License */
|
||||
;/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
;/* and in the root directory of this software. */
|
||||
;/* */
|
||||
;/**************************************************************************/
|
||||
;
|
||||
;
|
||||
;/**************************************************************************/
|
||||
;/**************************************************************************/
|
||||
;/** */
|
||||
;/** ThreadX Component */
|
||||
;/** */
|
||||
;/** Thread */
|
||||
;/** */
|
||||
;/**************************************************************************/
|
||||
;/**************************************************************************/
|
||||
;
|
||||
;
|
||||
;#define TX_SOURCE_CODE
|
||||
;
|
||||
;
|
||||
;/* Include necessary system files. */
|
||||
;
|
||||
;#include "tx_api.h"
|
||||
;#include "tx_thread.h"
|
||||
;#include "tx_timer.h"
|
||||
;
|
||||
FP .set A15
|
||||
DP .set B14
|
||||
SP .set B15
|
||||
;
|
||||
.global _tx_thread_system_state
|
||||
.global _tx_thread_current_ptr
|
||||
.global _tx_thread_system_stack_ptr
|
||||
;
|
||||
;
|
||||
.sect ".text"
|
||||
;/**************************************************************************/
|
||||
;/* */
|
||||
;/* FUNCTION RELEASE */
|
||||
;/* */
|
||||
;/* _tx_thread_context_save C667x/TI */
|
||||
;/* 6.0 */
|
||||
;/* AUTHOR */
|
||||
;/* */
|
||||
;/* William E. Lamie, Microsoft Corporation */
|
||||
;/* */
|
||||
;/* DESCRIPTION */
|
||||
;/* */
|
||||
;/* This function saves the context of an executing thread in the */
|
||||
;/* beginning of interrupt processing. The function also ensures that */
|
||||
;/* the system stack is used upon return to the calling ISR. */
|
||||
;/* */
|
||||
;/* INPUT */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* OUTPUT */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* CALLS */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* CALLED BY */
|
||||
;/* */
|
||||
;/* ISRs */
|
||||
;/* */
|
||||
;/* RELEASE HISTORY */
|
||||
;/* */
|
||||
;/* DATE NAME DESCRIPTION */
|
||||
;/* */
|
||||
;/* 05-19-2020 William E. Lamie Initial Version 6.0 */
|
||||
;/* */
|
||||
;/**************************************************************************/
|
||||
;VOID _tx_thread_context_save(VOID)
|
||||
;{
|
||||
.global _tx_thread_context_save
|
||||
_tx_thread_context_save:
|
||||
;
|
||||
; /* Upon entry to this routine, it is assumed that all interrupts are locked
|
||||
; out, an initial stack frame of 288 bytes has been allocated and registers
|
||||
; A0, A1, A2, A3, A4, and B3 have been saved in the frame. Additionally,
|
||||
; it is assumed that register B3 contains the ISR's return address. */
|
||||
;
|
||||
; /* Check for a nested interrupt condition. */
|
||||
; if (_tx_thread_system_state++)
|
||||
; {
|
||||
;
|
||||
MVKL _tx_thread_system_state,A0 ; Build address of system state
|
||||
MVKH _tx_thread_system_state,A0 ;
|
||||
LDW *A0,A1 ; Pickup current system state
|
||||
STW A5,*+SP(40) ; Save A5
|
||||
STW A6,*+SP(44) ; Save A6
|
||||
STW A7,*+SP(48) ; Save A7
|
||||
STW A8,*+SP(52) ; Save A8
|
||||
[!A1] B _tx_thread_not_nested_save ; If 0, not a nested save condition
|
||||
MVKL _tx_thread_current_ptr,A3 ; Build address of current thread ptr
|
||||
MVKH _tx_thread_current_ptr,A3 ;
|
||||
LDW *A3,A2 ; Pickup current thread pointer
|
||||
ADD 1,A1,A1 ; Increment the system state (nested) counter
|
||||
STW A1,*A0 ; Store system state
|
||||
;
|
||||
; /* Nested interrupt condition. Save remaining scratch registers, and control registers
|
||||
; and return to calling ISR. */
|
||||
;
|
||||
STW A9,*+SP(56) ; Save A9
|
||||
STW B0,*+SP(84) ; Save B0
|
||||
STW B1,*+SP(88) ; Save B1
|
||||
STW B2,*+SP(92) ; Save B2
|
||||
; B3 is already saved!
|
||||
STW B4,*+SP(100) ; Save B4
|
||||
STW B5,*+SP(104) ; Save B5
|
||||
STW B6,*+SP(108) ; Save B6
|
||||
STW B7,*+SP(112) ; Save B7
|
||||
STW B8,*+SP(116) ; Save B8
|
||||
STW B9,*+SP(120) ; Save B9
|
||||
MVC CSR,B0 ; Pickup CSR
|
||||
B B3 ; Return to calling ISR
|
||||
MVC IRP,B1 ; Pickup IRP
|
||||
MVC AMR,B2 ; Pickup AMR
|
||||
STW B0,*+SP(8) ; Save CSR
|
||||
STW B1,*+SP(12) ; Save IRP
|
||||
STW B2,*+SP(16) ; Save AMR
|
||||
ZERO B0 ; Clear B0
|
||||
MVC B0,AMR ; Clear AMR for linear addressing in ISR
|
||||
STW A16,*+SP(140) ; Save A16
|
||||
STW A17,*+SP(144) ; Save A17
|
||||
STW A18,*+SP(148) ; Save A18
|
||||
STW A19,*+SP(152) ; Save A19
|
||||
STW A20,*+SP(156) ; Save A20
|
||||
STW A21,*+SP(160) ; Save A21
|
||||
STW A22,*+SP(164) ; Save A22
|
||||
STW A23,*+SP(168) ; Save A23
|
||||
STW A24,*+SP(172) ; Save A24
|
||||
STW A25,*+SP(176) ; Save A25
|
||||
STW A26,*+SP(180) ; Save A26
|
||||
STW A27,*+SP(184) ; Save A27
|
||||
STW A28,*+SP(188) ; Save A28
|
||||
STW A29,*+SP(192) ; Save A29
|
||||
STW A30,*+SP(196) ; Save A30
|
||||
STW A31,*+SP(200) ; Save A31
|
||||
STW B16,*+SP(204) ; Save B16
|
||||
STW B17,*+SP(208) ; Save B17
|
||||
STW B18,*+SP(212) ; Save B18
|
||||
STW B19,*+SP(216) ; Save B19
|
||||
STW B20,*+SP(220) ; Save B20
|
||||
STW B21,*+SP(224) ; Save B21
|
||||
STW B22,*+SP(228) ; Save B22
|
||||
STW B23,*+SP(232) ; Save B23
|
||||
STW B24,*+SP(236) ; Save B24
|
||||
STW B25,*+SP(240) ; Save B25
|
||||
STW B26,*+SP(244) ; Save B26
|
||||
STW B27,*+SP(248) ; Save B27
|
||||
STW B28,*+SP(252) ; Save B28
|
||||
STW B29,*+SP(256) ; Save B29
|
||||
STW B30,*+SP(260) ; Save B30
|
||||
STW B31,*+SP(264) ; Save B31
|
||||
MVC ILC,B0 ; Pickup ILC
|
||||
MVC RILC,B1 ; Pickup RILC
|
||||
MVC ITSR,B2 ; Pickup ITSR
|
||||
STW B0,*+SP(268) ; Save ILC
|
||||
STW B1,*+SP(272) ; Save RILC
|
||||
STW B2,*+SP(276) ; Save ITSR
|
||||
;
|
||||
_tx_thread_not_nested_save:
|
||||
; }
|
||||
;
|
||||
; /* Otherwise, not nested, check to see if a thread was running. */
|
||||
; else if (_tx_thread_current_ptr)
|
||||
; {
|
||||
;
|
||||
MVKL _tx_thread_system_stack_ptr,A0 ; Build address of system
|
||||
MVKH _tx_thread_system_stack_ptr,A0 ; stack pointer
|
||||
MV A2,A1 ; Transfer to A1 for B compare
|
||||
[!A1] B _tx_thread_idle_system_save ; If Null, idle system save
|
||||
STW A9,*+SP(56) ; Save A9
|
||||
STW B0,*+SP(84) ; Save B0
|
||||
STW B1,*+SP(88) ; Save B1
|
||||
STW B2,*+SP(92) ; Save B2
|
||||
NOP ; Delay slot
|
||||
;
|
||||
; /* At this point, a thread was interrupted and the remainder of its scratch and
|
||||
; control registers must be saved. */
|
||||
;
|
||||
; B3 was already saved!
|
||||
STW B4,*+SP(100) ; Save B4
|
||||
STW B5,*+SP(104) ; Save B5
|
||||
STW B6,*+SP(108) ; Save B6
|
||||
STW B7,*+SP(112) ; Save B7
|
||||
STW B8,*+SP(116) ; Save B8
|
||||
STW B9,*+SP(120) ; Save B9
|
||||
MVC CSR,B0 ; Pickup CSR
|
||||
MVC IRP,B1 ; Pickup IRP
|
||||
MVC AMR,B2 ; Pickup AMR
|
||||
STW B0,*+SP(8) ; Save CSR
|
||||
STW B1,*+SP(12) ; Save IRP
|
||||
STW B2,*+SP(16) ; Save AMR
|
||||
ZERO B0 ; Clear B0
|
||||
MVC B0,AMR ; Clear AMR for linear addressing in ISR
|
||||
STW A16,*+SP(140) ; Save A16
|
||||
STW A17,*+SP(144) ; Save A17
|
||||
STW A18,*+SP(148) ; Save A18
|
||||
STW A19,*+SP(152) ; Save A19
|
||||
STW A20,*+SP(156) ; Save A20
|
||||
STW A21,*+SP(160) ; Save A21
|
||||
STW A22,*+SP(164) ; Save A22
|
||||
STW A23,*+SP(168) ; Save A23
|
||||
STW A24,*+SP(172) ; Save A24
|
||||
STW A25,*+SP(176) ; Save A25
|
||||
STW A26,*+SP(180) ; Save A26
|
||||
STW A27,*+SP(184) ; Save A27
|
||||
STW A28,*+SP(188) ; Save A28
|
||||
STW A29,*+SP(192) ; Save A29
|
||||
STW A30,*+SP(196) ; Save A30
|
||||
STW A31,*+SP(200) ; Save A31
|
||||
STW B16,*+SP(204) ; Save B16
|
||||
STW B17,*+SP(208) ; Save B17
|
||||
STW B18,*+SP(212) ; Save B18
|
||||
STW B19,*+SP(216) ; Save B19
|
||||
STW B20,*+SP(220) ; Save B20
|
||||
STW B21,*+SP(224) ; Save B21
|
||||
STW B22,*+SP(228) ; Save B22
|
||||
STW B23,*+SP(232) ; Save B23
|
||||
STW B24,*+SP(236) ; Save B24
|
||||
STW B25,*+SP(240) ; Save B25
|
||||
STW B26,*+SP(244) ; Save B26
|
||||
STW B27,*+SP(248) ; Save B27
|
||||
STW B28,*+SP(252) ; Save B28
|
||||
STW B29,*+SP(256) ; Save B29
|
||||
STW B30,*+SP(260) ; Save B30
|
||||
STW B31,*+SP(264) ; Save B31
|
||||
MVC ILC,B0 ; Pickup ILC
|
||||
MVC RILC,B1 ; Pickup RILC
|
||||
MVC ITSR,B2 ; Pickup ITSR
|
||||
STW B0,*+SP(268) ; Save ILC
|
||||
STW B1,*+SP(272) ; Save RILC
|
||||
STW B2,*+SP(276) ; Save ITSR
|
||||
;
|
||||
; /* Save the current stack pointer in the thread's control block. */
|
||||
; _tx_thread_current_ptr -> tx_thread_stack_ptr = SP;
|
||||
;
|
||||
; /* Switch to the system stack. */
|
||||
; SP = _tx_thread_system_stack_ptr;
|
||||
;
|
||||
STW SP,*+A1(8) ; Save stack pointer
|
||||
B B3 ; Return to calling ISR
|
||||
LDW *A0,SP ; Switch to system stack
|
||||
NOP 4 ; Stack pointer is valid upon return!
|
||||
;
|
||||
; }
|
||||
; else
|
||||
; {
|
||||
;
|
||||
_tx_thread_idle_system_save:
|
||||
;
|
||||
; /* Interrupt occurred in the scheduling loop. */
|
||||
;
|
||||
; /* Not much to do here, just adjust the stack pointer, and return to ISR
|
||||
; processing. */
|
||||
;
|
||||
B B3 ; Return to ISR
|
||||
ADDK.S2 288,SP ; Recover stack space
|
||||
NOP 4 ; Delay slot
|
||||
;
|
||||
; }
|
||||
;}
|
||||
|
||||
95
ports/c667x/ccs/src/tx_thread_interrupt_control.asm
Normal file
95
ports/c667x/ccs/src/tx_thread_interrupt_control.asm
Normal file
@@ -0,0 +1,95 @@
|
||||
;/**************************************************************************/
|
||||
;/* */
|
||||
;/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
;/* */
|
||||
;/* This software is licensed under the Microsoft Software License */
|
||||
;/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
;/* and in the root directory of this software. */
|
||||
;/* */
|
||||
;/**************************************************************************/
|
||||
;
|
||||
;
|
||||
;/**************************************************************************/
|
||||
;/**************************************************************************/
|
||||
;/** */
|
||||
;/** ThreadX Component */
|
||||
;/** */
|
||||
;/** Thread */
|
||||
;/** */
|
||||
;/**************************************************************************/
|
||||
;/**************************************************************************/
|
||||
;
|
||||
;#define TX_SOURCE_CODE
|
||||
;
|
||||
;
|
||||
;/* Include necessary system files. */
|
||||
;
|
||||
;#include "tx_api.h"
|
||||
;#include "tx_thread.h"
|
||||
;
|
||||
;
|
||||
FP .set A15
|
||||
DP .set B14
|
||||
SP .set B15
|
||||
;
|
||||
;
|
||||
.sect ".text"
|
||||
;/**************************************************************************/
|
||||
;/* */
|
||||
;/* FUNCTION RELEASE */
|
||||
;/* */
|
||||
;/* _tx_thread_interrupt_control C667x/TI */
|
||||
;/* 6.0 */
|
||||
;/* AUTHOR */
|
||||
;/* */
|
||||
;/* William E. Lamie, Microsoft Corporation */
|
||||
;/* */
|
||||
;/* DESCRIPTION */
|
||||
;/* */
|
||||
;/* This function is responsible for changing the interrupt lockout */
|
||||
;/* posture of the system. */
|
||||
;/* */
|
||||
;/* INPUT */
|
||||
;/* */
|
||||
;/* new_posture New interrupt lockout posture */
|
||||
;/* */
|
||||
;/* OUTPUT */
|
||||
;/* */
|
||||
;/* old_posture Old interrupt lockout posture */
|
||||
;/* */
|
||||
;/* CALLS */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* CALLED BY */
|
||||
;/* */
|
||||
;/* Application Code */
|
||||
;/* */
|
||||
;/* RELEASE HISTORY */
|
||||
;/* */
|
||||
;/* DATE NAME DESCRIPTION */
|
||||
;/* */
|
||||
;/* 05-19-2020 William E. Lamie Initial Version 6.0 */
|
||||
;/* */
|
||||
;/**************************************************************************/
|
||||
;UINT _tx_thread_interrupt_control(UINT new_posture)
|
||||
;{
|
||||
.global _tx_thread_interrupt_control
|
||||
_tx_thread_interrupt_control:
|
||||
;
|
||||
; /* Pickup current interrupt lockout posture. */
|
||||
;
|
||||
MVC CSR,B0 ; Pickup current CSR
|
||||
;
|
||||
; /* Apply the new interrupt posture. */
|
||||
;
|
||||
B B3 ; Return to caller
|
||||
AND -2,B0,B0 ; Clear GIE bit
|
||||
OR A4,B0,B0 ; Build new interrupt posture
|
||||
MVC CSR,B1 ; Return previous posture
|
||||
MVC B0,CSR ; Apply new interrupt posture
|
||||
AND 1,B1,A4 ; Clear non-GIE bits
|
||||
;
|
||||
;}
|
||||
|
||||
254
ports/c667x/ccs/src/tx_thread_schedule.asm
Normal file
254
ports/c667x/ccs/src/tx_thread_schedule.asm
Normal file
@@ -0,0 +1,254 @@
|
||||
;/**************************************************************************/
|
||||
;/* */
|
||||
;/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
;/* */
|
||||
;/* This software is licensed under the Microsoft Software License */
|
||||
;/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
;/* and in the root directory of this software. */
|
||||
;/* */
|
||||
;/**************************************************************************/
|
||||
;
|
||||
;
|
||||
;/**************************************************************************/
|
||||
;/**************************************************************************/
|
||||
;/** */
|
||||
;/** ThreadX Component */
|
||||
;/** */
|
||||
;/** Thread */
|
||||
;/** */
|
||||
;/**************************************************************************/
|
||||
;/**************************************************************************/
|
||||
;
|
||||
;
|
||||
;#define TX_SOURCE_CODE
|
||||
;
|
||||
;
|
||||
;/* Include necessary system files. */
|
||||
;
|
||||
;#include "tx_api.h"
|
||||
;#include "tx_thread.h"
|
||||
;#include "tx_timer.h"
|
||||
;
|
||||
FP .set A15
|
||||
DP .set B14
|
||||
SP .set B15
|
||||
;
|
||||
;
|
||||
.global _tx_thread_execute_ptr
|
||||
.global _tx_thread_current_ptr
|
||||
.global _tx_timer_time_slice
|
||||
;
|
||||
;
|
||||
.sect ".text"
|
||||
;/**************************************************************************/
|
||||
;/* */
|
||||
;/* FUNCTION RELEASE */
|
||||
;/* */
|
||||
;/* _tx_thread_schedule C667x/TI */
|
||||
;/* 6.0 */
|
||||
;/* AUTHOR */
|
||||
;/* */
|
||||
;/* William E. Lamie, Microsoft Corporation */
|
||||
;/* */
|
||||
;/* DESCRIPTION */
|
||||
;/* */
|
||||
;/* This function waits for a thread control block pointer to appear in */
|
||||
;/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */
|
||||
;/* in the variable, the corresponding thread is resumed. */
|
||||
;/* */
|
||||
;/* INPUT */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* OUTPUT */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* CALLS */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* CALLED BY */
|
||||
;/* */
|
||||
;/* _tx_initialize_kernel_enter ThreadX entry function */
|
||||
;/* _tx_thread_system_return Return to system from thread */
|
||||
;/* _tx_thread_context_restore Restore thread's context */
|
||||
;/* */
|
||||
;/* RELEASE HISTORY */
|
||||
;/* */
|
||||
;/* DATE NAME DESCRIPTION */
|
||||
;/* */
|
||||
;/* 05-19-2020 William E. Lamie Initial Version 6.0 */
|
||||
;/* */
|
||||
;/**************************************************************************/
|
||||
;VOID _tx_thread_schedule(VOID)
|
||||
;{
|
||||
.global _tx_thread_schedule
|
||||
_tx_thread_schedule
|
||||
;
|
||||
; /* Enable interrupts. */
|
||||
;
|
||||
MVC CSR,B0 ; Pickup current CSR
|
||||
OR 1,B0,B0 ; Build interrupt enable value
|
||||
MVC B0,CSR ; Enable interrupts
|
||||
MVKL _tx_thread_execute_ptr,A0 ; Build address of execute pointer
|
||||
MVKH _tx_thread_execute_ptr,A0 ;
|
||||
;
|
||||
; /* Wait for a thread to execute. */
|
||||
; do
|
||||
; {
|
||||
;
|
||||
_tx_thread_schedule_loop:
|
||||
;
|
||||
LDW *A0,A1 ; Pickup next thread to execute
|
||||
NOP 4 ; Delay slots
|
||||
[!A1] B _tx_thread_schedule_loop ; If Null, just wait here for thread
|
||||
; to become ready
|
||||
MV A1,A4 ; Move thread pointer to A4
|
||||
MVKL _tx_thread_current_ptr,A1 ; Build address of current thread ptr
|
||||
MVKH _tx_thread_current_ptr,A1 ;
|
||||
MVKL _tx_timer_time_slice,A2 ; Build address of time-slice
|
||||
MVKH _tx_timer_time_slice,A2 ;
|
||||
;
|
||||
; }
|
||||
; while(_tx_thread_execute_ptr == TX_NULL);
|
||||
;
|
||||
; /* Yes! We have a thread to execute. Lockout interrupts and
|
||||
; transfer control to it. */
|
||||
;
|
||||
AND -2,B0,B0 ; Build interrupt lockout value
|
||||
MVC B0,CSR ; Lockout interrupts
|
||||
;
|
||||
; /* Setup the current thread pointer. */
|
||||
; _tx_thread_current_ptr = _tx_thread_execute_ptr;
|
||||
;
|
||||
LDW *+A4(4),A3 ; Pickup run-count
|
||||
LDW *+A4(8),SP ; Switch to thread's stack
|
||||
LDW *+A4(24),B1 ; Pickup time-slice
|
||||
STW A4,*A1 ; Setup current pointer
|
||||
NOP ; Delay
|
||||
;
|
||||
; /* Increment the run count for this thread. */
|
||||
; _tx_thread_current_ptr -> tx_thread_run_count++;
|
||||
;
|
||||
ADD 1,A3,A3 ; Increment run-counter
|
||||
LDW *+SP(4),B0 ; Pickup stack-type
|
||||
STW A3,*+A4(4) ; Store run-counter
|
||||
;
|
||||
; /* Setup time-slice, if present. */
|
||||
; _tx_timer_time_slice = _tx_thread_current_ptr -> tx_thread_time_slice;
|
||||
;
|
||||
STW B1,*A2 ; Setup time-slice
|
||||
;
|
||||
; /* Switch to the thread's stack. */
|
||||
; SP = _tx_thread_execute_ptr -> tx_thread_stack_ptr;
|
||||
;
|
||||
; /* Determine if an interrupt frame or a synchronous task suspension frame
|
||||
; is present. */
|
||||
;
|
||||
NOP 2 ; Delay slots
|
||||
[B0] B _tx_thread_interrupt_stack ; Look for interrupt stack frame
|
||||
LDW *+SP(8),B0 ; Pickup saved CSR
|
||||
LDW *+SP(12),B3 ; Pickup saved B3/IPR
|
||||
LDW *+SP(16),B1 ; Pickup saved AMR
|
||||
LDW *+SP(20),A10 ; Restore A10
|
||||
LDW *+SP(24),A11 ; Restore A11
|
||||
LDW *+SP(28),A12 ; Restore A12
|
||||
LDW *+SP(32),A13 ; Restore A13
|
||||
MVC B0,CSR ; Restore CSR
|
||||
MVC B1,AMR ; Restore AMR
|
||||
LDW *+SP(36),A14 ; Restore A14
|
||||
LDW *+SP(40),A15 ; Restore A15
|
||||
LDW *+SP(44),B10 ; Restore B10
|
||||
LDW *+SP(48),B11 ; Restore B11
|
||||
LDW *+SP(52),B12 ; Restore B12
|
||||
LDW *+SP(56),B13 ; Restore B13
|
||||
LDW *+SP(60),B0 ; Restore ILC
|
||||
LDW *+SP(64),B1 ; Restore RILC
|
||||
NOP 4 ; Delay slots
|
||||
MVC B0,ILC ; Restore ILC
|
||||
MVC B1,RILC ; Restore RILC
|
||||
B B3 ; Return to caller
|
||||
ADDK 64,SP ; Recover stack space
|
||||
NOP 4 ; Delay slots
|
||||
;
|
||||
_tx_thread_interrupt_stack:
|
||||
MVC B0,CSR ; Restore CSR
|
||||
MVC B3,IRP ; Restore IPR
|
||||
MVC B1,AMR ; Restore AMR
|
||||
LDW *+SP(268),B0 ; Recover saved ILC
|
||||
LDW *+SP(272),B1 ; Recover saved RILC
|
||||
LDW *+SP(276),B2 ; Recover saved ITSR
|
||||
NOP 4 ; Delay
|
||||
MVC B0,ILC ; Setup ILC
|
||||
MVC B1,RILC ; Setup RILC
|
||||
MVC B2,ITSR ; Setup ITSR
|
||||
LDW *+SP(20),A0 ; Recover A0
|
||||
LDW *+SP(24),A1 ; Recover A1
|
||||
LDW *+SP(28),A2 ; Recover A2
|
||||
LDW *+SP(32),A3 ; Recover A3
|
||||
LDW *+SP(36),A4 ; Recover A4
|
||||
LDW *+SP(40),A5 ; Recover A5
|
||||
LDW *+SP(44),A6 ; Recover A6
|
||||
LDW *+SP(48),A7 ; Recover A7
|
||||
LDW *+SP(52),A8 ; Recover A8
|
||||
LDW *+SP(56),A9 ; Recover A9
|
||||
LDW *+SP(60),A10 ; Recover A10
|
||||
LDW *+SP(64),A11 ; Recover A11
|
||||
LDW *+SP(68),A12 ; Recover A12
|
||||
LDW *+SP(72),A13 ; Recover A13
|
||||
LDW *+SP(76),A14 ; Recover A14
|
||||
LDW *+SP(80),A15 ; Recover A15 (FP)
|
||||
LDW *+SP(84),B0 ; Recover B0
|
||||
LDW *+SP(88),B1 ; Recover B1
|
||||
LDW *+SP(92),B2 ; Recover B2
|
||||
LDW *+SP(96),B3 ; Recover B3
|
||||
LDW *+SP(100),B4 ; Recover B4
|
||||
LDW *+SP(104),B5 ; Recover B5
|
||||
LDW *+SP(108),B6 ; Recover B6
|
||||
LDW *+SP(112),B7 ; Recover B7
|
||||
LDW *+SP(116),B8 ; Recover B8
|
||||
LDW *+SP(120),B9 ; Recover B9
|
||||
LDW *+SP(124),B10 ; Recover B10
|
||||
LDW *+SP(128),B11 ; Recover B11
|
||||
LDW *+SP(140),A16 ; Recover A16
|
||||
LDW *+SP(144),A17 ; Recover A17
|
||||
LDW *+SP(148),A18 ; Recover A18
|
||||
LDW *+SP(152),A19 ; Recover A19
|
||||
LDW *+SP(156),A20 ; Recover A20
|
||||
LDW *+SP(160),A21 ; Recover A21
|
||||
LDW *+SP(164),A22 ; Recover A22
|
||||
LDW *+SP(168),A23 ; Recover A23
|
||||
LDW *+SP(172),A24 ; Recover A24
|
||||
LDW *+SP(176),A25 ; Recover A25
|
||||
LDW *+SP(180),A26 ; Recover A26
|
||||
LDW *+SP(184),A27 ; Recover A27
|
||||
LDW *+SP(188),A28 ; Recover A28
|
||||
LDW *+SP(192),A29 ; Recover A29
|
||||
LDW *+SP(196),A30 ; Recover A30
|
||||
LDW *+SP(200),A31 ; Recover A31
|
||||
LDW *+SP(204),B16 ; Recover B16
|
||||
LDW *+SP(208),B17 ; Recover B17
|
||||
LDW *+SP(212),B18 ; Recover B18
|
||||
LDW *+SP(216),B19 ; Recover B19
|
||||
LDW *+SP(220),B20 ; Recover B20
|
||||
LDW *+SP(224),B21 ; Recover B21
|
||||
LDW *+SP(228),B22 ; Recover B22
|
||||
LDW *+SP(232),B23 ; Recover B23
|
||||
LDW *+SP(236),B24 ; Recover B24
|
||||
LDW *+SP(240),B25 ; Recover B25
|
||||
LDW *+SP(244),B26 ; Recover B26
|
||||
LDW *+SP(248),B27 ; Recover B27
|
||||
LDW *+SP(252),B28 ; Recover B28
|
||||
LDW *+SP(256),B29 ; Recover B29
|
||||
LDW *+SP(260),B30 ; Recover B30
|
||||
LDW *+SP(264),B31 ; Recover B31
|
||||
B IRP ; Return to point of interrupt
|
||||
|| LDW *+SP(132),B12 ; Recover B12
|
||||
LDW *+SP(136),B13 ; Recover B13
|
||||
ADDK.S2 288,SP ; Recover stack space
|
||||
NOP 3 ; Delay slots
|
||||
;
|
||||
;}
|
||||
|
||||
257
ports/c667x/ccs/src/tx_thread_stack_build.asm
Normal file
257
ports/c667x/ccs/src/tx_thread_stack_build.asm
Normal file
@@ -0,0 +1,257 @@
|
||||
;/**************************************************************************/
|
||||
;/* */
|
||||
;/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
;/* */
|
||||
;/* This software is licensed under the Microsoft Software License */
|
||||
;/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
;/* and in the root directory of this software. */
|
||||
;/* */
|
||||
;/**************************************************************************/
|
||||
;
|
||||
;
|
||||
;/**************************************************************************/
|
||||
;/**************************************************************************/
|
||||
;/** */
|
||||
;/** ThreadX Component */
|
||||
;/** */
|
||||
;/** Thread */
|
||||
;/** */
|
||||
;/**************************************************************************/
|
||||
;/**************************************************************************/
|
||||
;
|
||||
;
|
||||
;#define TX_SOURCE_CODE
|
||||
;
|
||||
;
|
||||
;/* Include necessary system files. */
|
||||
;
|
||||
;#include "tx_api.h"
|
||||
;#include "tx_thread.h"
|
||||
;
|
||||
FP .set A15
|
||||
DP .set B14
|
||||
SP .set B15
|
||||
ADDRESS_MSK .set 0xFFFFFFF0
|
||||
;
|
||||
.sect ".text"
|
||||
;/**************************************************************************/
|
||||
;/* */
|
||||
;/* FUNCTION RELEASE */
|
||||
;/* */
|
||||
;/* _tx_thread_stack_build C667x/TI */
|
||||
;/* 6.0 */
|
||||
;/* AUTHOR */
|
||||
;/* */
|
||||
;/* William E. Lamie, Microsoft Corporation */
|
||||
;/* */
|
||||
;/* DESCRIPTION */
|
||||
;/* */
|
||||
;/* This function builds a stack frame on the supplied thread's stack. */
|
||||
;/* The stack frame results in a fake interrupt return to the supplied */
|
||||
;/* function pointer. */
|
||||
;/* */
|
||||
;/* INPUT */
|
||||
;/* */
|
||||
;/* thread_ptr Pointer to thread control blk */
|
||||
;/* function_ptr Pointer to return function */
|
||||
;/* */
|
||||
;/* OUTPUT */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* CALLS */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* CALLED BY */
|
||||
;/* */
|
||||
;/* _tx_thread_create Create thread service */
|
||||
;/* */
|
||||
;/* RELEASE HISTORY */
|
||||
;/* */
|
||||
;/* DATE NAME DESCRIPTION */
|
||||
;/* */
|
||||
;/* 05-19-2020 William E. Lamie Initial Version 6.0 */
|
||||
;/* */
|
||||
;/**************************************************************************/
|
||||
;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID))
|
||||
;{
|
||||
.global _tx_thread_stack_build
|
||||
_tx_thread_stack_build:
|
||||
;
|
||||
;
|
||||
; /* Build a fake interrupt frame. The form of the fake interrupt stack
|
||||
; on the C667x should look like the following after it is built:
|
||||
;
|
||||
; Stack Top: N/A Available for use
|
||||
; 1 Interrupt stack frame type 4
|
||||
; CSR Initial value for CSR 8
|
||||
; IRP Initial thread entry 12
|
||||
; AMR Initial thread addressing mode 16
|
||||
; A0 Initial A0 20
|
||||
; A1 Initial A1 24
|
||||
; A2 Initial A2 28
|
||||
; A3 Initial A3 32
|
||||
; A4 Initial A4 36
|
||||
; A5 Initial A5 40
|
||||
; A6 Initial A6 44
|
||||
; A7 Initial A7 48
|
||||
; A8 Initial A8 52
|
||||
; A9 Initial A9 56
|
||||
; A10 Initial A10 60
|
||||
; A11 Initial A11 64
|
||||
; A12 Initial A12 68
|
||||
; A13 Initial A13 72
|
||||
; A14 Initial A14 76
|
||||
; A15 (FP) Initial A15 (FP) 80
|
||||
; B0 Initial B0 84
|
||||
; B1 Initial B1 88
|
||||
; B2 Initial B2 92
|
||||
; B3 Initial B3 96
|
||||
; B4 Initial B4 100
|
||||
; B5 Initial B5 104
|
||||
; B6 Initial B6 108
|
||||
; B7 Initial B7 112
|
||||
; B8 Initial B8 116
|
||||
; B9 Initial B9 120
|
||||
; B10 Initial B10 124
|
||||
; B11 Initial B11 128
|
||||
; B12 Initial B12 132
|
||||
; B13 Initial B13 136
|
||||
; A16 Initial A16 140
|
||||
; A17 Initial A17 144
|
||||
; A18 Initial A18 148
|
||||
; A19 Initial A19 152
|
||||
; A20 Initial A20 156
|
||||
; A21 Initial A21 160
|
||||
; A22 Initial A22 164
|
||||
; A23 Initial A23 168
|
||||
; A24 Initial A24 172
|
||||
; A25 Initial A25 176
|
||||
; A26 Initial A26 180
|
||||
; A27 Initial A27 184
|
||||
; A28 Initial A28 188
|
||||
; A29 Initial A29 192
|
||||
; A30 Initial A30 196
|
||||
; A31 Initial A31 200
|
||||
; B16 Initial B16 204
|
||||
; B17 Initial B17 208
|
||||
; B18 Initial B18 212
|
||||
; B19 Initial B19 216
|
||||
; B20 Initial B20 220
|
||||
; B21 Initial B21 224
|
||||
; B22 Initial B22 228
|
||||
; B23 Initial B23 232
|
||||
; B24 Initial B24 236
|
||||
; B25 Initial B25 240
|
||||
; B26 Initial B26 244
|
||||
; B27 Initial B27 248
|
||||
; B28 Initial B28 252
|
||||
; B29 Initial B29 256
|
||||
; B30 Initial B30 260
|
||||
; B31 Initial B31 264
|
||||
; ILC Initial ILC 268
|
||||
; RILC Initial RILC 272
|
||||
; ITSR Initial ITSR 276
|
||||
|
||||
|
||||
;
|
||||
; Stack Bottom: (higher memory address) */
|
||||
;
|
||||
LDW *+A4(16),A0 ; Pickup end of stack area
|
||||
MVKL ADDRESS_MSK,A1 ; Build address mask
|
||||
MVKH ADDRESS_MSK,A1 ;
|
||||
MVC CSR,B0 ; Pickup current CSR
|
||||
AND -2,B0,B0 ; Clear GIE bit
|
||||
OR 2,B0,B0 ; Set PGIE bit for interrupt return
|
||||
AND A1,A0,A0 ; Ensure alignment
|
||||
MVKL 288,A2 ; Calculate stack size
|
||||
SUB A0,A2,A0 ; Allocate space on thread's stack
|
||||
;
|
||||
; /* Actually build the stack frame. */
|
||||
;
|
||||
MVKL 1,A2 ; Build stack type
|
||||
ZERO A3 ; Clear value
|
||||
STW A2,*+A0(4) ; Interrupt stack type
|
||||
STW B0,*+A0(8) ; Initial CSR
|
||||
STW B4,*+A0(12) ; Thread shell entry point
|
||||
STW A3,*+A0(16) ; Initial AMR
|
||||
STW A3,*+A0(20) ; Initial A0
|
||||
STW A3,*+A0(24) ; Initial A1
|
||||
STW A3,*+A0(28) ; Initial A2
|
||||
STW A3,*+A0(32) ; Initial A3
|
||||
STW A3,*+A0(36) ; Initial A4
|
||||
STW A3,*+A0(40) ; Initial A5
|
||||
STW A3,*+A0(44) ; Initial A6
|
||||
STW A3,*+A0(48) ; Initial A7
|
||||
STW A3,*+A0(52) ; Initial A8
|
||||
STW A3,*+A0(56) ; Initial A9
|
||||
STW A3,*+A0(60) ; Initial A10
|
||||
STW A3,*+A0(64) ; Initial A11
|
||||
STW A3,*+A0(68) ; Initial A12
|
||||
STW A3,*+A0(72) ; Initial A13
|
||||
STW A3,*+A0(76) ; Initial A14
|
||||
STW A3,*+A0(80) ; Initial A15
|
||||
STW A3,*+A0(84) ; Initial B0
|
||||
STW A3,*+A0(88) ; Initial B1
|
||||
STW A3,*+A0(92) ; Initial B2
|
||||
STW A3,*+A0(96) ; Initial B3
|
||||
STW A3,*+A0(100) ; Initial B4
|
||||
STW A3,*+A0(104) ; Initial B5
|
||||
STW A3,*+A0(108) ; Initial B6
|
||||
STW A3,*+A0(112) ; Initial B7
|
||||
STW A3,*+A0(116) ; Initial B8
|
||||
STW A3,*+A0(120) ; Initial B9
|
||||
STW A3,*+A0(124) ; Initial B10
|
||||
MVKL 128,A2 ; Stack adjustment value
|
||||
ADD A2,A0,A2 ; Adjust pointer into stack frame
|
||||
STW A3,*+A2(0) ; Initial B11
|
||||
STW A3,*+A2(4) ; Initial B12
|
||||
STW A3,*+A2(8) ; Initial B13
|
||||
STW A3,*+A2(12) ; Initial A16
|
||||
STW A3,*+A2(16) ; Initial A17
|
||||
STW A3,*+A2(20) ; Initial A18
|
||||
STW A3,*+A2(24) ; Initial A19
|
||||
STW A3,*+A2(28) ; Initial A20
|
||||
STW A3,*+A2(32) ; Initial A21
|
||||
STW A3,*+A2(36) ; Initial A22
|
||||
STW A3,*+A2(40) ; Initial A23
|
||||
STW A3,*+A2(44) ; Initial A24
|
||||
STW A3,*+A2(48) ; Initial A25
|
||||
STW A3,*+A2(52) ; Initial A26
|
||||
STW A3,*+A2(56) ; Initial A27
|
||||
STW A3,*+A2(60) ; Initial A28
|
||||
STW A3,*+A2(64) ; Initial A29
|
||||
STW A3,*+A2(68) ; Initial A30
|
||||
STW A3,*+A2(72) ; Initial A31
|
||||
STW A3,*+A2(76) ; Initial B16
|
||||
STW A3,*+A2(80) ; Initial B17
|
||||
STW A3,*+A2(84) ; Initial B18
|
||||
STW A3,*+A2(88) ; Initial B19
|
||||
STW A3,*+A2(92) ; Initial B20
|
||||
STW A3,*+A2(96) ; Initial B21
|
||||
STW A3,*+A2(100) ; Initial B22
|
||||
STW A3,*+A2(104) ; Initial B23
|
||||
STW A3,*+A2(108) ; Initial B24
|
||||
STW A3,*+A2(112) ; Initial B25
|
||||
STW A3,*+A2(116) ; Initial B26
|
||||
STW A3,*+A2(120) ; Initial B27
|
||||
STW A3,*+A2(124) ; Initial B28
|
||||
ADDK 128,A2 ; Adjust stack pointer again
|
||||
STW A3,*+A2(0) ; Initial B29
|
||||
STW A3,*+A2(4) ; Initial B30
|
||||
STW A3,*+A2(8) ; Initial B31
|
||||
B B3 ; Return to caller
|
||||
STW A3,*+A2(12) ; Initial ILC
|
||||
STW A3,*+A2(16) ; Initial RILC
|
||||
MVKL 0x3,B0 ; Build initial ITSR (set GIE and SGIE bits)
|
||||
STW B0,*+A2(20) ; Store ITSR
|
||||
;
|
||||
; /* Setup stack pointer. */
|
||||
; thread_ptr -> tx_thread_stack_ptr = A0;
|
||||
;
|
||||
STW A0,*+A4(8) ; Save stack pointer in thread's
|
||||
; control block
|
||||
;}
|
||||
|
||||
162
ports/c667x/ccs/src/tx_thread_system_return.asm
Normal file
162
ports/c667x/ccs/src/tx_thread_system_return.asm
Normal file
@@ -0,0 +1,162 @@
|
||||
;/**************************************************************************/
|
||||
;/* */
|
||||
;/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
;/* */
|
||||
;/* This software is licensed under the Microsoft Software License */
|
||||
;/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
;/* and in the root directory of this software. */
|
||||
;/* */
|
||||
;/**************************************************************************/
|
||||
;
|
||||
;
|
||||
;/**************************************************************************/
|
||||
;/**************************************************************************/
|
||||
;/** */
|
||||
;/** ThreadX Component */
|
||||
;/** */
|
||||
;/** Thread */
|
||||
;/** */
|
||||
;/**************************************************************************/
|
||||
;/**************************************************************************/
|
||||
;
|
||||
;#define TX_SOURCE_CODE
|
||||
;
|
||||
;
|
||||
;/* Include necessary system files. */
|
||||
;
|
||||
;#include "tx_api.h"
|
||||
;#include "tx_thread.h"
|
||||
;#include "tx_timer.h"
|
||||
;
|
||||
FP .set A15
|
||||
DP .set B14
|
||||
SP .set B15
|
||||
;
|
||||
;
|
||||
.global _tx_thread_current_ptr
|
||||
.global _tx_timer_time_slice
|
||||
.global _tx_thread_schedule
|
||||
.global _tx_thread_system_stack_ptr
|
||||
;
|
||||
;
|
||||
.sect ".text"
|
||||
;/**************************************************************************/
|
||||
;/* */
|
||||
;/* FUNCTION RELEASE */
|
||||
;/* */
|
||||
;/* _tx_thread_system_return C667x/TI */
|
||||
;/* 6.0 */
|
||||
;/* AUTHOR */
|
||||
;/* */
|
||||
;/* William E. Lamie, Microsoft Corporation */
|
||||
;/* */
|
||||
;/* DESCRIPTION */
|
||||
;/* */
|
||||
;/* This function is target processor specific. It is used to transfer */
|
||||
;/* control from a thread back to the ThreadX system. Only a */
|
||||
;/* minimal context is saved since the compiler assumes temp registers */
|
||||
;/* are going to get slicked by a function call anyway. */
|
||||
;/* */
|
||||
;/* INPUT */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* OUTPUT */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* CALLS */
|
||||
;/* */
|
||||
;/* _tx_thread_schedule Thread scheduling loop */
|
||||
;/* */
|
||||
;/* CALLED BY */
|
||||
;/* */
|
||||
;/* ThreadX components */
|
||||
;/* */
|
||||
;/* RELEASE HISTORY */
|
||||
;/* */
|
||||
;/* DATE NAME DESCRIPTION */
|
||||
;/* */
|
||||
;/* 05-19-2020 William E. Lamie Initial Version 6.0 */
|
||||
;/* */
|
||||
;/**************************************************************************/
|
||||
;VOID _tx_thread_system_return(VOID)
|
||||
;{
|
||||
.global _tx_thread_system_return
|
||||
_tx_thread_system_return:
|
||||
;
|
||||
; /* Save minimal context on the stack. */
|
||||
;
|
||||
MVC CSR,B0 ; Pickup current CSR
|
||||
MVC AMR,B1 ; Pickup current AMR
|
||||
ADDK -64,SP ; Allocate stack space
|
||||
ZERO B2 ; Build solicited stack type
|
||||
STW B2,*+SP(4) ; Save stack type
|
||||
STW B0,*+SP(8) ; Save CSR
|
||||
STW B3,*+SP(12) ; Save B3 (return address)
|
||||
STW B1,*+SP(16) ; Save AMR
|
||||
STW A10,*+SP(20) ; Save A10
|
||||
STW A11,*+SP(24) ; Save A11
|
||||
STW A12,*+SP(28) ; Save A12
|
||||
STW A13,*+SP(32) ; Save A13
|
||||
STW A14,*+SP(36) ; Save A14
|
||||
STW A15,*+SP(40) ; Save A15
|
||||
STW B10,*+SP(44) ; Save B10
|
||||
STW B11,*+SP(48) ; Save B11
|
||||
STW B12,*+SP(52) ; Save B12
|
||||
STW B13,*+SP(56) ; Save B13
|
||||
MVC ILC,B0 ; Pickup ILC
|
||||
MVC RILC,B1 ; Pickup RILC
|
||||
STW B0,*+SP(60) ; Save ILC
|
||||
STW B1,*+SP(64) ; Save RILC
|
||||
;
|
||||
; /* Lockout interrupts. */
|
||||
;
|
||||
AND -2,B0,B0 ; Build interrupt disable value
|
||||
MVC B0,CSR ; Lockout interrupts
|
||||
;
|
||||
; /* Save current stack and switch to system stack. */
|
||||
; _tx_thread_current_ptr -> tx_thread_stack_ptr = sp;
|
||||
; SP = _tx_thread_system_stack_ptr;
|
||||
;
|
||||
MVKL _tx_timer_time_slice,A2 ; Pickup address of time slice
|
||||
MVKH _tx_timer_time_slice,A2 ;
|
||||
LDW *A2,B0 ; Pickup time slice
|
||||
MVKL _tx_thread_current_ptr,A1 ; Pickup address of current thread
|
||||
MVKH _tx_thread_current_ptr,A1 ;
|
||||
LDW *A1,A4 ; Pickup current thread pointer
|
||||
MVKL _tx_thread_system_stack_ptr,A3 ; Pickup address of system stack
|
||||
MVKH _tx_thread_system_stack_ptr,A3 ;
|
||||
;
|
||||
; /* Determine if the time-slice is active. */
|
||||
; if (_tx_timer_time_slice)
|
||||
; {
|
||||
;
|
||||
[!B0] B _tx_thread_dont_save_ts ; If no-time slice, skip save
|
||||
NOP ; Delay slot
|
||||
STW SP,*+A4(8) ; Save thread's stack pointer
|
||||
LDW *A3,SP ; Switch to system stack pointer
|
||||
NOP ; Delay slot
|
||||
;
|
||||
; /* Save time-slice for the thread and clear the current time-slice. */
|
||||
; _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice;
|
||||
; _tx_timer_time_slice = 0;
|
||||
NOP ;
|
||||
STW B2,*A2 ; Clear time-slice
|
||||
NOP 2 ; Delay slots
|
||||
STW B0,*+A4(24) ; Save time-slice
|
||||
;
|
||||
;
|
||||
; }
|
||||
_tx_thread_dont_save_ts
|
||||
;
|
||||
; /* Clear the current thread pointer. */
|
||||
; _tx_thread_current_ptr = TX_NULL;
|
||||
;
|
||||
B _tx_thread_schedule ; Return to scheduling loop
|
||||
STW B2,*A1 ; Set current thread to NULL
|
||||
NOP 4 ; Delay slots
|
||||
;
|
||||
;}
|
||||
|
||||
300
ports/c667x/ccs/src/tx_timer_interrupt.asm
Normal file
300
ports/c667x/ccs/src/tx_timer_interrupt.asm
Normal file
@@ -0,0 +1,300 @@
|
||||
;/**************************************************************************/
|
||||
;/* */
|
||||
;/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
;/* */
|
||||
;/* This software is licensed under the Microsoft Software License */
|
||||
;/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
;/* and in the root directory of this software. */
|
||||
;/* */
|
||||
;/**************************************************************************/
|
||||
;
|
||||
;
|
||||
;/**************************************************************************/
|
||||
;/**************************************************************************/
|
||||
;/** */
|
||||
;/** ThreadX Component */
|
||||
;/** */
|
||||
;/** Timer */
|
||||
;/** */
|
||||
;/**************************************************************************/
|
||||
;/**************************************************************************/
|
||||
;
|
||||
;#define TX_SOURCE_CODE
|
||||
;
|
||||
;
|
||||
;/* Include necessary system files. */
|
||||
;
|
||||
;#include "tx_api.h"
|
||||
;#include "tx_timer.h"
|
||||
;#include "tx_thread.h"
|
||||
;
|
||||
FP .set A15
|
||||
DP .set B14
|
||||
SP .set B15
|
||||
;
|
||||
;Define Assembly language external references...
|
||||
;
|
||||
.global _tx_timer_time_slice
|
||||
.global _tx_timer_system_clock
|
||||
.global _tx_timer_current_ptr
|
||||
.global _tx_timer_list_start
|
||||
.global _tx_timer_list_end
|
||||
.global _tx_timer_expired_time_slice
|
||||
.global _tx_timer_expired
|
||||
.global _tx_timer_expiration_process
|
||||
.global _tx_thread_time_slice
|
||||
.global _tx_thread_context_save
|
||||
.global _tx_thread_context_restore
|
||||
;
|
||||
;
|
||||
.sect ".text"
|
||||
;/**************************************************************************/
|
||||
;/* */
|
||||
;/* FUNCTION RELEASE */
|
||||
;/* */
|
||||
;/* _tx_timer_interrupt C667x/TI */
|
||||
;/* 6.0 */
|
||||
;/* AUTHOR */
|
||||
;/* */
|
||||
;/* William E. Lamie, Microsoft Corporation */
|
||||
;/* */
|
||||
;/* DESCRIPTION */
|
||||
;/* */
|
||||
;/* This function processes the hardware timer interrupt. This */
|
||||
;/* processing includes incrementing the system clock and checking for */
|
||||
;/* time slice and/or timer expiration. If either is found, the */
|
||||
;/* interrupt context save/restore functions are called along with the */
|
||||
;/* expiration functions. */
|
||||
;/* */
|
||||
;/* INPUT */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* OUTPUT */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* CALLS */
|
||||
;/* */
|
||||
;/* _tx_thread_context_save Context save */
|
||||
;/* _tx_thread_context_restore Context restore */
|
||||
;/* _tx_thread_time_slice Time slice interrupted thread */
|
||||
;/* _tx_timer_expiration_process Timer expiration processing */
|
||||
;/* */
|
||||
;/* CALLED BY */
|
||||
;/* */
|
||||
;/* interrupt vector */
|
||||
;/* */
|
||||
;/* RELEASE HISTORY */
|
||||
;/* */
|
||||
;/* DATE NAME DESCRIPTION */
|
||||
;/* */
|
||||
;/* 05-19-2020 William E. Lamie Initial Version 6.0 */
|
||||
;/* */
|
||||
;/**************************************************************************/
|
||||
;VOID _tx_timer_interrupt(VOID)
|
||||
;{
|
||||
.global _tx_timer_interrupt
|
||||
_tx_timer_interrupt:
|
||||
;
|
||||
; /* Upon entry to this routine, it is assumed that registers B3, A0-A4 have
|
||||
; already been saved and the space for saving additional registers has
|
||||
; already been reserved. In addition, interrupts are locked out and must
|
||||
; remain so until context save returns. */
|
||||
;
|
||||
; /* Increment the system clock. */
|
||||
; _tx_timer_system_clock++;
|
||||
;
|
||||
MVKL _tx_timer_system_clock,A0 ; Build address of system clock
|
||||
MVKH _tx_timer_system_clock,A0 ;
|
||||
LDW *A0,A2 ; Pickup system clock
|
||||
MVKL _tx_timer_time_slice,A3 ; Build address of time slice
|
||||
MVKH _tx_timer_time_slice,A3 ;
|
||||
LDW *A3,A1 ; Pickup time slice
|
||||
NOP 2 ; Delay
|
||||
ADD 1,A2,A2 ; Increment the system clock
|
||||
STW A2,*A0 ; Store it back in memory
|
||||
;
|
||||
; /* Test for time-slice expiration. */
|
||||
; if (_tx_timer_time_slice)
|
||||
; {
|
||||
;
|
||||
[!A1] B _tx_timer_no_time_slice ; If 0, skip time slice processing
|
||||
SUB A1,1,A1 ; Decrement time-slice value
|
||||
NOP 4 ; Delay slots
|
||||
;
|
||||
; /* Decrement the time_slice. */
|
||||
; _tx_timer_time_slice--;
|
||||
;
|
||||
; /* Check for expiration. */
|
||||
; if (_tx_timer_time_slice == 0)
|
||||
;
|
||||
[A1] B _tx_timer_no_time_slice ; If non-zero, not expired yet
|
||||
STW A1,*A3 ; Store new time-slice
|
||||
MVKL _tx_timer_expired_time_slice,A0 ; Build address of expired flag
|
||||
MVKH _tx_timer_expired_time_slice,A0 ;
|
||||
MVKL 1,A4 ; Expired flag
|
||||
NOP ; Delay
|
||||
;
|
||||
; /* Set the time-slice expired flag. */
|
||||
; _tx_timer_expired_time_slice = TX_TRUE;
|
||||
;
|
||||
STW A4,*A0 ; Set expired flag
|
||||
; }
|
||||
;
|
||||
_tx_timer_no_time_slice:
|
||||
;
|
||||
; /* Test for timer expiration. */
|
||||
; if (*_tx_timer_current_ptr)
|
||||
; {
|
||||
;
|
||||
MVKL _tx_timer_current_ptr,A2 ; Build address of current timer pointer
|
||||
MVKH _tx_timer_current_ptr,A2 ;
|
||||
LDW *A2,A0 ; Pickup timer list address
|
||||
MVKL _tx_timer_expired,A3 ; Build address of expired flag
|
||||
MVKH _tx_timer_expired,A3 ;
|
||||
NOP 2 ; Delay slots
|
||||
LDW *A0,A1 ; Pickup current timer entry
|
||||
ADD 4,A0,A0 ; Increment the current pointer
|
||||
NOP 3 ; Delay slots
|
||||
[A1] B _tx_timer_done ; If non-NULL, something has expired
|
||||
;
|
||||
;
|
||||
; /* Set expiration flag. */
|
||||
; _tx_timer_expired = TX_TRUE;
|
||||
;
|
||||
MVKL 1,A4 ; Build expired flag
|
||||
[A1] STW A4,*A3 ; Set expired flag
|
||||
NOP 3 ; Delay slots
|
||||
;
|
||||
; }
|
||||
; else
|
||||
; {
|
||||
_tx_timer_no_timer:
|
||||
;
|
||||
; /* No timer expired, increment the timer pointer. */
|
||||
; _tx_timer_current_ptr++;
|
||||
;
|
||||
; /* Check for wrap-around. */
|
||||
; if (_tx_timer_current_ptr == _tx_timer_list_end)
|
||||
;
|
||||
MVKL _tx_timer_list_end,A3 ; Build timer list end address
|
||||
MVKH _tx_timer_list_end,A3 ;
|
||||
LDW *A3,A4 ; Pickup list end address
|
||||
MVKL _tx_timer_list_start,A3 ; Build timer list start address
|
||||
MVKH _tx_timer_list_start,A3 ;
|
||||
NOP 2 ; Delay slots
|
||||
CMPEQ A4,A0,A1 ; Compare current pointer with end
|
||||
[A1] LDW *A3,A0 ; If at the end, pickup timer list start
|
||||
NOP 4 ; Delay slots
|
||||
;
|
||||
; /* Wrap to beginning of list. */
|
||||
; _tx_timer_current_ptr = _tx_timer_list_start;
|
||||
;
|
||||
_tx_timer_skip_wrap:
|
||||
;
|
||||
;
|
||||
STW A0,*A2 ; Store current timer pointer
|
||||
; }
|
||||
;
|
||||
_tx_timer_done:
|
||||
;
|
||||
;
|
||||
; /* See if anything has expired. */
|
||||
; if ((_tx_timer_expired_time_slice) || (_tx_timer_expired))
|
||||
; {
|
||||
;
|
||||
MVKL _tx_timer_expired_time_slice,A3 ; Build time-slice expired flag
|
||||
MVKH _tx_timer_expired_time_slice,A3 ;
|
||||
LDW *A3,A4 ; Pickup time-slice expired flag
|
||||
MVKL _tx_timer_expired,A0 ; Build timer expired flag
|
||||
MVKH _tx_timer_expired,A0 ;
|
||||
LDW *A0,A2 ; Pickup timer expired flag
|
||||
NOP 4 ; Delay slots
|
||||
OR A2,A4,A1 ; Combine expired flags
|
||||
[!A1] B _tx_timer_nothing_expired
|
||||
NOP 5 ; Delay slots
|
||||
;
|
||||
_tx_something_expired:
|
||||
;
|
||||
;
|
||||
; /* Something expired, call context save. */
|
||||
; _tx_thread_context_save();
|
||||
;
|
||||
B _tx_thread_context_save ; Call context save routine
|
||||
MVKL _tx_timer_ISR_return,B3 ; Build return address
|
||||
MVKH _tx_timer_ISR_return,B3 ;
|
||||
NOP 3 ; Delay slots
|
||||
_tx_timer_ISR_return:
|
||||
;
|
||||
; /* Did a timer expire? */
|
||||
; if (_tx_timer_expired)
|
||||
; {
|
||||
;
|
||||
MVKL _tx_timer_expired,A0 ; Build timer expired address
|
||||
MVKH _tx_timer_expired,A0 ;
|
||||
LDW *A0,A1 ; Pickup expired flag
|
||||
NOP 4 ; Delay slots
|
||||
[!A1] B _tx_timer_dont_activate ; If not set, skip timer activation
|
||||
NOP 5 ; Delay slots
|
||||
;
|
||||
; /* Process timer expiration. */
|
||||
; _tx_timer_expiration_process();
|
||||
;
|
||||
B _tx_timer_expiration_process ; Process timer expiration
|
||||
MVKL _tx_timer_ISR_return_1,B3 ; Build return address
|
||||
MVKH _tx_timer_ISR_return_1,B3 ;
|
||||
NOP 3 ; Delay slots
|
||||
_tx_timer_ISR_return_1:
|
||||
;
|
||||
; }
|
||||
_tx_timer_dont_activate:
|
||||
;
|
||||
; /* Did time slice expire? */
|
||||
; if (_tx_timer_expired_time_slice)
|
||||
; {
|
||||
;
|
||||
MVKL _tx_timer_expired_time_slice,A0 ; Build address of expired flag
|
||||
MVKH _tx_timer_expired_time_slice,A0 ;
|
||||
LDW *A0,A1 ; Pickup expired flag
|
||||
NOP 4 ; Delay slots
|
||||
[!A1] B _tx_timer_not_ts_expiration ; If not set, skip time-slice processing
|
||||
NOP 5 ; Delay slots
|
||||
;
|
||||
; /* Time slice interrupted thread. */
|
||||
; _tx_thread_time_slice();
|
||||
;
|
||||
B _tx_thread_time_slice ; Call time-slice processing
|
||||
MVKL _tx_timer_ISR_return_2,B3 ; Build return address
|
||||
MVKH _tx_timer_ISR_return_2,B3 ;
|
||||
NOP 3 ; Delay slots
|
||||
_tx_timer_ISR_return_2:
|
||||
;
|
||||
; }
|
||||
;
|
||||
_tx_timer_not_ts_expiration:
|
||||
;
|
||||
;
|
||||
; /* Call context restore. */
|
||||
; _tx_thread_context_restore();
|
||||
;
|
||||
B _tx_thread_context_restore ; Jump to context restore - no return!
|
||||
NOP 5 ; Delay slots
|
||||
;
|
||||
; }
|
||||
;
|
||||
_tx_timer_nothing_expired:
|
||||
;
|
||||
LDW *+SP(20),A0 ; Recover A0
|
||||
LDW *+SP(24),A1 ; Recover A1
|
||||
LDW *+SP(28),A2 ; Recover A2
|
||||
LDW *+SP(32),A3 ; Recover A3
|
||||
B IRP ; Return to point of interrupt
|
||||
|| LDW *+SP(36),A4 ; Recover A4
|
||||
LDW *+SP(96),B3 ; Recover B3
|
||||
ADDK.S2 288,SP ; Recover stack space
|
||||
NOP 3 ; Delay slots
|
||||
;
|
||||
;}
|
||||
|
||||
Reference in New Issue
Block a user