updated to 6.0.1 and added additional processors/toolchains
This commit is contained in:
tameraw
254
ports/c667x/ccs/src/tx_thread_schedule.asm
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254
ports/c667x/ccs/src/tx_thread_schedule.asm
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;/**************************************************************************/
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;/* */
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;/* Copyright (c) Microsoft Corporation. All rights reserved. */
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;/* */
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;/* This software is licensed under the Microsoft Software License */
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;/* Terms for Microsoft Azure RTOS. Full text of the license can be */
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;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
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;/* and in the root directory of this software. */
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;/* */
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;/**************************************************************************/
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;
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;
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;/**************************************************************************/
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;/**************************************************************************/
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;/** */
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;/** ThreadX Component */
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;/** */
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;/** Thread */
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;/** */
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;/**************************************************************************/
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;/**************************************************************************/
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;
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;
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;#define TX_SOURCE_CODE
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;
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;
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;/* Include necessary system files. */
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;
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;#include "tx_api.h"
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;#include "tx_thread.h"
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;#include "tx_timer.h"
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;
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FP .set A15
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DP .set B14
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SP .set B15
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;
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;
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.global _tx_thread_execute_ptr
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.global _tx_thread_current_ptr
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.global _tx_timer_time_slice
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;
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;
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.sect ".text"
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;/**************************************************************************/
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;/* */
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;/* FUNCTION RELEASE */
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;/* */
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;/* _tx_thread_schedule C667x/TI */
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;/* 6.0 */
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;/* AUTHOR */
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;/* */
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;/* William E. Lamie, Microsoft Corporation */
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;/* */
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;/* DESCRIPTION */
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;/* */
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;/* This function waits for a thread control block pointer to appear in */
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;/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */
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;/* in the variable, the corresponding thread is resumed. */
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;/* */
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;/* INPUT */
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;/* */
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;/* None */
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;/* */
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;/* OUTPUT */
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;/* */
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;/* None */
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;/* */
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;/* CALLS */
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;/* */
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;/* None */
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;/* */
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;/* CALLED BY */
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;/* */
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;/* _tx_initialize_kernel_enter ThreadX entry function */
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;/* _tx_thread_system_return Return to system from thread */
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;/* _tx_thread_context_restore Restore thread's context */
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;/* */
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;/* RELEASE HISTORY */
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;/* */
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;/* DATE NAME DESCRIPTION */
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;/* */
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;/* 05-19-2020 William E. Lamie Initial Version 6.0 */
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;/* */
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;/**************************************************************************/
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;VOID _tx_thread_schedule(VOID)
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;{
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.global _tx_thread_schedule
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_tx_thread_schedule
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;
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; /* Enable interrupts. */
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;
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MVC CSR,B0 ; Pickup current CSR
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OR 1,B0,B0 ; Build interrupt enable value
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MVC B0,CSR ; Enable interrupts
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MVKL _tx_thread_execute_ptr,A0 ; Build address of execute pointer
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MVKH _tx_thread_execute_ptr,A0 ;
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;
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; /* Wait for a thread to execute. */
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; do
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; {
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;
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_tx_thread_schedule_loop:
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;
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LDW *A0,A1 ; Pickup next thread to execute
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NOP 4 ; Delay slots
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[!A1] B _tx_thread_schedule_loop ; If Null, just wait here for thread
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; to become ready
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MV A1,A4 ; Move thread pointer to A4
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MVKL _tx_thread_current_ptr,A1 ; Build address of current thread ptr
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MVKH _tx_thread_current_ptr,A1 ;
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MVKL _tx_timer_time_slice,A2 ; Build address of time-slice
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MVKH _tx_timer_time_slice,A2 ;
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;
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; }
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; while(_tx_thread_execute_ptr == TX_NULL);
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;
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; /* Yes! We have a thread to execute. Lockout interrupts and
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; transfer control to it. */
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;
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AND -2,B0,B0 ; Build interrupt lockout value
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MVC B0,CSR ; Lockout interrupts
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;
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; /* Setup the current thread pointer. */
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; _tx_thread_current_ptr = _tx_thread_execute_ptr;
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;
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LDW *+A4(4),A3 ; Pickup run-count
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LDW *+A4(8),SP ; Switch to thread's stack
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LDW *+A4(24),B1 ; Pickup time-slice
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STW A4,*A1 ; Setup current pointer
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NOP ; Delay
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;
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; /* Increment the run count for this thread. */
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; _tx_thread_current_ptr -> tx_thread_run_count++;
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;
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ADD 1,A3,A3 ; Increment run-counter
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LDW *+SP(4),B0 ; Pickup stack-type
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STW A3,*+A4(4) ; Store run-counter
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;
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; /* Setup time-slice, if present. */
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; _tx_timer_time_slice = _tx_thread_current_ptr -> tx_thread_time_slice;
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;
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STW B1,*A2 ; Setup time-slice
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;
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; /* Switch to the thread's stack. */
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; SP = _tx_thread_execute_ptr -> tx_thread_stack_ptr;
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;
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; /* Determine if an interrupt frame or a synchronous task suspension frame
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; is present. */
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;
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NOP 2 ; Delay slots
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[B0] B _tx_thread_interrupt_stack ; Look for interrupt stack frame
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LDW *+SP(8),B0 ; Pickup saved CSR
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LDW *+SP(12),B3 ; Pickup saved B3/IPR
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LDW *+SP(16),B1 ; Pickup saved AMR
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LDW *+SP(20),A10 ; Restore A10
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LDW *+SP(24),A11 ; Restore A11
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LDW *+SP(28),A12 ; Restore A12
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LDW *+SP(32),A13 ; Restore A13
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MVC B0,CSR ; Restore CSR
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MVC B1,AMR ; Restore AMR
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LDW *+SP(36),A14 ; Restore A14
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LDW *+SP(40),A15 ; Restore A15
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LDW *+SP(44),B10 ; Restore B10
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LDW *+SP(48),B11 ; Restore B11
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LDW *+SP(52),B12 ; Restore B12
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LDW *+SP(56),B13 ; Restore B13
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LDW *+SP(60),B0 ; Restore ILC
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LDW *+SP(64),B1 ; Restore RILC
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NOP 4 ; Delay slots
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MVC B0,ILC ; Restore ILC
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MVC B1,RILC ; Restore RILC
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B B3 ; Return to caller
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ADDK 64,SP ; Recover stack space
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NOP 4 ; Delay slots
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;
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_tx_thread_interrupt_stack:
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MVC B0,CSR ; Restore CSR
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MVC B3,IRP ; Restore IPR
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MVC B1,AMR ; Restore AMR
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LDW *+SP(268),B0 ; Recover saved ILC
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LDW *+SP(272),B1 ; Recover saved RILC
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LDW *+SP(276),B2 ; Recover saved ITSR
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NOP 4 ; Delay
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MVC B0,ILC ; Setup ILC
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MVC B1,RILC ; Setup RILC
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MVC B2,ITSR ; Setup ITSR
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LDW *+SP(20),A0 ; Recover A0
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LDW *+SP(24),A1 ; Recover A1
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LDW *+SP(28),A2 ; Recover A2
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LDW *+SP(32),A3 ; Recover A3
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LDW *+SP(36),A4 ; Recover A4
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LDW *+SP(40),A5 ; Recover A5
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LDW *+SP(44),A6 ; Recover A6
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LDW *+SP(48),A7 ; Recover A7
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LDW *+SP(52),A8 ; Recover A8
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LDW *+SP(56),A9 ; Recover A9
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LDW *+SP(60),A10 ; Recover A10
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LDW *+SP(64),A11 ; Recover A11
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LDW *+SP(68),A12 ; Recover A12
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LDW *+SP(72),A13 ; Recover A13
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LDW *+SP(76),A14 ; Recover A14
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LDW *+SP(80),A15 ; Recover A15 (FP)
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LDW *+SP(84),B0 ; Recover B0
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LDW *+SP(88),B1 ; Recover B1
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LDW *+SP(92),B2 ; Recover B2
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LDW *+SP(96),B3 ; Recover B3
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LDW *+SP(100),B4 ; Recover B4
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LDW *+SP(104),B5 ; Recover B5
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LDW *+SP(108),B6 ; Recover B6
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LDW *+SP(112),B7 ; Recover B7
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LDW *+SP(116),B8 ; Recover B8
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LDW *+SP(120),B9 ; Recover B9
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LDW *+SP(124),B10 ; Recover B10
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LDW *+SP(128),B11 ; Recover B11
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LDW *+SP(140),A16 ; Recover A16
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LDW *+SP(144),A17 ; Recover A17
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LDW *+SP(148),A18 ; Recover A18
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LDW *+SP(152),A19 ; Recover A19
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LDW *+SP(156),A20 ; Recover A20
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LDW *+SP(160),A21 ; Recover A21
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LDW *+SP(164),A22 ; Recover A22
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LDW *+SP(168),A23 ; Recover A23
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LDW *+SP(172),A24 ; Recover A24
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LDW *+SP(176),A25 ; Recover A25
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LDW *+SP(180),A26 ; Recover A26
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LDW *+SP(184),A27 ; Recover A27
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LDW *+SP(188),A28 ; Recover A28
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LDW *+SP(192),A29 ; Recover A29
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LDW *+SP(196),A30 ; Recover A30
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LDW *+SP(200),A31 ; Recover A31
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LDW *+SP(204),B16 ; Recover B16
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LDW *+SP(208),B17 ; Recover B17
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LDW *+SP(212),B18 ; Recover B18
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LDW *+SP(216),B19 ; Recover B19
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LDW *+SP(220),B20 ; Recover B20
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LDW *+SP(224),B21 ; Recover B21
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LDW *+SP(228),B22 ; Recover B22
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LDW *+SP(232),B23 ; Recover B23
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LDW *+SP(236),B24 ; Recover B24
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LDW *+SP(240),B25 ; Recover B25
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LDW *+SP(244),B26 ; Recover B26
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LDW *+SP(248),B27 ; Recover B27
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LDW *+SP(252),B28 ; Recover B28
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LDW *+SP(256),B29 ; Recover B29
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LDW *+SP(260),B30 ; Recover B30
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LDW *+SP(264),B31 ; Recover B31
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B IRP ; Return to point of interrupt
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|| LDW *+SP(132),B12 ; Recover B12
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LDW *+SP(136),B13 ; Recover B13
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ADDK.S2 288,SP ; Recover stack space
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NOP 3 ; Delay slots
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;
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;}
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