updated to 6.0.1 and added additional processors/toolchains
This commit is contained in:
tameraw
257
ports/c667x/ccs/src/tx_thread_stack_build.asm
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257
ports/c667x/ccs/src/tx_thread_stack_build.asm
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;/**************************************************************************/
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;/* */
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;/* Copyright (c) Microsoft Corporation. All rights reserved. */
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;/* */
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;/* This software is licensed under the Microsoft Software License */
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;/* Terms for Microsoft Azure RTOS. Full text of the license can be */
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;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
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;/* and in the root directory of this software. */
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;/* */
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;/**************************************************************************/
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;
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;
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;/**************************************************************************/
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;/**************************************************************************/
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;/** */
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;/** ThreadX Component */
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;/** */
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;/** Thread */
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;/** */
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;/**************************************************************************/
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;/**************************************************************************/
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;
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;
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;#define TX_SOURCE_CODE
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;
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;
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;/* Include necessary system files. */
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;
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;#include "tx_api.h"
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;#include "tx_thread.h"
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;
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FP .set A15
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DP .set B14
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SP .set B15
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ADDRESS_MSK .set 0xFFFFFFF0
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;
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.sect ".text"
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;/**************************************************************************/
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;/* */
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;/* FUNCTION RELEASE */
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;/* */
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;/* _tx_thread_stack_build C667x/TI */
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;/* 6.0 */
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;/* AUTHOR */
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;/* */
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;/* William E. Lamie, Microsoft Corporation */
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;/* */
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;/* DESCRIPTION */
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;/* */
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;/* This function builds a stack frame on the supplied thread's stack. */
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;/* The stack frame results in a fake interrupt return to the supplied */
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;/* function pointer. */
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;/* */
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;/* INPUT */
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;/* */
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;/* thread_ptr Pointer to thread control blk */
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;/* function_ptr Pointer to return function */
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;/* */
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;/* OUTPUT */
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;/* */
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;/* None */
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;/* */
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;/* CALLS */
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;/* */
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;/* None */
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;/* */
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;/* CALLED BY */
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;/* */
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;/* _tx_thread_create Create thread service */
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;/* */
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;/* RELEASE HISTORY */
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;/* */
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;/* DATE NAME DESCRIPTION */
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;/* */
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;/* 05-19-2020 William E. Lamie Initial Version 6.0 */
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;/* */
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;/**************************************************************************/
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;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID))
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;{
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.global _tx_thread_stack_build
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_tx_thread_stack_build:
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;
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;
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; /* Build a fake interrupt frame. The form of the fake interrupt stack
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; on the C667x should look like the following after it is built:
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;
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; Stack Top: N/A Available for use
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; 1 Interrupt stack frame type 4
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; CSR Initial value for CSR 8
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; IRP Initial thread entry 12
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; AMR Initial thread addressing mode 16
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; A0 Initial A0 20
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; A1 Initial A1 24
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; A2 Initial A2 28
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; A3 Initial A3 32
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; A4 Initial A4 36
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; A5 Initial A5 40
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; A6 Initial A6 44
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; A7 Initial A7 48
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; A8 Initial A8 52
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; A9 Initial A9 56
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; A10 Initial A10 60
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; A11 Initial A11 64
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; A12 Initial A12 68
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; A13 Initial A13 72
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; A14 Initial A14 76
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; A15 (FP) Initial A15 (FP) 80
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; B0 Initial B0 84
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; B1 Initial B1 88
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; B2 Initial B2 92
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; B3 Initial B3 96
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; B4 Initial B4 100
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; B5 Initial B5 104
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; B6 Initial B6 108
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; B7 Initial B7 112
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; B8 Initial B8 116
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; B9 Initial B9 120
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; B10 Initial B10 124
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; B11 Initial B11 128
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; B12 Initial B12 132
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; B13 Initial B13 136
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; A16 Initial A16 140
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; A17 Initial A17 144
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; A18 Initial A18 148
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; A19 Initial A19 152
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; A20 Initial A20 156
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; A21 Initial A21 160
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; A22 Initial A22 164
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; A23 Initial A23 168
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; A24 Initial A24 172
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; A25 Initial A25 176
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; A26 Initial A26 180
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; A27 Initial A27 184
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; A28 Initial A28 188
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; A29 Initial A29 192
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; A30 Initial A30 196
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; A31 Initial A31 200
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; B16 Initial B16 204
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; B17 Initial B17 208
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; B18 Initial B18 212
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; B19 Initial B19 216
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; B20 Initial B20 220
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; B21 Initial B21 224
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; B22 Initial B22 228
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; B23 Initial B23 232
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; B24 Initial B24 236
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; B25 Initial B25 240
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; B26 Initial B26 244
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; B27 Initial B27 248
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; B28 Initial B28 252
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; B29 Initial B29 256
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; B30 Initial B30 260
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; B31 Initial B31 264
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; ILC Initial ILC 268
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; RILC Initial RILC 272
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; ITSR Initial ITSR 276
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;
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; Stack Bottom: (higher memory address) */
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;
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LDW *+A4(16),A0 ; Pickup end of stack area
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MVKL ADDRESS_MSK,A1 ; Build address mask
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MVKH ADDRESS_MSK,A1 ;
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MVC CSR,B0 ; Pickup current CSR
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AND -2,B0,B0 ; Clear GIE bit
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OR 2,B0,B0 ; Set PGIE bit for interrupt return
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AND A1,A0,A0 ; Ensure alignment
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MVKL 288,A2 ; Calculate stack size
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SUB A0,A2,A0 ; Allocate space on thread's stack
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;
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; /* Actually build the stack frame. */
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;
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MVKL 1,A2 ; Build stack type
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ZERO A3 ; Clear value
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STW A2,*+A0(4) ; Interrupt stack type
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STW B0,*+A0(8) ; Initial CSR
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STW B4,*+A0(12) ; Thread shell entry point
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STW A3,*+A0(16) ; Initial AMR
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STW A3,*+A0(20) ; Initial A0
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STW A3,*+A0(24) ; Initial A1
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STW A3,*+A0(28) ; Initial A2
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STW A3,*+A0(32) ; Initial A3
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STW A3,*+A0(36) ; Initial A4
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STW A3,*+A0(40) ; Initial A5
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STW A3,*+A0(44) ; Initial A6
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STW A3,*+A0(48) ; Initial A7
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STW A3,*+A0(52) ; Initial A8
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STW A3,*+A0(56) ; Initial A9
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STW A3,*+A0(60) ; Initial A10
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STW A3,*+A0(64) ; Initial A11
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STW A3,*+A0(68) ; Initial A12
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STW A3,*+A0(72) ; Initial A13
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STW A3,*+A0(76) ; Initial A14
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STW A3,*+A0(80) ; Initial A15
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STW A3,*+A0(84) ; Initial B0
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STW A3,*+A0(88) ; Initial B1
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STW A3,*+A0(92) ; Initial B2
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STW A3,*+A0(96) ; Initial B3
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STW A3,*+A0(100) ; Initial B4
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STW A3,*+A0(104) ; Initial B5
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STW A3,*+A0(108) ; Initial B6
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STW A3,*+A0(112) ; Initial B7
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STW A3,*+A0(116) ; Initial B8
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STW A3,*+A0(120) ; Initial B9
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STW A3,*+A0(124) ; Initial B10
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MVKL 128,A2 ; Stack adjustment value
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ADD A2,A0,A2 ; Adjust pointer into stack frame
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STW A3,*+A2(0) ; Initial B11
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STW A3,*+A2(4) ; Initial B12
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STW A3,*+A2(8) ; Initial B13
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STW A3,*+A2(12) ; Initial A16
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STW A3,*+A2(16) ; Initial A17
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STW A3,*+A2(20) ; Initial A18
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STW A3,*+A2(24) ; Initial A19
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STW A3,*+A2(28) ; Initial A20
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STW A3,*+A2(32) ; Initial A21
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STW A3,*+A2(36) ; Initial A22
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STW A3,*+A2(40) ; Initial A23
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STW A3,*+A2(44) ; Initial A24
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STW A3,*+A2(48) ; Initial A25
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STW A3,*+A2(52) ; Initial A26
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STW A3,*+A2(56) ; Initial A27
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STW A3,*+A2(60) ; Initial A28
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STW A3,*+A2(64) ; Initial A29
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STW A3,*+A2(68) ; Initial A30
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STW A3,*+A2(72) ; Initial A31
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STW A3,*+A2(76) ; Initial B16
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STW A3,*+A2(80) ; Initial B17
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STW A3,*+A2(84) ; Initial B18
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STW A3,*+A2(88) ; Initial B19
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STW A3,*+A2(92) ; Initial B20
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STW A3,*+A2(96) ; Initial B21
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STW A3,*+A2(100) ; Initial B22
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STW A3,*+A2(104) ; Initial B23
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STW A3,*+A2(108) ; Initial B24
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STW A3,*+A2(112) ; Initial B25
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STW A3,*+A2(116) ; Initial B26
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STW A3,*+A2(120) ; Initial B27
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STW A3,*+A2(124) ; Initial B28
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ADDK 128,A2 ; Adjust stack pointer again
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STW A3,*+A2(0) ; Initial B29
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STW A3,*+A2(4) ; Initial B30
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STW A3,*+A2(8) ; Initial B31
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B B3 ; Return to caller
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STW A3,*+A2(12) ; Initial ILC
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STW A3,*+A2(16) ; Initial RILC
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MVKL 0x3,B0 ; Build initial ITSR (set GIE and SGIE bits)
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STW B0,*+A2(20) ; Store ITSR
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;
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; /* Setup stack pointer. */
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; thread_ptr -> tx_thread_stack_ptr = A0;
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;
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STW A0,*+A4(8) ; Save stack pointer in thread's
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; control block
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;}
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