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updated to 6.0.1 and added additional processors/toolchains

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This commit is contained in:
tameraw
2020-07-16 14:32:40 -07:00
parent f8e91d4762
commit 2c35570dc9
1285 changed files with 550383 additions and 50 deletions
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230
ports/cortex_m0/ac5/example_build/build_threadx.bat Normal file
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del tx.a
armasm -g --cpu=cortex-m0 --apcs=interwork tx_initialize_low_level.s
armasm -g --cpu=cortex-m0 --apcs=interwork ../src/tx_thread_stack_build.s
armasm -g --cpu=cortex-m0 --apcs=interwork ../src/tx_thread_schedule.s
armasm -g --cpu=cortex-m0 --apcs=interwork ../src/tx_thread_system_return.s
armasm -g --cpu=cortex-m0 --apcs=interwork ../src/tx_thread_context_save.s
armasm -g --cpu=cortex-m0 --apcs=interwork ../src/tx_thread_context_restore.s
armasm -g --cpu=cortex-m0 --apcs=interwork ../src/tx_thread_interrupt_control.s
armasm -g --cpu=cortex-m0 --apcs=interwork ../src/tx_thread_interrupt_disable.s
armasm -g --cpu=cortex-m0 --apcs=interwork ../src/tx_thread_interrupt_restore.s
armasm -g --cpu=cortex-m0 --apcs=interwork ../src/tx_timer_interrupt.s
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_block_allocate.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_block_pool_cleanup.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_block_pool_create.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_block_pool_delete.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_block_pool_info_get.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_block_pool_initialize.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_block_pool_performance_info_get.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_block_pool_performance_system_info_get.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_block_pool_prioritize.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_block_release.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_byte_allocate.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_byte_pool_cleanup.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_byte_pool_create.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_byte_pool_delete.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_byte_pool_info_get.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_byte_pool_initialize.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_byte_pool_performance_info_get.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_byte_pool_performance_system_info_get.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_byte_pool_prioritize.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_byte_pool_search.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_byte_release.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_event_flags_cleanup.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_event_flags_create.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_event_flags_delete.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_event_flags_get.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_event_flags_info_get.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_event_flags_initialize.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_event_flags_performance_info_get.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_event_flags_performance_system_info_get.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_event_flags_set.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_event_flags_set_notify.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_initialize_high_level.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_initialize_kernel_enter.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_initialize_kernel_setup.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_mutex_cleanup.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_mutex_create.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_mutex_delete.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_mutex_get.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_mutex_info_get.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_mutex_initialize.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_mutex_performance_info_get.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_mutex_performance_system_info_get.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_mutex_prioritize.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_mutex_priority_change.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_mutex_put.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_queue_cleanup.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_queue_create.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_queue_delete.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_queue_flush.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_queue_front_send.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_queue_info_get.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_queue_initialize.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_queue_performance_info_get.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_queue_performance_system_info_get.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_queue_prioritize.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_queue_receive.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_queue_send.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_queue_send_notify.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_semaphore_ceiling_put.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_semaphore_cleanup.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_semaphore_create.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_semaphore_delete.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_semaphore_get.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_semaphore_info_get.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_semaphore_initialize.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_semaphore_performance_info_get.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_semaphore_performance_system_info_get.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_semaphore_prioritize.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_semaphore_put.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_semaphore_put_notify.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_create.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_delete.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_entry_exit_notify.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_identify.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_info_get.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_initialize.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_performance_info_get.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_performance_system_info_get.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_preemption_change.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_priority_change.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_relinquish.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_reset.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_resume.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_shell_entry.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_sleep.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_stack_analyze.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_stack_error_handler.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_stack_error_notify.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_suspend.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_system_preempt_check.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_system_resume.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_system_suspend.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_terminate.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_time_slice.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_time_slice_change.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_timeout.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_wait_abort.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_time_get.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_time_set.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_timer_activate.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_timer_change.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_timer_create.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_timer_deactivate.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_timer_delete.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_timer_expiration_process.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_timer_info_get.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_timer_initialize.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_timer_performance_info_get.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_timer_performance_system_info_get.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_timer_system_activate.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_timer_system_deactivate.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_timer_thread_entry.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_trace_buffer_full_notify.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_trace_enable.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_trace_event_filter.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_trace_event_unfilter.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_trace_disable.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_trace_initialize.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_trace_interrupt_control.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_trace_isr_enter_insert.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_trace_isr_exit_insert.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_trace_object_register.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_trace_object_unregister.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_trace_user_event_insert.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/txe_block_allocate.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/txe_block_pool_create.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/txe_block_pool_delete.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/txe_block_pool_info_get.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/txe_block_pool_prioritize.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/txe_block_release.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/txe_byte_allocate.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/txe_byte_pool_create.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/txe_byte_pool_delete.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/txe_byte_pool_info_get.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/txe_byte_pool_prioritize.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/txe_byte_release.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/txe_event_flags_create.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/txe_event_flags_delete.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/txe_event_flags_get.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/txe_event_flags_info_get.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/txe_event_flags_set.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/txe_event_flags_set_notify.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/txe_mutex_create.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/txe_mutex_delete.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/txe_mutex_get.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/txe_mutex_info_get.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/txe_mutex_prioritize.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/txe_mutex_put.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/txe_queue_create.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/txe_queue_delete.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/txe_queue_flush.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/txe_queue_front_send.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/txe_queue_info_get.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/txe_queue_prioritize.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/txe_queue_receive.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/txe_queue_send.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/txe_queue_send_notify.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/txe_semaphore_ceiling_put.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/txe_semaphore_create.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/txe_semaphore_delete.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/txe_semaphore_get.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/txe_semaphore_info_get.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/txe_semaphore_prioritize.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/txe_semaphore_put.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/txe_semaphore_put_notify.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/txe_thread_create.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/txe_thread_delete.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/txe_thread_entry_exit_notify.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/txe_thread_info_get.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/txe_thread_preemption_change.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/txe_thread_priority_change.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/txe_thread_relinquish.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/txe_thread_reset.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/txe_thread_resume.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/txe_thread_suspend.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/txe_thread_terminate.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/txe_thread_time_slice_change.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/txe_thread_wait_abort.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/txe_timer_activate.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/txe_timer_change.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/txe_timer_create.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/txe_timer_deactivate.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/txe_timer_delete.c
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/txe_timer_info_get.c
armar --create tx.a tx_thread_stack_build.o tx_thread_schedule.o tx_thread_system_return.o tx_thread_context_save.o tx_thread_context_restore.o tx_timer_interrupt.o tx_thread_interrupt_control.o
armar -r tx.a tx_initialize_low_level.o tx_thread_interrupt_disable.o tx_thread_interrupt_restore.o
armar -r tx.a tx_block_allocate.o tx_block_pool_cleanup.o tx_block_pool_create.o tx_block_pool_delete.o tx_block_pool_info_get.o
armar -r tx.a tx_block_pool_initialize.o tx_block_pool_performance_info_get.o tx_block_pool_performance_system_info_get.o tx_block_pool_prioritize.o
armar -r tx.a tx_block_release.o tx_byte_allocate.o tx_byte_pool_cleanup.o tx_byte_pool_create.o tx_byte_pool_delete.o tx_byte_pool_info_get.o
armar -r tx.a tx_byte_pool_initialize.o tx_byte_pool_performance_info_get.o tx_byte_pool_performance_system_info_get.o tx_byte_pool_prioritize.o
armar -r tx.a tx_byte_pool_search.o tx_byte_release.o tx_event_flags_cleanup.o tx_event_flags_create.o tx_event_flags_delete.o tx_event_flags_get.o
armar -r tx.a tx_event_flags_info_get.o tx_event_flags_initialize.o tx_event_flags_performance_info_get.o tx_event_flags_performance_system_info_get.o
armar -r tx.a tx_event_flags_set.o tx_event_flags_set_notify.o tx_initialize_high_level.o tx_initialize_kernel_enter.o tx_initialize_kernel_setup.o
armar -r tx.a tx_mutex_cleanup.o tx_mutex_create.o tx_mutex_delete.o tx_mutex_get.o tx_mutex_info_get.o tx_mutex_initialize.o tx_mutex_performance_info_get.o
armar -r tx.a tx_mutex_performance_system_info_get.o tx_mutex_prioritize.o tx_mutex_priority_change.o tx_mutex_put.o tx_queue_cleanup.o tx_queue_create.o
armar -r tx.a tx_queue_delete.o tx_queue_flush.o tx_queue_front_send.o tx_queue_info_get.o tx_queue_initialize.o tx_queue_performance_info_get.o
armar -r tx.a tx_queue_performance_system_info_get.o tx_queue_prioritize.o tx_queue_receive.o tx_queue_send.o tx_queue_send_notify.o tx_semaphore_ceiling_put.o
armar -r tx.a tx_semaphore_cleanup.o tx_semaphore_create.o tx_semaphore_delete.o tx_semaphore_get.o tx_semaphore_info_get.o tx_semaphore_initialize.o
armar -r tx.a tx_semaphore_performance_info_get.o tx_semaphore_performance_system_info_get.o tx_semaphore_prioritize.o tx_semaphore_put.o tx_semaphore_put_notify.o
armar -r tx.a tx_thread_create.o tx_thread_delete.o tx_thread_entry_exit_notify.o tx_thread_identify.o tx_thread_info_get.o tx_thread_initialize.o
armar -r tx.a tx_thread_performance_info_get.o tx_thread_performance_system_info_get.o tx_thread_preemption_change.o tx_thread_priority_change.o tx_thread_relinquish.o
armar -r tx.a tx_thread_reset.o tx_thread_resume.o tx_thread_shell_entry.o tx_thread_sleep.o tx_thread_stack_analyze.o tx_thread_stack_error_handler.o
armar -r tx.a tx_thread_stack_error_notify.o tx_thread_suspend.o tx_thread_system_preempt_check.o tx_thread_system_resume.o tx_thread_system_suspend.o
armar -r tx.a tx_thread_terminate.o tx_thread_time_slice.o tx_thread_time_slice_change.o tx_thread_timeout.o tx_thread_wait_abort.o tx_time_get.o
armar -r tx.a tx_time_set.o tx_timer_activate.o tx_timer_change.o tx_timer_create.o tx_timer_deactivate.o tx_timer_delete.o tx_timer_expiration_process.o
armar -r tx.a tx_timer_info_get.o tx_timer_initialize.o tx_timer_performance_info_get.o tx_timer_performance_system_info_get.o tx_timer_system_activate.o
armar -r tx.a tx_timer_system_deactivate.o tx_timer_thread_entry.o tx_trace_enable.o tx_trace_disable.o tx_trace_initialize.o tx_trace_interrupt_control.o
armar -r tx.a tx_trace_isr_enter_insert.o tx_trace_isr_exit_insert.o tx_trace_object_register.o tx_trace_object_unregister.o tx_trace_user_event_insert.o
armar -r tx.a tx_trace_buffer_full_notify.o tx_trace_event_filter.o tx_trace_event_unfilter.o
armar -r tx.a txe_block_allocate.o txe_block_pool_create.o txe_block_pool_delete.o txe_block_pool_info_get.o txe_block_pool_prioritize.o txe_block_release.o
armar -r tx.a txe_byte_allocate.o txe_byte_pool_create.o txe_byte_pool_delete.o txe_byte_pool_info_get.o txe_byte_pool_prioritize.o txe_byte_release.o
armar -r tx.a txe_event_flags_create.o txe_event_flags_delete.o txe_event_flags_get.o txe_event_flags_info_get.o txe_event_flags_set.o
armar -r tx.a txe_event_flags_set_notify.o txe_mutex_create.o txe_mutex_delete.o txe_mutex_get.o txe_mutex_info_get.o txe_mutex_prioritize.o
armar -r tx.a txe_mutex_put.o txe_queue_create.o txe_queue_delete.o txe_queue_flush.o txe_queue_front_send.o txe_queue_info_get.o txe_queue_prioritize.o
armar -r tx.a txe_queue_receive.o txe_queue_send.o txe_queue_send_notify.o txe_semaphore_ceiling_put.o txe_semaphore_create.o txe_semaphore_delete.o
armar -r tx.a txe_semaphore_get.o txe_semaphore_info_get.o txe_semaphore_prioritize.o txe_semaphore_put.o txe_semaphore_put_notify.o txe_thread_create.o
armar -r tx.a txe_thread_delete.o txe_thread_entry_exit_notify.o txe_thread_info_get.o txe_thread_preemption_change.o txe_thread_priority_change.o
armar -r tx.a txe_thread_relinquish.o txe_thread_reset.o txe_thread_resume.o txe_thread_suspend.o txe_thread_terminate.o txe_thread_time_slice_change.o
armar -r tx.a txe_thread_wait_abort.o txe_timer_activate.o txe_timer_change.o txe_timer_create.o txe_timer_deactivate.o txe_timer_delete.o txe_timer_info_get.o

4
ports/cortex_m0/ac5/example_build/build_threadx_sample.bat Normal file
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armasm -g --cpu=cortex-m0 --apcs=interwork tx_initialize_low_level.s
armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc sample_threadx.c
armlink -d -o sample_threadx.axf --elf --map --ro-base=0x00000000 --rw-base=0x20000000 --first __tx_vectors --datacompressor=off --inline --info=inline --callgraph --list sample_threadx.map tx_initialize_low_level.o sample_threadx.o tx.a

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ports/cortex_m0/ac5/example_build/sample_threadx.c Normal file
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/* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight
threads of different priorities, using a message queue, semaphore, mutex, event flags group,
byte pool, and block pool. */
#include "tx_api.h"
#define DEMO_STACK_SIZE 1024
#define DEMO_BYTE_POOL_SIZE 9120
#define DEMO_BLOCK_POOL_SIZE 100
#define DEMO_QUEUE_SIZE 100
/* Define the ThreadX object control blocks... */
TX_THREAD thread_0;
TX_THREAD thread_1;
TX_THREAD thread_2;
TX_THREAD thread_3;
TX_THREAD thread_4;
TX_THREAD thread_5;
TX_THREAD thread_6;
TX_THREAD thread_7;
TX_QUEUE queue_0;
TX_SEMAPHORE semaphore_0;
TX_MUTEX mutex_0;
TX_EVENT_FLAGS_GROUP event_flags_0;
TX_BYTE_POOL byte_pool_0;
TX_BLOCK_POOL block_pool_0;
/* Define the counters used in the demo application... */
ULONG thread_0_counter;
ULONG thread_1_counter;
ULONG thread_1_messages_sent;
ULONG thread_2_counter;
ULONG thread_2_messages_received;
ULONG thread_3_counter;
ULONG thread_4_counter;
ULONG thread_5_counter;
ULONG thread_6_counter;
ULONG thread_7_counter;
/* Define thread prototypes. */
void thread_0_entry(ULONG thread_input);
void thread_1_entry(ULONG thread_input);
void thread_2_entry(ULONG thread_input);
void thread_3_and_4_entry(ULONG thread_input);
void thread_5_entry(ULONG thread_input);
void thread_6_and_7_entry(ULONG thread_input);
/* Define main entry point. */
int main()
{
/* Enter the ThreadX kernel. */
tx_kernel_enter();
}
/* Define what the initial system looks like. */
void tx_application_define(void *first_unused_memory)
{
CHAR *pointer = TX_NULL;
/* Create a byte memory pool from which to allocate the thread stacks. */
tx_byte_pool_create(&byte_pool_0, "byte pool 0", first_unused_memory, DEMO_BYTE_POOL_SIZE);
/* Put system definition stuff in here, e.g. thread creates and other assorted
create information. */
/* Allocate the stack for thread 0. */
tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
/* Create the main thread. */
tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0,
pointer, DEMO_STACK_SIZE,
1, 1, TX_NO_TIME_SLICE, TX_AUTO_START);
/* Allocate the stack for thread 1. */
tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
/* Create threads 1 and 2. These threads pass information through a ThreadX
message queue. It is also interesting to note that these threads have a time
slice. */
tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1,
pointer, DEMO_STACK_SIZE,
16, 16, 4, TX_AUTO_START);
/* Allocate the stack for thread 2. */
tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2,
pointer, DEMO_STACK_SIZE,
16, 16, 4, TX_AUTO_START);
/* Allocate the stack for thread 3. */
tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
/* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore.
An interesting thing here is that both threads share the same instruction area. */
tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3,
pointer, DEMO_STACK_SIZE,
8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
/* Allocate the stack for thread 4. */
tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4,
pointer, DEMO_STACK_SIZE,
8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
/* Allocate the stack for thread 5. */
tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
/* Create thread 5. This thread simply pends on an event flag which will be set
by thread_0. */
tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5,
pointer, DEMO_STACK_SIZE,
4, 4, TX_NO_TIME_SLICE, TX_AUTO_START);
/* Allocate the stack for thread 6. */
tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
/* Create threads 6 and 7. These threads compete for a ThreadX mutex. */
tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6,
pointer, DEMO_STACK_SIZE,
8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
/* Allocate the stack for thread 7. */
tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7,
pointer, DEMO_STACK_SIZE,
8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
/* Allocate the message queue. */
tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT);
/* Create the message queue shared by threads 1 and 2. */
tx_queue_create(&queue_0, "queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG));
/* Create the semaphore used by threads 3 and 4. */
tx_semaphore_create(&semaphore_0, "semaphore 0", 1);
/* Create the event flags group used by threads 1 and 5. */
tx_event_flags_create(&event_flags_0, "event flags 0");
/* Create the mutex used by thread 6 and 7 without priority inheritance. */
tx_mutex_create(&mutex_0, "mutex 0", TX_NO_INHERIT);
/* Allocate the memory for a small block pool. */
tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT);
/* Create a block memory pool to allocate a message buffer from. */
tx_block_pool_create(&block_pool_0, "block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE);
/* Allocate a block and release the block memory. */
tx_block_allocate(&block_pool_0, (VOID **) &pointer, TX_NO_WAIT);
/* Release the block back to the pool. */
tx_block_release(pointer);
}
/* Define the test threads. */
void thread_0_entry(ULONG thread_input)
{
UINT status;
/* This thread simply sits in while-forever-sleep loop. */
while(1)
{
/* Increment the thread counter. */
thread_0_counter++;
/* Sleep for 10 ticks. */
tx_thread_sleep(10);
/* Set event flag 0 to wakeup thread 5. */
status = tx_event_flags_set(&event_flags_0, 0x1, TX_OR);
/* Check status. */
if (status != TX_SUCCESS)
break;
}
}
void thread_1_entry(ULONG thread_input)
{
UINT status;
/* This thread simply sends messages to a queue shared by thread 2. */
while(1)
{
/* Increment the thread counter. */
thread_1_counter++;
/* Send message to queue 0. */
status = tx_queue_send(&queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER);
/* Check completion status. */
if (status != TX_SUCCESS)
break;
/* Increment the message sent. */
thread_1_messages_sent++;
}
}
void thread_2_entry(ULONG thread_input)
{
ULONG received_message;
UINT status;
/* This thread retrieves messages placed on the queue by thread 1. */
while(1)
{
/* Increment the thread counter. */
thread_2_counter++;
/* Retrieve a message from the queue. */
status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER);
/* Check completion status and make sure the message is what we
expected. */
if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received))
break;
/* Otherwise, all is okay. Increment the received message count. */
thread_2_messages_received++;
}
}
void thread_3_and_4_entry(ULONG thread_input)
{
UINT status;
/* This function is executed from thread 3 and thread 4. As the loop
below shows, these function compete for ownership of semaphore_0. */
while(1)
{
/* Increment the thread counter. */
if (thread_input == 3)
thread_3_counter++;
else
thread_4_counter++;
/* Get the semaphore with suspension. */
status = tx_semaphore_get(&semaphore_0, TX_WAIT_FOREVER);
/* Check status. */
if (status != TX_SUCCESS)
break;
/* Sleep for 2 ticks to hold the semaphore. */
tx_thread_sleep(2);
/* Release the semaphore. */
status = tx_semaphore_put(&semaphore_0);
/* Check status. */
if (status != TX_SUCCESS)
break;
}
}
void thread_5_entry(ULONG thread_input)
{
UINT status;
ULONG actual_flags;
/* This thread simply waits for an event in a forever loop. */
while(1)
{
/* Increment the thread counter. */
thread_5_counter++;
/* Wait for event flag 0. */
status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR,
&actual_flags, TX_WAIT_FOREVER);
/* Check status. */
if ((status != TX_SUCCESS) || (actual_flags != 0x1))
break;
}
}
void thread_6_and_7_entry(ULONG thread_input)
{
UINT status;
/* This function is executed from thread 6 and thread 7. As the loop
below shows, these function compete for ownership of mutex_0. */
while(1)
{
/* Increment the thread counter. */
if (thread_input == 6)
thread_6_counter++;
else
thread_7_counter++;
/* Get the mutex with suspension. */
status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER);
/* Check status. */
if (status != TX_SUCCESS)
break;
/* Get the mutex again with suspension. This shows
that an owning thread may retrieve the mutex it
owns multiple times. */
status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER);
/* Check status. */
if (status != TX_SUCCESS)
break;
/* Sleep for 2 ticks to hold the mutex. */
tx_thread_sleep(2);
/* Release the mutex. */
status = tx_mutex_put(&mutex_0);
/* Check status. */
if (status != TX_SUCCESS)
break;
/* Release the mutex again. This will actually
release ownership since it was obtained twice. */
status = tx_mutex_put(&mutex_0);
/* Check status. */
if (status != TX_SUCCESS)
break;
}
}

284
ports/cortex_m0/ac5/example_build/tx_initialize_low_level.s Normal file
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;/**************************************************************************/
;/* */
;/* Copyright (c) Microsoft Corporation. All rights reserved. */
;/* */
;/* This software is licensed under the Microsoft Software License */
;/* Terms for Microsoft Azure RTOS. Full text of the license can be */
;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
;/* and in the root directory of this software. */
;/* */
;/**************************************************************************/
;
;
;/**************************************************************************/
;/**************************************************************************/
;/** */
;/** ThreadX Component */
;/** */
;/** Initialize */
;/** */
;/**************************************************************************/
;/**************************************************************************/
;
;#define TX_SOURCE_CODE
;
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_initialize.h"
;#include "tx_thread.h"
;#include "tx_timer.h"
;
;
IMPORT _tx_thread_system_stack_ptr
IMPORT _tx_initialize_unused_memory
IMPORT _tx_timer_interrupt
IMPORT __main
IMPORT |Image$$RO$$Limit|
IMPORT |Image$$RW$$Base|
IMPORT |Image$$ZI$$Base|
IMPORT |Image$$ZI$$Limit|
IMPORT __tx_PendSVHandler
;
;
SYSTEM_CLOCK EQU 6000000
SYSTICK_CYCLES EQU ((SYSTEM_CLOCK / 100) -1)
;
;
;/* Setup the stack and heap areas. */
;
STACK_SIZE EQU 0x00000400
HEAP_SIZE EQU 0x00000000
AREA STACK, NOINIT, READWRITE, ALIGN=3
StackMem
SPACE STACK_SIZE
__initial_sp
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
HeapMem
SPACE HEAP_SIZE
__heap_limit
AREA RESET, CODE, READONLY
;
EXPORT __tx_vectors
__tx_vectors
DCD __initial_sp ; Reset and system stack ptr
DCD Reset_Handler ; Reset goes to startup function
DCD __tx_NMIHandler ; NMI
DCD __tx_BadHandler ; HardFault
DCD 0 ; MemManage
DCD 0 ; BusFault
DCD 0 ; UsageFault
DCD 0 ; 7
DCD 0 ; 8
DCD 0 ; 9
DCD 0 ; 10
DCD __tx_SVCallHandler ; SVCall
DCD __tx_DBGHandler ; Monitor
DCD 0 ; 13
DCD __tx_PendSVHandler ; PendSV
DCD __tx_SysTickHandler ; SysTick
DCD __tx_IntHandler ; Int 0
DCD __tx_IntHandler ; Int 1
DCD __tx_IntHandler ; Int 2
DCD __tx_IntHandler ; Int 3
;
;
AREA ||.text||, CODE, READONLY
EXPORT Reset_Handler
Reset_Handler
CPSID i
LDR R0, =__main
BX R0
;/**************************************************************************/
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* _tx_initialize_low_level Cortex-M0/AC5 */
;/* 6.0.1 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
;/* */
;/* DESCRIPTION */
;/* */
;/* This function is responsible for any low-level processor */
;/* initialization, including setting up interrupt vectors, setting */
;/* up a periodic timer interrupt source, saving the system stack */
;/* pointer for use in ISR processing later, and finding the first */
;/* available RAM memory address for tx_application_define. */
;/* */
;/* INPUT */
;/* */
;/* None */
;/* */
;/* OUTPUT */
;/* */
;/* None */
;/* */
;/* CALLS */
;/* */
;/* None */
;/* */
;/* CALLED BY */
;/* */
;/* _tx_initialize_kernel_enter ThreadX entry function */
;/* */
;/* RELEASE HISTORY */
;/* */
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* */
;/**************************************************************************/
;VOID _tx_initialize_low_level(VOID)
;{
EXPORT _tx_initialize_low_level
_tx_initialize_low_level
;
; /* Ensure that interrupts are disabled. */
;
CPSID i ; Disable interrupts
;
; /* Set base of available memory to end of non-initialised RAM area. */
;
LDR r0, =_tx_initialize_unused_memory ; Build address of unused memory pointer
LDR r1, =|Image$$ZI$$Limit| ; Build first free address
ADDS r1, r1, #4 ;
STR r1, [r0] ; Setup first unused memory pointer
;
; /* Setup Vector Table Offset Register. */
;
LDR r0, =0xE000ED08 ; Build address of NVIC registers
LDR r1, =__tx_vectors ; Pickup address of vector table
STR r1, [r0] ; Set vector table address
;
; /* Enable the cycle count register. */
;
; LDR r0, =0xE0001000 ; Build address of DWT register
; LDR r1, [r0] ; Pickup the current value
; MOVS r2, #1
; ORRS r1, r1, r2 ; Set the CYCCNTENA bit
; STR r1, [r0] ; Enable the cycle count register
;
; /* Setup Vector Table Offset Register. */
;
LDR r0, =0xE000E000 ; Build address of NVIC registers
LDR r2, =0xD08 ; Offset to vector base register
ADD r0, r0, r2 ; Build vector base register
LDR r1, =__tx_vectors ; Pickup address of vector table
STR r1, [r0] ; Set vector table address
;
; /* Set system stack pointer from vector value. */
;
LDR r0, =_tx_thread_system_stack_ptr ; Build address of system stack pointer
LDR r1, =__tx_vectors ; Pickup address of vector table
LDR r1, [r1] ; Pickup reset stack pointer
STR r1, [r0] ; Save system stack pointer
;
; /* Configure SysTick. */
;
LDR r0, =0xE000E000 ; Build address of NVIC registers
LDR r1, =SYSTICK_CYCLES
STR r1, [r0, #0x14] ; Setup SysTick Reload Value
MOVS r1, #0x7 ; Build SysTick Control Enable Value
STR r1, [r0, #0x10] ; Setup SysTick Control
;
; /* Configure handler priorities. */
;
LDR r1, =0x00000000 ; Rsrv, UsgF, BusF, MemM
LDR r0, =0xE000E000 ; Build address of NVIC registers
LDR r2, =0xD18 ;
ADD r0, r0, r2 ;
STR r1, [r0] ; Setup System Handlers 4-7 Priority Registers
LDR r1, =0xFF000000 ; SVCl, Rsrv, Rsrv, Rsrv
LDR r0, =0xE000E000 ; Build address of NVIC registers
LDR r2, =0xD1C ;
ADD r0, r0, r2 ;
STR r1, [r0] ; Setup System Handlers 8-11 Priority Registers
; Note: SVC must be lowest priority, which is 0xFF
LDR r1, =0x40FF0000 ; SysT, PnSV, Rsrv, DbgM
LDR r0, =0xE000E000 ; Build address of NVIC registers
LDR r2, =0xD20 ;
ADD r0, r0, r2 ;
STR r1, [r0] ; Setup System Handlers 12-15 Priority Registers
; Note: PnSV must be lowest priority, which is 0xFF
;
; /* Return to caller. */
;
BX lr
;}
;
;
;/* Define initial heap/stack routine for the ARM RVCT startup code.
; This routine will set the initial stack and heap locations */
;
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, =HeapMem
LDR R1, =(StackMem + STACK_SIZE)
LDR R2, =(HeapMem + HEAP_SIZE)
LDR R3, =StackMem
BX LR
;
;
;/* Define shells for each of the unused vectors. */
;
EXPORT __tx_BadHandler
__tx_BadHandler
B __tx_BadHandler
EXPORT __tx_SVCallHandler
__tx_SVCallHandler
B __tx_SVCallHandler
EXPORT __tx_IntHandler
__tx_IntHandler
; VOID InterruptHandler (VOID)
; {
PUSH {r0, lr}
; /* Do interrupt handler work here */
; /* .... */
POP {r0, r1}
MOV lr, r1
BX lr
; }
EXPORT SysTick_Handler
EXPORT __tx_SysTickHandler
__tx_SysTickHandler
SysTick_Handler
; VOID TimerInterruptHandler (VOID)
; {
;
PUSH {r0, lr}
BL _tx_timer_interrupt
POP {r0, r1}
MOV lr, r1
BX lr
; }
EXPORT __tx_NMIHandler
__tx_NMIHandler
B __tx_NMIHandler
EXPORT __tx_DBGHandler
__tx_DBGHandler
B __tx_DBGHandler
ALIGN
LTORG
END

335
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/**************************************************************************/
/* */
/* Copyright (c) Microsoft Corporation. All rights reserved. */
/* */
/* This software is licensed under the Microsoft Software License */
/* Terms for Microsoft Azure RTOS. Full text of the license can be */
/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
/* and in the root directory of this software. */
/* */
/**************************************************************************/
/**************************************************************************/
/**************************************************************************/
/** */
/** ThreadX Component */
/** */
/** Port Specific */
/** */
/**************************************************************************/
/**************************************************************************/
/**************************************************************************/
/* */
/* PORT SPECIFIC C INFORMATION RELEASE */
/* */
/* tx_port.h Cortex-M0/AC5 */
/* 6.0.1 */
/* */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
/* */
/* DESCRIPTION */
/* */
/* This file contains data type definitions that make the ThreadX */
/* real-time kernel function identically on a variety of different */
/* processor architectures. For example, the size or number of bits */
/* in an "int" data type vary between microprocessor architectures and */
/* even C compilers for the same microprocessor. ThreadX does not */
/* directly use native C data types. Instead, ThreadX creates its */
/* own special types that can be mapped to actual data types by this */
/* file to guarantee consistency in the interface and functionality. */
/* */
/* RELEASE HISTORY */
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
/* */
/**************************************************************************/
#ifndef TX_PORT_H
#define TX_PORT_H
/* Determine if the optional ThreadX user define file should be used. */
#ifdef TX_INCLUDE_USER_DEFINE_FILE
/* Yes, include the user defines in tx_user.h. The defines in this file may
alternately be defined on the command line. */
#include "tx_user.h"
#endif
/* Define compiler library include files. */
#include <stdlib.h>
#include <string.h>
/* Define ThreadX basic types for this port. */
#define VOID void
typedef char CHAR;
typedef unsigned char UCHAR;
typedef int INT;
typedef unsigned int UINT;
typedef long LONG;
typedef unsigned long ULONG;
typedef short SHORT;
typedef unsigned short USHORT;
/* Define the priority levels for ThreadX. Legal values range
from 32 to 1024 and MUST be evenly divisible by 32. */
#ifndef TX_MAX_PRIORITIES
#define TX_MAX_PRIORITIES 32
#endif
/* Define the minimum stack for a ThreadX thread on this processor. If the size supplied during
thread creation is less than this value, the thread create call will return an error. */
#ifndef TX_MINIMUM_STACK
#define TX_MINIMUM_STACK 200 /* Minimum stack size for this port */
#endif
/* Define the system timer thread's default stack size and priority. These are only applicable
if TX_TIMER_PROCESS_IN_ISR is not defined. */
#ifndef TX_TIMER_THREAD_STACK_SIZE
#define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */
#endif
#ifndef TX_TIMER_THREAD_PRIORITY
#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */
#endif
/* Define various constants for the ThreadX Cortex-M0 port. */
#define TX_INT_DISABLE 1 /* Disable interrupts */
#define TX_INT_ENABLE 0 /* Enable interrupts */
/* Define the clock source for trace event entry time stamp. The following two item are port specific.
For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock
source constants would be:
#define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024)
#define TX_TRACE_TIME_MASK 0x0000FFFFUL
*/
#ifndef TX_MISRA_ENABLE
#ifndef TX_TRACE_TIME_SOURCE
#define TX_TRACE_TIME_SOURCE *((ULONG *) 0xE0001004)
#endif
#else
ULONG _tx_misra_time_stamp_get(VOID);
#define TX_TRACE_TIME_SOURCE _tx_misra_time_stamp_get()
#endif
#ifndef TX_TRACE_TIME_MASK
#define TX_TRACE_TIME_MASK 0xFFFFFFFFUL
#endif
/* Define the port specific options for the _tx_build_options variable. This variable indicates
how the ThreadX library was built. */
#define TX_PORT_SPECIFIC_BUILD_OPTIONS (0)
/* Define the in-line initialization constant so that modules with in-line
initialization capabilities can prevent their initialization from being
a function call. */
#ifdef TX_MISRA_ENABLE
#define TX_DISABLE_INLINE
#else
#define TX_INLINE_INITIALIZATION
#endif
/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is
disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack
checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING
define is negated, thereby forcing the stack fill which is necessary for the stack checking
logic. */
#ifndef TX_MISRA_ENABLE
#ifdef TX_ENABLE_STACK_CHECKING
#undef TX_DISABLE_STACK_FILLING
#endif
#endif
/* Define the TX_THREAD control block extensions for this port. The main reason
for the multiple macros is so that backward compatibility can be maintained with
existing ThreadX kernel awareness modules. */
#define TX_THREAD_EXTENSION_0
#define TX_THREAD_EXTENSION_1
#define TX_THREAD_EXTENSION_2
#define TX_THREAD_EXTENSION_3
/* Define the port extensions of the remaining ThreadX objects. */
#define TX_BLOCK_POOL_EXTENSION
#define TX_BYTE_POOL_EXTENSION
#define TX_EVENT_FLAGS_GROUP_EXTENSION
#define TX_MUTEX_EXTENSION
#define TX_QUEUE_EXTENSION
#define TX_SEMAPHORE_EXTENSION
#define TX_TIMER_EXTENSION
/* Define the user extension field of the thread control block. Nothing
additional is needed for this port so it is defined as white space. */
#ifndef TX_THREAD_USER_EXTENSION
#define TX_THREAD_USER_EXTENSION
#endif
/* Define the macros for processing extensions in tx_thread_create, tx_thread_delete,
tx_thread_shell_entry, and tx_thread_terminate. */
#define TX_THREAD_CREATE_EXTENSION(thread_ptr)
#define TX_THREAD_DELETE_EXTENSION(thread_ptr)
#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr)
#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr)
#ifndef TX_MISRA_ENABLE
register unsigned int _ipsr __asm("ipsr");
#endif
/* Define the ThreadX object creation extensions for the remaining objects. */
#define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr)
#define TX_BYTE_POOL_CREATE_EXTENSION(pool_ptr)
#define TX_EVENT_FLAGS_GROUP_CREATE_EXTENSION(group_ptr)
#define TX_MUTEX_CREATE_EXTENSION(mutex_ptr)
#define TX_QUEUE_CREATE_EXTENSION(queue_ptr)
#define TX_SEMAPHORE_CREATE_EXTENSION(semaphore_ptr)
#define TX_TIMER_CREATE_EXTENSION(timer_ptr)
/* Define the ThreadX object deletion extensions for the remaining objects. */
#define TX_BLOCK_POOL_DELETE_EXTENSION(pool_ptr)
#define TX_BYTE_POOL_DELETE_EXTENSION(pool_ptr)
#define TX_EVENT_FLAGS_GROUP_DELETE_EXTENSION(group_ptr)
#define TX_MUTEX_DELETE_EXTENSION(mutex_ptr)
#define TX_QUEUE_DELETE_EXTENSION(queue_ptr)
#define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr)
#define TX_TIMER_DELETE_EXTENSION(timer_ptr)
/* Define the get system state macro. */
#ifndef TX_THREAD_GET_SYSTEM_STATE
#ifndef TX_MISRA_ENABLE
#define TX_THREAD_GET_SYSTEM_STATE() (_tx_thread_system_state | _ipsr)
#else
ULONG _tx_misra_ipsr_get(VOID);
#define TX_THREAD_GET_SYSTEM_STATE() (_tx_thread_system_state | _tx_misra_ipsr_get())
#endif
#endif
/* Define the check for whether or not to call the _tx_thread_system_return function. A non-zero value
indicates that _tx_thread_system_return should not be called. This overrides the definition in tx_thread.h
for Cortex-M since so we don't waste time checking the _tx_thread_system_state variable that is always
zero after initialization for Cortex-M ports. */
#ifndef TX_THREAD_SYSTEM_RETURN_CHECK
#define TX_THREAD_SYSTEM_RETURN_CHECK(c) (c) = ((ULONG) _tx_thread_preempt_disable);
#endif
/* Define the macro to ensure _tx_thread_preempt_disable is set early in initialization in order to
prevent early scheduling on Cortex-M parts. */
#define TX_PORT_SPECIFIC_POST_INITIALIZATION _tx_thread_preempt_disable++;
/* Define ThreadX interrupt lockout and restore macros for protection on
access of critical kernel information. The restore interrupt macro must
restore the interrupt posture of the running thread prior to the value
present prior to the disable macro. In most cases, the save area macro
is used to define a local function save area for the disable and restore
macros. */
#ifdef TX_DISABLE_INLINE
UINT _tx_thread_interrupt_disable(VOID);
VOID _tx_thread_interrupt_restore(UINT previous_posture);
#define TX_INTERRUPT_SAVE_AREA register UINT interrupt_save;
#define TX_DISABLE interrupt_save = _tx_thread_interrupt_disable();
#define TX_RESTORE _tx_thread_interrupt_restore(interrupt_save);
#else
#define TX_INTERRUPT_SAVE_AREA unsigned int was_masked;
#define TX_DISABLE was_masked = __disable_irq();
#define TX_RESTORE if (was_masked == 0) __enable_irq();
#define _tx_thread_system_return _tx_thread_system_return_inline
static void _tx_thread_system_return_inline(void)
{
unsigned int was_masked;
/* Set PendSV to invoke ThreadX scheduler. */
*((ULONG *) 0xE000ED04) = ((ULONG) 0x10000000);
if (_ipsr == 0)
{
was_masked = __disable_irq();
__enable_irq();
if (was_masked != 0)
__disable_irq();
}
}
#endif
/* Define the version ID of ThreadX. This may be utilized by the application. */
#ifdef TX_THREAD_INIT
CHAR _tx_version_id[] =
"Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M0/AC5 Version 6.0 *";
#else
#ifdef TX_MISRA_ENABLE
extern CHAR _tx_version_id[100];
#else
extern CHAR _tx_version_id[];
#endif
#endif
#endif

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Microsoft's Azure RTOS ThreadX for Cortex-M0
Using ARM Compiler 5 (AC5)
1. Building the ThreadX run-time Library
First make sure you are in the "example_build" directory. Also, make sure that
you have setup your path and other environment variables necessary for the AC5
development environment. At this point you may run the build_threadx.bat batch
file. This will build the ThreadX run-time environment in the "example_build"
directory.
You should observe assembly and compilation of a series of ThreadX source
files. At the end of the batch file, they are all combined into the
run-time library file: tx.a. This file must be linked with your
application in order to use ThreadX.
2. Demonstration System
The ThreadX demonstration is designed to execute under the ARM
Windows-based simulator.
Building the demonstration is easy; simply execute the build_threadx_sample.bat
batch file while inside the "example_build" directory.
You should observe the compilation of sample_threadx.c (which is the demonstration
application) and linking with tx.a. The resulting file sample_threadx.axf
is a binary file that can be downloaded and executed on the ARM simulator.
3. System Initialization
The entry point in ThreadX for the Cortex-M0 using AC5 tools is at label
__main. This is defined within the AC5 compiler's startup code. In
addition, this is where all static and global pre-set C variable
initialization processing takes place.
The ThreadX tx_initialize_low_level.s file is responsible for setting up
various system data structures, the vector area, and a periodic timer interrupt
source.
In addition, _tx_initialize_low_level determines the first available
address for use by the application, which is supplied as the sole input
parameter to your application definition function, tx_application_define.
4. Register Usage and Stack Frames
The following defines the saved context stack frames for context switches
that occur as a result of interrupt handling or from thread-level API calls.
All suspended threads have the same stack frame in the Cortex-M0 version of
ThreadX. The top of the suspended thread's stack is pointed to by
tx_thread_stack_ptr in the associated thread control block TX_THREAD.
Stack Offset Stack Contents
0x00 r8
0x04 r9
0x08 r10
0x0C r11
0x10 r4
0x14 r5
0x18 r6
0x1C r7
0x20 r0 (Hardware stack starts here!!)
0x24 r1
0x28 r2
0x2C r3
0x30 r12
0x34 lr
0x38 pc
0x3C xPSR
5. Improving Performance
The distribution version of ThreadX is built without any compiler
optimizations. This makes it easy to debug because you can trace or set
breakpoints inside of ThreadX itself. Of course, this costs some
performance. To make it run faster, you can change the build_threadx.bat file to
remove the -g option and enable all compiler optimizations.
In addition, you can eliminate the ThreadX basic API error checking by
compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING
defined.
6. Interrupt Handling
ThreadX provides complete and high-performance interrupt handling for Cortex-M0
targets. There are a certain set of requirements that are defined in the
following sub-sections:
6.1 Vector Area
The Cortex-M0 vectors start at the label __tx_vectors. The application may modify
the vector area according to its needs.
6.2 Managed Interrupts
ISRs for Cortex-M can be written completely in C (or assembly language) without any
calls to _tx_thread_context_save or _tx_thread_context_restore. These ISRs are allowed
access to the ThreadX API that is available to ISRs.
ISRs written in C will take the form (where "your_C_isr" is an entry in the vector table):
void your_C_isr(void)
{
/* ISR processing goes here, including any needed function calls. */
}
ISRs written in assembly language will take the form:
EXPORT your_assembly_isr
your_assembly_isr
PUSH {r0, lr}
; ISR processing goes here, including any needed function calls.
POP {r0, r1}
MOV lr, r1
BX lr
7. Revision History
For generic code revision information, please refer to the readme_threadx_generic.txt
file, which is included in your distribution. The following details the revision
information associated with this specific port of ThreadX:
06/30/2020 Initial ThreadX 6.0.1 version for Cortex-M0 using AC5 tools.
Copyright(c) 1996-2020 Microsoft Corporation
https://azure.com/rtos

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;/**************************************************************************/
;/* */
;/* Copyright (c) Microsoft Corporation. All rights reserved. */
;/* */
;/* This software is licensed under the Microsoft Software License */
;/* Terms for Microsoft Azure RTOS. Full text of the license can be */
;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
;/* and in the root directory of this software. */
;/* */
;/**************************************************************************/
;
;
;/**************************************************************************/
;/**************************************************************************/
;/** */
;/** ThreadX Component */
;/** */
;/** Thread */
;/** */
;/**************************************************************************/
;/**************************************************************************/
;
;
;#define TX_SOURCE_CODE
;
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_thread.h"
;#include "tx_timer.h"
;
;
IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
IMPORT _tx_execution_isr_exit
ENDIF
;
AREA ||.text||, CODE, READONLY
PRESERVE8
;/**************************************************************************/
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_context_restore Cortex-M0/AC5 */
;/* 6.0.1 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
;/* */
;/* DESCRIPTION */
;/* */
;/* This function restores the interrupt context if it is processing a */
;/* nested interrupt. If not, it returns to the interrupt thread if no */
;/* preemption is necessary. Otherwise, if preemption is necessary or */
;/* if no thread was running, the function returns to the scheduler. */
;/* */
;/* INPUT */
;/* */
;/* None */
;/* */
;/* OUTPUT */
;/* */
;/* None */
;/* */
;/* CALLS */
;/* */
;/* _tx_thread_schedule Thread scheduling routine */
;/* */
;/* CALLED BY */
;/* */
;/* ISRs Interrupt Service Routines */
;/* */
;/* RELEASE HISTORY */
;/* */
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* */
;/**************************************************************************/
;VOID _tx_thread_context_restore(VOID)
;{
EXPORT _tx_thread_context_restore
_tx_thread_context_restore
IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
;
; /* Call the ISR exit function to indicate an ISR is complete. */
;
BL _tx_execution_isr_exit ; Call the ISR exit function
ENDIF
;
; /* Preemption has already been addressed - just return! */
;
POP {r0}
MOV lr, r0
BX lr
;}
ALIGN
LTORG
END

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;/**************************************************************************/
;/* */
;/* Copyright (c) Microsoft Corporation. All rights reserved. */
;/* */
;/* This software is licensed under the Microsoft Software License */
;/* Terms for Microsoft Azure RTOS. Full text of the license can be */
;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
;/* and in the root directory of this software. */
;/* */
;/**************************************************************************/
;
;
;/**************************************************************************/
;/**************************************************************************/
;/** */
;/** ThreadX Component */
;/** */
;/** Thread */
;/** */
;/**************************************************************************/
;/**************************************************************************/
;
;
;#define TX_SOURCE_CODE
;
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_thread.h"
;#include "tx_timer.h"
;
;
IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
IMPORT _tx_execution_isr_enter
ENDIF
;
;
AREA ||.text||, CODE, READONLY
PRESERVE8
;/**************************************************************************/
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_context_save Cortex-M0/AC5 */
;/* 6.0.1 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
;/* */
;/* DESCRIPTION */
;/* */
;/* This function saves the context of an executing thread in the */
;/* beginning of interrupt processing. The function also ensures that */
;/* the system stack is used upon return to the calling ISR. */
;/* */
;/* INPUT */
;/* */
;/* None */
;/* */
;/* OUTPUT */
;/* */
;/* None */
;/* */
;/* CALLS */
;/* */
;/* None */
;/* */
;/* CALLED BY */
;/* */
;/* ISRs */
;/* */
;/* RELEASE HISTORY */
;/* */
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* */
;/**************************************************************************/
;VOID _tx_thread_context_save(VOID)
;{
EXPORT _tx_thread_context_save
_tx_thread_context_save
IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
;
; /* Call the ISR enter function to indicate an ISR is executing. */
;
PUSH {r0, lr} ; Save ISR lr
BL _tx_execution_isr_enter ; Call the ISR enter function
POP {r0, r1} ; Recover ISR lr
MOV lr, r1
ENDIF
;
; /* Return to interrupt processing. */
;
BX lr ; Return to interrupt processing caller
;}
ALIGN
LTORG
END

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;/**************************************************************************/
;/* */
;/* Copyright (c) Microsoft Corporation. All rights reserved. */
;/* */
;/* This software is licensed under the Microsoft Software License */
;/* Terms for Microsoft Azure RTOS. Full text of the license can be */
;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
;/* and in the root directory of this software. */
;/* */
;/**************************************************************************/
;
;
;/**************************************************************************/
;/**************************************************************************/
;/** */
;/** ThreadX Component */
;/** */
;/** Thread */
;/** */
;/**************************************************************************/
;/**************************************************************************/
;
;#define TX_SOURCE_CODE
;
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_thread.h"
;
;
AREA ||.text||, CODE, READONLY
;/**************************************************************************/
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_interrupt_control Cortex-M0/AC5 */
;/* 6.0.1 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
;/* */
;/* DESCRIPTION */
;/* */
;/* This function is responsible for changing the interrupt lockout */
;/* posture of the system. */
;/* */
;/* INPUT */
;/* */
;/* new_posture New interrupt lockout posture */
;/* */
;/* OUTPUT */
;/* */
;/* old_posture Old interrupt lockout posture */
;/* */
;/* CALLS */
;/* */
;/* None */
;/* */
;/* CALLED BY */
;/* */
;/* Application Code */
;/* */
;/* RELEASE HISTORY */
;/* */
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* */
;/**************************************************************************/
;UINT _tx_thread_interrupt_control(UINT new_posture)
;{
EXPORT _tx_thread_interrupt_control
_tx_thread_interrupt_control
;
; /* Pickup current interrupt lockout posture. */
;
MRS r1, PRIMASK
MSR PRIMASK, r0
MOV r0, r1
BX lr
;
;}
ALIGN
LTORG
END

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;/**************************************************************************/
;/* */
;/* Copyright (c) Microsoft Corporation. All rights reserved. */
;/* */
;/* This software is licensed under the Microsoft Software License */
;/* Terms for Microsoft Azure RTOS. Full text of the license can be */
;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
;/* and in the root directory of this software. */
;/* */
;/**************************************************************************/
;
;
;/**************************************************************************/
;/**************************************************************************/
;/** */
;/** ThreadX Component */
;/** */
;/** Thread */
;/** */
;/**************************************************************************/
;/**************************************************************************/
;
;#define TX_SOURCE_CODE
;
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_thread.h"
;
;
AREA ||.text||, CODE, READONLY
;/**************************************************************************/
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_interrupt_disable Cortex-M0/AC5 */
;/* 6.0.1 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
;/* */
;/* DESCRIPTION */
;/* */
;/* This function is responsible for disabling interrupts and returning */
;/* the previous interrupt lockout posture. */
;/* */
;/* INPUT */
;/* */
;/* old_posture Old interrupt lockout posture */
;/* */
;/* OUTPUT */
;/* */
;/* None */
;/* */
;/* CALLS */
;/* */
;/* None */
;/* */
;/* CALLED BY */
;/* */
;/* Application Code */
;/* */
;/* RELEASE HISTORY */
;/* */
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* */
;/**************************************************************************/
;UINT _tx_thread_interrupt_disable(UINT new_posture)
;{
EXPORT _tx_thread_interrupt_disable
_tx_thread_interrupt_disable
;
; /* Return current interrupt lockout posture. */
;
MRS r0, PRIMASK
CPSID i
BX lr
;
;}
END

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;/**************************************************************************/
;/* */
;/* Copyright (c) Microsoft Corporation. All rights reserved. */
;/* */
;/* This software is licensed under the Microsoft Software License */
;/* Terms for Microsoft Azure RTOS. Full text of the license can be */
;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
;/* and in the root directory of this software. */
;/* */
;/**************************************************************************/
;
;
;/**************************************************************************/
;/**************************************************************************/
;/** */
;/** ThreadX Component */
;/** */
;/** Thread */
;/** */
;/**************************************************************************/
;/**************************************************************************/
;
;#define TX_SOURCE_CODE
;
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_thread.h"
;
;
AREA ||.text||, CODE, READONLY
;/**************************************************************************/
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_interrupt_restore Cortex-M0/AC5 */
;/* 6.0.1 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
;/* */
;/* DESCRIPTION */
;/* */
;/* This function is responsible for restoring the previous */
;/* interrupt lockout posture. */
;/* */
;/* INPUT */
;/* */
;/* None */
;/* */
;/* OUTPUT */
;/* */
;/* previous_posture Previous interrupt posture */
;/* */
;/* CALLS */
;/* */
;/* None */
;/* */
;/* CALLED BY */
;/* */
;/* Application Code */
;/* */
;/* RELEASE HISTORY */
;/* */
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* */
;/**************************************************************************/
;VOID _tx_thread_interrupt_restore(UINT new_posture)
;{
EXPORT _tx_thread_interrupt_restore
_tx_thread_interrupt_restore
;
; /* Restore previous interrupt lockout posture. */
;
MSR PRIMASK, r0
BX lr
;
;}
END

278
ports/cortex_m0/ac5/src/tx_thread_schedule.s Normal file
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;/**************************************************************************/
;/* */
;/* Copyright (c) Microsoft Corporation. All rights reserved. */
;/* */
;/* This software is licensed under the Microsoft Software License */
;/* Terms for Microsoft Azure RTOS. Full text of the license can be */
;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
;/* and in the root directory of this software. */
;/* */
;/**************************************************************************/
;
;
;/**************************************************************************/
;/**************************************************************************/
;/** */
;/** ThreadX Component */
;/** */
;/** Thread */
;/** */
;/**************************************************************************/
;/**************************************************************************/
;
;
;#define TX_SOURCE_CODE
;
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_thread.h"
;#include "tx_timer.h"
;
IMPORT _tx_thread_current_ptr
IMPORT _tx_thread_execute_ptr
IMPORT _tx_timer_time_slice
IMPORT _tx_thread_system_stack_ptr
IMPORT _tx_thread_preempt_disable
IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
IMPORT _tx_execution_thread_enter
IMPORT _tx_execution_thread_exit
ENDIF
;
;
AREA ||.text||, CODE, READONLY
PRESERVE8
;/**************************************************************************/
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_schedule Cortex-M0/AC5 */
;/* 6.0.1 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
;/* */
;/* DESCRIPTION */
;/* */
;/* This function waits for a thread control block pointer to appear in */
;/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */
;/* in the variable, the corresponding thread is resumed. */
;/* */
;/* INPUT */
;/* */
;/* None */
;/* */
;/* OUTPUT */
;/* */
;/* None */
;/* */
;/* CALLS */
;/* */
;/* None */
;/* */
;/* CALLED BY */
;/* */
;/* _tx_initialize_kernel_enter ThreadX entry function */
;/* _tx_thread_system_return Return to system from thread */
;/* _tx_thread_context_restore Restore thread's context */
;/* */
;/* RELEASE HISTORY */
;/* */
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* */
;/**************************************************************************/
;VOID _tx_thread_schedule(VOID)
;{
EXPORT _tx_thread_schedule
_tx_thread_schedule
;
; /* This function should only ever be called on Cortex-M0
; from the first schedule request. Subsequent scheduling occurs
; from the PendSV handling routines below. */
;
; /* Clear the preempt-disable flag to enable rescheduling after initialization on Cortex-M targets. */
;
MOVS r0, #0 ; Build value for TX_FALSE
LDR r2, =_tx_thread_preempt_disable ; Build address of preempt disable flag
STR r0, [r2, #0] ; Clear preempt disable flag
;
; /* Enable interrupts */
;
CPSIE i
;
; /* Enter the scheduler for the first time. */
;
LDR r0, =0x10000000 ; Load PENDSVSET bit
LDR r1, =0xE000ED04 ; Load ICSR address
STR r0, [r1] ; Set PENDSVBIT in ICSR
DSB ; Complete all memory accesses
ISB ; Flush pipeline
;
; /* Wait here for the PendSV to take place. */
;
__tx_wait_here
B __tx_wait_here ; Wait for the PendSV to happen
;}
;
; /* Generic context switch-out switch-in handler... Note that this handler is
; common for both PendSV and SVCall. */
;
EXPORT PendSV_Handler
EXPORT __tx_PendSVHandler
PendSV_Handler
__tx_PendSVHandler
;
; /* Get current thread value and new thread pointer. */
;
__tx_ts_handler
IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
;
; /* Call the thread exit function to indicate the thread is no longer executing. */
;
CPSID i ; Disable interrupts
PUSH {r0, lr} ; Save LR (and r0 just for alignment)
BL _tx_execution_thread_exit ; Call the thread exit function
POP {r0, r1} ; Recover LR
MOV lr, r1 ;
CPSIE i ; Enable interrupts
ENDIF
LDR r0, =_tx_thread_current_ptr ; Build current thread pointer address
LDR r2, =_tx_thread_execute_ptr ; Build execute thread pointer address
MOVS r3, #0 ; Build NULL value
LDR r1, [r0] ; Pickup current thread pointer
;
; /* Determine if there is a current thread to finish preserving. */
;
CMP r1,#0 ; If NULL, skip preservation
BEQ __tx_ts_new ;
;
; /* Recover PSP and preserve current thread context. */
;
STR r3, [r0] ; Set _tx_thread_current_ptr to NULL
MRS r3, PSP ; Pickup PSP pointer (thread's stack pointer)
SUBS r3, r3, #16 ; Allocate stack space
STM r3!, {r4-r7} ; Save its remaining registers (M3 Instruction: STMDB r12!, {r4-r11})
MOV r4,r8 ;
MOV r5,r9 ;
MOV r6,r10 ;
MOV r7,r11 ;
SUBS r3, r3, #32 ; Allocate stack space
STM r3!, {r4-r7} ;
SUBS r3, r3, #20 ; Allocate stack space
MOV r5, LR ;
STR r5, [r3] ; Save LR on the stack
STR r3, [r1, #8] ; Save its stack pointer
;
; /* Determine if time-slice is active. If it isn't, skip time handling processing. */
;
LDR r4, =_tx_timer_time_slice ; Build address of time-slice variable
LDR r5, [r4] ; Pickup current time-slice
CMP r5, #0 ; If not active, skip processing
BEQ __tx_ts_new ;
;
; /* Time-slice is active, save the current thread's time-slice and clear the global time-slice variable. */
;
STR r5, [r1, #24] ; Save current time-slice
;
; /* Clear the global time-slice. */
;
MOVS r5, #0 ; Build clear value
STR r5, [r4] ; Clear time-slice
;
;
; /* Executing thread is now completely preserved!!! */
;
__tx_ts_new
;
; /* Now we are looking for a new thread to execute! */
;
CPSID i ; Disable interrupts
LDR r1, [r2] ; Is there another thread ready to execute?
CMP r1, #0 ;
BEQ __tx_ts_wait ; No, skip to the wait processing
;
; /* Yes, another thread is ready for else, make the current thread the new thread. */
;
STR r1, [r0] ; Setup the current thread pointer to the new thread
CPSIE i ; Enable interrupts
;
; /* Increment the thread run count. */
;
__tx_ts_restore
LDR r7, [r1, #4] ; Pickup the current thread run count
LDR r4, =_tx_timer_time_slice ; Build address of time-slice variable
LDR r5, [r1, #24] ; Pickup thread's current time-slice
ADDS r7, r7, #1 ; Increment the thread run count
STR r7, [r1, #4] ; Store the new run count
;
; /* Setup global time-slice with thread's current time-slice. */
;
STR r5, [r4] ; Setup global time-slice
IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
;
; /* Call the thread entry function to indicate the thread is executing. */
;
PUSH {r0, r1} ; Save r0/r1
BL _tx_execution_thread_enter ; Call the thread execution enter function
POP {r0, r1} ; Recover r0/r1
ENDIF
;
; /* Restore the thread context and PSP. */
;
LDR r3, [r1, #8] ; Pickup thread's stack pointer
LDR r5, [r3] ; Recover saved LR
ADDS r3, r3, #4 ; Position past LR
MOV lr, r5 ; Restore LR
LDM r3!,{r4-r7} ; Recover thread's registers (r4-r11)
MOV r11,r7 ;
MOV r10,r6 ;
MOV r9,r5 ;
MOV r8,r4 ;
LDM r3!,{r4-r7} ;
MSR PSP, r3 ; Setup the thread's stack pointer
;
; /* Return to thread. */
;
BX lr ; Return to thread!
;
; /* The following is the idle wait processing... in this case, no threads are ready for execution and the
; system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts
; are disabled to allow use of WFI for waiting for a thread to arrive. */
;
__tx_ts_wait
CPSID i ; Disable interrupts
LDR r1, [r2] ; Pickup the next thread to execute pointer
STR r1, [r0] ; Store it in the current pointer
CMP r1, #0 ; If non-NULL, a new thread is ready!
BNE __tx_ts_ready ;
IF :DEF:TX_ENABLE_WFI
DSB ; Ensure no outstanding memory transactions
WFI ; Wait for interrupt
ISB ; Ensure pipeline is flushed
ENDIF
__tx_ts_ISB
CPSIE i ; Enable interrupts
B __tx_ts_wait ; Loop to continue waiting
;
; /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are
; already in the handler! */
;
__tx_ts_ready
LDR r7, =0x08000000 ; Build clear PendSV value
LDR r5, =0xE000ED04 ; Build base NVIC address
STR r7, [r5] ; Clear any PendSV
;
; /* Re-enable interrupts and restore new thread. */
;
CPSIE i ; Enable interrupts
B __tx_ts_restore ; Restore the thread
ALIGN
LTORG
END

146
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;/**************************************************************************/
;/* */
;/* Copyright (c) Microsoft Corporation. All rights reserved. */
;/* */
;/* This software is licensed under the Microsoft Software License */
;/* Terms for Microsoft Azure RTOS. Full text of the license can be */
;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
;/* and in the root directory of this software. */
;/* */
;/**************************************************************************/
;
;
;/**************************************************************************/
;/**************************************************************************/
;/** */
;/** ThreadX Component */
;/** */
;/** Thread */
;/** */
;/**************************************************************************/
;/**************************************************************************/
;
;
;#define TX_SOURCE_CODE
;
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_thread.h"
;
;
AREA ||.text||, CODE, READONLY
;/**************************************************************************/
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_stack_build Cortex-M0/AC5 */
;/* 6.0.1 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
;/* */
;/* DESCRIPTION */
;/* */
;/* This function builds a stack frame on the supplied thread's stack. */
;/* The stack frame results in a fake interrupt return to the supplied */
;/* function pointer. */
;/* */
;/* INPUT */
;/* */
;/* thread_ptr Pointer to thread control blk */
;/* function_ptr Pointer to return function */
;/* */
;/* OUTPUT */
;/* */
;/* None */
;/* */
;/* CALLS */
;/* */
;/* None */
;/* */
;/* CALLED BY */
;/* */
;/* _tx_thread_create Create thread service */
;/* */
;/* RELEASE HISTORY */
;/* */
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* */
;/**************************************************************************/
;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID))
;{
EXPORT _tx_thread_stack_build
_tx_thread_stack_build
;
;
; /* Build a fake interrupt frame. The form of the fake interrupt stack
; on the Cortex-M0 should look like the following after it is built:
;
; Stack Top:
; LR Interrupted LR (LR at time of PENDSV)
; r8 Initial value for r8
; r9 Initial value for r9
; r10 Initial value for r10
; r11 Initial value for r11
; r4 Initial value for r4
; r5 Initial value for r5
; r6 Initial value for r6
; r7 Initial value for r7
; r0 Initial value for r0 (Hardware stack starts here!!)
; r1 Initial value for r1
; r2 Initial value for r2
; r3 Initial value for r3
; r12 Initial value for r12
; lr Initial value for lr
; pc Initial value for pc
; xPSR Initial value for xPSR
;
; Stack Bottom: (higher memory address) */
;
LDR r2, [r0, #16] ; Pickup end of stack area
MOVS r3, #0x7 ;
BICS r2, r2, r3 ; Align frame for 8-byte alignment
SUBS r2, r2, #68 ; Subtract frame size
LDR r3, =0xFFFFFFFD ; Build initial LR value
STR r3, [r2, #0] ; Save on the stack
;
; /* Actually build the stack frame. */
;
MOVS r3, #0 ; Build initial register value
STR r3, [r2, #4] ; Store initial r8
STR r3, [r2, #8] ; Store initial r9
STR r3, [r2, #12] ; Store initial r10
STR r3, [r2, #16] ; Store initial r11
STR r3, [r2, #20] ; Store initial r4
STR r3, [r2, #24] ; Store initial r5
STR r3, [r2, #28] ; Store initial r6
STR r3, [r2, #32] ; Store initial r7
;
; /* Hardware stack follows. */
;
STR r3, [r2, #36] ; Store initial r0
STR r3, [r2, #40] ; Store initial r1
STR r3, [r2, #44] ; Store initial r2
STR r3, [r2, #48] ; Store initial r3
STR r3, [r2, #52] ; Store initial r12
LDR r3, =0xFFFFFFFF ; Poison EXC_RETURN value
STR r3, [r2, #56] ; Store initial lr
STR r1, [r2, #60] ; Store initial pc
LDR r3, =0x01000000 ; Only T-bit need be set
STR r3, [r2, #64] ; Store initial xPSR
;
; /* Setup stack pointer. */
; thread_ptr -> tx_thread_stack_ptr = r2;
;
STR r2, [r0, #8] ; Save stack pointer in thread's
; control block
BX lr ; Return to caller
;}
ALIGN
LTORG
END

97
ports/cortex_m0/ac5/src/tx_thread_system_return.s Normal file
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;/**************************************************************************/
;/* */
;/* Copyright (c) Microsoft Corporation. All rights reserved. */
;/* */
;/* This software is licensed under the Microsoft Software License */
;/* Terms for Microsoft Azure RTOS. Full text of the license can be */
;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
;/* and in the root directory of this software. */
;/* */
;/**************************************************************************/
;
;
;/**************************************************************************/
;/**************************************************************************/
;/** */
;/** ThreadX Component */
;/** */
;/** Thread */
;/** */
;/**************************************************************************/
;/**************************************************************************/
;
;#define TX_SOURCE_CODE
;
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_thread.h"
;#include "tx_timer.h"
;
;
;
AREA ||.text||, CODE, READONLY
;/**************************************************************************/
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_system_return Cortex-M0/AC5 */
;/* 6.0.1 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
;/* */
;/* DESCRIPTION */
;/* */
;/* This function is target processor specific. It is used to transfer */
;/* control from a thread back to the ThreadX system. Only a */
;/* minimal context is saved since the compiler assumes temp registers */
;/* are going to get slicked by a function call anyway. */
;/* */
;/* INPUT */
;/* */
;/* None */
;/* */
;/* OUTPUT */
;/* */
;/* None */
;/* */
;/* CALLS */
;/* */
;/* _tx_thread_schedule Thread scheduling loop */
;/* */
;/* CALLED BY */
;/* */
;/* ThreadX components */
;/* */
;/* RELEASE HISTORY */
;/* */
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* */
;/**************************************************************************/
;VOID _tx_thread_system_return(VOID)
;{
EXPORT _tx_thread_system_return
_tx_thread_system_return
;
; /* Return to real scheduler via PendSV. Note that this routine is often
; replaced with in-line assembly in tx_port.h to improved performance. */
;
LDR r0, =0x10000000 ; Load PENDSVSET bit
LDR r1, =0xE000ED04 ; Load NVIC base
STR r0, [r1] ; Set PENDSVBIT in ICSR
MRS r0, IPSR ; Pickup IPSR
CMP r0, #0 ; Is it a thread returning?
BNE _isr_context ; If ISR, skip interrupt enable
MRS r1, PRIMASK ; Thread context returning, pickup PRIMASK
CPSIE i ; Enable interrupts
MSR PRIMASK, r1 ; Restore original interrupt posture
_isr_context
BX lr ; Return to caller
NOP
;}
END

274
ports/cortex_m0/ac5/src/tx_timer_interrupt.s Normal file
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;/**************************************************************************/
;/* */
;/* Copyright (c) Microsoft Corporation. All rights reserved. */
;/* */
;/* This software is licensed under the Microsoft Software License */
;/* Terms for Microsoft Azure RTOS. Full text of the license can be */
;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
;/* and in the root directory of this software. */
;/* */
;/**************************************************************************/
;
;
;/**************************************************************************/
;/**************************************************************************/
;/** */
;/** ThreadX Component */
;/** */
;/** Timer */
;/** */
;/**************************************************************************/
;/**************************************************************************/
;
;#define TX_SOURCE_CODE
;
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_timer.h"
;#include "tx_thread.h"
;
;
;Define Assembly language external references...
;
IMPORT _tx_timer_time_slice
IMPORT _tx_timer_system_clock
IMPORT _tx_timer_current_ptr
IMPORT _tx_timer_list_start
IMPORT _tx_timer_list_end
IMPORT _tx_timer_expired_time_slice
IMPORT _tx_timer_expired
IMPORT _tx_thread_time_slice
IMPORT _tx_timer_expiration_process
IMPORT _tx_thread_current_ptr
IMPORT _tx_thread_execute_ptr
IMPORT _tx_thread_preempt_disable
;
;
AREA ||.text||, CODE, READONLY
PRESERVE8
;/**************************************************************************/
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* _tx_timer_interrupt Cortex-M0/AC5 */
;/* 6.0.1 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
;/* */
;/* DESCRIPTION */
;/* */
;/* This function processes the hardware timer interrupt. This */
;/* processing includes incrementing the system clock and checking for */
;/* time slice and/or timer expiration. If either is found, the */
;/* interrupt context save/restore functions are called along with the */
;/* expiration functions. */
;/* */
;/* INPUT */
;/* */
;/* None */
;/* */
;/* OUTPUT */
;/* */
;/* None */
;/* */
;/* CALLS */
;/* */
;/* _tx_timer_expiration_process Timer expiration processing */
;/* _tx_thread_time_slice Time slice interrupted thread */
;/* */
;/* CALLED BY */
;/* */
;/* interrupt vector */
;/* */
;/* RELEASE HISTORY */
;/* */
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* */
;/**************************************************************************/
;VOID _tx_timer_interrupt(VOID)
;{
EXPORT _tx_timer_interrupt
_tx_timer_interrupt
;
; /* Upon entry to this routine, it is assumed that context save has already
; been called, and therefore the compiler scratch registers are available
; for use. */
;
; /* Increment the system clock. */
; _tx_timer_system_clock++;
;
LDR r1, =_tx_timer_system_clock ; Pickup address of system clock
LDR r0, [r1, #0] ; Pickup system clock
ADDS r0, r0, #1 ; Increment system clock
STR r0, [r1, #0] ; Store new system clock
;
; /* Test for time-slice expiration. */
; if (_tx_timer_time_slice)
; {
;
LDR r3, =_tx_timer_time_slice ; Pickup address of time-slice
LDR r2, [r3, #0] ; Pickup time-slice
CMP r2, #0 ; Is it non-active?
BEQ __tx_timer_no_time_slice ; Yes, skip time-slice processing
;
; /* Decrement the time_slice. */
; _tx_timer_time_slice--;
;
SUBS r2, r2, #1 ; Decrement the time-slice
STR r2, [r3, #0] ; Store new time-slice value
;
; /* Check for expiration. */
; if (__tx_timer_time_slice == 0)
;
CMP r2, #0 ; Has it expired?
BNE __tx_timer_no_time_slice ; No, skip expiration processing
;
; /* Set the time-slice expired flag. */
; _tx_timer_expired_time_slice = TX_TRUE;
;
LDR r3, =_tx_timer_expired_time_slice ; Pickup address of expired flag
MOVS r0, #1 ; Build expired value
STR r0, [r3, #0] ; Set time-slice expiration flag
;
; }
;
__tx_timer_no_time_slice
;
; /* Test for timer expiration. */
; if (*_tx_timer_current_ptr)
; {
;
LDR r1, =_tx_timer_current_ptr ; Pickup current timer pointer address
LDR r0, [r1, #0] ; Pickup current timer
LDR r2, [r0, #0] ; Pickup timer list entry
CMP r2, #0 ; Is there anything in the list?
BEQ __tx_timer_no_timer ; No, just increment the timer
;
; /* Set expiration flag. */
; _tx_timer_expired = TX_TRUE;
;
LDR r3, =_tx_timer_expired ; Pickup expiration flag address
MOVS r2, #1 ; Build expired value
STR r2, [r3, #0] ; Set expired flag
B __tx_timer_done ; Finished timer processing
;
; }
; else
; {
__tx_timer_no_timer
;
; /* No timer expired, increment the timer pointer. */
; _tx_timer_current_ptr++;
;
ADDS r0, r0, #4 ; Move to next timer
;
; /* Check for wrap-around. */
; if (_tx_timer_current_ptr == _tx_timer_list_end)
;
LDR r3, =_tx_timer_list_end ; Pickup addr of timer list end
LDR r2, [r3, #0] ; Pickup list end
CMP r0, r2 ; Are we at list end?
BNE __tx_timer_skip_wrap ; No, skip wrap-around logic
;
; /* Wrap to beginning of list. */
; _tx_timer_current_ptr = _tx_timer_list_start;
;
LDR r3, =_tx_timer_list_start ; Pickup addr of timer list start
LDR r0, [r3, #0] ; Set current pointer to list start
;
__tx_timer_skip_wrap
;
STR r0, [r1, #0] ; Store new current timer pointer
; }
;
__tx_timer_done
;
;
; /* See if anything has expired. */
; if ((_tx_timer_expired_time_slice) || (_tx_timer_expired))
; {
;
LDR r3, =_tx_timer_expired_time_slice ; Pickup addr of expired flag
LDR r2, [r3, #0] ; Pickup time-slice expired flag
CMP r2, #0 ; Did a time-slice expire?
BNE __tx_something_expired ; If non-zero, time-slice expired
LDR r1, =_tx_timer_expired ; Pickup addr of other expired flag
LDR r0, [r1, #0] ; Pickup timer expired flag
CMP r0, #0 ; Did a timer expire?
BEQ __tx_timer_nothing_expired ; No, nothing expired
;
__tx_something_expired
;
;
PUSH {r0, lr} ; Save the lr register on the stack
; and save r0 just to keep 8-byte alignment
;
; /* Did a timer expire? */
; if (_tx_timer_expired)
; {
;
LDR r1, =_tx_timer_expired ; Pickup addr of expired flag
LDR r0, [r1, #0] ; Pickup timer expired flag
CMP r0, #0 ; Check for timer expiration
BEQ __tx_timer_dont_activate ; If not set, skip timer activation
;
; /* Process timer expiration. */
; _tx_timer_expiration_process();
;
BL _tx_timer_expiration_process ; Call the timer expiration handling routine
;
; }
__tx_timer_dont_activate
;
; /* Did time slice expire? */
; if (_tx_timer_expired_time_slice)
; {
;
LDR r3, =_tx_timer_expired_time_slice ; Pickup addr of time-slice expired
LDR r2, [r3, #0] ; Pickup the actual flag
CMP r2, #0 ; See if the flag is set
BEQ __tx_timer_not_ts_expiration ; No, skip time-slice processing
;
; /* Time slice interrupted thread. */
; _tx_thread_time_slice();
;
BL _tx_thread_time_slice ; Call time-slice processing
LDR r0, =_tx_thread_preempt_disable ; Build address of preempt disable flag
LDR r1, [r0] ; Is the preempt disable flag set?
CMP r1, #0 ;
BNE __tx_timer_skip_time_slice ; Yes, skip the PendSV logic
LDR r0, =_tx_thread_current_ptr ; Build current thread pointer address
LDR r1, [r0] ; Pickup the current thread pointer
LDR r2, =_tx_thread_execute_ptr ; Build execute thread pointer address
LDR r3, [r2] ; Pickup the execute thread pointer
LDR r0, =0xE000ED04 ; Build address of control register
LDR r2, =0x10000000 ; Build value for PendSV bit
CMP r1, r3 ; Are they the same?
BEQ __tx_timer_skip_time_slice ; If the same, there was no time-slice performed
STR r2, [r0] ; Not the same, issue the PendSV for preemption
__tx_timer_skip_time_slice
;
; }
;
__tx_timer_not_ts_expiration
;
POP {r0, r1} ; Recover lr register (r0 is just there for
MOV lr, r1 ; the 8-byte stack alignment
;
; }
;
__tx_timer_nothing_expired
DSB ; Complete all memory access
BX lr ; Return to caller
;
;}
ALIGN
LTORG
END