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updated to 6.0.1 and added additional processors/toolchains

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tameraw
2020-07-16 14:32:40 -07:00
parent f8e91d4762
commit 2c35570dc9
1285 changed files with 550383 additions and 50 deletions
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185
ports/cortex_m0/gnu/src/tx_initialize_low_level_sample.S
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@@ -1,185 +0,0 @@
@/**************************************************************************/
@/* */
@/* Copyright (c) Microsoft Corporation. All rights reserved. */
@/* */
@/* This software is licensed under the Microsoft Software License */
@/* Terms for Microsoft Azure RTOS. Full text of the license can be */
@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
@/* and in the root directory of this software. */
@/* */
@/**************************************************************************/
@
@
@/**************************************************************************/
@/**************************************************************************/
@/** */
@/** ThreadX Component */
@/** */
@/** Initialize */
@/** */
@/**************************************************************************/
@/**************************************************************************/
@
@#define TX_SOURCE_CODE
@
@
@/* Include necessary system files. */
@
@#include "tx_api.h"
@#include "tx_initialize.h"
@#include "tx_thread.h"
@#include "tx_timer.h"
@
@
.global _tx_thread_system_stack_ptr
.global _tx_initialize_unused_memory
.global __RAM_segment_used_end__
.global _tx_thread_context_save
.global _tx_thread_context_restore
.global _tx_timer_interrupt
.global _vectors
@
@
SYSTEM_CLOCK = 8000000
SYSTICK_CYCLES = ((SYSTEM_CLOCK / 100) -1)
.text
.align 4
.syntax unified
@/**************************************************************************/
@/* */
@/* FUNCTION RELEASE */
@/* */
@/* _tx_initialize_low_level Cortex-M0/GNU */
@/* 6.0 */
@/* AUTHOR */
@/* */
@/* William E. Lamie, Microsoft Corporation */
@/* */
@/* DESCRIPTION */
@/* */
@/* This function is responsible for any low-level processor */
@/* initialization, including setting up interrupt vectors, setting */
@/* up a periodic timer interrupt source, saving the system stack */
@/* pointer for use in ISR processing later, and finding the first */
@/* available RAM memory address for tx_application_define. */
@/* */
@/* INPUT */
@/* */
@/* None */
@/* */
@/* OUTPUT */
@/* */
@/* None */
@/* */
@/* CALLS */
@/* */
@/* None */
@/* */
@/* CALLED BY */
@/* */
@/* _tx_initialize_kernel_enter ThreadX entry function */
@/* */
@/* RELEASE HISTORY */
@/* */
@/* DATE NAME DESCRIPTION */
@/* */
@/* 05-19-2020 William E. Lamie Initial Version 6.0 */
@/* */
@/**************************************************************************/
@VOID _tx_initialize_low_level(VOID)
@{
.global _tx_initialize_low_level
.thumb_func
_tx_initialize_low_level:
@
@ /* Disable interrupts during ThreadX initialization. */
@
CPSID i
@
@ /* Set base of available memory to end of non-initialised RAM area. */
@
LDR r0, =_tx_initialize_unused_memory @ Build address of unused memory pointer
LDR r1, =__RAM_segment_used_end__ @ Build first free address
ADDS r1, r1, #4 @
STR r1, [r0] @ Setup first unused memory pointer
@
@ /* Enable the cycle count register. */
@
LDR r0, =0xE0001000 @ Build address of DWT register
LDR r1, [r0] @ Pickup the current value
MOVS r2, #1
ORRS r1, r1, r2 @ Set the CYCCNTENA bit
STR r1, [r0] @ Enable the cycle count register
@
@ /* Setup Vector Table Offset Register. */
@
LDR r0, =0xE000E000 @ Build address of NVIC registers
LDR r2, =0xD08 @ Offset to vector base register
ADD r0, r0, r2 @ Build vector base register
LDR r1, =_vectors @ Pickup address of vector table
STR r1, [r0] @ Set vector table address
@
@ /* Set system stack pointer from vector value. */
@
LDR r0, =_tx_thread_system_stack_ptr @ Build address of system stack pointer
LDR r1, =_vectors @ Pickup address of vector table
LDR r1, [r1] @ Pickup reset stack pointer
STR r1, [r0] @ Save system stack pointer
@
@ /* Configure SysTick for 100Hz clock, or 16384 cycles if no reference. */
@
LDR r0, =0xE000E000 @ Build address of NVIC registers
LDR r1, =SYSTICK_CYCLES
STR r1, [r0, #0x14] @ Setup SysTick Reload Value
LDR r1, =0x7 @ Build SysTick Control Enable Value
STR r1, [r0, #0x10] @ Setup SysTick Control
@
@ /* Configure handler priorities. */
@
LDR r1, =0x00000000 @ Rsrv, UsgF, BusF, MemM
LDR r0, =0xE000E000 @ Build address of NVIC registers
LDR r2, =0xD18 @
ADD r0, r0, r2 @
STR r1, [r0] @ Setup System Handlers 4-7 Priority Registers
LDR r1, =0xFF000000 @ SVCl, Rsrv, Rsrv, Rsrv
LDR r0, =0xE000E000 @ Build address of NVIC registers
LDR r2, =0xD1C @
ADD r0, r0, r2 @
STR r1, [r0] @ Setup System Handlers 8-11 Priority Registers
@ Note: SVC must be lowest priority, which is 0xFF
LDR r1, =0x40FF0000 @ SysT, PnSV, Rsrv, DbgM
LDR r0, =0xE000E000 @ Build address of NVIC registers
LDR r2, =0xD20 @
ADD r0, r0, r2 @
STR r1, [r0] @ Setup System Handlers 12-15 Priority Registers
@ Note: PnSV must be lowest priority, which is 0xFF
@
@ /* Return to caller. */
@
BX lr
@}
@
@ /* System Tick timer interrupt handler */
.global __tx_SysTickHandler
.global SysTick_Handler
.thumb_func
__tx_SysTickHandler:
.thumb_func
SysTick_Handler:
@ VOID SysTick_Handler (VOID)
@ {
@
PUSH {r0, lr}
#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
BL _tx_execution_isr_enter @ Call the ISR enter function
#endif
BL _tx_timer_interrupt
#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
BL _tx_execution_isr_exit @ Call the ISR exit function
#endif
POP {r0, r1}
MOV lr, r1
BX lr
@ }

33
ports/cortex_m0/gnu/src/tx_thread_stack_build.S
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@@ -38,7 +38,7 @@
@/* FUNCTION RELEASE */
@/* */
@/* _tx_thread_stack_build Cortex-M0/GNU */
@/* 6.0 */
@/* 6.0.1 */
@/* AUTHOR */
@/* */
@/* William E. Lamie, Microsoft Corporation */
@@ -71,6 +71,11 @@
@/* DATE NAME DESCRIPTION */
@/* */
@/* 05-19-2020 William E. Lamie Initial Version 6.0 */
@/* 06-30-2020 William E. Lamie Modified Comment(s), setting */
@/* R10 to top of stack is not */
@/* needed. Removed references */
@/* to stack frame, resulting */
@/* in version 6.0.1 */
@/* */
@/**************************************************************************/
@VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID))
@@ -85,14 +90,14 @@ _tx_thread_stack_build:
@
@ Stack Top:
@ LR Interrupted LR (LR at time of PENDSV)
@ r8 Initial value for r8
@ r9 Initial value for r9
@ r10 Initial value for r10
@ r11 Initial value for r11
@ r4 Initial value for r4
@ r5 Initial value for r5
@ r6 Initial value for r6
@ r7 Initial value for r7
@ r8 Initial value for r8
@ r9 Initial value for r9
@ r10 (sl) Initial value for r10 (sl)
@ r11 Initial value for r11
@ r0 Initial value for r0 (Hardware stack starts here!!)
@ r1 Initial value for r1
@ r2 Initial value for r2
@@ -114,16 +119,14 @@ _tx_thread_stack_build:
@ /* Actually build the stack frame. */
@
MOVS r3, #0 @ Build initial register value
STR r3, [r2, #4] @ Store initial r4
STR r3, [r2, #8] @ Store initial r5
STR r3, [r2, #12] @ Store initial r6
STR r3, [r2, #16] @ Store initial r7
STR r3, [r2, #20] @ Store initial r8
STR r3, [r2, #24] @ Store initial r9
LDR r3, [r0, #12] @ Pickup stack starting address
STR r3, [r2, #28] @ Store initial r10 (sl)
MOVS r3, #0 @ Build initial register value
STR r3, [r2, #32] @ Store initial r11
STR r3, [r2, #4] @ Store initial r8
STR r3, [r2, #8] @ Store initial r9
STR r3, [r2, #12] @ Store initial r10
STR r3, [r2, #16] @ Store initial r11
STR r3, [r2, #20] @ Store initial r4
STR r3, [r2, #24] @ Store initial r5
STR r3, [r2, #28] @ Store initial r6
STR r3, [r2, #32] @ Store initial r7
@
@ /* Hardware stack follows. */
@

102
ports/cortex_m0/gnu/src/tx_vector_table_sample.S
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@@ -1,102 +0,0 @@
.global reset_handler
.global __tx_NMIHandler
.global __tx_BadHandler
.global __tx_SVCallHandler
.global __tx_DBGHandler
.global __tx_PendSVHandler
.global __tx_SysTickHandler
.global __tx_BadHandler
.global __tx_HardfaultHandler
.syntax unified
.section .vectors, "ax"
.code 16
.align 0
.global _vectors
_vectors:
.word __stack_end__
.word reset_handler
.word __tx_NMIHandler
.word __tx_HardfaultHandler
.word __tx_BadHandler
.word __tx_BadHandler
.word __tx_BadHandler
.word 0 // Reserved
.word 0 // Reserved
.word 0 // Reserved
.word 0 // Reserved
.word __tx_SVCallHandler //_SVC_Handler - used by Threadx scheduler //
.word __tx_DBGHandler
.word 0 // Reserved
.word __tx_PendSVHandler
.word __tx_SysTickHandler // Used by Threadx timer functionality
.word __tx_BadHandler // Populate with user Interrupt handler
.word __tx_BadHandler
.word __tx_BadHandler
.word __tx_BadHandler
.word __tx_BadHandler
.word __tx_BadHandler
.word __tx_BadHandler
.word __tx_BadHandler
.word __tx_BadHandler
.word __tx_BadHandler
.word __tx_BadHandler
.word __tx_BadHandler
.word __tx_BadHandler
.word __tx_BadHandler
.word __tx_BadHandler
.word __tx_BadHandler
.word __tx_BadHandler
.word __tx_BadHandler
.word __tx_BadHandler
.word __tx_BadHandler
.word __tx_BadHandler
.word __tx_BadHandler
.word __tx_BadHandler
.word __tx_BadHandler
.word __tx_BadHandler
.word __tx_BadHandler
.word __tx_BadHandler
.word __tx_BadHandler
.word __tx_BadHandler
.word __tx_BadHandler
.word __tx_BadHandler
.word __tx_BadHandler
.word __tx_BadHandler
.word __tx_BadHandler
.word __tx_BadHandler
.section .init, "ax"
.thumb_func
reset_handler:
// low level hardware config, such as PLL setup goes here
b _start
.text 32
.align 4
.syntax unified
__tx_NMIHandler:
b __tx_NMIHandler
__tx_BadHandler:
b __tx_BadHandler
__tx_DBGHandler:
b __tx_DBGHandler
__tx_HardfaultHandler:
b __tx_HardfaultHandler