7iwind/threadx
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Release 6.2.0

Browse Source
This commit is contained in:
Tiejun Zhou
2022-10-26 23:41:13 +00:00
parent b871c33620
commit 3e8e85cdc1
173 changed files with 26264 additions and 3989 deletions
Download Patch File Download Diff File Expand all files Collapse all files

21
ports/rxv1/gnu/readme_threadx.txt
View File

@@ -27,7 +27,8 @@ initialization code.
The ThreadX demonstration for the RXv1 utilizes CMT0 as a periodic timer interrupt
source. The CMT0 interrupt is typically setup for 10ms periodic interrupts and the
interrupt priority level is set to level 7. You may change any of the timer
interrupt priority level is set to level 5 with the symbol CMT_RX_CFG_IPR in
r_cmt_rx_config.h of Renesas CMT timer module(r_cmt_rx). You may change any of the timer
parameters as needed. Increasing the timer interrupt frequency increases the overhead
of the timer handling code on the system.
@@ -41,12 +42,12 @@ sections in your linker control file.
4. Context Switch, Register Usage and Stack Frames
The RXv1 port for ThreadX uses the first software interrupt, SWINT, i.e., interrupt #17,
to perform context switch. This ISR is thus reserved when using ThreadX and the SWINT
should not be manipulated in any way by the application. The port will setup the
interrupt within _tx_initialize_low_level and the compiler will automatically install
the necessary interrupt vector. As such no additional initialization is necessary by the
application.
The RXv1 port for ThreadX uses the first software interrupt, SWINT, i.e., interrupt #27,
to perform context switch with the interrupt priority level 1. This ISR is thus reserved
when using ThreadX and the SWINT should not be manipulated in any way by the application.
The port will setup the interrupt within _tx_initialize_low_level and the compiler will
automatically install the necessary interrupt vector. As such no additional initialization
is necessary by the application.
The following defines the saved context stack frame used by the ThreadX port. The
state of the CPU registers at the time of a context switch is saved on the running
@@ -96,15 +97,15 @@ is included.
Timer processign is performed by calling __tx_timer_interrupt(). This should usually be done
from within the callback of a periodic timer with a period of 100Hz. In the sample projects
a Renesas Fit CMT periodic timer module (rx_cmt) is used as the timer source.
a Renesas Fit CMT periodic timer module (r_cmt_rx) is used as the timer source.
7. Interrupt Handling
Interrupt handling is unaffected by the ThreadX port as such user interrupts can be
written according to the toolchain's documentation. It is recommended not to use interrupt
priority 15 as this is the priority of the context switch interrupt. However using interrupt
priority 15 won't cause any negative side effects but doing so may slightly reduce
priority 1 as this is the priority of the context switch interrupt. However using interrupt
priority 1 won't cause any negative side effects but doing so may slightly reduce
performance. Please refer to the toolchain documentation for additional details on how to
define interrupt service routines.