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Release 6.2.0

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This commit is contained in:
Tiejun Zhou
2022-10-26 23:41:13 +00:00
parent b871c33620
commit 3e8e85cdc1
173 changed files with 26264 additions and 3989 deletions
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18
ports_module/cortex_m33/iar/module_manager/src/tx_thread_schedule.s
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@@ -42,7 +42,7 @@
/* FUNCTION RELEASE */
/* */
/* _tx_thread_schedule Cortex-M33/IAR */
/* 6.1.12 */
/* 6.2.0 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -87,6 +87,8 @@
/* 07-29-2022 Scott Larson Removed the code path to skip */
/* MPU reloading, */
/* resulting in version 6.1.12 */
/* 10-31-2022 Scott Larson Added low power support, */
/* resulting in version 6.2.0 */
/* */
/**************************************************************************/
// VOID _tx_thread_schedule(VOID)
@@ -341,11 +343,25 @@ __tx_ts_wait:
#endif
LDR r1, [r2] // Pickup the next thread to execute pointer
CBNZ r1, __tx_ts_ready // If non-NULL, a new thread is ready!
#ifdef TX_LOW_POWER
PUSH {r0-r3}
BL tx_low_power_enter // Possibly enter low power mode
POP {r0-r3}
#endif
#ifdef TX_ENABLE_WFI
DSB // Ensure no outstanding memory transactions
WFI // Wait for interrupt
ISB // Ensure pipeline is flushed
#endif
#ifdef TX_LOW_POWER
PUSH {r0-r3}
BL tx_low_power_exit // Exit low power mode
POP {r0-r3}
#endif
#ifdef TX_PORT_USE_BASEPRI
MOV r4, #0 // Disable BASEPRI masking (enable interrupts)
MSR BASEPRI, r4