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apply 6.0.2 patch

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This commit is contained in:
Scott Larson
2020-08-14 09:10:48 -07:00
parent 6a018a4cfd
commit 40a402b827
227 changed files with 2232 additions and 3212 deletions
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72
ports/cortex_m0/iar/example_build/tx_initialize_low_level.s
View File

@@ -20,43 +20,33 @@
;/**************************************************************************/
;/**************************************************************************/
;
;#define TX_SOURCE_CODE
;
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_initialize.h"
;#include "tx_thread.h"
;#include "tx_timer.h"
;
;
EXTERN _tx_thread_system_stack_ptr
EXTERN _tx_initialize_unused_memory
EXTERN _tx_timer_interrupt
EXTERN __vector_table
EXTERN _tx_execution_isr_enter
EXTERN _tx_execution_isr_exit
EXTERN _tx_thread_system_stack_ptr
EXTERN _tx_initialize_unused_memory
EXTERN _tx_timer_interrupt
EXTERN __vector_table
EXTERN _tx_execution_isr_enter
EXTERN _tx_execution_isr_exit
;
;
SYSTEM_CLOCK EQU 50000000
SYSTICK_CYCLES EQU ((SYSTEM_CLOCK / 100) -1)
RSEG FREE_MEM:DATA
PUBLIC __tx_free_memory_start
__tx_free_memory_start
DS32 4
DS32 4
;
;
SECTION `.text`:CODE:NOROOT(2)
THUMB
SECTION `.text`:CODE:NOROOT(2)
THUMB
;/**************************************************************************/
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* _tx_initialize_low_level Cortex-M0/IAR */
;/* 6.0.1 */
;/* 6.0.2 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
@@ -90,6 +80,10 @@ __tx_free_memory_start
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* 08-14-2020 Scott Larson Modified comment(s), and */
;/* commented out code for */
;/* enabling DWT, */
;/* resulting in version 6.0.2 */
;/* */
;/**************************************************************************/
;VOID _tx_initialize_low_level(VOID)
@@ -97,33 +91,33 @@ __tx_free_memory_start
PUBLIC _tx_initialize_low_level
_tx_initialize_low_level:
;
;
; /* Ensure that interrupts are disabled. */
;
CPSID i ; Disable interrupts
;
;
; /* Set base of available memory to end of non-initialised RAM area. */
;
;
LDR r0, =__tx_free_memory_start ; Get end of non-initialized RAM area
LDR r2, =_tx_initialize_unused_memory ; Build address of unused memory pointer
STR r0, [r2, #0] ; Save first free memory address
;
; /* Enable the cycle count register. */
;
LDR r0, =0xE0001000 ; Build address of DWT register
LDR r1, [r0] ; Pickup the current value
MOVS r2, #1
ORRS r1, r1, r2 ; Set the CYCCNTENA bit
STR r1, [r0] ; Enable the cycle count register
; /* Not all M0 have DWT, uncomment if you have a DWT and want to use it. */
; LDR r0, =0xE0001000 ; Build address of DWT register
; LDR r1, [r0] ; Pickup the current value
; MOVS r2, #1
; ORRS r1, r1, r2 ; Set the CYCCNTENA bit
; STR r1, [r0] ; Enable the cycle count register
;
; /* Setup Vector Table Offset Register. */
;
;
LDR r0, =0xE000E000 ; Build address of NVIC registers
LDR r2, =0xD08 ; Offset to vector base register
ADD r0, r0, r2 ; Build vector base register
LDR r1, =__vector_table ; Pickup address of vector table
STR r1, [r0] ; Set vector table address
STR r1, [r0] ; Set vector table address
;
; /* Set system stack pointer from vector value. */
;
@@ -144,26 +138,26 @@ _tx_initialize_low_level:
;
LDR r1, =0x00000000 ; Rsrv, UsgF, BusF, MemM
LDR r0, =0xE000E000 ; Build address of NVIC registers
LDR r2, =0xD18 ;
ADD r0, r0, r2 ;
LDR r2, =0xD18 ;
ADD r0, r0, r2 ;
STR r1, [r0] ; Setup System Handlers 4-7 Priority Registers
LDR r1, =0xFF000000 ; SVCl, Rsrv, Rsrv, Rsrv
LDR r0, =0xE000E000 ; Build address of NVIC registers
LDR r2, =0xD1C ;
ADD r0, r0, r2 ;
LDR r2, =0xD1C ;
ADD r0, r0, r2 ;
STR r1, [r0] ; Setup System Handlers 8-11 Priority Registers
; Note: SVC must be lowest priority, which is 0xFF
LDR r1, =0x40FF0000 ; SysT, PnSV, Rsrv, DbgM
LDR r0, =0xE000E000 ; Build address of NVIC registers
LDR r2, =0xD20 ;
ADD r0, r0, r2 ;
LDR r2, =0xD20 ;
ADD r0, r0, r2 ;
STR r1, [r0] ; Setup System Handlers 12-15 Priority Registers
; Note: PnSV must be lowest priority, which is 0xFF
;
; /* Return to caller. */
;
;
BX lr
;}
;

6
ports/cortex_m0/iar/readme_threadx.txt
View File

@@ -148,6 +148,12 @@ For generic code revision information, please refer to the readme_threadx_generi
file, which is included in your distribution. The following details the revision
information associated with this specific port of ThreadX:
08-14-2020 ThreadX update of Cortex-M0/IAR port. The following files were
changed/added for port specific version 6.0.2:
tx_initialize_low_level.s Comment out DWT code.
*.s Modified comments and whitespace.
06/30/2020 Initial ThreadX version 6.0.1 for Cortex-M0 using IAR's ARM tools.

38
ports/cortex_m0/iar/src/tx_thread_context_restore.s
View File

@@ -21,40 +21,32 @@
;/**************************************************************************/
;
;
;#define TX_SOURCE_CODE
EXTERN _tx_thread_system_state
EXTERN _tx_thread_current_ptr
EXTERN _tx_thread_system_stack_ptr
EXTERN _tx_thread_execute_ptr
EXTERN _tx_timer_time_slice
EXTERN _tx_thread_schedule
EXTERN _tx_thread_preempt_disable
EXTERN _tx_execution_isr_exit
;
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_thread.h"
;#include "tx_timer.h"
;
;
EXTERN _tx_thread_system_state
EXTERN _tx_thread_current_ptr
EXTERN _tx_thread_system_stack_ptr
EXTERN _tx_thread_execute_ptr
EXTERN _tx_timer_time_slice
EXTERN _tx_thread_schedule
EXTERN _tx_thread_preempt_disable
EXTERN _tx_execution_isr_exit
;
;
SECTION `.text`:CODE:NOROOT(2)
THUMB
SECTION `.text`:CODE:NOROOT(2)
THUMB
;/**************************************************************************/
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_context_restore Cortex-M0/IAR */
;/* 6.0.1 */
;/* 6.0.2 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
;/* */
;/* DESCRIPTION */
;/* */
;/* This function is only needed for legacy applications and it should */
;/* not be called in any new development on a Cortex-M. */
;/* This function restores the interrupt context if it is processing a */
;/* nested interrupt. If not, it returns to the interrupt thread if no */
;/* preemption is necessary. Otherwise, if preemption is necessary or */
@@ -81,6 +73,9 @@
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* 08-14-2020 Scott Larson Modified comment(s), clean up */
;/* whitespace, resulting */
;/* in version 6.0.2 */
;/* */
;/**************************************************************************/
;VOID _tx_thread_context_restore(VOID)
@@ -103,4 +98,3 @@ _tx_thread_context_restore:
;
;}
END

31
ports/cortex_m0/iar/src/tx_thread_context_save.s
View File

@@ -21,35 +21,27 @@
;/**************************************************************************/
;
;
;#define TX_SOURCE_CODE
EXTERN _tx_thread_system_state
EXTERN _tx_thread_current_ptr
EXTERN _tx_execution_isr_enter
;
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_thread.h"
;#include "tx_timer.h"
;
;
EXTERN _tx_thread_system_state
EXTERN _tx_thread_current_ptr
EXTERN _tx_execution_isr_enter
;
;
SECTION `.text`:CODE:NOROOT(2)
THUMB
SECTION `.text`:CODE:NOROOT(2)
THUMB
;/**************************************************************************/
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_context_save Cortex-M0/IAR */
;/* 6.0.1 */
;/* 6.0.2 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
;/* */
;/* DESCRIPTION */
;/* */
;/* This function is only needed for legacy applications and it should */
;/* not be called in any new development on a Cortex-M. */
;/* This function saves the context of an executing thread in the */
;/* beginning of interrupt processing. The function also ensures that */
;/* the system stack is used upon return to the calling ISR. */
@@ -75,6 +67,9 @@
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* 08-14-2020 Scott Larson Modified comment(s), clean up */
;/* whitespace, resulting */
;/* in version 6.0.2 */
;/* */
;/**************************************************************************/
;VOID _tx_thread_context_save(VOID)
@@ -84,11 +79,11 @@ _tx_thread_context_save:
#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
;
; /* Call the ISR enter function to indicate an ISR is starting. */
;
;
PUSH {r0, lr} ; Save return address
BL _tx_execution_isr_enter ; Call the ISR enter function
POP {r0, r1} ; Recover return address
MOV lr, r1 ;
MOV lr, r1 ;
#endif
;
; /* Context is already saved - just return! */

18
ports/cortex_m0/iar/src/tx_thread_interrupt_control.s
View File

@@ -20,23 +20,15 @@
;/**************************************************************************/
;/**************************************************************************/
;
;#define TX_SOURCE_CODE
;
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_thread.h"
;
;
SECTION `.text`:CODE:NOROOT(2)
THUMB
SECTION `.text`:CODE:NOROOT(2)
THUMB
;/**************************************************************************/
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_interrupt_control Cortex-M0/IAR */
;/* 6.0.1 */
;/* 6.0.2 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
@@ -67,6 +59,9 @@
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* 08-14-2020 Scott Larson Modified comment(s), clean up */
;/* whitespace, resulting */
;/* in version 6.0.2 */
;/* */
;/**************************************************************************/
;UINT _tx_thread_interrupt_control(UINT new_posture)
@@ -83,4 +78,3 @@ _tx_thread_interrupt_control:
;
;}
END

17
ports/cortex_m0/iar/src/tx_thread_interrupt_disable.s
View File

@@ -20,23 +20,15 @@
;/**************************************************************************/
;/**************************************************************************/
;
;#define TX_SOURCE_CODE
;
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_thread.h"
;
;
SECTION `.text`:CODE:NOROOT(2)
THUMB
SECTION `.text`:CODE:NOROOT(2)
THUMB
;/**************************************************************************/
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_interrupt_restore Cortex-M0/IAR */
;/* 6.0.1 */
;/* 6.0.2 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
@@ -67,6 +59,9 @@
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* 08-14-2020 Scott Larson Modified comment(s), clean up */
;/* whitespace, resulting */
;/* in version 6.0.2 */
;/* */
;/**************************************************************************/
;UINT _tx_thread_interrupt_disable(UINT new_posture)

17
ports/cortex_m0/iar/src/tx_thread_interrupt_restore.s
View File

@@ -20,23 +20,15 @@
;/**************************************************************************/
;/**************************************************************************/
;
;#define TX_SOURCE_CODE
;
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_thread.h"
;
;
SECTION `.text`:CODE:NOROOT(2)
THUMB
SECTION `.text`:CODE:NOROOT(2)
THUMB
;/**************************************************************************/
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_interrupt_restore Cortex-M0/IAR */
;/* 6.0.1 */
;/* 6.0.2 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
@@ -67,6 +59,9 @@
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* 08-14-2020 Scott Larson Modified comment(s), clean up */
;/* whitespace, resulting */
;/* in version 6.0.2 */
;/* */
;/**************************************************************************/
;VOID _tx_thread_interrupt_restore(UINT new_posture)

93
ports/cortex_m0/iar/src/tx_thread_schedule.s
View File

@@ -21,32 +21,23 @@
;/**************************************************************************/
;
;
;#define TX_SOURCE_CODE
EXTERN _tx_thread_current_ptr
EXTERN _tx_thread_execute_ptr
EXTERN _tx_timer_time_slice
EXTERN _tx_thread_system_stack_ptr
EXTERN _tx_thread_preempt_disable
EXTERN _tx_execution_thread_enter
EXTERN _tx_execution_thread_exit
;
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_thread.h"
;#include "tx_timer.h"
;
EXTERN _tx_thread_current_ptr
EXTERN _tx_thread_execute_ptr
EXTERN _tx_timer_time_slice
EXTERN _tx_thread_system_stack_ptr
EXTERN _tx_thread_preempt_disable
EXTERN _tx_execution_thread_enter
EXTERN _tx_execution_thread_exit
;
;
SECTION `.text`:CODE:NOROOT(2)
THUMB
SECTION `.text`:CODE:NOROOT(2)
THUMB
;/**************************************************************************/
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_schedule Cortex-M0/IAR */
;/* 6.0.1 */
;/* 6.0.2 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
@@ -80,6 +71,9 @@
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* 08-14-2020 Scott Larson Modified comment(s), clean up */
;/* whitespace, resulting */
;/* in version 6.0.2 */
;/* */
;/**************************************************************************/
;VOID _tx_thread_schedule(VOID)
@@ -92,7 +86,7 @@ _tx_thread_schedule:
; from the PendSV handling routines below. */
;
; /* Clear the preempt-disable flag to enable rescheduling after initialization on Cortex-M targets. */
;
;
MOVS r0, #0 ; Build value for TX_FALSE
LDR r2, =_tx_thread_preempt_disable ; Build address of preempt disable flag
STR r0, [r2, #0] ; Clear preempt disable flag
@@ -100,7 +94,7 @@ _tx_thread_schedule:
; /* Enable interrupts */
;
CPSIE i
;
;
; /* Enter the scheduler for the first time. */
;
LDR r0, =0x10000000 ; Load PENDSVSET bit
@@ -110,21 +104,21 @@ _tx_thread_schedule:
ISB ; Flush pipeline
;
; /* Wait here for the PendSV to take place. */
;
;
__tx_wait_here:
B __tx_wait_here ; Wait for the PendSV to happen
;}
;
; /* Generic context switch-out switch-in handler... */
;
;
PUBLIC PendSV_Handler
PUBLIC __tx_PendSVHandler
PendSV_Handler:
__tx_PendSVHandler:
;
; /* Get current thread value and new thread pointer. */
;
__tx_ts_handler:
;
__tx_ts_handler:
#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
;
@@ -134,7 +128,7 @@ __tx_ts_handler:
PUSH {r0, lr} ; Save LR (and r0 just for alignment)
BL _tx_execution_thread_exit ; Call the thread exit function
POP {r0, r1} ; Recover LR
MOV lr, r1 ;
MOV lr, r1 ;
CPSIE i ; Enable interrupts
#endif
LDR r0, =_tx_thread_current_ptr ; Build current thread pointer address
@@ -143,9 +137,9 @@ __tx_ts_handler:
LDR r1, [r0] ; Pickup current thread pointer
;
; /* Determine if there is a current thread to finish preserving. */
;
;
CMP r1,#0 ; If NULL, skip preservation
BEQ __tx_ts_new ;
BEQ __tx_ts_new ;
;
; /* Recover PSP and preserve current thread context. */
;
@@ -153,15 +147,15 @@ __tx_ts_handler:
MRS r3, PSP ; Pickup PSP pointer (thread's stack pointer)
SUBS r3, r3, #16 ; Allocate stack space
STM r3!, {r4-r7} ; Save its remaining registers (M3 Instruction: STMDB r12!, {r4-r11})
MOV r4,r8 ;
MOV r5,r9 ;
MOV r6,r10 ;
MOV r7,r11 ;
MOV r4,r8 ;
MOV r5,r9 ;
MOV r6,r10 ;
MOV r7,r11 ;
SUBS r3, r3, #32 ; Allocate stack space
STM r3!, {r4-r7} ;
STM r3!, {r4-r7} ;
SUBS r3, r3, #20 ; Allocate stack space
MOV r5, LR ;
STR r5, [r3] ; Save LR on the stack
MOV r5, LR ;
STR r5, [r3] ; Save LR on the stack
STR r3, [r1, #8] ; Save its stack pointer
;
; /* Determine if time-slice is active. If it isn't, skip time handling processing. */
@@ -169,7 +163,7 @@ __tx_ts_handler:
LDR r4, =_tx_timer_time_slice ; Build address of time-slice variable
LDR r5, [r4] ; Pickup current time-slice
CMP r5, #0 ; If not active, skip processing
BEQ __tx_ts_new ;
BEQ __tx_ts_new ;
;
; /* Time-slice is active, save the current thread's time-slice and clear the global time-slice variable. */
;
@@ -180,7 +174,7 @@ __tx_ts_handler:
MOVS r5, #0 ; Build clear value
STR r5, [r4] ; Clear time-slice
;
;
;
; /* Executing thread is now completely preserved!!! */
;
__tx_ts_new:
@@ -189,7 +183,7 @@ __tx_ts_new:
;
CPSID i ; Disable interrupts
LDR r1, [r2] ; Is there another thread ready to execute?
CMP r1, #0 ;
CMP r1, #0 ;
BEQ __tx_ts_wait ; No, skip to the wait processing
;
; /* Yes, another thread is ready for else, make the current thread the new thread. */
@@ -226,26 +220,26 @@ __tx_ts_restore:
ADDS r3, r3, #4 ; Position past LR
MOV lr, r5 ; Restore LR
LDM r3!,{r4-r7} ; Recover thread's registers (r4-r11)
MOV r11,r7 ;
MOV r10,r6 ;
MOV r9,r5 ;
MOV r8,r4 ;
LDM r3!,{r4-r7} ;
MOV r11,r7 ;
MOV r10,r6 ;
MOV r9,r5 ;
MOV r8,r4 ;
LDM r3!,{r4-r7} ;
MSR PSP, r3 ; Setup the thread's stack pointer
;
; /* Return to thread. */
;
;
BX lr ; Return to thread!
;
; /* The following is the idle wait processing... in this case, no threads are ready for execution and the
; system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts
; system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts
; are disabled to allow use of WFI for waiting for a thread to arrive. */
;
__tx_ts_wait:
CPSID i ; Disable interrupts
LDR r1, [r2] ; Pickup the next thread to execute pointer
STR r1, [r0] ; Store it in the current pointer
CMP r1, #0 ; If non-NULL, a new thread is ready!
CMP r1, #0 ; If non-NULL, a new thread is ready!
BNE __tx_ts_ready ;
#ifdef TX_ENABLE_WFI
DSB ; Ensure no outstanding memory transactions
@@ -255,18 +249,17 @@ __tx_ts_wait:
CPSIE i ; Enable interrupts
B __tx_ts_wait ; Loop to continue waiting
;
; /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are
; /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are
; already in the handler! */
;
__tx_ts_ready:
LDR r7, =0x08000000 ; Build clear PendSV value
LDR r5, =0xE000ED04 ; Build base NVIC address
STR r7, [r5] ; Clear any PendSV
STR r7, [r5] ; Clear any PendSV
;
; /* Re-enable interrupts and restore new thread. */
;
;
CPSIE i ; Enable interrupts
B __tx_ts_restore ; Restore the thread
END

27
ports/cortex_m0/iar/src/tx_thread_stack_build.s
View File

@@ -21,23 +21,14 @@
;/**************************************************************************/
;
;
;#define TX_SOURCE_CODE
;
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_thread.h"
;
;
SECTION `.text`:CODE:NOROOT(2)
THUMB
SECTION `.text`:CODE:NOROOT(2)
THUMB
;/**************************************************************************/
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_stack_build Cortex-M0/IAR */
;/* 6.0.1 */
;/* 6.0.2 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
@@ -70,6 +61,9 @@
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* 08-14-2020 Scott Larson Modified comment(s), clean up */
;/* whitespace, resulting */
;/* in version 6.0.2 */
;/* */
;/**************************************************************************/
;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID))
@@ -77,11 +71,11 @@
PUBLIC _tx_thread_stack_build
_tx_thread_stack_build:
;
;
;
; /* Build a fake interrupt frame. The form of the fake interrupt stack
; on the Cortex-M0 should look like the following after it is built:
;
; Stack Top:
;
; Stack Top:
; LR Interrupted LR (LR at time of PENDSV)
; r8 Initial value for r8
; r9 Initial value for r9
@@ -103,7 +97,7 @@ _tx_thread_stack_build:
; Stack Bottom: (higher memory address) */
;
LDR r2, [r0, #16] ; Pickup end of stack area
MOVS r3, #0x7 ;
MOVS r3, #0x7 ;
BICS r2, r2, r3 ; Align frame for 8-byte alignment
SUBS r2, r2, #68 ; Subtract frame size
LDR r3, =0xFFFFFFFD ; Build initial LR value
@@ -142,4 +136,3 @@ _tx_thread_stack_build:
BX lr ; Return to caller
;}
END

28
ports/cortex_m0/iar/src/tx_thread_system_return.s
View File

@@ -20,25 +20,15 @@
;/**************************************************************************/
;/**************************************************************************/
;
;#define TX_SOURCE_CODE
;
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_thread.h"
;#include "tx_timer.h"
;
;
;
SECTION `.text`:CODE:NOROOT(2)
THUMB
SECTION `.text`:CODE:NOROOT(2)
THUMB
;/**************************************************************************/
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_system_return Cortex-M0/IAR */
;/* 6.0.1 */
;/* 6.0.2 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
@@ -71,6 +61,9 @@
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* 08-14-2020 Scott Larson Modified comment(s), clean up */
;/* whitespace, resulting */
;/* in version 6.0.2 */
;/* */
;/**************************************************************************/
;VOID _tx_thread_system_return(VOID)
@@ -79,9 +72,9 @@
_tx_thread_system_return??rA:
_tx_thread_system_return:
;
; /* Return to real scheduler via PendSV. Note that this routine is often
; /* Return to real scheduler via PendSV. Note that this routine is often
; replaced with in-line assembly in tx_port.h to improved performance. */
;
;
LDR r0, =0x10000000 ; Load PENDSVSET bit
LDR r1, =0xE000ED04 ; Load NVIC base
STR r0, [r1] ; Set PENDSVBIT in ICSR
@@ -92,7 +85,6 @@ _tx_thread_system_return:
CPSIE i ; Enable interrupts
MSR PRIMASK, r1 ; Restore original interrupt posture
_isr_context:
BX lr ; Return to caller
BX lr ; Return to caller
;}
END
END

29
ports/cortex_m0/iar/src/tx_timer_interrupt.s
View File

@@ -20,17 +20,6 @@
;/**************************************************************************/
;/**************************************************************************/
;
;#define TX_SOURCE_CODE
;
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_timer.h"
;#include "tx_thread.h"
;
;
;Define Assembly language external references...
;
EXTERN _tx_timer_time_slice
EXTERN _tx_timer_system_clock
@@ -46,14 +35,14 @@
EXTERN _tx_thread_preempt_disable
;
;
SECTION `.text`:CODE:NOROOT(2)
THUMB
SECTION `.text`:CODE:NOROOT(2)
THUMB
;/**************************************************************************/
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* _tx_timer_interrupt Cortex-M0/IAR */
;/* 6.0.1 */
;/* 6.0.2 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
@@ -88,6 +77,9 @@
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* 08-14-2020 Scott Larson Modified comment(s), clean up */
;/* whitespace, resulting */
;/* in version 6.0.2 */
;/* */
;/**************************************************************************/
;VOID _tx_timer_interrupt(VOID)
@@ -110,7 +102,7 @@ _tx_timer_interrupt:
; if (_tx_timer_time_slice)
; {
;
LDR r3, =_tx_timer_time_slice ; Pickup address of time-slice
LDR r3, =_tx_timer_time_slice ; Pickup address of time-slice
LDR r2, [r3, #0] ; Pickup time-slice
CMP r2, #0 ; Is it non-active?
BEQ __tx_timer_no_time_slice ; Yes, skip time-slice processing
@@ -228,18 +220,18 @@ __tx_timer_dont_activate:
; if (_tx_timer_expired_time_slice)
; {
;
LDR r3, =_tx_timer_expired_time_slice ; Pickup addr of time-slice expired
LDR r3, =_tx_timer_expired_time_slice ; Pickup addr of time-slice expired
LDR r2, [r3, #0] ; Pickup the actual flag
CMP r2, #0 ; See if the flag is set
BEQ __tx_timer_not_ts_expiration ; No, skip time-slice processing
;
; /* Time slice interrupted thread. */
; _tx_thread_time_slice();
; _tx_thread_time_slice();
BL _tx_thread_time_slice ; Call time-slice processing
LDR r0, =_tx_thread_preempt_disable ; Build address of preempt disable flag
LDR r1, [r0] ; Is the preempt disable flag set?
CMP r1, #0 ;
CMP r1, #0 ;
BNE __tx_timer_skip_time_slice ; Yes, skip the PendSV logic
LDR r0, =_tx_thread_current_ptr ; Build current thread pointer address
LDR r1, [r0] ; Pickup the current thread pointer
@@ -268,4 +260,3 @@ __tx_timer_nothing_expired:
;
;}
END