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apply 6.0.2 patch

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This commit is contained in:
Scott Larson
2020-08-14 09:10:48 -07:00
parent 6a018a4cfd
commit 40a402b827
227 changed files with 2232 additions and 3212 deletions
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19
ports/cortex_m0/keil/src/tx_thread_context_restore.s
View File

@@ -20,16 +20,6 @@
;/**************************************************************************/
;/**************************************************************************/
;
;
;#define TX_SOURCE_CODE
;
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_thread.h"
;#include "tx_timer.h"
;
;
IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
IMPORT _tx_execution_isr_exit
@@ -42,13 +32,15 @@
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_context_restore Cortex-M0/AC5 */
;/* 6.0.1 */
;/* 6.0.2 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
;/* */
;/* DESCRIPTION */
;/* */
;/* This function is only needed for legacy applications and it should */
;/* not be called in any new development on a Cortex-M. */
;/* This function restores the interrupt context if it is processing a */
;/* nested interrupt. If not, it returns to the interrupt thread if no */
;/* preemption is necessary. Otherwise, if preemption is necessary or */
@@ -75,6 +67,9 @@
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* 08-14-2020 Scott Larson Modified comment(s), clean up */
;/* whitespace, resulting */
;/* in version 6.0.2 */
;/* */
;/**************************************************************************/
;VOID _tx_thread_context_restore(VOID)
@@ -98,4 +93,4 @@ _tx_thread_context_restore
ALIGN
LTORG
END

21
ports/cortex_m0/keil/src/tx_thread_context_save.s
View File

@@ -20,16 +20,6 @@
;/**************************************************************************/
;/**************************************************************************/
;
;
;#define TX_SOURCE_CODE
;
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_thread.h"
;#include "tx_timer.h"
;
;
IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
IMPORT _tx_execution_isr_enter
@@ -43,13 +33,15 @@
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_context_save Cortex-M0/AC5 */
;/* 6.0.1 */
;/* 6.0.2 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
;/* */
;/* DESCRIPTION */
;/* */
;/* This function is only needed for legacy applications and it should */
;/* not be called in any new development on a Cortex-M. */
;/* This function saves the context of an executing thread in the */
;/* beginning of interrupt processing. The function also ensures that */
;/* the system stack is used upon return to the calling ISR. */
@@ -75,6 +67,9 @@
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* 08-14-2020 Scott Larson Modified comment(s), clean up */
;/* whitespace, resulting */
;/* in version 6.0.2 */
;/* */
;/**************************************************************************/
;VOID _tx_thread_context_save(VOID)
@@ -92,10 +87,10 @@ _tx_thread_context_save
ENDIF
;
; /* Return to interrupt processing. */
;
;
BX lr ; Return to interrupt processing caller
;}
ALIGN
LTORG
END

15
ports/cortex_m0/keil/src/tx_thread_interrupt_control.s
View File

@@ -20,14 +20,6 @@
;/**************************************************************************/
;/**************************************************************************/
;
;#define TX_SOURCE_CODE
;
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_thread.h"
;
;
AREA ||.text||, CODE, READONLY
;/**************************************************************************/
@@ -35,7 +27,7 @@
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_interrupt_control Cortex-M0/AC5 */
;/* 6.0.1 */
;/* 6.0.2 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
@@ -66,6 +58,9 @@
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* 08-14-2020 Scott Larson Modified comment(s), clean up */
;/* whitespace, resulting */
;/* in version 6.0.2 */
;/* */
;/**************************************************************************/
;UINT _tx_thread_interrupt_control(UINT new_posture)
@@ -84,4 +79,4 @@ _tx_thread_interrupt_control
ALIGN
LTORG
END

13
ports/cortex_m0/keil/src/tx_thread_interrupt_disable.s
View File

@@ -20,14 +20,6 @@
;/**************************************************************************/
;/**************************************************************************/
;
;#define TX_SOURCE_CODE
;
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_thread.h"
;
;
AREA ||.text||, CODE, READONLY
;/**************************************************************************/
@@ -35,7 +27,7 @@
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_interrupt_disable Cortex-M0/AC5 */
;/* 6.0.1 */
;/* 6.0.2 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
@@ -66,6 +58,9 @@
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* 08-14-2020 Scott Larson Modified comment(s), clean up */
;/* whitespace, resulting */
;/* in version 6.0.2 */
;/* */
;/**************************************************************************/
;UINT _tx_thread_interrupt_disable(UINT new_posture)

13
ports/cortex_m0/keil/src/tx_thread_interrupt_restore.s
View File

@@ -20,14 +20,6 @@
;/**************************************************************************/
;/**************************************************************************/
;
;#define TX_SOURCE_CODE
;
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_thread.h"
;
;
AREA ||.text||, CODE, READONLY
;/**************************************************************************/
@@ -35,7 +27,7 @@
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_interrupt_restore Cortex-M0/AC5 */
;/* 6.0.1 */
;/* 6.0.2 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
@@ -66,6 +58,9 @@
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* 08-14-2020 Scott Larson Modified comment(s), clean up */
;/* whitespace, resulting */
;/* in version 6.0.2 */
;/* */
;/**************************************************************************/
;VOID _tx_thread_interrupt_restore(UINT new_posture)

79
ports/cortex_m0/keil/src/tx_thread_schedule.s
View File

@@ -21,15 +21,6 @@
;/**************************************************************************/
;
;
;#define TX_SOURCE_CODE
;
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_thread.h"
;#include "tx_timer.h"
;
IMPORT _tx_thread_current_ptr
IMPORT _tx_thread_execute_ptr
IMPORT _tx_timer_time_slice
@@ -37,7 +28,7 @@
IMPORT _tx_thread_preempt_disable
IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
IMPORT _tx_execution_thread_enter
IMPORT _tx_execution_thread_exit
IMPORT _tx_execution_thread_exit
ENDIF
;
;
@@ -48,7 +39,7 @@
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_schedule Cortex-M0/AC5 */
;/* 6.0.1 */
;/* 6.0.2 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
@@ -82,6 +73,9 @@
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* 08-14-2020 Scott Larson Modified comment(s), clean up */
;/* whitespace, resulting */
;/* in version 6.0.2 */
;/* */
;/**************************************************************************/
;VOID _tx_thread_schedule(VOID)
@@ -94,7 +88,7 @@ _tx_thread_schedule
; from the PendSV handling routines below. */
;
; /* Clear the preempt-disable flag to enable rescheduling after initialization on Cortex-M targets. */
;
;
MOVS r0, #0 ; Build value for TX_FALSE
LDR r2, =_tx_thread_preempt_disable ; Build address of preempt disable flag
STR r0, [r2, #0] ; Clear preempt disable flag
@@ -102,7 +96,7 @@ _tx_thread_schedule
; /* Enable interrupts */
;
CPSIE i
;
;
; /* Enter the scheduler for the first time. */
;
LDR r0, =0x10000000 ; Load PENDSVSET bit
@@ -112,22 +106,22 @@ _tx_thread_schedule
ISB ; Flush pipeline
;
; /* Wait here for the PendSV to take place. */
;
;
__tx_wait_here
B __tx_wait_here ; Wait for the PendSV to happen
;}
;
; /* Generic context switch-out switch-in handler... Note that this handler is
; /* Generic context switch-out switch-in handler... Note that this handler is
; common for both PendSV and SVCall. */
;
;
EXPORT PendSV_Handler
EXPORT __tx_PendSVHandler
PendSV_Handler
__tx_PendSVHandler
;
; /* Get current thread value and new thread pointer. */
;
__tx_ts_handler
;
__tx_ts_handler
IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
;
@@ -137,7 +131,7 @@ __tx_ts_handler
PUSH {r0, lr} ; Save LR (and r0 just for alignment)
BL _tx_execution_thread_exit ; Call the thread exit function
POP {r0, r1} ; Recover LR
MOV lr, r1 ;
MOV lr, r1 ;
CPSIE i ; Enable interrupts
ENDIF
LDR r0, =_tx_thread_current_ptr ; Build current thread pointer address
@@ -146,9 +140,9 @@ __tx_ts_handler
LDR r1, [r0] ; Pickup current thread pointer
;
; /* Determine if there is a current thread to finish preserving. */
;
;
CMP r1,#0 ; If NULL, skip preservation
BEQ __tx_ts_new ;
BEQ __tx_ts_new ;
;
; /* Recover PSP and preserve current thread context. */
;
@@ -156,15 +150,15 @@ __tx_ts_handler
MRS r3, PSP ; Pickup PSP pointer (thread's stack pointer)
SUBS r3, r3, #16 ; Allocate stack space
STM r3!, {r4-r7} ; Save its remaining registers (M3 Instruction: STMDB r12!, {r4-r11})
MOV r4,r8 ;
MOV r5,r9 ;
MOV r6,r10 ;
MOV r7,r11 ;
MOV r4,r8 ;
MOV r5,r9 ;
MOV r6,r10 ;
MOV r7,r11 ;
SUBS r3, r3, #32 ; Allocate stack space
STM r3!, {r4-r7} ;
STM r3!, {r4-r7} ;
SUBS r3, r3, #20 ; Allocate stack space
MOV r5, LR ;
STR r5, [r3] ; Save LR on the stack
MOV r5, LR ;
STR r5, [r3] ; Save LR on the stack
STR r3, [r1, #8] ; Save its stack pointer
;
; /* Determine if time-slice is active. If it isn't, skip time handling processing. */
@@ -172,7 +166,7 @@ __tx_ts_handler
LDR r4, =_tx_timer_time_slice ; Build address of time-slice variable
LDR r5, [r4] ; Pickup current time-slice
CMP r5, #0 ; If not active, skip processing
BEQ __tx_ts_new ;
BEQ __tx_ts_new ;
;
; /* Time-slice is active, save the current thread's time-slice and clear the global time-slice variable. */
;
@@ -183,7 +177,7 @@ __tx_ts_handler
MOVS r5, #0 ; Build clear value
STR r5, [r4] ; Clear time-slice
;
;
;
; /* Executing thread is now completely preserved!!! */
;
__tx_ts_new
@@ -192,7 +186,7 @@ __tx_ts_new
;
CPSID i ; Disable interrupts
LDR r1, [r2] ; Is there another thread ready to execute?
CMP r1, #0 ;
CMP r1, #0 ;
BEQ __tx_ts_wait ; No, skip to the wait processing
;
; /* Yes, another thread is ready for else, make the current thread the new thread. */
@@ -229,26 +223,26 @@ __tx_ts_restore
ADDS r3, r3, #4 ; Position past LR
MOV lr, r5 ; Restore LR
LDM r3!,{r4-r7} ; Recover thread's registers (r4-r11)
MOV r11,r7 ;
MOV r10,r6 ;
MOV r9,r5 ;
MOV r8,r4 ;
LDM r3!,{r4-r7} ;
MOV r11,r7 ;
MOV r10,r6 ;
MOV r9,r5 ;
MOV r8,r4 ;
LDM r3!,{r4-r7} ;
MSR PSP, r3 ; Setup the thread's stack pointer
;
; /* Return to thread. */
;
;
BX lr ; Return to thread!
;
; /* The following is the idle wait processing... in this case, no threads are ready for execution and the
; system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts
; system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts
; are disabled to allow use of WFI for waiting for a thread to arrive. */
;
__tx_ts_wait
CPSID i ; Disable interrupts
LDR r1, [r2] ; Pickup the next thread to execute pointer
STR r1, [r0] ; Store it in the current pointer
CMP r1, #0 ; If non-NULL, a new thread is ready!
CMP r1, #0 ; If non-NULL, a new thread is ready!
BNE __tx_ts_ready ;
IF :DEF:TX_ENABLE_WFI
DSB ; Ensure no outstanding memory transactions
@@ -259,20 +253,19 @@ __tx_ts_ISB
CPSIE i ; Enable interrupts
B __tx_ts_wait ; Loop to continue waiting
;
; /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are
; /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are
; already in the handler! */
;
__tx_ts_ready
LDR r7, =0x08000000 ; Build clear PendSV value
LDR r5, =0xE000ED04 ; Build base NVIC address
STR r7, [r5] ; Clear any PendSV
STR r7, [r5] ; Clear any PendSV
;
; /* Re-enable interrupts and restore new thread. */
;
;
CPSIE i ; Enable interrupts
B __tx_ts_restore ; Restore the thread
ALIGN
LTORG
END

23
ports/cortex_m0/keil/src/tx_thread_stack_build.s
View File

@@ -20,15 +20,6 @@
;/**************************************************************************/
;/**************************************************************************/
;
;
;#define TX_SOURCE_CODE
;
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_thread.h"
;
;
AREA ||.text||, CODE, READONLY
;/**************************************************************************/
@@ -36,7 +27,7 @@
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_stack_build Cortex-M0/AC5 */
;/* 6.0.1 */
;/* 6.0.2 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
@@ -69,6 +60,9 @@
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* 08-14-2020 Scott Larson Modified comment(s), clean up */
;/* whitespace, resulting */
;/* in version 6.0.2 */
;/* */
;/**************************************************************************/
;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID))
@@ -76,11 +70,11 @@
EXPORT _tx_thread_stack_build
_tx_thread_stack_build
;
;
;
; /* Build a fake interrupt frame. The form of the fake interrupt stack
; on the Cortex-M0 should look like the following after it is built:
;
; Stack Top:
;
; Stack Top:
; LR Interrupted LR (LR at time of PENDSV)
; r8 Initial value for r8
; r9 Initial value for r9
@@ -102,7 +96,7 @@ _tx_thread_stack_build
; Stack Bottom: (higher memory address) */
;
LDR r2, [r0, #16] ; Pickup end of stack area
MOVS r3, #0x7 ;
MOVS r3, #0x7 ;
BICS r2, r2, r3 ; Align frame for 8-byte alignment
SUBS r2, r2, #68 ; Subtract frame size
LDR r3, =0xFFFFFFFD ; Build initial LR value
@@ -143,4 +137,3 @@ _tx_thread_stack_build
ALIGN
LTORG
END

25
ports/cortex_m0/keil/src/tx_thread_system_return.s
View File

@@ -20,16 +20,6 @@
;/**************************************************************************/
;/**************************************************************************/
;
;#define TX_SOURCE_CODE
;
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_thread.h"
;#include "tx_timer.h"
;
;
;
AREA ||.text||, CODE, READONLY
;/**************************************************************************/
@@ -37,7 +27,7 @@
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_system_return Cortex-M0/AC5 */
;/* 6.0.1 */
;/* 6.0.2 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
@@ -70,6 +60,9 @@
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* 08-14-2020 Scott Larson Modified comment(s), clean up */
;/* whitespace, resulting */
;/* in version 6.0.2 */
;/* */
;/**************************************************************************/
;VOID _tx_thread_system_return(VOID)
@@ -77,9 +70,9 @@
EXPORT _tx_thread_system_return
_tx_thread_system_return
;
; /* Return to real scheduler via PendSV. Note that this routine is often
; /* Return to real scheduler via PendSV. Note that this routine is often
; replaced with in-line assembly in tx_port.h to improved performance. */
;
;
LDR r0, =0x10000000 ; Load PENDSVSET bit
LDR r1, =0xE000ED04 ; Load NVIC base
STR r0, [r1] ; Set PENDSVBIT in ICSR
@@ -90,8 +83,8 @@ _tx_thread_system_return
CPSIE i ; Enable interrupts
MSR PRIMASK, r1 ; Restore original interrupt posture
_isr_context
BX lr ; Return to caller
BX lr ; Return to caller
NOP
;}
END
END

25
ports/cortex_m0/keil/src/tx_timer_interrupt.s
View File

@@ -20,17 +20,6 @@
;/**************************************************************************/
;/**************************************************************************/
;
;#define TX_SOURCE_CODE
;
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_timer.h"
;#include "tx_thread.h"
;
;
;Define Assembly language external references...
;
IMPORT _tx_timer_time_slice
IMPORT _tx_timer_system_clock
@@ -53,7 +42,7 @@
;/* FUNCTION RELEASE */
;/* */
;/* _tx_timer_interrupt Cortex-M0/AC5 */
;/* 6.0.1 */
;/* 6.0.2 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
@@ -88,6 +77,9 @@
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* 08-14-2020 Scott Larson Modified comment(s), clean up */
;/* whitespace, resulting */
;/* in version 6.0.2 */
;/* */
;/**************************************************************************/
;VOID _tx_timer_interrupt(VOID)
@@ -111,7 +103,7 @@ _tx_timer_interrupt
; if (_tx_timer_time_slice)
; {
;
LDR r3, =_tx_timer_time_slice ; Pickup address of time-slice
LDR r3, =_tx_timer_time_slice ; Pickup address of time-slice
LDR r2, [r3, #0] ; Pickup time-slice
CMP r2, #0 ; Is it non-active?
BEQ __tx_timer_no_time_slice ; Yes, skip time-slice processing
@@ -229,18 +221,18 @@ __tx_timer_dont_activate
; if (_tx_timer_expired_time_slice)
; {
;
LDR r3, =_tx_timer_expired_time_slice ; Pickup addr of time-slice expired
LDR r3, =_tx_timer_expired_time_slice ; Pickup addr of time-slice expired
LDR r2, [r3, #0] ; Pickup the actual flag
CMP r2, #0 ; See if the flag is set
BEQ __tx_timer_not_ts_expiration ; No, skip time-slice processing
;
; /* Time slice interrupted thread. */
; _tx_thread_time_slice();
; _tx_thread_time_slice();
;
BL _tx_thread_time_slice ; Call time-slice processing
LDR r0, =_tx_thread_preempt_disable ; Build address of preempt disable flag
LDR r1, [r0] ; Is the preempt disable flag set?
CMP r1, #0 ;
CMP r1, #0 ;
BNE __tx_timer_skip_time_slice ; Yes, skip the PendSV logic
LDR r0, =_tx_thread_current_ptr ; Build current thread pointer address
LDR r1, [r0] ; Pickup the current thread pointer
@@ -271,4 +263,3 @@ __tx_timer_nothing_expired
ALIGN
LTORG
END