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apply 6.0.2 patch

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This commit is contained in:
Scott Larson
2020-08-14 09:10:48 -07:00
parent 6a018a4cfd
commit 40a402b827
227 changed files with 2232 additions and 3212 deletions
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41
ports/cortex_m4/ac5/example_build/tx_initialize_low_level.s
View File

@@ -15,16 +15,6 @@
;/**************************************************************************/
;/**************************************************************************/
;
;#define TX_SOURCE_CODE
;
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_initialize.h"
;#include "tx_thread.h"
;#include "tx_timer.h"
;
;
IMPORT _tx_thread_system_stack_ptr
IMPORT _tx_initialize_unused_memory
@@ -85,7 +75,6 @@ __tx_vectors
DCD __tx_IntHandler ; Int 1
DCD __tx_IntHandler ; Int 2
DCD __tx_IntHandler ; Int 3
;
;
AREA ||.text||, CODE, READONLY
@@ -108,7 +97,7 @@ Reset_Handler
;/* FUNCTION RELEASE */
;/* */
;/* _tx_initialize_low_level Cortex-M4/AC5 */
;/* 6.0.1 */
;/* 6.0.2 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation. */
@@ -142,6 +131,9 @@ Reset_Handler
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* 08-14-2020 Scott Larson Modified comment(s), clean up */
;/* whitespace, resulting */
;/* in version 6.0.2 */
;/* */
;/**************************************************************************/
;VOID _tx_initialize_low_level(VOID)
@@ -154,24 +146,24 @@ _tx_initialize_low_level
CPSID i
;
; /* Set base of available memory to end of non-initialised RAM area. */
;
;
LDR r0, =_tx_initialize_unused_memory ; Build address of unused memory pointer
LDR r1, =|Image$$ZI$$Limit| ; Build first free address
ADD r1, r1, #4 ;
ADD r1, r1, #4 ;
STR r1, [r0] ; Setup first unused memory pointer
;
; /* Setup Vector Table Offset Register. */
;
;
MOV r0, #0xE000E000 ; Build address of NVIC registers
LDR r1, =__tx_vectors ; Pickup address of vector table
STR r1, [r0, #0xD08] ; Set vector table address
STR r1, [r0, #0xD08] ; Set vector table address
;
; /* Enable the cycle count register. */
;
; LDR r0, =0xE0001000 ; Build address of DWT register
; LDR r1, [r0] ; Pickup the current value
; ORR r1, r1, #1 ; Set the CYCCNTENA bit
; STR r1, [r0] ; Enable the cycle count register
; STR r1, [r0] ; Enable the cycle count register
;
; /* Set system stack pointer from vector value. */
;
@@ -202,11 +194,11 @@ _tx_initialize_low_level
; Note: PnSV must be lowest priority, which is 0xFF
;
; /* Return to caller. */
;
BX lr
;
BX lr
;}
;
;
;
;/* Define initial heap/stack routine for the ARM RVCT startup code.
; This routine will set the initial stack and heap locations */
;
@@ -222,19 +214,19 @@ __user_initial_stackheap
;/* Define shells for each of the unused vectors. */
;
EXPORT __tx_BadHandler
__tx_BadHandler
__tx_BadHandler
B __tx_BadHandler
EXPORT __tx_SVCallHandler
__tx_SVCallHandler
B __tx_SVCallHandler
B __tx_SVCallHandler
EXPORT __tx_IntHandler
__tx_IntHandler
; VOID InterruptHandler (VOID)
; {
PUSH {r0, lr}
; /* Do interrupt handler work here */
; /* .... */
@@ -253,7 +245,7 @@ __tx_SysTickHandler
BX LR
; }
EXPORT __tx_NMIHandler
EXPORT __tx_NMIHandler
__tx_NMIHandler
B __tx_NMIHandler
@@ -264,4 +256,3 @@ __tx_DBGHandler
ALIGN
LTORG
END

35
ports/cortex_m4/ac5/readme_threadx.txt
View File

@@ -112,22 +112,22 @@ FPU Stack Frame (only interrupted thread with FPU enabled):
0x78 s30
0x7C s31
0x80 fpscr
0x84 r4
0x88 r5
0x8C r6
0x90 r7
0x94 r8
0x98 r9
0x9C r10 (sl)
0xA0 r11
0x84 r4
0x88 r5
0x8C r6
0x90 r7
0x94 r8
0x98 r9
0x9C r10
0xA0 r11
0xA4 r0 (Hardware stack starts here!!)
0xA8 r1
0xAC r2
0xB0 r3
0xB4 r12
0xB8 lr
0xBC pc
0xC0 xPSR
0xA8 r1
0xAC r2
0xB0 r3
0xB4 r12
0xB8 lr
0xBC pc
0xC0 xPSR
5. Improving Performance
@@ -197,6 +197,11 @@ For generic code revision information, please refer to the readme_threadx_generi
file, which is included in your distribution. The following details the revision
information associated with this specific port of ThreadX:
08-14-2020 ThreadX update of Cortex-M4/AC5 port. The following files were
changed/added for port specific version 6.0.2:
tx_thread_context_save.s Fixed register names.
*.s Modified comments and whitespace.
06/30/2020 Initial ThreadX 6.0.1 version for Cortex-M4 using AC5 tools.

22
ports/cortex_m4/ac5/src/tx_thread_context_restore.s
View File

@@ -2,6 +2,11 @@
;/* */
;/* Copyright (c) Microsoft Corporation. All rights reserved. */
;/* */
;/* This software is licensed under the Microsoft Software License */
;/* Terms for Microsoft Azure RTOS. Full text of the license can be */
;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
;/* and in the root directory of this software. */
;/* */
;/**************************************************************************/
;
;
@@ -15,16 +20,6 @@
;/**************************************************************************/
;/**************************************************************************/
;
;
;#define TX_SOURCE_CODE
;
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_thread.h"
;#include "tx_timer.h"
;
;
IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
IMPORT _tx_execution_isr_exit
@@ -38,13 +33,15 @@
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_context_restore Cortex-M4/AC5 */
;/* 6.0.1 */
;/* 6.0.2 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
;/* */
;/* DESCRIPTION */
;/* */
;/* This function is only needed for legacy applications and it should */
;/* not be called in any new development on a Cortex-M. */
;/* This function restores the interrupt context if it is processing a */
;/* nested interrupt. If not, it returns to the interrupt thread if no */
;/* preemption is necessary. Otherwise, if preemption is necessary or */
@@ -71,6 +68,9 @@
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* 08-14-2020 Scott Larson Modified comment(s), clean up */
;/* whitespace, resulting */
;/* in version 6.0.2 */
;/* */
;/**************************************************************************/
;VOID _tx_thread_context_restore(VOID)

26
ports/cortex_m4/ac5/src/tx_thread_context_save.s
View File

@@ -2,6 +2,11 @@
;/* */
;/* Copyright (c) Microsoft Corporation. All rights reserved. */
;/* */
;/* This software is licensed under the Microsoft Software License */
;/* Terms for Microsoft Azure RTOS. Full text of the license can be */
;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
;/* and in the root directory of this software. */
;/* */
;/**************************************************************************/
;
;
@@ -15,16 +20,6 @@
;/**************************************************************************/
;/**************************************************************************/
;
;
;#define TX_SOURCE_CODE
;
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_thread.h"
;#include "tx_timer.h"
;
;
IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
IMPORT _tx_execution_isr_enter
@@ -38,13 +33,15 @@
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_context_save Cortex-M4/AC5 */
;/* 6.0.1 */
;/* 6.0.2 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
;/* */
;/* DESCRIPTION */
;/* */
;/* This function is only needed for legacy applications and it should */
;/* not be called in any new development on a Cortex-M. */
;/* This function saves the context of an executing thread in the */
;/* beginning of interrupt processing. The function also ensures that */
;/* the system stack is used upon return to the calling ISR. */
@@ -70,6 +67,9 @@
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* 08-14-2020 Scott Larson Modified comment(s), clean up */
;/* whitespace, resulting */
;/* in version 6.0.2 */
;/* */
;/**************************************************************************/
;VOID _tx_thread_context_save(VOID)
@@ -82,11 +82,11 @@ _tx_thread_context_save
;
PUSH {r0, lr} ; Save ISR lr
BL _tx_execution_isr_enter ; Call the ISR enter function
POP {lr0, r} ; Recover ISR lr
POP {r0, lr} ; Recover ISR lr
ENDIF
;
; /* Return to interrupt processing. */
;
;
BX lr ; Return to interrupt processing caller
;}
ALIGN

19
ports/cortex_m4/ac5/src/tx_thread_interrupt_control.s
View File

@@ -2,6 +2,11 @@
;/* */
;/* Copyright (c) Microsoft Corporation. All rights reserved. */
;/* */
;/* This software is licensed under the Microsoft Software License */
;/* Terms for Microsoft Azure RTOS. Full text of the license can be */
;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
;/* and in the root directory of this software. */
;/* */
;/**************************************************************************/
;
;
@@ -15,14 +20,6 @@
;/**************************************************************************/
;/**************************************************************************/
;
;#define TX_SOURCE_CODE
;
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_thread.h"
;
;
AREA ||.text||, CODE, READONLY
;/**************************************************************************/
@@ -30,7 +27,7 @@
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_interrupt_control Cortex-M4/AC5 */
;/* 6.0.1 */
;/* 6.0.2 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
@@ -61,6 +58,9 @@
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* 08-14-2020 Scott Larson Modified comment(s), clean up */
;/* whitespace, resulting */
;/* in version 6.0.2 */
;/* */
;/**************************************************************************/
;UINT _tx_thread_interrupt_control(UINT new_posture)
@@ -77,4 +77,3 @@ _tx_thread_interrupt_control
;
;}
END

18
ports/cortex_m4/ac5/src/tx_thread_interrupt_disable.s
View File

@@ -2,6 +2,11 @@
;/* */
;/* Copyright (c) Microsoft Corporation. All rights reserved. */
;/* */
;/* This software is licensed under the Microsoft Software License */
;/* Terms for Microsoft Azure RTOS. Full text of the license can be */
;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
;/* and in the root directory of this software. */
;/* */
;/**************************************************************************/
;
;
@@ -15,14 +20,6 @@
;/**************************************************************************/
;/**************************************************************************/
;
;#define TX_SOURCE_CODE
;
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_thread.h"
;
;
AREA ||.text||, CODE, READONLY
;/**************************************************************************/
@@ -30,7 +27,7 @@
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_interrupt_disable Cortex-M4/AC5 */
;/* 6.0.1 */
;/* 6.0.2 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation. */
@@ -61,6 +58,9 @@
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* 08-14-2020 Scott Larson Modified comment(s), clean up */
;/* whitespace, resulting */
;/* in version 6.0.2 */
;/* */
;/**************************************************************************/
;UINT _tx_thread_interrupt_disable(UINT new_posture)

18
ports/cortex_m4/ac5/src/tx_thread_interrupt_restore.s
View File

@@ -2,6 +2,11 @@
;/* */
;/* Copyright (c) Microsoft Corporation. All rights reserved. */
;/* */
;/* This software is licensed under the Microsoft Software License */
;/* Terms for Microsoft Azure RTOS. Full text of the license can be */
;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
;/* and in the root directory of this software. */
;/* */
;/**************************************************************************/
;
;
@@ -15,14 +20,6 @@
;/**************************************************************************/
;/**************************************************************************/
;
;#define TX_SOURCE_CODE
;
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_thread.h"
;
;
AREA ||.text||, CODE, READONLY
;/**************************************************************************/
@@ -30,7 +27,7 @@
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_interrupt_restore Cortex-M4/AC5 */
;/* 6.0.1 */
;/* 6.0.2 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation. */
@@ -61,6 +58,9 @@
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* 08-14-2020 Scott Larson Modified comment(s), clean up */
;/* whitespace, resulting */
;/* in version 6.0.2 */
;/* */
;/**************************************************************************/
;VOID _tx_thread_interrupt_restore(UINT new_posture)

66
ports/cortex_m4/ac5/src/tx_thread_schedule.s
View File

@@ -2,6 +2,11 @@
;/* */
;/* Copyright (c) Microsoft Corporation. All rights reserved. */
;/* */
;/* This software is licensed under the Microsoft Software License */
;/* Terms for Microsoft Azure RTOS. Full text of the license can be */
;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
;/* and in the root directory of this software. */
;/* */
;/**************************************************************************/
;
;
@@ -16,15 +21,6 @@
;/**************************************************************************/
;
;
;#define TX_SOURCE_CODE
;
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_thread.h"
;#include "tx_timer.h"
;
IMPORT _tx_thread_current_ptr
IMPORT _tx_thread_execute_ptr
IMPORT _tx_timer_time_slice
@@ -32,7 +28,7 @@
IMPORT _tx_thread_preempt_disable
IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
IMPORT _tx_execution_thread_enter
IMPORT _tx_execution_thread_exit
IMPORT _tx_execution_thread_exit
ENDIF
;
;
@@ -43,7 +39,7 @@
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_schedule Cortex-M4/AC5 */
;/* 6.0.1 */
;/* 6.0.2 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
@@ -77,6 +73,9 @@
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* 08-14-2020 Scott Larson Modified comment(s), clean up */
;/* whitespace, resulting */
;/* in version 6.0.2 */
;/* */
;/**************************************************************************/
;VOID _tx_thread_schedule(VOID)
@@ -89,7 +88,7 @@ _tx_thread_schedule
; from the PendSV handling routines below. */
;
; /* Clear the preempt-disable flag to enable rescheduling after initialization on Cortex-M targets. */
;
;
MOV r0, #0 ; Build value for TX_FALSE
LDR r2, =_tx_thread_preempt_disable ; Build address of preempt disable flag
STR r0, [r2, #0] ; Clear preempt disable flag
@@ -98,14 +97,14 @@ _tx_thread_schedule
;
IF {TARGET_FPU_VFP} = {TRUE}
MRS r0, CONTROL ; Pickup current CONTROL register
BIC r0, r0, #4 ; Clear the FPCA bit
BIC r0, r0, #4 ; Clear the FPCA bit
MSR CONTROL, r0 ; Setup new CONTROL register
ENDIF
;
; /* Enable the interrupts */
;
CPSIE i
;
;
; /* Enter the scheduler for the first time. */
;
MOV r0, #0x10000000 ; Load PENDSVSET bit
@@ -115,21 +114,21 @@ _tx_thread_schedule
ISB ; Flush pipeline
;
; /* Wait here for the PendSV to take place. */
;
;
__tx_wait_here
B __tx_wait_here ; Wait for the PendSV to happen
;}
;
; /* Generic context switching PendSV handler. */
;
;
EXPORT __tx_PendSVHandler
EXPORT PendSV_Handler
__tx_PendSVHandler
__tx_PendSVHandler
PendSV_Handler
;
; /* Get current thread value and new thread pointer. */
;
__tx_ts_handler
;
__tx_ts_handler
IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
;
@@ -147,7 +146,7 @@ __tx_ts_handler
LDR r1, [r0] ; Pickup current thread pointer
;
; /* Determine if there is a current thread to finish preserving. */
;
;
CBZ r1, __tx_ts_new ; If NULL, skip preservation
;
; /* Recover PSP and preserve current thread context. */
@@ -177,10 +176,10 @@ _skip_vfp_save
; /* Clear the global time-slice. */
;
STR r3, [r4] ; Clear time-slice
;
;
; /* Executing thread is now completely preserved!!! */
;
__tx_ts_new
__tx_ts_new
;
; /* Now we are looking for a new thread to execute! */
;
@@ -195,7 +194,7 @@ __tx_ts_new
;
; /* Increment the thread run count. */
;
__tx_ts_restore
__tx_ts_restore
LDR r7, [r1, #4] ; Pickup the current thread run count
MOV32 r4, _tx_timer_time_slice ; Build address of time-slice variable
LDR r5, [r1, #24] ; Pickup thread's current time-slice
@@ -221,7 +220,7 @@ __tx_ts_restore
LDMIA r12!, {LR} ; Pickup LR
IF {TARGET_FPU_VFP} = {TRUE}
TST LR, #0x10 ; Determine if the VFP extended frame is present
BNE _skip_vfp_restore ; If not, skip VFP restore
BNE _skip_vfp_restore ; If not, skip VFP restore
VLDMIA r12!, {s16-s31} ; Yes, restore additional VFP registers
_skip_vfp_restore
ENDIF
@@ -229,14 +228,14 @@ _skip_vfp_restore
MSR PSP, r12 ; Setup the thread's stack pointer
;
; /* Return to thread. */
;
;
BX lr ; Return to thread!
;
; /* The following is the idle wait processing... in this case, no threads are ready for execution and the
; system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts
; system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts
; are disabled to allow use of WFI for waiting for a thread to arrive. */
;
__tx_ts_wait
__tx_ts_wait
CPSID i ; Disable interrupts
LDR r1, [r2] ; Pickup the next thread to execute pointer
STR r1, [r0] ; Store it in the current pointer
@@ -249,16 +248,16 @@ __tx_ts_wait
CPSIE i ; Enable interrupts
B __tx_ts_wait ; Loop to continue waiting
;
; /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are
; /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are
; already in the handler! */
;
__tx_ts_ready
__tx_ts_ready
MOV r7, #0x08000000 ; Build clear PendSV value
MOV r8, #0xE000E000 ; Build base NVIC address
STR r7, [r8, #0xD04] ; Clear any PendSV
STR r7, [r8, #0xD04] ; Clear any PendSV
;
; /* Re-enable interrupts and restore new thread. */
;
;
CPSIE i ; Enable interrupts
B __tx_ts_restore ; Restore the thread
@@ -266,7 +265,7 @@ __tx_ts_ready
EXPORT tx_thread_fpu_enable
tx_thread_fpu_enable
;
; /* Automatic VPF logic is supported, this function is present only for
; /* Automatic VPF logic is supported, this function is present only for
; backward compatibility purposes and therefore simply returns. */
;
BX LR ; Return to caller
@@ -274,7 +273,7 @@ tx_thread_fpu_enable
EXPORT tx_thread_fpu_disable
tx_thread_fpu_disable
;
; /* Automatic VPF logic is supported, this function is present only for
; /* Automatic VPF logic is supported, this function is present only for
; backward compatibility purposes and therefore simply returns. */
;
BX LR ; Return to caller
@@ -290,4 +289,3 @@ _tx_vfp_access
ALIGN
LTORG
END

17
ports/cortex_m4/ac5/src/tx_thread_stack_build.s
View File

@@ -2,6 +2,11 @@
;/* */
;/* Copyright (c) Microsoft Corporation. All rights reserved. */
;/* */
;/* This software is licensed under the Microsoft Software License */
;/* Terms for Microsoft Azure RTOS. Full text of the license can be */
;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
;/* and in the root directory of this software. */
;/* */
;/**************************************************************************/
;
;
@@ -31,7 +36,7 @@
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_stack_build Cortex-M4/AC5 */
;/* 6.0.1 */
;/* 6.0.2 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
@@ -64,6 +69,9 @@
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* 08-14-2020 Scott Larson Modified comment(s), clean up */
;/* whitespace, resulting */
;/* in version 6.0.2 */
;/* */
;/**************************************************************************/
;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID))
@@ -71,11 +79,11 @@
EXPORT _tx_thread_stack_build
_tx_thread_stack_build
;
;
;
; /* Build a fake interrupt frame. The form of the fake interrupt stack
; on the Cortex-M4 should look like the following after it is built:
;
; Stack Top:
;
; Stack Top:
; LR Interrupted LR (LR at time of PENDSV)
; r4 Initial value for r4
; r5 Initial value for r5
@@ -135,4 +143,3 @@ _tx_thread_stack_build
BX lr ; Return to caller
;}
END

29
ports/cortex_m4/ac5/src/tx_thread_system_return.s
View File

@@ -2,6 +2,11 @@
;/* */
;/* Copyright (c) Microsoft Corporation. All rights reserved. */
;/* */
;/* This software is licensed under the Microsoft Software License */
;/* Terms for Microsoft Azure RTOS. Full text of the license can be */
;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
;/* and in the root directory of this software. */
;/* */
;/**************************************************************************/
;
;
@@ -15,16 +20,6 @@
;/**************************************************************************/
;/**************************************************************************/
;
;#define TX_SOURCE_CODE
;
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_thread.h"
;#include "tx_timer.h"
;
;
;
AREA ||.text||, CODE, READONLY
;/**************************************************************************/
@@ -32,7 +27,7 @@
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_system_return Cortex-M4/AC5 */
;/* 6.0.1 */
;/* 6.0.2 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
@@ -65,6 +60,9 @@
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* 08-14-2020 Scott Larson Modified comment(s), clean up */
;/* whitespace, resulting */
;/* in version 6.0.2 */
;/* */
;/**************************************************************************/
;VOID _tx_thread_system_return(VOID)
@@ -72,9 +70,9 @@
EXPORT _tx_thread_system_return
_tx_thread_system_return
;
; /* Return to real scheduler via PendSV. Note that this routine is often
; /* Return to real scheduler via PendSV. Note that this routine is often
; replaced with in-line assembly in tx_port.h to improved performance. */
;
;
MOV r0, #0x10000000 ; Load PENDSVSET bit
MOV r1, #0xE000E000 ; Load NVIC base
STR r0, [r1, #0xD04] ; Set PENDSVBIT in ICSR
@@ -85,7 +83,6 @@ _tx_thread_system_return
CPSIE i ; Enable interrupts
MSR PRIMASK, r1 ; Restore original interrupt posture
_isr_context
BX lr ; Return to caller
BX lr ; Return to caller
;}
END
END

28
ports/cortex_m4/ac5/src/tx_timer_interrupt.s
View File

@@ -2,6 +2,11 @@
;/* */
;/* Copyright (c) Microsoft Corporation. All rights reserved. */
;/* */
;/* This software is licensed under the Microsoft Software License */
;/* Terms for Microsoft Azure RTOS. Full text of the license can be */
;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
;/* and in the root directory of this software. */
;/* */
;/**************************************************************************/
;
;
@@ -15,17 +20,6 @@
;/**************************************************************************/
;/**************************************************************************/
;
;#define TX_SOURCE_CODE
;
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_timer.h"
;#include "tx_thread.h"
;
;
;Define Assembly language external references...
;
IMPORT _tx_timer_time_slice
IMPORT _tx_timer_system_clock
@@ -48,7 +42,7 @@
;/* FUNCTION RELEASE */
;/* */
;/* _tx_timer_interrupt Cortex-M4/AC5 */
;/* 6.0.1 */
;/* 6.0.2 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
@@ -83,6 +77,9 @@
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* 08-14-2020 Scott Larson Modified comment(s), clean up */
;/* whitespace, resulting */
;/* in version 6.0.2 */
;/* */
;/**************************************************************************/
;VOID _tx_timer_interrupt(VOID)
@@ -106,7 +103,7 @@ _tx_timer_interrupt
; if (_tx_timer_time_slice)
; {
;
MOV32 r3, _tx_timer_time_slice ; Pickup address of time-slice
MOV32 r3, _tx_timer_time_slice ; Pickup address of time-slice
LDR r2, [r3, #0] ; Pickup time-slice
CBZ r2, __tx_timer_no_time_slice ; Is it non-active?
; Yes, skip time-slice processing
@@ -223,13 +220,13 @@ __tx_timer_dont_activate
; if (_tx_timer_expired_time_slice)
; {
;
MOV32 r3, _tx_timer_expired_time_slice ; Pickup addr of time-slice expired
MOV32 r3, _tx_timer_expired_time_slice ; Pickup addr of time-slice expired
LDR r2, [r3, #0] ; Pickup the actual flag
CBZ r2, __tx_timer_not_ts_expiration ; See if the flag is set
; No, skip time-slice processing
;
; /* Time slice interrupted thread. */
; _tx_thread_time_slice();
; _tx_thread_time_slice();
BL _tx_thread_time_slice ; Call time-slice processing
MOV32 r0, _tx_thread_preempt_disable ; Build address of preempt disable flag
@@ -263,4 +260,3 @@ __tx_timer_nothing_expired
ALIGN
LTORG
END