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apply 6.0.2 patch

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This commit is contained in:
Scott Larson
2020-08-14 09:10:48 -07:00
parent 6a018a4cfd
commit 40a402b827
227 changed files with 2232 additions and 3212 deletions
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50
ports/cortex_m4/iar/example_build/tx_initialize_low_level.s
View File

@@ -20,42 +20,32 @@
;/**************************************************************************/
;/**************************************************************************/
;
;#define TX_SOURCE_CODE
;
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_initialize.h"
;#include "tx_thread.h"
;#include "tx_timer.h"
;
;
EXTERN _tx_thread_system_stack_ptr
EXTERN _tx_initialize_unused_memory
EXTERN _tx_timer_interrupt
EXTERN __vector_table
EXTERN _tx_execution_isr_enter
EXTERN _tx_execution_isr_exit
EXTERN _tx_thread_system_stack_ptr
EXTERN _tx_initialize_unused_memory
EXTERN _tx_timer_interrupt
EXTERN __vector_table
EXTERN _tx_execution_isr_enter
EXTERN _tx_execution_isr_exit
;
;
SYSTEM_CLOCK EQU 25000000
SYSTICK_CYCLES EQU ((SYSTEM_CLOCK / 100) -1)
RSEG FREE_MEM:DATA
PUBLIC __tx_free_memory_start
__tx_free_memory_start
DS32 4
DS32 4
;
;
SECTION `.text`:CODE:NOROOT(2)
THUMB
SECTION `.text`:CODE:NOROOT(2)
THUMB
;/**************************************************************************/
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* _tx_initialize_low_level Cortex-M4/IAR */
;/* 6.0.1 */
;/* 6.0.2 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
@@ -89,20 +79,23 @@ __tx_free_memory_start
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* 08-14-2020 Scott Larson Modified comment(s), clean up */
;/* whitespace, resulting */
;/* in version 6.0.2 */
;/* */
;/**************************************************************************/
;VOID _tx_initialize_low_level(VOID)
;{
PUBLIC _tx_initialize_low_level
_tx_initialize_low_level:
;
;
; /* Ensure that interrupts are disabled. */
;
CPSID i ; Disable interrupts
;
;
; /* Set base of available memory to end of non-initialised RAM area. */
;
;
LDR r0, =__tx_free_memory_start ; Get end of non-initialized RAM area
LDR r2, =_tx_initialize_unused_memory ; Build address of unused memory pointer
STR r0, [r2, #0] ; Save first free memory address
@@ -112,13 +105,13 @@ _tx_initialize_low_level:
LDR r0, =0xE0001000 ; Build address of DWT register
LDR r1, [r0] ; Pickup the current value
ORR r1, r1, #1 ; Set the CYCCNTENA bit
STR r1, [r0] ; Enable the cycle count register
STR r1, [r0] ; Enable the cycle count register
;
; /* Setup Vector Table Offset Register. */
;
;
MOV r0, #0xE000E000 ; Build address of NVIC registers
LDR r1, =__vector_table ; Pickup address of vector table
STR r1, [r0, #0xD08] ; Set vector table address
STR r1, [r0, #0xD08] ; Set vector table address
;
; /* Set system stack pointer from vector value. */
;
@@ -149,8 +142,8 @@ _tx_initialize_low_level:
; Note: PnSV must be lowest priority, which is 0xFF
;
; /* Return to caller. */
;
BX lr
;
BX lr
;}
;
PUBLIC SysTick_Handler
@@ -173,4 +166,3 @@ SysTick_Handler:
BX LR
; }
END

5
ports/cortex_m4/iar/readme_threadx.txt
View File

@@ -214,6 +214,11 @@ For generic code revision information, please refer to the readme_threadx_generi
file, which is included in your distribution. The following details the revision
information associated with this specific port of ThreadX:
08-14-2020 ThreadX update of Cortex-M4/IAR port. The following files were
changed/added for port specific version 6.0.2:
*.s Modified comments and whitespace.
06/30/2020 Initial ThreadX 6.0.1 version for Cortex-M4 using IAR's ARM tools.

26
ports/cortex_m4/iar/src/tx_thread_context_restore.s
View File

@@ -21,33 +21,25 @@
;/**************************************************************************/
;
;
;#define TX_SOURCE_CODE
EXTERN _tx_execution_isr_exit
;
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_thread.h"
;#include "tx_timer.h"
;
;
EXTERN _tx_execution_isr_exit
;
;
SECTION `.text`:CODE:NOROOT(2)
THUMB
SECTION `.text`:CODE:NOROOT(2)
THUMB
;/**************************************************************************/
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_context_restore Cortex-M4/IAR */
;/* 6.0.1 */
;/* 6.0.2 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
;/* */
;/* DESCRIPTION */
;/* */
;/* This function is only needed for legacy applications and it should */
;/* not be called in any new development on a Cortex-M. */
;/* This function restores the interrupt context if it is processing a */
;/* nested interrupt. If not, it returns to the interrupt thread if no */
;/* preemption is necessary. Otherwise, if preemption is necessary or */
@@ -74,6 +66,9 @@
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* 08-14-2020 Scott Larson Modified comment(s), clean up */
;/* whitespace, resulting */
;/* in version 6.0.2 */
;/* */
;/**************************************************************************/
;VOID _tx_thread_context_restore(VOID)
@@ -94,5 +89,4 @@ _tx_thread_context_restore:
BX lr
;
;}
END
END

25
ports/cortex_m4/iar/src/tx_thread_context_save.s
View File

@@ -21,33 +21,25 @@
;/**************************************************************************/
;
;
;#define TX_SOURCE_CODE
EXTERN _tx_execution_isr_enter
;
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_thread.h"
;#include "tx_timer.h"
;
;
EXTERN _tx_execution_isr_enter
;
;
SECTION `.text`:CODE:NOROOT(2)
THUMB
SECTION `.text`:CODE:NOROOT(2)
THUMB
;/**************************************************************************/
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_context_save Cortex-M4/IAR */
;/* 6.0.1 */
;/* 6.0.2 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
;/* */
;/* DESCRIPTION */
;/* */
;/* This function is only needed for legacy applications and it should */
;/* not be called in any new development on a Cortex-M. */
;/* This function saves the context of an executing thread in the */
;/* beginning of interrupt processing. The function also ensures that */
;/* the system stack is used upon return to the calling ISR. */
@@ -73,6 +65,9 @@
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* 08-14-2020 Scott Larson Modified comment(s), clean up */
;/* whitespace, resulting */
;/* in version 6.0.2 */
;/* */
;/**************************************************************************/
;VOID _tx_thread_context_save(VOID)
@@ -82,7 +77,7 @@ _tx_thread_context_save:
#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
;
; /* Call the ISR enter function to indicate an ISR is starting. */
;
;
PUSH {r0, lr} ; Save return address
BL _tx_execution_isr_enter ; Call the ISR enter function
POP {r0, lr} ; Recover return address

18
ports/cortex_m4/iar/src/tx_thread_interrupt_control.s
View File

@@ -20,23 +20,15 @@
;/**************************************************************************/
;/**************************************************************************/
;
;#define TX_SOURCE_CODE
;
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_thread.h"
;
;
SECTION `.text`:CODE:NOROOT(2)
THUMB
SECTION `.text`:CODE:NOROOT(2)
THUMB
;/**************************************************************************/
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_interrupt_control Cortex-M4/IAR */
;/* 6.0.1 */
;/* 6.0.2 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
@@ -67,6 +59,9 @@
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* 08-14-2020 Scott Larson Modified comment(s), clean up */
;/* whitespace, resulting */
;/* in version 6.0.2 */
;/* */
;/**************************************************************************/
;UINT _tx_thread_interrupt_control(UINT new_posture)
@@ -83,4 +78,3 @@ _tx_thread_interrupt_control:
;
;}
END

17
ports/cortex_m4/iar/src/tx_thread_interrupt_disable.s
View File

@@ -20,23 +20,15 @@
;/**************************************************************************/
;/**************************************************************************/
;
;#define TX_SOURCE_CODE
;
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_thread.h"
;
;
SECTION `.text`:CODE:NOROOT(2)
THUMB
SECTION `.text`:CODE:NOROOT(2)
THUMB
;/**************************************************************************/
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_interrupt_restore Cortex-M4/IAR */
;/* 6.0.1 */
;/* 6.0.2 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
@@ -67,6 +59,9 @@
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* 08-14-2020 Scott Larson Modified comment(s), clean up */
;/* whitespace, resulting */
;/* in version 6.0.2 */
;/* */
;/**************************************************************************/
;UINT _tx_thread_interrupt_disable(UINT new_posture)

17
ports/cortex_m4/iar/src/tx_thread_interrupt_restore.s
View File

@@ -20,23 +20,15 @@
;/**************************************************************************/
;/**************************************************************************/
;
;#define TX_SOURCE_CODE
;
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_thread.h"
;
;
SECTION `.text`:CODE:NOROOT(2)
THUMB
SECTION `.text`:CODE:NOROOT(2)
THUMB
;/**************************************************************************/
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_interrupt_restore Cortex-M4/IAR */
;/* 6.0.1 */
;/* 6.0.2 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
@@ -67,6 +59,9 @@
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* 08-14-2020 Scott Larson Modified comment(s), clean up */
;/* whitespace, resulting */
;/* in version 6.0.2 */
;/* */
;/**************************************************************************/
;VOID _tx_thread_interrupt_restore(UINT new_posture)

67
ports/cortex_m4/iar/src/tx_thread_schedule.s
View File

@@ -21,32 +21,23 @@
;/**************************************************************************/
;
;
;#define TX_SOURCE_CODE
EXTERN _tx_thread_current_ptr
EXTERN _tx_thread_execute_ptr
EXTERN _tx_timer_time_slice
EXTERN _tx_thread_system_stack_ptr
EXTERN _tx_execution_thread_enter
EXTERN _tx_execution_thread_exit
EXTERN _tx_thread_preempt_disable
;
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_thread.h"
;#include "tx_timer.h"
;
EXTERN _tx_thread_current_ptr
EXTERN _tx_thread_execute_ptr
EXTERN _tx_timer_time_slice
EXTERN _tx_thread_system_stack_ptr
EXTERN _tx_execution_thread_enter
EXTERN _tx_execution_thread_exit
EXTERN _tx_thread_preempt_disable
;
;
SECTION `.text`:CODE:NOROOT(2)
THUMB
SECTION `.text`:CODE:NOROOT(2)
THUMB
;/**************************************************************************/
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_schedule Cortex-M4/IAR */
;/* 6.0.1 */
;/* 6.0.2 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
@@ -80,6 +71,9 @@
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* 08-14-2020 Scott Larson Modified comment(s), clean up */
;/* whitespace, resulting */
;/* in version 6.0.2 */
;/* */
;/**************************************************************************/
;VOID _tx_thread_schedule(VOID)
@@ -92,7 +86,7 @@ _tx_thread_schedule:
; from the PendSV handling routines below. */
;
; /* Clear the preempt-disable flag to enable rescheduling after initialization on Cortex-M targets. */
;
;
MOV r0, #0 ; Build value for TX_FALSE
LDR r2, =_tx_thread_preempt_disable ; Build address of preempt disable flag
STR r0, [r2, #0] ; Clear preempt disable flag
@@ -101,14 +95,14 @@ _tx_thread_schedule:
;
#ifdef __ARMVFP__
MRS r0, CONTROL ; Pickup current CONTROL register
BIC r0, r0, #4 ; Clear the FPCA bit
BIC r0, r0, #4 ; Clear the FPCA bit
MSR CONTROL, r0 ; Setup new CONTROL register
#endif
;
; /* Enable interrupts */
;
CPSIE i
;
;
; /* Enter the scheduler for the first time. */
;
MOV r0, #0x10000000 ; Load PENDSVSET bit
@@ -118,21 +112,21 @@ _tx_thread_schedule:
ISB ; Flush pipeline
;
; /* Wait here for the PendSV to take place. */
;
;
__tx_wait_here:
B __tx_wait_here ; Wait for the PendSV to happen
;}
;
; /* Generic context PendSV handler. */
;
;
PUBLIC PendSV_Handler
PUBLIC __tx_PendSVHandler
PendSV_Handler:
__tx_PendSVHandler:
;
; /* Get current thread value and new thread pointer. */
;
__tx_ts_handler:
;
__tx_ts_handler:
#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
;
@@ -150,7 +144,7 @@ __tx_ts_handler:
LDR r1, [r0] ; Pickup current thread pointer
;
; /* Determine if there is a current thread to finish preserving. */
;
;
CBZ r1, __tx_ts_new ; If NULL, skip preservation
;
; /* Recover PSP and preserve current thread context. */
@@ -181,7 +175,7 @@ _skip_vfp_save:
;
STR r3, [r4] ; Clear time-slice
;
;
;
; /* Executing thread is now completely preserved!!! */
;
__tx_ts_new:
@@ -225,7 +219,7 @@ __tx_ts_restore:
LDMIA r12!, {LR} ; Pickup LR
#ifdef __ARMVFP__
TST LR, #0x10 ; Determine if the VFP extended frame is present
BNE _skip_vfp_restore ; If not, skip VFP restore
BNE _skip_vfp_restore ; If not, skip VFP restore
VLDMIA r12!, {s16-s31} ; Yes, restore additional VFP registers
_skip_vfp_restore:
#endif
@@ -233,11 +227,11 @@ _skip_vfp_restore:
MSR PSP, r12 ; Setup the thread's stack pointer
;
; /* Return to thread. */
;
;
BX lr ; Return to thread!
;
; /* The following is the idle wait processing... in this case, no threads are ready for execution and the
; system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts
; system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts
; are disabled to allow use of WFI for waiting for a thread to arrive. */
;
__tx_ts_wait:
@@ -253,16 +247,16 @@ __tx_ts_wait:
CPSIE i ; Enable interrupts
B __tx_ts_wait ; Loop to continue waiting
;
; /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are
; /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are
; already in the handler! */
;
__tx_ts_ready:
MOV r7, #0x08000000 ; Build clear PendSV value
MOV r8, #0xE000E000 ; Build base NVIC address
STR r7, [r8, #0xD04] ; Clear any PendSV
STR r7, [r8, #0xD04] ; Clear any PendSV
;
; /* Re-enable interrupts and restore new thread. */
;
;
CPSIE i ; Enable interrupts
B __tx_ts_restore ; Restore the thread
;}
@@ -272,7 +266,7 @@ __tx_ts_ready:
PUBLIC tx_thread_fpu_enable
tx_thread_fpu_enable:
;
; /* Automatic VPF logic is supported, this function is present only for
; /* Automatic VPF logic is supported, this function is present only for
; backward compatibility purposes and therefore simply returns. */
;
BX LR ; Return to caller
@@ -280,7 +274,7 @@ tx_thread_fpu_enable:
PUBLIC tx_thread_fpu_disable
tx_thread_fpu_disable:
;
; /* Automatic VPF logic is supported, this function is present only for
; /* Automatic VPF logic is supported, this function is present only for
; backward compatibility purposes and therefore simply returns. */
;
BX LR ; Return to caller
@@ -288,4 +282,3 @@ tx_thread_fpu_disable:
#endif
END

25
ports/cortex_m4/iar/src/tx_thread_stack_build.s
View File

@@ -21,23 +21,14 @@
;/**************************************************************************/
;
;
;#define TX_SOURCE_CODE
;
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_thread.h"
;
;
SECTION `.text`:CODE:NOROOT(2)
THUMB
SECTION `.text`:CODE:NOROOT(2)
THUMB
;/**************************************************************************/
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_stack_build Cortex-M4/IAR */
;/* 6.0.1 */
;/* 6.0.2 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
@@ -70,6 +61,9 @@
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* 08-14-2020 Scott Larson Modified comment(s), clean up */
;/* whitespace, resulting */
;/* in version 6.0.2 */
;/* */
;/**************************************************************************/
;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID))
@@ -77,11 +71,11 @@
PUBLIC _tx_thread_stack_build
_tx_thread_stack_build:
;
;
;
; /* Build a fake interrupt frame. The form of the fake interrupt stack
; on the Cortex-M should look like the following after it is built:
;
; Stack Top:
;
; Stack Top:
; LR Interrupted LR (LR at time of PENDSV)
; r4 Initial value for r4
; r5 Initial value for r5
@@ -141,4 +135,3 @@ _tx_thread_stack_build:
BX lr ; Return to caller
;}
END

28
ports/cortex_m4/iar/src/tx_thread_system_return.s
View File

@@ -20,25 +20,15 @@
;/**************************************************************************/
;/**************************************************************************/
;
;#define TX_SOURCE_CODE
;
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_thread.h"
;#include "tx_timer.h"
;
;
;
SECTION `.text`:CODE:NOROOT(2)
THUMB
SECTION `.text`:CODE:NOROOT(2)
THUMB
;/**************************************************************************/
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_system_return Cortex-M4/IAR */
;/* 6.0.1 */
;/* 6.0.2 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
@@ -71,6 +61,9 @@
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* 08-14-2020 Scott Larson Modified comment(s), clean up */
;/* whitespace, resulting */
;/* in version 6.0.2 */
;/* */
;/**************************************************************************/
;VOID _tx_thread_system_return(VOID)
@@ -79,9 +72,9 @@
_tx_thread_system_return??rA:
_tx_thread_system_return:
;
; /* Return to real scheduler via PendSV. Note that this routine is often
; /* Return to real scheduler via PendSV. Note that this routine is often
; replaced with in-line assembly in tx_port.h to improved performance. */
;
;
MOV r0, #0x10000000 ; Load PENDSVSET bit
MOV r1, #0xE000E000 ; Load NVIC base
STR r0, [r1, #0xD04] ; Set PENDSVBIT in ICSR
@@ -92,7 +85,6 @@ _tx_thread_system_return:
CPSIE i ; Enable interrupts
MSR PRIMASK, r1 ; Restore original interrupt posture
_isr_context:
BX lr ; Return to caller
BX lr ; Return to caller
;}
END
END

27
ports/cortex_m4/iar/src/tx_timer_interrupt.s
View File

@@ -20,17 +20,6 @@
;/**************************************************************************/
;/**************************************************************************/
;
;#define TX_SOURCE_CODE
;
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_timer.h"
;#include "tx_thread.h"
;
;
;Define Assembly language external references...
;
EXTERN _tx_timer_time_slice
EXTERN _tx_timer_system_clock
@@ -46,14 +35,14 @@
EXTERN _tx_thread_preempt_disable
;
;
SECTION `.text`:CODE:NOROOT(2)
THUMB
SECTION `.text`:CODE:NOROOT(2)
THUMB
;/**************************************************************************/
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* _tx_timer_interrupt Cortex-M4/IAR */
;/* 6.0.1 */
;/* 6.0.2 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
@@ -87,6 +76,9 @@
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* 08-14-2020 Scott Larson Modified comment(s), clean up */
;/* whitespace, resulting */
;/* in version 6.0.2 */
;/* */
;/**************************************************************************/
;VOID _tx_timer_interrupt(VOID)
@@ -109,7 +101,7 @@ _tx_timer_interrupt:
; if (_tx_timer_time_slice)
; {
;
MOV32 r3, _tx_timer_time_slice ; Pickup address of time-slice
MOV32 r3, _tx_timer_time_slice ; Pickup address of time-slice
LDR r2, [r3, #0] ; Pickup time-slice
CBZ r2, __tx_timer_no_time_slice ; Is it non-active?
; Yes, skip time-slice processing
@@ -226,13 +218,13 @@ __tx_timer_dont_activate:
; if (_tx_timer_expired_time_slice)
; {
;
MOV32 r3, _tx_timer_expired_time_slice ; Pickup addr of time-slice expired
MOV32 r3, _tx_timer_expired_time_slice ; Pickup addr of time-slice expired
LDR r2, [r3, #0] ; Pickup the actual flag
CBZ r2, __tx_timer_not_ts_expiration ; See if the flag is set
; No, skip time-slice processing
;
; /* Time slice interrupted thread. */
; _tx_thread_time_slice();
; _tx_thread_time_slice();
BL _tx_thread_time_slice ; Call time-slice processing
MOV32 r0, _tx_thread_preempt_disable ; Build address of preempt disable flag
@@ -265,4 +257,3 @@ __tx_timer_nothing_expired:
;
;}
END