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apply 6.0.2 patch

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This commit is contained in:
Scott Larson
2020-08-14 09:10:48 -07:00
parent 6a018a4cfd
commit 40a402b827
227 changed files with 2232 additions and 3212 deletions
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52
ports/cortex_m7/ac5/example_build/tx_initialize_low_level.s
View File

@@ -20,16 +20,6 @@
;/**************************************************************************/
;/**************************************************************************/
;
;#define TX_SOURCE_CODE
;
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_initialize.h"
;#include "tx_thread.h"
;#include "tx_timer.h"
;
;
IMPORT _tx_thread_system_stack_ptr
IMPORT _tx_initialize_unused_memory
@@ -90,7 +80,7 @@ __tx_vectors
DCD __tx_IntHandler ; Int 1
DCD __tx_IntHandler ; Int 2
DCD __tx_IntHandler ; Int 3
;
;
AREA ||.text||, CODE, READONLY
@@ -99,10 +89,10 @@ Reset_Handler
CPSID i
IF {TARGET_FPU_VFP} = {TRUE}
LDR r0, =0xE000ED88 ; Pickup address of CPACR
LDR r1, [r0] ; Pickup CPACR
MOV32 r2, 0x00F00000 ; Build enable value
ORR r1, r1, r2 ; Or in enable value
STR r1, [r0] ; Setup CPACR
LDR r1, [r0] ; Pickup CPACR
MOV32 r2, 0x00F00000 ; Build enable value
ORR r1, r1, r2 ; Or in enable value
STR r1, [r0] ; Setup CPACR
ENDIF
LDR r0, =__main
BX r0
@@ -113,7 +103,7 @@ Reset_Handler
;/* FUNCTION RELEASE */
;/* */
;/* _tx_initialize_low_level Cortex-M7/AC5 */
;/* 6.0.1 */
;/* 6.0.2 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
@@ -147,6 +137,9 @@ Reset_Handler
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* 08-14-2020 Scott Larson Modified comment(s), clean up */
;/* whitespace, resulting */
;/* in version 6.0.2 */
;/* */
;/**************************************************************************/
;VOID _tx_initialize_low_level(VOID)
@@ -159,24 +152,24 @@ _tx_initialize_low_level
CPSID i
;
; /* Set base of available memory to end of non-initialised RAM area. */
;
;
LDR r0, =_tx_initialize_unused_memory ; Build address of unused memory pointer
LDR r1, =|Image$$ZI$$Limit| ; Build first free address
ADD r1, r1, #4 ;
ADD r1, r1, #4 ;
STR r1, [r0] ; Setup first unused memory pointer
;
; /* Setup Vector Table Offset Register. */
;
;
MOV r0, #0xE000E000 ; Build address of NVIC registers
LDR r1, =__tx_vectors ; Pickup address of vector table
STR r1, [r0, #0xD08] ; Set vector table address
STR r1, [r0, #0xD08] ; Set vector table address
;
; /* Enable the cycle count register. */
;
; LDR r0, =0xE0001000 ; Build address of DWT register
; LDR r1, [r0] ; Pickup the current value
; ORR r1, r1, #1 ; Set the CYCCNTENA bit
; STR r1, [r0] ; Enable the cycle count register
; STR r1, [r0] ; Enable the cycle count register
;
; /* Set system stack pointer from vector value. */
;
@@ -207,11 +200,11 @@ _tx_initialize_low_level
; Note: PnSV must be lowest priority, which is 0xFF
;
; /* Return to caller. */
;
BX lr
;
BX lr
;}
;
;
;
;/* Define initial heap/stack routine for the ARM RVCT startup code.
; This routine will set the initial stack and heap locations */
;
@@ -227,19 +220,19 @@ __user_initial_stackheap
;/* Define shells for each of the unused vectors. */
;
EXPORT __tx_BadHandler
__tx_BadHandler
__tx_BadHandler
B __tx_BadHandler
EXPORT __tx_SVCallHandler
__tx_SVCallHandler
B __tx_SVCallHandler
B __tx_SVCallHandler
EXPORT __tx_IntHandler
__tx_IntHandler
; VOID InterruptHandler (VOID)
; {
PUSH {r0, lr}
; /* Do interrupt handler work here */
; /* .... */
@@ -247,7 +240,7 @@ __tx_IntHandler
BX LR
; }
EXPORT __tx_SysTickHandler
EXPORT __tx_SysTickHandler
__tx_SysTickHandler
; VOID TimerInterruptHandler (VOID)
; {
@@ -258,7 +251,7 @@ __tx_SysTickHandler
BX LR
; }
EXPORT __tx_NMIHandler
EXPORT __tx_NMIHandler
__tx_NMIHandler
B __tx_NMIHandler
@@ -269,4 +262,3 @@ __tx_DBGHandler
ALIGN
LTORG
END

5
ports/cortex_m7/ac5/readme_threadx.txt
View File

@@ -197,6 +197,11 @@ For generic code revision information, please refer to the readme_threadx_generi
file, which is included in your distribution. The following details the revision
information associated with this specific port of ThreadX:
08-14-2020 ThreadX update of Cortex-M7/AC5 port. The following files were
changed/added for port specific version 6.0.2:
*.s Modified comments and whitespace.
06/30/2020 Initial ThreadX 6.0.1 version for Cortex-M7 using AC5 tools.

17
ports/cortex_m7/ac5/src/tx_thread_context_restore.s
View File

@@ -20,16 +20,6 @@
;/**************************************************************************/
;/**************************************************************************/
;
;
;#define TX_SOURCE_CODE
;
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_thread.h"
;#include "tx_timer.h"
;
;
IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
IMPORT _tx_execution_isr_exit
@@ -43,13 +33,15 @@
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_context_restore Cortex-M7/AC5 */
;/* 6.0.1 */
;/* 6.0.2 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
;/* */
;/* DESCRIPTION */
;/* */
;/* This function is only needed for legacy applications and it should */
;/* not be called in any new development on a Cortex-M. */
;/* This function restores the interrupt context if it is processing a */
;/* nested interrupt. If not, it returns to the interrupt thread if no */
;/* preemption is necessary. Otherwise, if preemption is necessary or */
@@ -76,6 +68,9 @@
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* 08-14-2020 Scott Larson Modified comment(s), clean up */
;/* whitespace, resulting */
;/* in version 6.0.2 */
;/* */
;/**************************************************************************/
;VOID _tx_thread_context_restore(VOID)

19
ports/cortex_m7/ac5/src/tx_thread_context_save.s
View File

@@ -20,16 +20,6 @@
;/**************************************************************************/
;/**************************************************************************/
;
;
;#define TX_SOURCE_CODE
;
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_thread.h"
;#include "tx_timer.h"
;
;
IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
IMPORT _tx_execution_isr_enter
@@ -43,13 +33,15 @@
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_context_save Cortex-M7/AC5 */
;/* 6.0.1 */
;/* 6.0.2 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
;/* */
;/* DESCRIPTION */
;/* */
;/* This function is only needed for legacy applications and it should */
;/* not be called in any new development on a Cortex-M. */
;/* This function saves the context of an executing thread in the */
;/* beginning of interrupt processing. The function also ensures that */
;/* the system stack is used upon return to the calling ISR. */
@@ -75,6 +67,9 @@
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* 08-14-2020 Scott Larson Modified comment(s), clean up */
;/* whitespace, resulting */
;/* in version 6.0.2 */
;/* */
;/**************************************************************************/
;VOID _tx_thread_context_save(VOID)
@@ -91,7 +86,7 @@ _tx_thread_context_save
ENDIF
;
; /* Return to interrupt processing. */
;
;
BX lr ; Return to interrupt processing caller
;}
ALIGN

14
ports/cortex_m7/ac5/src/tx_thread_interrupt_control.s
View File

@@ -20,14 +20,6 @@
;/**************************************************************************/
;/**************************************************************************/
;
;#define TX_SOURCE_CODE
;
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_thread.h"
;
;
AREA ||.text||, CODE, READONLY
;/**************************************************************************/
@@ -35,7 +27,7 @@
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_interrupt_control Cortex-M7/AC5 */
;/* 6.0.1 */
;/* 6.0.2 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
@@ -66,6 +58,9 @@
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* 08-14-2020 Scott Larson Modified comment(s), clean up */
;/* whitespace, resulting */
;/* in version 6.0.2 */
;/* */
;/**************************************************************************/
;UINT _tx_thread_interrupt_control(UINT new_posture)
@@ -82,4 +77,3 @@ _tx_thread_interrupt_control
;
;}
END

13
ports/cortex_m7/ac5/src/tx_thread_interrupt_disable.s
View File

@@ -20,14 +20,6 @@
;/**************************************************************************/
;/**************************************************************************/
;
;#define TX_SOURCE_CODE
;
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_thread.h"
;
;
AREA ||.text||, CODE, READONLY
;/**************************************************************************/
@@ -35,7 +27,7 @@
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_interrupt_disable Cortex-M7/AC5 */
;/* 6.0.1 */
;/* 6.0.2 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
@@ -66,6 +58,9 @@
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* 08-14-2020 Scott Larson Modified comment(s), clean up */
;/* whitespace, resulting */
;/* in version 6.0.2 */
;/* */
;/**************************************************************************/
;UINT _tx_thread_interrupt_disable(UINT new_posture)

13
ports/cortex_m7/ac5/src/tx_thread_interrupt_restore.s
View File

@@ -20,14 +20,6 @@
;/**************************************************************************/
;/**************************************************************************/
;
;#define TX_SOURCE_CODE
;
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_thread.h"
;
;
AREA ||.text||, CODE, READONLY
;/**************************************************************************/
@@ -35,7 +27,7 @@
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_interrupt_restore Cortex-M7/AC5 */
;/* 6.0.1 */
;/* 6.0.2 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
@@ -66,6 +58,9 @@
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* 08-14-2020 Scott Larson Modified comment(s), clean up */
;/* whitespace, resulting */
;/* in version 6.0.2 */
;/* */
;/**************************************************************************/
;VOID _tx_thread_interrupt_restore(UINT new_posture)

62
ports/cortex_m7/ac5/src/tx_thread_schedule.s
View File

@@ -21,15 +21,6 @@
;/**************************************************************************/
;
;
;#define TX_SOURCE_CODE
;
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_thread.h"
;#include "tx_timer.h"
;
IMPORT _tx_thread_current_ptr
IMPORT _tx_thread_execute_ptr
IMPORT _tx_timer_time_slice
@@ -37,7 +28,7 @@
IMPORT _tx_thread_preempt_disable
IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
IMPORT _tx_execution_thread_enter
IMPORT _tx_execution_thread_exit
IMPORT _tx_execution_thread_exit
ENDIF
;
;
@@ -48,7 +39,7 @@
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_schedule Cortex-M7/AC5 */
;/* 6.0.1 */
;/* 6.0.2 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
@@ -82,6 +73,9 @@
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* 08-14-2020 Scott Larson Modified comment(s), clean up */
;/* whitespace, resulting */
;/* in version 6.0.2 */
;/* */
;/**************************************************************************/
;VOID _tx_thread_schedule(VOID)
@@ -94,7 +88,7 @@ _tx_thread_schedule
; from the PendSV handling routines below. */
;
; /* Clear the preempt-disable flag to enable rescheduling after initialization on Cortex-M targets. */
;
;
MOV r0, #0 ; Build value for TX_FALSE
LDR r2, =_tx_thread_preempt_disable ; Build address of preempt disable flag
STR r0, [r2, #0] ; Clear preempt disable flag
@@ -103,14 +97,14 @@ _tx_thread_schedule
;
IF {TARGET_FPU_VFP} = {TRUE}
MRS r0, CONTROL ; Pickup current CONTROL register
BIC r0, r0, #4 ; Clear the FPCA bit
BIC r0, r0, #4 ; Clear the FPCA bit
MSR CONTROL, r0 ; Setup new CONTROL register
ENDIF
;
; /* Enable the interrupts */
;
CPSIE i
;
;
; /* Enter the scheduler for the first time. */
;
MOV r0, #0x10000000 ; Load PENDSVSET bit
@@ -120,21 +114,21 @@ _tx_thread_schedule
ISB ; Flush pipeline
;
; /* Wait here for the PendSV to take place. */
;
;
__tx_wait_here
B __tx_wait_here ; Wait for the PendSV to happen
;}
;
; /* Generic context switching PendSV handler. */
;
;
EXPORT __tx_PendSVHandler
EXPORT PendSV_Handler
__tx_PendSVHandler
__tx_PendSVHandler
PendSV_Handler
;
; /* Get current thread value and new thread pointer. */
;
__tx_ts_handler
;
__tx_ts_handler
IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
;
@@ -152,7 +146,7 @@ __tx_ts_handler
LDR r1, [r0] ; Pickup current thread pointer
;
; /* Determine if there is a current thread to finish preserving. */
;
;
CBZ r1, __tx_ts_new ; If NULL, skip preservation
;
; /* Recover PSP and preserve current thread context. */
@@ -182,10 +176,10 @@ _skip_vfp_save
; /* Clear the global time-slice. */
;
STR r3, [r4] ; Clear time-slice
;
;
; /* Executing thread is now completely preserved!!! */
;
__tx_ts_new
__tx_ts_new
;
; /* Now we are looking for a new thread to execute! */
;
@@ -200,7 +194,7 @@ __tx_ts_new
;
; /* Increment the thread run count. */
;
__tx_ts_restore
__tx_ts_restore
LDR r7, [r1, #4] ; Pickup the current thread run count
MOV32 r4, _tx_timer_time_slice ; Build address of time-slice variable
LDR r5, [r1, #24] ; Pickup thread's current time-slice
@@ -226,7 +220,7 @@ __tx_ts_restore
LDMIA r12!, {LR} ; Pickup LR
IF {TARGET_FPU_VFP} = {TRUE}
TST LR, #0x10 ; Determine if the VFP extended frame is present
BNE _skip_vfp_restore ; If not, skip VFP restore
BNE _skip_vfp_restore ; If not, skip VFP restore
VLDMIA r12!, {s16-s31} ; Yes, restore additional VFP registers
_skip_vfp_restore
ENDIF
@@ -234,14 +228,14 @@ _skip_vfp_restore
MSR PSP, r12 ; Setup the thread's stack pointer
;
; /* Return to thread. */
;
;
BX lr ; Return to thread!
;
; /* The following is the idle wait processing... in this case, no threads are ready for execution and the
; system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts
; system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts
; are disabled to allow use of WFI for waiting for a thread to arrive. */
;
__tx_ts_wait
__tx_ts_wait
CPSID i ; Disable interrupts
LDR r1, [r2] ; Pickup the next thread to execute pointer
STR r1, [r0] ; Store it in the current pointer
@@ -254,16 +248,16 @@ __tx_ts_wait
CPSIE i ; Enable interrupts
B __tx_ts_wait ; Loop to continue waiting
;
; /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are
; /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are
; already in the handler! */
;
__tx_ts_ready
__tx_ts_ready
MOV r7, #0x08000000 ; Build clear PendSV value
MOV r8, #0xE000E000 ; Build base NVIC address
STR r7, [r8, #0xD04] ; Clear any PendSV
STR r7, [r8, #0xD04] ; Clear any PendSV
;
; /* Re-enable interrupts and restore new thread. */
;
;
CPSIE i ; Enable interrupts
B __tx_ts_restore ; Restore the thread
@@ -271,7 +265,7 @@ __tx_ts_ready
EXPORT tx_thread_fpu_enable
tx_thread_fpu_enable
;
; /* Automatic VPF logic is supported, this function is present only for
; /* Automatic VPF logic is supported, this function is present only for
; backward compatibility purposes and therefore simply returns. */
;
BX LR ; Return to caller
@@ -279,7 +273,7 @@ tx_thread_fpu_enable
EXPORT tx_thread_fpu_disable
tx_thread_fpu_disable
;
; /* Automatic VPF logic is supported, this function is present only for
; /* Automatic VPF logic is supported, this function is present only for
; backward compatibility purposes and therefore simply returns. */
;
BX LR ; Return to caller
@@ -289,10 +283,8 @@ _tx_vfp_access
VMOV.F32 s0, s0 ; Simply access the VFP
BX lr ; Return to caller
ENDIF
ALIGN
LTORG
END

23
ports/cortex_m7/ac5/src/tx_thread_stack_build.s
View File

@@ -20,15 +20,6 @@
;/**************************************************************************/
;/**************************************************************************/
;
;
;#define TX_SOURCE_CODE
;
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_thread.h"
;
;
AREA ||.text||, CODE, READONLY
;/**************************************************************************/
@@ -36,7 +27,7 @@
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_stack_build Cortex-M7/AC5 */
;/* 6.0.1 */
;/* 6.0.2 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
@@ -69,6 +60,9 @@
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* 08-14-2020 Scott Larson Modified comment(s), clean up */
;/* whitespace, resulting */
;/* in version 6.0.2 */
;/* */
;/**************************************************************************/
;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID))
@@ -76,11 +70,11 @@
EXPORT _tx_thread_stack_build
_tx_thread_stack_build
;
;
;
; /* Build a fake interrupt frame. The form of the fake interrupt stack
; on the Cortex-M7 should look like the following after it is built:
;
; Stack Top:
;
; Stack Top:
; LR Interrupted LR (LR at time of PENDSV)
; r4 Initial value for r4
; r5 Initial value for r5
@@ -119,7 +113,7 @@ _tx_thread_stack_build
STR r3, [r2, #28] ; Store initial r10
STR r3, [r2, #32] ; Store initial r11
;
; /* Hardware stack follows. /
; /* Hardware stack follows. */
;
STR r3, [r2, #36] ; Store initial r0
STR r3, [r2, #40] ; Store initial r1
@@ -140,4 +134,3 @@ _tx_thread_stack_build
BX lr ; Return to caller
;}
END

24
ports/cortex_m7/ac5/src/tx_thread_system_return.s
View File

@@ -20,16 +20,6 @@
;/**************************************************************************/
;/**************************************************************************/
;
;#define TX_SOURCE_CODE
;
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_thread.h"
;#include "tx_timer.h"
;
;
;
AREA ||.text||, CODE, READONLY
;/**************************************************************************/
@@ -37,7 +27,7 @@
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_system_return Cortex-M7/AC5 */
;/* 6.0.1 */
;/* 6.0.2 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
@@ -70,6 +60,9 @@
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* 08-14-2020 Scott Larson Modified comment(s), clean up */
;/* whitespace, resulting */
;/* in version 6.0.2 */
;/* */
;/**************************************************************************/
;VOID _tx_thread_system_return(VOID)
@@ -77,9 +70,9 @@
EXPORT _tx_thread_system_return
_tx_thread_system_return
;
; /* Return to real scheduler via PendSV. Note that this routine is often
; /* Return to real scheduler via PendSV. Note that this routine is often
; replaced with in-line assembly in tx_port.h to improved performance. */
;
;
MOV r0, #0x10000000 ; Load PENDSVSET bit
MOV r1, #0xE000E000 ; Load NVIC base
STR r0, [r1, #0xD04] ; Set PENDSVBIT in ICSR
@@ -90,7 +83,6 @@ _tx_thread_system_return
CPSIE i ; Enable interrupts
MSR PRIMASK, r1 ; Restore original interrupt posture
_isr_context
BX lr ; Return to caller
BX lr ; Return to caller
;}
END
END

23
ports/cortex_m7/ac5/src/tx_timer_interrupt.s
View File

@@ -20,17 +20,6 @@
;/**************************************************************************/
;/**************************************************************************/
;
;#define TX_SOURCE_CODE
;
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_timer.h"
;#include "tx_thread.h"
;
;
;Define Assembly language external references...
;
IMPORT _tx_timer_time_slice
IMPORT _tx_timer_system_clock
@@ -53,7 +42,7 @@
;/* FUNCTION RELEASE */
;/* */
;/* _tx_timer_interrupt Cortex-M7/AC5 */
;/* 6.0.1 */
;/* 6.0.2 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
@@ -88,6 +77,9 @@
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* 08-14-2020 Scott Larson Modified comment(s), clean up */
;/* whitespace, resulting */
;/* in version 6.0.2 */
;/* */
;/**************************************************************************/
;VOID _tx_timer_interrupt(VOID)
@@ -111,7 +103,7 @@ _tx_timer_interrupt
; if (_tx_timer_time_slice)
; {
;
MOV32 r3, _tx_timer_time_slice ; Pickup address of time-slice
MOV32 r3, _tx_timer_time_slice ; Pickup address of time-slice
LDR r2, [r3, #0] ; Pickup time-slice
CBZ r2, __tx_timer_no_time_slice ; Is it non-active?
; Yes, skip time-slice processing
@@ -228,13 +220,13 @@ __tx_timer_dont_activate
; if (_tx_timer_expired_time_slice)
; {
;
MOV32 r3, _tx_timer_expired_time_slice ; Pickup addr of time-slice expired
MOV32 r3, _tx_timer_expired_time_slice ; Pickup addr of time-slice expired
LDR r2, [r3, #0] ; Pickup the actual flag
CBZ r2, __tx_timer_not_ts_expiration ; See if the flag is set
; No, skip time-slice processing
;
; /* Time slice interrupted thread. */
; _tx_thread_time_slice();
; _tx_thread_time_slice();
BL _tx_thread_time_slice ; Call time-slice processing
MOV32 r0, _tx_thread_preempt_disable ; Build address of preempt disable flag
@@ -268,4 +260,3 @@ __tx_timer_nothing_expired
ALIGN
LTORG
END

34
ports/cortex_m7/ac6/example_build/sample_threadx/tx_initialize_low_level.S
View File

@@ -20,16 +20,6 @@
@/**************************************************************************/
@/**************************************************************************/
@
@#define TX_SOURCE_CODE
@
@
@/* Include necessary system files. */
@
@#include "tx_api.h"
@#include "tx_initialize.h"
@#include "tx_thread.h"
@#include "tx_timer.h"
@
@
.global _tx_thread_system_stack_ptr
.global _tx_initialize_unused_memory
@@ -57,7 +47,7 @@ SYSTICK_CYCLES = ((SYSTEM_CLOCK / 100) -1)
@/* FUNCTION RELEASE */
@/* */
@/* _tx_initialize_low_level Cortex-M7/AC6 */
@/* 6.0.1 */
@/* 6.0.2 */
@/* AUTHOR */
@/* */
@/* William E. Lamie, Microsoft Corporation */
@@ -91,6 +81,9 @@ SYSTICK_CYCLES = ((SYSTEM_CLOCK / 100) -1)
@/* DATE NAME DESCRIPTION */
@/* */
@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
@/* 08-14-2020 Scott Larson Modified comment(s), clean up */
@/* whitespace, resulting */
@/* in version 6.0.2 */
@/* */
@/**************************************************************************/
@VOID _tx_initialize_low_level(VOID)
@@ -104,17 +97,17 @@ _tx_initialize_low_level:
CPSID i
@
@ /* Set base of available memory to end of non-initialised RAM area. */
@
@
LDR r0, =_tx_initialize_unused_memory @ Build address of unused memory pointer
LDR r1, =Image$$ARM_LIB_STACKHEAP$$ZI$$Limit @ Build first free address
ADD r1, r1, #4 @
ADD r1, r1, #4 @
STR r1, [r0] @ Setup first unused memory pointer
@
@ /* Setup Vector Table Offset Register. */
@
@
MOV r0, #0xE000E000 @ Build address of NVIC registers
LDR r1, =vector_table @ Pickup address of vector table
STR r1, [r0, #0xD08] @ Set vector table address
STR r1, [r0, #0xD08] @ Set vector table address
@
@ /* Set system stack pointer from vector value. */
@
@@ -128,7 +121,7 @@ _tx_initialize_low_level:
LDR r0, =0xE0001000 @ Build address of DWT register
LDR r1, [r0] @ Pickup the current value
ORR r1, r1, #1 @ Set the CYCCNTENA bit
STR r1, [r0] @ Enable the cycle count register
STR r1, [r0] @ Enable the cycle count register
@
@ /* Configure SysTick for 100Hz clock, or 16384 cycles if no reference. */
@
@@ -150,11 +143,10 @@ _tx_initialize_low_level:
LDR r1, =0x40FF0000 @ SysT, PnSV, Rsrv, DbgM
STR r1, [r0, #0xD20] @ Setup System Handlers 12-15 Priority Registers
@ Note: PnSV must be lowest priority, which is 0xFF
@
@ /* Return to caller. */
@
BX lr
@
BX lr
@}
@
@@ -190,7 +182,7 @@ __tx_IntHandler:
PUSH {r0, lr}
#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
BL _tx_execution_isr_enter @ Call the ISR enter function
#endif
#endif
@ /* Do interrupt handler work here */
@ /* BL <your C Function>.... */
@@ -226,7 +218,7 @@ SysTick_Handler:
@ /* NMI, DBG handlers */
.global __tx_NMIHandler
.global __tx_NMIHandler
.thumb_func
__tx_NMIHandler:
B __tx_NMIHandler

5
ports/cortex_m7/ac6/readme_threadx.txt
View File

@@ -144,6 +144,11 @@ For generic code revision information, please refer to the readme_threadx_generi
file, which is included in your distribution. The following details the revision
information associated with this specific port of ThreadX:
08-14-2020 ThreadX update of Cortex-M7/AC6 port. The following files were
changed/added for port specific version 6.0.2:
*.s Modified comments and whitespace.
06/30/2020 Initial ThreadX 6.0.1 version for Cortex-M7 using AC6 tools.

18
ports/cortex_m7/ac6/src/tx_thread_context_restore.S
View File

@@ -20,16 +20,6 @@
@/**************************************************************************/
@/**************************************************************************/
@
@
@#define TX_SOURCE_CODE
@
@
@/* Include necessary system files. */
@
@#include "tx_api.h"
@#include "tx_thread.h"
@#include "tx_timer.h"
@
@
.global _tx_thread_system_state
.global _tx_thread_current_ptr
@@ -48,13 +38,15 @@
@/* FUNCTION RELEASE */
@/* */
@/* _tx_thread_context_restore Cortex-M7/AC6 */
@/* 6.0.1 */
@/* 6.0.2 */
@/* AUTHOR */
@/* */
@/* William E. Lamie, Microsoft Corporation */
@/* */
@/* DESCRIPTION */
@/* */
@/* This function is only needed for legacy applications and it should */
@/* not be called in any new development on a Cortex-M. */
@/* This function restores the interrupt context if it is processing a */
@/* nested interrupt. If not, it returns to the interrupt thread if no */
@/* preemption is necessary. Otherwise, if preemption is necessary or */
@@ -81,6 +73,9 @@
@/* DATE NAME DESCRIPTION */
@/* */
@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
@/* 08-14-2020 Scott Larson Modified comment(s), clean up */
@/* whitespace, resulting */
@/* in version 6.0.2 */
@/* */
@/**************************************************************************/
@VOID _tx_thread_context_restore(VOID)
@@ -92,4 +87,3 @@ _tx_thread_context_restore:
@ /* Not needed for this port - just return! */
BX lr
@}

17
ports/cortex_m7/ac6/src/tx_thread_context_save.S
View File

@@ -20,16 +20,6 @@
@/**************************************************************************/
@/**************************************************************************/
@
@
@#define TX_SOURCE_CODE
@
@
@/* Include necessary system files. */
@
@#include "tx_api.h"
@#include "tx_thread.h"
@#include "tx_timer.h"
@
@
.global _tx_thread_system_state
.global _tx_thread_current_ptr
@@ -43,13 +33,15 @@
@/* FUNCTION RELEASE */
@/* */
@/* _tx_thread_context_save Cortex-M7/AC6 */
@/* 6.0.1 */
@/* 6.0.2 */
@/* AUTHOR */
@/* */
@/* William E. Lamie, Microsoft Corporation */
@/* */
@/* DESCRIPTION */
@/* */
@/* This function is only needed for legacy applications and it should */
@/* not be called in any new development on a Cortex-M. */
@/* This function saves the context of an executing thread in the */
@/* beginning of interrupt processing. The function also ensures that */
@/* the system stack is used upon return to the calling ISR. */
@@ -75,6 +67,9 @@
@/* DATE NAME DESCRIPTION */
@/* */
@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
@/* 08-14-2020 Scott Larson Modified comment(s), clean up */
@/* whitespace, resulting */
@/* in version 6.0.2 */
@/* */
@/**************************************************************************/
@VOID _tx_thread_context_save(VOID)

17
ports/cortex_m7/ac6/src/tx_thread_interrupt_control.S
View File

@@ -20,15 +20,6 @@
@/**************************************************************************/
@/**************************************************************************/
@/* #define TX_SOURCE_CODE */
@/* Include necessary system files. */
@/* #include "tx_api.h"
#include "tx_thread.h" */
.text 32
.align 4
.syntax unified
@@ -37,7 +28,7 @@
@/* FUNCTION RELEASE */
@/* */
@/* _tx_thread_interrupt_control Cortex-M7/AC6 */
@/* 6.0.1 */
@/* 6.0.2 */
@/* AUTHOR */
@/* */
@/* William E. Lamie, Microsoft Corporation */
@@ -68,6 +59,9 @@
@/* DATE NAME DESCRIPTION */
@/* */
@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
@/* 08-14-2020 Scott Larson Modified comment(s), clean up */
@/* whitespace, resulting */
@/* in version 6.0.2 */
@/* */
@/**************************************************************************/
@/* UINT _tx_thread_interrupt_control(UINT new_posture)
@@ -87,6 +81,3 @@ _tx_thread_interrupt_control:
BX lr @ Return to caller
@/* } */

60
ports/cortex_m7/ac6/src/tx_thread_schedule.S
View File

@@ -21,15 +21,6 @@
@/**************************************************************************/
@
@
@#define TX_SOURCE_CODE
@
@
@/* Include necessary system files. */
@
@#include "tx_api.h"
@#include "tx_thread.h"
@#include "tx_timer.h"
@
.global _tx_thread_current_ptr
.global _tx_thread_execute_ptr
.global _tx_timer_time_slice
@@ -44,7 +35,7 @@
@/* FUNCTION RELEASE */
@/* */
@/* _tx_thread_schedule Cortex-M7/AC6 */
@/* 6.0.1 */
@/* 6.0.2 */
@/* AUTHOR */
@/* */
@/* William E. Lamie, Microsoft Corporation */
@@ -78,6 +69,9 @@
@/* DATE NAME DESCRIPTION */
@/* */
@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
@/* 08-14-2020 Scott Larson Modified comment(s), clean up */
@/* whitespace, resulting */
@/* in version 6.0.2 */
@/* */
@/**************************************************************************/
@VOID _tx_thread_schedule(VOID)
@@ -91,7 +85,7 @@ _tx_thread_schedule:
@ from the PendSV handling routines below. */
@
@ /* Clear the preempt-disable flag to enable rescheduling after initialization on Cortex-M targets. */
@
@
MOV r0, #0 @ Build value for TX_FALSE
LDR r2, =_tx_thread_preempt_disable @ Build address of preempt disable flag
STR r0, [r2, #0] @ Clear preempt disable flag
@@ -100,14 +94,14 @@ _tx_thread_schedule:
@
#ifdef TX_ENABLE_FPU_SUPPORT
MRS r0, CONTROL @ Pickup current CONTROL register
BIC r0, r0, #4 @ Clear the FPCA bit
BIC r0, r0, #4 @ Clear the FPCA bit
MSR CONTROL, r0 @ Setup new CONTROL register
#endif
@
@ /* Enable interrupts */
@
CPSIE i
@
@
@ /* Enter the scheduler for the first time. */
@
MOV r0, #0x10000000 @ Load PENDSVSET bit
@@ -117,14 +111,14 @@ _tx_thread_schedule:
ISB @ Flush pipeline
@
@ /* Wait here for the PendSV to take place. */
@
@
__tx_wait_here:
B __tx_wait_here @ Wait for the PendSV to happen
@}
@
@ /* Generic context switch-out switch-in handler... Note that this handler is
@ /* Generic context switch-out switch-in handler... Note that this handler is
@ common for both PendSV and SVCall. */
@
@
.global PendSV_Handler
.global __tx_PendSVHandler
.thumb_func
@@ -133,8 +127,8 @@ PendSV_Handler:
__tx_PendSVHandler:
@
@ /* Get current thread value and new thread pointer. */
@
__tx_ts_handler:
@
__tx_ts_handler:
#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
@
@@ -152,7 +146,7 @@ __tx_ts_handler:
LDR r1, [r0] @ Pickup current thread pointer
@
@ /* Determine if there is a current thread to finish preserving. */
@
@
CBZ r1, __tx_ts_new @ If NULL, skip preservation
@
@ /* Recover PSP and preserve current thread context. */
@@ -183,7 +177,6 @@ _skip_vfp_save:
@
STR r3, [r4] @ Clear time-slice
@
@
@ /* Executing thread is now completely preserved!!! */
@
__tx_ts_new:
@@ -227,7 +220,7 @@ __tx_ts_restore:
LDMIA r12!, {LR} @ Pickup LR
#ifdef TX_ENABLE_FPU_SUPPORT
TST LR, #0x10 @ Determine if the VFP extended frame is present
BNE _skip_vfp_restore @ If not, skip VFP restore
BNE _skip_vfp_restore @ If not, skip VFP restore
VLDMIA r12!, {s16-s31} @ Yes, restore additional VFP registers
_skip_vfp_restore:
#endif
@@ -235,11 +228,11 @@ _skip_vfp_restore:
MSR PSP, r12 @ Setup the thread's stack pointer
@
@ /* Return to thread. */
@
@
BX lr @ Return to thread!
@
@ /* The following is the idle wait processing... in this case, no threads are ready for execution and the
@ system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts
@ system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts
@ are disabled to allow use of WFI for waiting for a thread to arrive. */
@
__tx_ts_wait:
@@ -255,40 +248,37 @@ __tx_ts_wait:
CPSIE i @ Enable interrupts
B __tx_ts_wait @ Loop to continue waiting
@
@ /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are
@ /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are
@ already in the handler! */
@
__tx_ts_ready:
MOV r7, #0x08000000 @ Build clear PendSV value
MOV r8, #0xE000E000 @ Build base NVIC address
STR r7, [r8, #0xD04] @ Clear any PendSV
STR r7, [r8, #0xD04] @ Clear any PendSV
@
@ /* Re-enable interrupts and restore new thread. */
@
@
CPSIE i @ Enable interrupts
B __tx_ts_restore @ Restore the thread
#ifdef TX_ENABLE_FPU_SUPPORT
.global tx_thread_fpu_enable
.thumb_func
.global tx_thread_fpu_enable
.thumb_func
tx_thread_fpu_enable:
@
@ /* Automatic VPF logic is supported, this function is present only for
@ /* Automatic VPF logic is supported, this function is present only for
@ backward compatibility purposes and therefore simply returns. */
@
BX LR @ Return to caller
.global tx_thread_fpu_disable
.thumb_func
.global tx_thread_fpu_disable
.thumb_func
tx_thread_fpu_disable:
@
@ /* Automatic VPF logic is supported, this function is present only for
@ /* Automatic VPF logic is supported, this function is present only for
@ backward compatibility purposes and therefore simply returns. */
@
BX LR @ Return to caller
#endif

22
ports/cortex_m7/ac6/src/tx_thread_stack_build.S
View File

@@ -20,15 +20,6 @@
@/**************************************************************************/
@/**************************************************************************/
@
@
@#define TX_SOURCE_CODE
@
@
@/* Include necessary system files. */
@
@#include "tx_api.h"
@#include "tx_thread.h"
@
@
.text
.align 4
@@ -38,7 +29,7 @@
@/* FUNCTION RELEASE */
@/* */
@/* _tx_thread_stack_build Cortex-M7/AC6 */
@/* 6.0.1 */
@/* 6.0.2 */
@/* AUTHOR */
@/* */
@/* William E. Lamie, Microsoft Corporation */
@@ -71,6 +62,9 @@
@/* DATE NAME DESCRIPTION */
@/* */
@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
@/* 08-14-2020 Scott Larson Modified comment(s), clean up */
@/* whitespace, resulting */
@/* in version 6.0.2 */
@/* */
@/**************************************************************************/
@VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID))
@@ -79,11 +73,11 @@
.thumb_func
_tx_thread_stack_build:
@
@
@
@ /* Build a fake interrupt frame. The form of the fake interrupt stack
@ on the Cortex-M7 should look like the following after it is built:
@
@ Stack Top:
@
@ Stack Top:
@ LR Interrupted LR (LR at time of PENDSV)
@ r4 Initial value for r4
@ r5 Initial value for r5
@@ -142,5 +136,3 @@ _tx_thread_stack_build:
@ control block
BX lr @ Return to caller
@}

21
ports/cortex_m7/ac6/src/tx_thread_system_return.S
View File

@@ -19,15 +19,6 @@
@/** */
@/**************************************************************************/
@/**************************************************************************/
@
@/* #define TX_SOURCE_CODE */
@
@
@/* Include necessary system files. */
@
@/* #include "tx_api.h"
@ #include "tx_thread.h"
@ #include "tx_timer.h" */
.text 32
@@ -38,7 +29,7 @@
@/* FUNCTION RELEASE */
@/* */
@/* _tx_thread_system_return Cortex-M7/AC6 */
@/* 6.0.1 */
@/* 6.0.2 */
@/* AUTHOR */
@/* */
@/* William E. Lamie, Microsoft Corporation */
@@ -71,6 +62,9 @@
@/* DATE NAME DESCRIPTION */
@/* */
@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
@/* 08-14-2020 Scott Larson Modified comment(s), clean up */
@/* whitespace, resulting */
@/* in version 6.0.2 */
@/* */
@/**************************************************************************/
@/* VOID _tx_thread_system_return(VOID)
@@ -79,9 +73,9 @@
.global _tx_thread_system_return
_tx_thread_system_return:
@
@ /* Return to real scheduler via PendSV. Note that this routine is often
@ /* Return to real scheduler via PendSV. Note that this routine is often
@ replaced with in-line assembly in tx_port.h to improved performance. */
@
@
MOV r0, #0x10000000 @ Load PENDSVSET bit
MOV r1, #0xE000E000 @ Load NVIC base
STR r0, [r1, #0xD04] @ Set PENDSVBIT in ICSR
@@ -92,7 +86,6 @@ _tx_thread_system_return:
CPSIE i @ Enable interrupts
MSR PRIMASK, r1 @ Restore original interrupt posture
_isr_context:
BX lr @ Return to caller
BX lr @ Return to caller
@/* } */

24
ports/cortex_m7/ac6/src/tx_timer_interrupt.S
View File

@@ -20,17 +20,6 @@
@/**************************************************************************/
@/**************************************************************************/
@
@#define TX_SOURCE_CODE
@
@
@/* Include necessary system files. */
@
@#include "tx_api.h"
@#include "tx_timer.h"
@#include "tx_thread.h"
@
@
@Define Assembly language external references...
@
.global _tx_timer_time_slice
.global _tx_timer_system_clock
@@ -51,7 +40,7 @@
@/* FUNCTION RELEASE */
@/* */
@/* _tx_timer_interrupt Cortex-M7/AC6 */
@/* 6.0.1 */
@/* 6.0.2 */
@/* AUTHOR */
@/* */
@/* William E. Lamie, Microsoft Corporation */
@@ -86,6 +75,9 @@
@/* DATE NAME DESCRIPTION */
@/* */
@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
@/* 08-14-2020 Scott Larson Modified comment(s), clean up */
@/* whitespace, resulting */
@/* in version 6.0.2 */
@/* */
@/**************************************************************************/
@VOID _tx_timer_interrupt(VOID)
@@ -110,7 +102,7 @@ _tx_timer_interrupt:
@ if (_tx_timer_time_slice)
@ {
@
LDR r3, =_tx_timer_time_slice @ Pickup address of time-slice
LDR r3, =_tx_timer_time_slice @ Pickup address of time-slice
LDR r2, [r3, #0] @ Pickup time-slice
CMP r2, #0 @ Is it non-active?
BEQ __tx_timer_no_time_slice @ Yes, skip time-slice processing
@@ -228,13 +220,13 @@ __tx_timer_dont_activate:
@ if (_tx_timer_expired_time_slice)
@ {
@
LDR r3, =_tx_timer_expired_time_slice @ Pickup addr of time-slice expired
LDR r3, =_tx_timer_expired_time_slice @ Pickup addr of time-slice expired
LDR r2, [r3, #0] @ Pickup the actual flag
CMP r2, #0 @ See if the flag is set
BEQ __tx_timer_not_ts_expiration @ No, skip time-slice processing
@
@ /* Time slice interrupted thread. */
@ _tx_thread_time_slice();
@ _tx_thread_time_slice();
@
BL _tx_thread_time_slice @ Call time-slice processing
LDR r0, =_tx_thread_preempt_disable @ Build address of preempt disable flag
@@ -266,5 +258,3 @@ __tx_timer_nothing_expired:
BX lr @ Return to caller
@
@}

38
ports/cortex_m7/gnu/example_build/tx_initialize_low_level.S
View File

@@ -20,16 +20,6 @@
@/**************************************************************************/
@/**************************************************************************/
@
@#define TX_SOURCE_CODE
@
@
@/* Include necessary system files. */
@
@#include "tx_api.h"
@#include "tx_initialize.h"
@#include "tx_thread.h"
@#include "tx_timer.h"
@
@
.global _tx_thread_system_stack_ptr
.global _tx_initialize_unused_memory
@@ -59,7 +49,7 @@ SYSTICK_CYCLES = ((SYSTEM_CLOCK / 100) -1)
@/* FUNCTION RELEASE */
@/* */
@/* _tx_initialize_low_level Cortex-M7/GNU */
@/* 6.0.1 */
@/* 6.0.2 */
@/* AUTHOR */
@/* */
@/* William E. Lamie, Microsoft Corporation */
@@ -96,6 +86,9 @@ SYSTICK_CYCLES = ((SYSTEM_CLOCK / 100) -1)
@/* 06-30-2020 William E. Lamie Modified Comment(s), fixed */
@/* GNU assembly comment, */
@/* resulting in version 6.0.1 */
@/* 08-14-2020 William E. Lamie Modified Comment(s), clean */
@/* up whitespace, resulting */
@/* in version 6.0.2 */
@/* */
@/**************************************************************************/
@VOID _tx_initialize_low_level(VOID)
@@ -109,17 +102,17 @@ _tx_initialize_low_level:
CPSID i
@
@ /* Set base of available memory to end of non-initialised RAM area. */
@
@
LDR r0, =_tx_initialize_unused_memory @ Build address of unused memory pointer
LDR r1, =__RAM_segment_used_end__ @ Build first free address
ADD r1, r1, #4 @
LDR r1, =__RAM_segment_used_end__ @ Build first free address
ADD r1, r1, #4 @
STR r1, [r0] @ Setup first unused memory pointer
@
@ /* Setup Vector Table Offset Register. */
@
@
MOV r0, #0xE000E000 @ Build address of NVIC registers
LDR r1, =_vectors @ Pickup address of vector table
STR r1, [r0, #0xD08] @ Set vector table address
LDR r1, =_vectors @ Pickup address of vector table
STR r1, [r0, #0xD08] @ Set vector table address
@
@ /* Set system stack pointer from vector value. */
@
@@ -133,7 +126,7 @@ _tx_initialize_low_level:
LDR r0, =0xE0001000 @ Build address of DWT register
LDR r1, [r0] @ Pickup the current value
ORR r1, r1, #1 @ Set the CYCCNTENA bit
STR r1, [r0] @ Enable the cycle count register
STR r1, [r0] @ Enable the cycle count register
@
@ /* Configure SysTick for 100Hz clock, or 16384 cycles if no reference. */
@
@@ -155,11 +148,10 @@ _tx_initialize_low_level:
LDR r1, =0x40FF0000 @ SysT, PnSV, Rsrv, DbgM
STR r1, [r0, #0xD20] @ Setup System Handlers 12-15 Priority Registers
@ Note: PnSV must be lowest priority, which is 0xFF
@
@ /* Return to caller. */
@
BX lr
@
BX lr
@}
@
@@ -195,7 +187,7 @@ __tx_IntHandler:
PUSH {r0, lr}
#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
BL _tx_execution_isr_enter @ Call the ISR enter function
#endif
#endif
@ /* Do interrupt handler work here */
@ /* BL <your C Function>.... */
@@ -231,7 +223,7 @@ SysTick_Handler:
@ /* NMI, DBG handlers */
.global __tx_NMIHandler
.global __tx_NMIHandler
.thumb_func
__tx_NMIHandler:
B __tx_NMIHandler

5
ports/cortex_m7/gnu/readme_threadx.txt
View File

@@ -141,6 +141,11 @@ For generic code revision information, please refer to the readme_threadx_generi
file, which is included in your distribution. The following details the revision
information associated with this specific port of ThreadX:
08-14-2020 ThreadX update of Cortex-M7/GNU port. The following files were
changed/added for port specific version 6.0.2:
*.S Modified comments and whitespace.
05/19/2020 Initial ThreadX 6.0 version for Cortex-M7 using GNU tools.

28
ports/cortex_m7/gnu/src/tx_thread_context_restore.S
View File

@@ -20,26 +20,6 @@
@/**************************************************************************/
@/**************************************************************************/
@
@
@#define TX_SOURCE_CODE
@
@
@/* Include necessary system files. */
@
@#include "tx_api.h"
@#include "tx_thread.h"
@#include "tx_timer.h"
@
@
.global _tx_thread_system_state
.global _tx_thread_current_ptr
.global _tx_thread_system_stack_ptr
.global _tx_thread_execute_ptr
.global _tx_timer_time_slice
.global _tx_thread_schedule
.global _tx_thread_preempt_disable
.global _tx_execution_isr_exit
@
@
.text
.align 4
@@ -49,13 +29,15 @@
@/* FUNCTION RELEASE */
@/* */
@/* _tx_thread_context_restore Cortex-M7/GNU */
@/* 6.0 */
@/* 6.0.2 */
@/* AUTHOR */
@/* */
@/* William E. Lamie, Microsoft Corporation */
@/* */
@/* DESCRIPTION */
@/* */
@/* This function is only needed for legacy applications and it should */
@/* not be called in any new development on a Cortex-M. */
@/* This function restores the interrupt context if it is processing a */
@/* nested interrupt. If not, it returns to the interrupt thread if no */
@/* preemption is necessary. Otherwise, if preemption is necessary or */
@@ -82,6 +64,9 @@
@/* DATE NAME DESCRIPTION */
@/* */
@/* 05-19-2020 William E. Lamie Initial Version 6.0 */
@/* 08-14-2020 Scott Larson Modified comment(s), clean up */
@/* whitespace, resulting */
@/* in version 6.0.2 */
@/* */
@/**************************************************************************/
@VOID _tx_thread_context_restore(VOID)
@@ -93,4 +78,3 @@ _tx_thread_context_restore:
@ /* Not needed for this port - just return! */
BX lr
@}

22
ports/cortex_m7/gnu/src/tx_thread_context_save.S
View File

@@ -20,21 +20,6 @@
@/**************************************************************************/
@/**************************************************************************/
@
@
@#define TX_SOURCE_CODE
@
@
@/* Include necessary system files. */
@
@#include "tx_api.h"
@#include "tx_thread.h"
@#include "tx_timer.h"
@
@
.global _tx_thread_system_state
.global _tx_thread_current_ptr
.global _tx_execution_isr_enter
@
@
.text
.align 4
@@ -44,13 +29,15 @@
@/* FUNCTION RELEASE */
@/* */
@/* _tx_thread_context_save Cortex-M7/GNU */
@/* 6.0 */
@/* 6.0.2 */
@/* AUTHOR */
@/* */
@/* William E. Lamie, Microsoft Corporation */
@/* */
@/* DESCRIPTION */
@/* */
@/* This function is only needed for legacy applications and it should */
@/* not be called in any new development on a Cortex-M. */
@/* This function saves the context of an executing thread in the */
@/* beginning of interrupt processing. The function also ensures that */
@/* the system stack is used upon return to the calling ISR. */
@@ -76,6 +63,9 @@
@/* DATE NAME DESCRIPTION */
@/* */
@/* 05-19-2020 William E. Lamie Initial Version 6.0 */
@/* 08-14-2020 Scott Larson Modified comment(s), clean up */
@/* whitespace, resulting */
@/* in version 6.0.2 */
@/* */
@/**************************************************************************/
@VOID _tx_thread_context_save(VOID)

17
ports/cortex_m7/gnu/src/tx_thread_interrupt_control.S
View File

@@ -20,15 +20,6 @@
@/**************************************************************************/
@/**************************************************************************/
@/* #define TX_SOURCE_CODE */
@/* Include necessary system files. */
@/* #include "tx_api.h"
#include "tx_thread.h" */
.text 32
.align 4
.syntax unified
@@ -37,7 +28,7 @@
@/* FUNCTION RELEASE */
@/* */
@/* _tx_thread_interrupt_control Cortex-M7/GNU */
@/* 6.0 */
@/* 6.0.2 */
@/* AUTHOR */
@/* */
@/* William E. Lamie, Microsoft Corporation */
@@ -68,6 +59,9 @@
@/* DATE NAME DESCRIPTION */
@/* */
@/* 05-19-2020 William E. Lamie Initial Version 6.0 */
@/* 08-14-2020 Scott Larson Modified comment(s), clean up */
@/* whitespace, resulting */
@/* in version 6.0.2 */
@/* */
@/**************************************************************************/
@/* UINT _tx_thread_interrupt_control(UINT new_posture)
@@ -87,6 +81,3 @@ _tx_thread_interrupt_control:
BX lr @ Return to caller
@/* } */

60
ports/cortex_m7/gnu/src/tx_thread_schedule.S
View File

@@ -21,15 +21,6 @@
@/**************************************************************************/
@
@
@#define TX_SOURCE_CODE
@
@
@/* Include necessary system files. */
@
@#include "tx_api.h"
@#include "tx_thread.h"
@#include "tx_timer.h"
@
.global _tx_thread_current_ptr
.global _tx_thread_execute_ptr
.global _tx_timer_time_slice
@@ -46,7 +37,7 @@
@/* FUNCTION RELEASE */
@/* */
@/* _tx_thread_schedule Cortex-M7/GNU */
@/* 6.0 */
@/* 6.0.2 */
@/* AUTHOR */
@/* */
@/* William E. Lamie, Microsoft Corporation */
@@ -80,6 +71,9 @@
@/* DATE NAME DESCRIPTION */
@/* */
@/* 05-19-2020 William E. Lamie Initial Version 6.0 */
@/* 08-14-2020 Scott Larson Modified comment(s), clean up */
@/* whitespace, resulting */
@/* in version 6.0.2 */
@/* */
@/**************************************************************************/
@VOID _tx_thread_schedule(VOID)
@@ -93,7 +87,7 @@ _tx_thread_schedule:
@ from the PendSV handling routines below. */
@
@ /* Clear the preempt-disable flag to enable rescheduling after initialization on Cortex-M targets. */
@
@
MOV r0, #0 @ Build value for TX_FALSE
LDR r2, =_tx_thread_preempt_disable @ Build address of preempt disable flag
STR r0, [r2, #0] @ Clear preempt disable flag
@@ -102,14 +96,14 @@ _tx_thread_schedule:
@
#ifdef TX_ENABLE_FPU_SUPPORT
MRS r0, CONTROL @ Pickup current CONTROL register
BIC r0, r0, #4 @ Clear the FPCA bit
BIC r0, r0, #4 @ Clear the FPCA bit
MSR CONTROL, r0 @ Setup new CONTROL register
#endif
@
@ /* Enable interrupts */
@
CPSIE i
@
@
@ /* Enter the scheduler for the first time. */
@
MOV r0, #0x10000000 @ Load PENDSVSET bit
@@ -119,14 +113,14 @@ _tx_thread_schedule:
ISB @ Flush pipeline
@
@ /* Wait here for the PendSV to take place. */
@
@
__tx_wait_here:
B __tx_wait_here @ Wait for the PendSV to happen
@}
@
@ /* Generic context switch-out switch-in handler... Note that this handler is
@ /* Generic context switch-out switch-in handler... Note that this handler is
@ common for both PendSV and SVCall. */
@
@
.global PendSV_Handler
.global __tx_PendSVHandler
.thumb_func
@@ -135,8 +129,8 @@ PendSV_Handler:
__tx_PendSVHandler:
@
@ /* Get current thread value and new thread pointer. */
@
__tx_ts_handler:
@
__tx_ts_handler:
#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
@
@@ -154,7 +148,7 @@ __tx_ts_handler:
LDR r1, [r0] @ Pickup current thread pointer
@
@ /* Determine if there is a current thread to finish preserving. */
@
@
CBZ r1, __tx_ts_new @ If NULL, skip preservation
@
@ /* Recover PSP and preserve current thread context. */
@@ -185,7 +179,6 @@ _skip_vfp_save:
@
STR r3, [r4] @ Clear time-slice
@
@
@ /* Executing thread is now completely preserved!!! */
@
__tx_ts_new:
@@ -229,7 +222,7 @@ __tx_ts_restore:
LDMIA r12!, {LR} @ Pickup LR
#ifdef TX_ENABLE_FPU_SUPPORT
TST LR, #0x10 @ Determine if the VFP extended frame is present
BNE _skip_vfp_restore @ If not, skip VFP restore
BNE _skip_vfp_restore @ If not, skip VFP restore
VLDMIA r12!, {s16-s31} @ Yes, restore additional VFP registers
_skip_vfp_restore:
#endif
@@ -237,11 +230,11 @@ _skip_vfp_restore:
MSR PSP, r12 @ Setup the thread's stack pointer
@
@ /* Return to thread. */
@
@
BX lr @ Return to thread!
@
@ /* The following is the idle wait processing... in this case, no threads are ready for execution and the
@ system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts
@ system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts
@ are disabled to allow use of WFI for waiting for a thread to arrive. */
@
__tx_ts_wait:
@@ -257,40 +250,37 @@ __tx_ts_wait:
CPSIE i @ Enable interrupts
B __tx_ts_wait @ Loop to continue waiting
@
@ /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are
@ /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are
@ already in the handler! */
@
__tx_ts_ready:
MOV r7, #0x08000000 @ Build clear PendSV value
MOV r8, #0xE000E000 @ Build base NVIC address
STR r7, [r8, #0xD04] @ Clear any PendSV
STR r7, [r8, #0xD04] @ Clear any PendSV
@
@ /* Re-enable interrupts and restore new thread. */
@
@
CPSIE i @ Enable interrupts
B __tx_ts_restore @ Restore the thread
#ifdef TX_ENABLE_FPU_SUPPORT
.global tx_thread_fpu_enable
.thumb_func
.global tx_thread_fpu_enable
.thumb_func
tx_thread_fpu_enable:
@
@ /* Automatic VPF logic is supported, this function is present only for
@ /* Automatic VPF logic is supported, this function is present only for
@ backward compatibility purposes and therefore simply returns. */
@
BX LR @ Return to caller
.global tx_thread_fpu_disable
.thumb_func
.global tx_thread_fpu_disable
.thumb_func
tx_thread_fpu_disable:
@
@ /* Automatic VPF logic is supported, this function is present only for
@ /* Automatic VPF logic is supported, this function is present only for
@ backward compatibility purposes and therefore simply returns. */
@
BX LR @ Return to caller
#endif

22
ports/cortex_m7/gnu/src/tx_thread_stack_build.S
View File

@@ -20,15 +20,6 @@
@/**************************************************************************/
@/**************************************************************************/
@
@
@#define TX_SOURCE_CODE
@
@
@/* Include necessary system files. */
@
@#include "tx_api.h"
@#include "tx_thread.h"
@
@
.text
.align 4
@@ -38,7 +29,7 @@
@/* FUNCTION RELEASE */
@/* */
@/* _tx_thread_stack_build Cortex-M7/GNU */
@/* 6.0.1 */
@/* 6.0.2 */
@/* AUTHOR */
@/* */
@/* William E. Lamie, Microsoft Corporation */
@@ -76,6 +67,9 @@
@/* needed. Removed references */
@/* to stack frame, resulting */
@/* in version 6.0.1 */
@/* 08-14-2020 William E. Lamie Modified Comment(s), clean up */
@/* whitespace, resulting */
@/* in version 6.0.2 */
@/* */
@/**************************************************************************/
@VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID))
@@ -84,11 +78,11 @@
.thumb_func
_tx_thread_stack_build:
@
@
@
@ /* Build a fake interrupt frame. The form of the fake interrupt stack
@ on the Cortex-M7 should look like the following after it is built:
@
@ Stack Top:
@
@ Stack Top:
@ LR Interrupted LR (LR at time of PENDSV)
@ r4 Initial value for r4
@ r5 Initial value for r5
@@ -147,5 +141,3 @@ _tx_thread_stack_build:
@ control block
BX lr @ Return to caller
@}

21
ports/cortex_m7/gnu/src/tx_thread_system_return.S
View File

@@ -19,15 +19,6 @@
@/** */
@/**************************************************************************/
@/**************************************************************************/
@
@/* #define TX_SOURCE_CODE */
@
@
@/* Include necessary system files. */
@
@/* #include "tx_api.h"
@ #include "tx_thread.h"
@ #include "tx_timer.h" */
.text 32
@@ -38,7 +29,7 @@
@/* FUNCTION RELEASE */
@/* */
@/* _tx_thread_system_return Cortex-M7/GNU */
@/* 6.0 */
@/* 6.0.2 */
@/* AUTHOR */
@/* */
@/* William E. Lamie, Microsoft Corporation */
@@ -71,6 +62,9 @@
@/* DATE NAME DESCRIPTION */
@/* */
@/* 05-19-2020 William E. Lamie Initial Version 6.0 */
@/* 08-14-2020 Scott Larson Modified comment(s), clean up */
@/* whitespace, resulting */
@/* in version 6.0.2 */
@/* */
@/**************************************************************************/
@/* VOID _tx_thread_system_return(VOID)
@@ -79,9 +73,9 @@
.global _tx_thread_system_return
_tx_thread_system_return:
@
@ /* Return to real scheduler via PendSV. Note that this routine is often
@ /* Return to real scheduler via PendSV. Note that this routine is often
@ replaced with in-line assembly in tx_port.h to improved performance. */
@
@
MOV r0, #0x10000000 @ Load PENDSVSET bit
MOV r1, #0xE000E000 @ Load NVIC base
STR r0, [r1, #0xD04] @ Set PENDSVBIT in ICSR
@@ -92,7 +86,6 @@ _tx_thread_system_return:
CPSIE i @ Enable interrupts
MSR PRIMASK, r1 @ Restore original interrupt posture
_isr_context:
BX lr @ Return to caller
BX lr @ Return to caller
@/* } */

24
ports/cortex_m7/gnu/src/tx_timer_interrupt.S
View File

@@ -20,17 +20,6 @@
@/**************************************************************************/
@/**************************************************************************/
@
@#define TX_SOURCE_CODE
@
@
@/* Include necessary system files. */
@
@#include "tx_api.h"
@#include "tx_timer.h"
@#include "tx_thread.h"
@
@
@Define Assembly language external references...
@
.global _tx_timer_time_slice
.global _tx_timer_system_clock
@@ -51,7 +40,7 @@
@/* FUNCTION RELEASE */
@/* */
@/* _tx_timer_interrupt Cortex-M7/GNU */
@/* 6.0 */
@/* 6.0.2 */
@/* AUTHOR */
@/* */
@/* William E. Lamie, Microsoft Corporation */
@@ -86,6 +75,9 @@
@/* DATE NAME DESCRIPTION */
@/* */
@/* 05-19-2020 William E. Lamie Initial Version 6.0 */
@/* 08-14-2020 Scott Larson Modified comment(s), clean up */
@/* whitespace, resulting */
@/* in version 6.0.2 */
@/* */
@/**************************************************************************/
@VOID _tx_timer_interrupt(VOID)
@@ -110,7 +102,7 @@ _tx_timer_interrupt:
@ if (_tx_timer_time_slice)
@ {
@
LDR r3, =_tx_timer_time_slice @ Pickup address of time-slice
LDR r3, =_tx_timer_time_slice @ Pickup address of time-slice
LDR r2, [r3, #0] @ Pickup time-slice
CMP r2, #0 @ Is it non-active?
BEQ __tx_timer_no_time_slice @ Yes, skip time-slice processing
@@ -228,13 +220,13 @@ __tx_timer_dont_activate:
@ if (_tx_timer_expired_time_slice)
@ {
@
LDR r3, =_tx_timer_expired_time_slice @ Pickup addr of time-slice expired
LDR r3, =_tx_timer_expired_time_slice @ Pickup addr of time-slice expired
LDR r2, [r3, #0] @ Pickup the actual flag
CMP r2, #0 @ See if the flag is set
BEQ __tx_timer_not_ts_expiration @ No, skip time-slice processing
@
@ /* Time slice interrupted thread. */
@ _tx_thread_time_slice();
@ _tx_thread_time_slice();
@
BL _tx_thread_time_slice @ Call time-slice processing
LDR r0, =_tx_thread_preempt_disable @ Build address of preempt disable flag
@@ -266,5 +258,3 @@ __tx_timer_nothing_expired:
BX lr @ Return to caller
@
@}

50
ports/cortex_m7/iar/example_build/tx_initialize_low_level.s
View File

@@ -20,42 +20,32 @@
;/**************************************************************************/
;/**************************************************************************/
;
;#define TX_SOURCE_CODE
;
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_initialize.h"
;#include "tx_thread.h"
;#include "tx_timer.h"
;
;
EXTERN _tx_thread_system_stack_ptr
EXTERN _tx_initialize_unused_memory
EXTERN _tx_timer_interrupt
EXTERN __vector_table
EXTERN _tx_execution_isr_enter
EXTERN _tx_execution_isr_exit
EXTERN _tx_thread_system_stack_ptr
EXTERN _tx_initialize_unused_memory
EXTERN _tx_timer_interrupt
EXTERN __vector_table
EXTERN _tx_execution_isr_enter
EXTERN _tx_execution_isr_exit
;
;
SYSTEM_CLOCK EQU 25000000
SYSTICK_CYCLES EQU ((SYSTEM_CLOCK / 100) -1)
RSEG FREE_MEM:DATA
PUBLIC __tx_free_memory_start
__tx_free_memory_start
DS32 4
DS32 4
;
;
SECTION `.text`:CODE:NOROOT(2)
THUMB
SECTION `.text`:CODE:NOROOT(2)
THUMB
;/**************************************************************************/
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* _tx_initialize_low_level Cortex-M7/IAR */
;/* 6.0.1 */
;/* 6.0.2 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
@@ -89,20 +79,23 @@ __tx_free_memory_start
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* 08-14-2020 Scott Larson Modified comment(s), clean up */
;/* whitespace, resulting */
;/* in version 6.0.2 */
;/* */
;/**************************************************************************/
;VOID _tx_initialize_low_level(VOID)
;{
PUBLIC _tx_initialize_low_level
_tx_initialize_low_level:
;
;
; /* Ensure that interrupts are disabled. */
;
CPSID i ; Disable interrupts
;
;
; /* Set base of available memory to end of non-initialised RAM area. */
;
;
LDR r0, =__tx_free_memory_start ; Get end of non-initialized RAM area
LDR r2, =_tx_initialize_unused_memory ; Build address of unused memory pointer
STR r0, [r2, #0] ; Save first free memory address
@@ -112,13 +105,13 @@ _tx_initialize_low_level:
LDR r0, =0xE0001000 ; Build address of DWT register
LDR r1, [r0] ; Pickup the current value
ORR r1, r1, #1 ; Set the CYCCNTENA bit
STR r1, [r0] ; Enable the cycle count register
STR r1, [r0] ; Enable the cycle count register
;
; /* Setup Vector Table Offset Register. */
;
;
MOV r0, #0xE000E000 ; Build address of NVIC registers
LDR r1, =__vector_table ; Pickup address of vector table
STR r1, [r0, #0xD08] ; Set vector table address
STR r1, [r0, #0xD08] ; Set vector table address
;
; /* Set system stack pointer from vector value. */
;
@@ -149,8 +142,8 @@ _tx_initialize_low_level:
; Note: PnSV must be lowest priority, which is 0xFF
;
; /* Return to caller. */
;
BX lr
;
BX lr
;}
;
;
@@ -174,4 +167,3 @@ SysTick_Handler:
BX LR
; }
END

5
ports/cortex_m7/iar/readme_threadx.txt
View File

@@ -206,6 +206,11 @@ For generic code revision information, please refer to the readme_threadx_generi
file, which is included in your distribution. The following details the revision
information associated with this specific port of ThreadX:
08-14-2020 ThreadX update of Cortex-M7/IAR port. The following files were
changed/added for port specific version 6.0.2:
*.s Modified comments and whitespace.
06/30/2020 Initial ThreadX version 6.0.1 for Cortex-M7 using IAR's ARM tools.

40
ports/cortex_m7/iar/src/tx_thread_context_restore.s
View File

@@ -21,40 +21,32 @@
;/**************************************************************************/
;
;
;#define TX_SOURCE_CODE
EXTERN _tx_thread_system_state
EXTERN _tx_thread_current_ptr
EXTERN _tx_thread_system_stack_ptr
EXTERN _tx_thread_execute_ptr
EXTERN _tx_timer_time_slice
EXTERN _tx_thread_schedule
EXTERN _tx_thread_preempt_disable
EXTERN _tx_execution_isr_exit
;
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_thread.h"
;#include "tx_timer.h"
;
;
EXTERN _tx_thread_system_state
EXTERN _tx_thread_current_ptr
EXTERN _tx_thread_system_stack_ptr
EXTERN _tx_thread_execute_ptr
EXTERN _tx_timer_time_slice
EXTERN _tx_thread_schedule
EXTERN _tx_thread_preempt_disable
EXTERN _tx_execution_isr_exit
;
;
SECTION `.text`:CODE:NOROOT(2)
THUMB
SECTION `.text`:CODE:NOROOT(2)
THUMB
;/**************************************************************************/
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_context_restore Cortex-M7/IAR */
;/* 6.0.1 */
;/* 6.0.2 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
;/* */
;/* DESCRIPTION */
;/* */
;/* This function is only needed for legacy applications and it should */
;/* not be called in any new development on a Cortex-M. */
;/* This function restores the interrupt context if it is processing a */
;/* nested interrupt. If not, it returns to the interrupt thread if no */
;/* preemption is necessary. Otherwise, if preemption is necessary or */
@@ -81,6 +73,9 @@
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* 08-14-2020 Scott Larson Modified comment(s), clean up */
;/* whitespace, resulting */
;/* in version 6.0.2 */
;/* */
;/**************************************************************************/
;VOID _tx_thread_context_restore(VOID)
@@ -101,5 +96,4 @@ _tx_thread_context_restore:
BX lr
;
;}
END
END

29
ports/cortex_m7/iar/src/tx_thread_context_save.s
View File

@@ -21,35 +21,27 @@
;/**************************************************************************/
;
;
;#define TX_SOURCE_CODE
EXTERN _tx_thread_system_state
EXTERN _tx_thread_current_ptr
EXTERN _tx_execution_isr_enter
;
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_thread.h"
;#include "tx_timer.h"
;
;
EXTERN _tx_thread_system_state
EXTERN _tx_thread_current_ptr
EXTERN _tx_execution_isr_enter
;
;
SECTION `.text`:CODE:NOROOT(2)
THUMB
SECTION `.text`:CODE:NOROOT(2)
THUMB
;/**************************************************************************/
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_context_save Cortex-M7/IAR */
;/* 6.0.1 */
;/* 6.0.2 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
;/* */
;/* DESCRIPTION */
;/* */
;/* This function is only needed for legacy applications and it should */
;/* not be called in any new development on a Cortex-M. */
;/* This function saves the context of an executing thread in the */
;/* beginning of interrupt processing. The function also ensures that */
;/* the system stack is used upon return to the calling ISR. */
@@ -75,6 +67,9 @@
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* 08-14-2020 Scott Larson Modified comment(s), clean up */
;/* whitespace, resulting */
;/* in version 6.0.2 */
;/* */
;/**************************************************************************/
;VOID _tx_thread_context_save(VOID)
@@ -84,7 +79,7 @@ _tx_thread_context_save:
#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
;
; /* Call the ISR enter function to indicate an ISR is starting. */
;
;
PUSH {r0, lr} ; Save return address
BL _tx_execution_isr_enter ; Call the ISR enter function
POP {r0, lr} ; Recover return address

20
ports/cortex_m7/iar/src/tx_thread_interrupt_control.s
View File

@@ -20,23 +20,15 @@
;/**************************************************************************/
;/**************************************************************************/
;
;#define TX_SOURCE_CODE
;
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_thread.h"
;
;
SECTION `.text`:CODE:NOROOT(2)
THUMB
SECTION `.text`:CODE:NOROOT(2)
THUMB
;/**************************************************************************/
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_interrupt_control Cortex-M7/IAR */
;/* 6.0.1 */
;/* 6.0.2 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
@@ -67,6 +59,9 @@
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* 08-14-2020 Scott Larson Modified comment(s), clean up */
;/* whitespace, resulting */
;/* in version 6.0.2 */
;/* */
;/**************************************************************************/
;UINT _tx_thread_interrupt_control(UINT new_posture)
@@ -82,5 +77,4 @@ _tx_thread_interrupt_control:
BX lr
;
;}
END
END

17
ports/cortex_m7/iar/src/tx_thread_interrupt_disable.s
View File

@@ -20,23 +20,15 @@
;/**************************************************************************/
;/**************************************************************************/
;
;#define TX_SOURCE_CODE
;
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_thread.h"
;
;
SECTION `.text`:CODE:NOROOT(2)
THUMB
SECTION `.text`:CODE:NOROOT(2)
THUMB
;/**************************************************************************/
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_interrupt_restore Cortex-M7/IAR */
;/* 6.0.1 */
;/* 6.0.2 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
@@ -67,6 +59,9 @@
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* 08-14-2020 Scott Larson Modified comment(s), clean up */
;/* whitespace, resulting */
;/* in version 6.0.2 */
;/* */
;/**************************************************************************/
;UINT _tx_thread_interrupt_disable(UINT new_posture)

17
ports/cortex_m7/iar/src/tx_thread_interrupt_restore.s
View File

@@ -20,23 +20,15 @@
;/**************************************************************************/
;/**************************************************************************/
;
;#define TX_SOURCE_CODE
;
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_thread.h"
;
;
SECTION `.text`:CODE:NOROOT(2)
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SECTION `.text`:CODE:NOROOT(2)
THUMB
;/**************************************************************************/
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_interrupt_restore Cortex-M7/IAR */
;/* 6.0.1 */
;/* 6.0.2 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
@@ -67,6 +59,9 @@
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* 08-14-2020 Scott Larson Modified comment(s), clean up */
;/* whitespace, resulting */
;/* in version 6.0.2 */
;/* */
;/**************************************************************************/
;VOID _tx_thread_interrupt_restore(UINT new_posture)

67
ports/cortex_m7/iar/src/tx_thread_schedule.s
View File

@@ -21,32 +21,23 @@
;/**************************************************************************/
;
;
;#define TX_SOURCE_CODE
EXTERN _tx_thread_current_ptr
EXTERN _tx_thread_execute_ptr
EXTERN _tx_timer_time_slice
EXTERN _tx_thread_system_stack_ptr
EXTERN _tx_execution_thread_enter
EXTERN _tx_execution_thread_exit
EXTERN _tx_thread_preempt_disable
;
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_thread.h"
;#include "tx_timer.h"
;
EXTERN _tx_thread_current_ptr
EXTERN _tx_thread_execute_ptr
EXTERN _tx_timer_time_slice
EXTERN _tx_thread_system_stack_ptr
EXTERN _tx_execution_thread_enter
EXTERN _tx_execution_thread_exit
EXTERN _tx_thread_preempt_disable
;
;
SECTION `.text`:CODE:NOROOT(2)
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SECTION `.text`:CODE:NOROOT(2)
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;/**************************************************************************/
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_schedule Cortex-M7/IAR */
;/* 6.0.1 */
;/* 6.0.2 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
@@ -80,6 +71,9 @@
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* 08-14-2020 Scott Larson Modified comment(s), clean up */
;/* whitespace, resulting */
;/* in version 6.0.2 */
;/* */
;/**************************************************************************/
;VOID _tx_thread_schedule(VOID)
@@ -92,7 +86,7 @@ _tx_thread_schedule:
; from the PendSV handling routines below. */
;
; /* Clear the preempt-disable flag to enable rescheduling after initialization on Cortex-M targets. */
;
;
MOV r0, #0 ; Build value for TX_FALSE
LDR r2, =_tx_thread_preempt_disable ; Build address of preempt disable flag
STR r0, [r2, #0] ; Clear preempt disable flag
@@ -101,14 +95,14 @@ _tx_thread_schedule:
;
#ifdef __ARMVFP__
MRS r0, CONTROL ; Pickup current CONTROL register
BIC r0, r0, #4 ; Clear the FPCA bit
BIC r0, r0, #4 ; Clear the FPCA bit
MSR CONTROL, r0 ; Setup new CONTROL register
#endif
;
; /* Enable interrupts */
;
CPSIE i
;
;
; /* Enter the scheduler for the first time. */
;
MOV r0, #0x10000000 ; Load PENDSVSET bit
@@ -118,21 +112,21 @@ _tx_thread_schedule:
ISB ; Flush pipeline
;
; /* Wait here for the PendSV to take place. */
;
;
__tx_wait_here:
B __tx_wait_here ; Wait for the PendSV to happen
;}
;
; /* Generic context PendSV handler. */
;
;
PUBLIC PendSV_Handler
PUBLIC __tx_PendSVHandler
PendSV_Handler:
__tx_PendSVHandler:
;
; /* Get current thread value and new thread pointer. */
;
__tx_ts_handler:
;
__tx_ts_handler:
#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
;
@@ -150,7 +144,7 @@ __tx_ts_handler:
LDR r1, [r0] ; Pickup current thread pointer
;
; /* Determine if there is a current thread to finish preserving. */
;
;
CBZ r1, __tx_ts_new ; If NULL, skip preservation
;
; /* Recover PSP and preserve current thread context. */
@@ -181,7 +175,7 @@ _skip_vfp_save:
;
STR r3, [r4] ; Clear time-slice
;
;
;
; /* Executing thread is now completely preserved!!! */
;
__tx_ts_new:
@@ -225,7 +219,7 @@ __tx_ts_restore:
LDMIA r12!, {LR} ; Pickup LR
#ifdef __ARMVFP__
TST LR, #0x10 ; Determine if the VFP extended frame is present
BNE _skip_vfp_restore ; If not, skip VFP restore
BNE _skip_vfp_restore ; If not, skip VFP restore
VLDMIA r12!, {s16-s31} ; Yes, restore additional VFP registers
_skip_vfp_restore:
#endif
@@ -233,11 +227,11 @@ _skip_vfp_restore:
MSR PSP, r12 ; Setup the thread's stack pointer
;
; /* Return to thread. */
;
;
BX lr ; Return to thread!
;
; /* The following is the idle wait processing... in this case, no threads are ready for execution and the
; system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts
; system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts
; are disabled to allow use of WFI for waiting for a thread to arrive. */
;
__tx_ts_wait:
@@ -253,16 +247,16 @@ __tx_ts_wait:
CPSIE i ; Enable interrupts
B __tx_ts_wait ; Loop to continue waiting
;
; /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are
; /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are
; already in the handler! */
;
__tx_ts_ready:
MOV r7, #0x08000000 ; Build clear PendSV value
MOV r8, #0xE000E000 ; Build base NVIC address
STR r7, [r8, #0xD04] ; Clear any PendSV
STR r7, [r8, #0xD04] ; Clear any PendSV
;
; /* Re-enable interrupts and restore new thread. */
;
;
CPSIE i ; Enable interrupts
B __tx_ts_restore ; Restore the thread
;}
@@ -272,7 +266,7 @@ __tx_ts_ready:
PUBLIC tx_thread_fpu_enable
tx_thread_fpu_enable:
;
; /* Automatic VPF logic is supported, this function is present only for
; /* Automatic VPF logic is supported, this function is present only for
; backward compatibility purposes and therefore simply returns. */
;
BX LR ; Return to caller
@@ -280,7 +274,7 @@ tx_thread_fpu_enable:
PUBLIC tx_thread_fpu_disable
tx_thread_fpu_disable:
;
; /* Automatic VPF logic is supported, this function is present only for
; /* Automatic VPF logic is supported, this function is present only for
; backward compatibility purposes and therefore simply returns. */
;
BX LR ; Return to caller
@@ -288,4 +282,3 @@ tx_thread_fpu_disable:
#endif
END

27
ports/cortex_m7/iar/src/tx_thread_stack_build.s
View File

@@ -21,23 +21,14 @@
;/**************************************************************************/
;
;
;#define TX_SOURCE_CODE
;
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_thread.h"
;
;
SECTION `.text`:CODE:NOROOT(2)
THUMB
SECTION `.text`:CODE:NOROOT(2)
THUMB
;/**************************************************************************/
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_stack_build Cortex-M7/IAR */
;/* 6.0.1 */
;/* 6.0.2 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
@@ -70,6 +61,9 @@
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* 08-14-2020 Scott Larson Modified comment(s), clean up */
;/* whitespace, resulting */
;/* in version 6.0.2 */
;/* */
;/**************************************************************************/
;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID))
@@ -77,11 +71,11 @@
PUBLIC _tx_thread_stack_build
_tx_thread_stack_build:
;
;
;
; /* Build a fake interrupt frame. The form of the fake interrupt stack
; on the Cortex-M7 should look like the following after it is built:
;
; Stack Top:
;
; Stack Top:
; LR Interrupted LR (LR at time of PENDSV)
; r4 Initial value for r4
; r5 Initial value for r5
@@ -120,7 +114,7 @@ _tx_thread_stack_build:
STR r3, [r2, #28] ; Store initial r10
STR r3, [r2, #32] ; Store initial r11
;
; /* Hardware stack follows. /
; /* Hardware stack follows. */
;
STR r3, [r2, #36] ; Store initial r0
STR r3, [r2, #40] ; Store initial r1
@@ -141,4 +135,3 @@ _tx_thread_stack_build:
BX lr ; Return to caller
;}
END

27
ports/cortex_m7/iar/src/tx_thread_system_return.s
View File

@@ -20,25 +20,15 @@
;/**************************************************************************/
;/**************************************************************************/
;
;#define TX_SOURCE_CODE
;
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_thread.h"
;#include "tx_timer.h"
;
;
;
SECTION `.text`:CODE:NOROOT(2)
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SECTION `.text`:CODE:NOROOT(2)
THUMB
;/**************************************************************************/
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_system_return Cortex-M7/IAR */
;/* 6.0.1 */
;/* 6.0.2 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
@@ -71,6 +61,9 @@
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* 08-14-2020 Scott Larson Modified comment(s), clean up */
;/* whitespace, resulting */
;/* in version 6.0.2 */
;/* */
;/**************************************************************************/
;VOID _tx_thread_system_return(VOID)
@@ -79,9 +72,9 @@
_tx_thread_system_return??rA:
_tx_thread_system_return:
;
; /* Return to real scheduler via PendSV. Note that this routine is often
; /* Return to real scheduler via PendSV. Note that this routine is often
; replaced with in-line assembly in tx_port.h to improved performance. */
;
;
MOV r0, #0x10000000 ; Load PENDSVSET bit
MOV r1, #0xE000E000 ; Load NVIC base
STR r0, [r1, #0xD04] ; Set PENDSVBIT in ICSR
@@ -92,6 +85,6 @@ _tx_thread_system_return:
CPSIE i ; Enable interrupts
MSR PRIMASK, r1 ; Restore original interrupt posture
_isr_context:
BX lr ; Return to caller
BX lr ; Return to caller
;}
END
END

27
ports/cortex_m7/iar/src/tx_timer_interrupt.s
View File

@@ -20,17 +20,6 @@
;/**************************************************************************/
;/**************************************************************************/
;
;#define TX_SOURCE_CODE
;
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_timer.h"
;#include "tx_thread.h"
;
;
;Define Assembly language external references...
;
EXTERN _tx_timer_time_slice
EXTERN _tx_timer_system_clock
@@ -46,14 +35,14 @@
EXTERN _tx_thread_preempt_disable
;
;
SECTION `.text`:CODE:NOROOT(2)
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SECTION `.text`:CODE:NOROOT(2)
THUMB
;/**************************************************************************/
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* _tx_timer_interrupt Cortex-M7/IAR */
;/* 6.0.1 */
;/* 6.0.2 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
@@ -87,6 +76,9 @@
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* 08-14-2020 Scott Larson Modified comment(s), clean up */
;/* whitespace, resulting */
;/* in version 6.0.2 */
;/* */
;/**************************************************************************/
;VOID _tx_timer_interrupt(VOID)
@@ -109,7 +101,7 @@ _tx_timer_interrupt:
; if (_tx_timer_time_slice)
; {
;
MOV32 r3, _tx_timer_time_slice ; Pickup address of time-slice
MOV32 r3, _tx_timer_time_slice ; Pickup address of time-slice
LDR r2, [r3, #0] ; Pickup time-slice
CBZ r2, __tx_timer_no_time_slice ; Is it non-active?
; Yes, skip time-slice processing
@@ -226,13 +218,13 @@ __tx_timer_dont_activate:
; if (_tx_timer_expired_time_slice)
; {
;
MOV32 r3, _tx_timer_expired_time_slice ; Pickup addr of time-slice expired
MOV32 r3, _tx_timer_expired_time_slice ; Pickup addr of time-slice expired
LDR r2, [r3, #0] ; Pickup the actual flag
CBZ r2, __tx_timer_not_ts_expiration ; See if the flag is set
; No, skip time-slice processing
;
; /* Time slice interrupted thread. */
; _tx_thread_time_slice();
; _tx_thread_time_slice();
BL _tx_thread_time_slice ; Call time-slice processing
MOV32 r0, _tx_thread_preempt_disable ; Build address of preempt disable flag
@@ -265,4 +257,3 @@ __tx_timer_nothing_expired:
;
;}
END