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Release ARMv7-A architecture ports and add tx_user.h to GNU port assembly files (#250)

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* Release ARMv7-A architecture ports

* Add tx_user.h to GNU port assembly files

* Update GitHub action to perform check for Cortex-A ports
This commit is contained in:
TiejunZhou
2023-04-19 17:56:09 +08:00
committed by GitHub
parent 23680f5e5f
commit 672c5e953e
416 changed files with 43000 additions and 463 deletions
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148
ports_arch/ARMv8-A/threadx_smp/ports/ac6/example_build/sample_threadx/.cproject Normal file
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ports_arch/ARMv8-A/threadx_smp/ports/ac6/example_build/sample_threadx/.project Normal file
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561
ports_arch/ARMv8-A/threadx_smp/ports/ac6/example_build/sample_threadx/GICv3.h Normal file
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/*
* GICv3.h - data types and function prototypes for GICv3 utility routines
*
* Copyright (c) 2014-2017 Arm Limited (or its affiliates). All rights reserved.
* Use, modification and redistribution of this file is subject to your possession of a
* valid End User License Agreement for the Arm Product of which these examples are part of
* and your compliance with all applicable terms and conditions of such licence agreement.
*/
#ifndef GICV3_h
#define GICV3_h
#include <stdint.h>
/*
* extra flags for GICD enable
*/
typedef enum
{
gicdctlr_EnableGrp0 = (1 << 0),
gicdctlr_EnableGrp1NS = (1 << 1),
gicdctlr_EnableGrp1A = (1 << 1),
gicdctlr_EnableGrp1S = (1 << 2),
gicdctlr_EnableAll = (1 << 2) | (1 << 1) | (1 << 0),
gicdctlr_ARE_S = (1 << 4), /* Enable Secure state affinity routing */
gicdctlr_ARE_NS = (1 << 5), /* Enable Non-Secure state affinity routing */
gicdctlr_DS = (1 << 6), /* Disable Security support */
gicdctlr_E1NWF = (1 << 7) /* Enable "1-of-N" wakeup model */
} GICDCTLRFlags_t;
/*
* modes for SPI routing
*/
typedef enum
{
gicdirouter_ModeSpecific = 0,
gicdirouter_ModeAny = (1 << 31)
} GICDIROUTERBits_t;
typedef enum
{
gicdicfgr_Level = 0,
gicdicfgr_Edge = (1 << 1)
} GICDICFGRBits_t;
typedef enum
{
gicigroupr_G0S = 0,
gicigroupr_G1NS = (1 << 0),
gicigroupr_G1S = (1 << 2)
} GICIGROUPRBits_t;
typedef enum
{
gicrwaker_ProcessorSleep = (1 << 1),
gicrwaker_ChildrenAsleep = (1 << 2)
} GICRWAKERBits_t;
/**********************************************************************/
/*
* Utility macros & functions
*/
#define RANGE_LIMIT(x) ((sizeof(x) / sizeof((x)[0])) - 1)
static inline uint64_t gicv3PackAffinity(uint32_t aff3, uint32_t aff2,
uint32_t aff1, uint32_t aff0)
{
/*
* only need to cast aff3 to get type promotion for all affinities
*/
return ((((uint64_t)aff3 & 0xff) << 32) |
((aff2 & 0xff) << 16) |
((aff1 & 0xff) << 8) | aff0);
}
/**********************************************************************/
/*
* GIC Distributor Function Prototypes
*/
/*
* ConfigGICD - configure GIC Distributor prior to enabling it
*
* Inputs:
*
* control - control flags
*
* Returns:
*
* <nothing>
*
* NOTE:
*
* ConfigGICD() will set an absolute flags value, whereas
* {En,Dis}ableGICD() will only {set,clear} the flag bits
* passed as a parameter
*/
void ConfigGICD(GICDCTLRFlags_t flags);
/*
* EnableGICD - top-level enable for GIC Distributor
*
* Inputs:
*
* flags - new control flags to set
*
* Returns:
*
* <nothing>
*
* NOTE:
*
* ConfigGICD() will set an absolute flags value, whereas
* {En,Dis}ableGICD() will only {set,clear} the flag bits
* passed as a parameter
*/
void EnableGICD(GICDCTLRFlags_t flags);
/*
* DisableGICD - top-level disable for GIC Distributor
*
* Inputs
*
* flags - control flags to clear
*
* Returns
*
* <nothing>
*
* NOTE:
*
* ConfigGICD() will set an absolute flags value, whereas
* {En,Dis}ableGICD() will only {set,clear} the flag bits
* passed as a parameter
*/
void DisableGICD(GICDCTLRFlags_t flags);
/*
* SyncAREinGICD - synchronise GICD Address Routing Enable bits
*
* Inputs
*
* flags - absolute flag bits to set in GIC Distributor
*
* dosync - flag whether to wait for ARE bits to match passed
* flag field (dosync = true), or whether to set absolute
* flag bits (dosync = false)
*
* Returns
*
* <nothing>
*
* NOTE:
*
* This function is used to resolve a race in an MP system whereby secondary
* CPUs cannot reliably program all Redistributor registers until the
* primary CPU has enabled Address Routing. The primary CPU will call this
* function with dosync = false, while the secondaries will call it with
* dosync = true.
*/
void SyncAREinGICD(GICDCTLRFlags_t flags, uint32_t dosync);
/*
* EnableSPI - enable a specific shared peripheral interrupt
*
* Inputs:
*
* id - which interrupt to enable
*
* Returns:
*
* <nothing>
*/
void EnableSPI(uint32_t id);
/*
* DisableSPI - disable a specific shared peripheral interrupt
*
* Inputs:
*
* id - which interrupt to disable
*
* Returns:
*
* <nothing>
*/
void DisableSPI(uint32_t id);
/*
* SetSPIPriority - configure the priority for a shared peripheral interrupt
*
* Inputs:
*
* id - interrupt identifier
*
* priority - 8-bit priority to program (see note below)
*
* Returns:
*
* <nothing>
*
* Note:
*
* The GICv3 architecture makes this function sensitive to the Security
* context in terms of what effect it has on the programmed priority: no
* attempt is made to adjust for the reduced priority range available
* when making Non-Secure accesses to the GIC
*/
void SetSPIPriority(uint32_t id, uint32_t priority);
/*
* GetSPIPriority - determine the priority for a shared peripheral interrupt
*
* Inputs:
*
* id - interrupt identifier
*
* Returns:
*
* interrupt priority in the range 0 - 0xff
*/
uint32_t GetSPIPriority(uint32_t id);
/*
* SetSPIRoute - specify interrupt routing when gicdctlr_ARE is enabled
*
* Inputs:
*
* id - interrupt identifier
*
* affinity - prepacked "dotted quad" affinity routing. NOTE: use the
* gicv3PackAffinity() helper routine to generate this input
*
* mode - select routing mode (specific affinity, or any recipient)
*
* Returns:
*
* <nothing>
*/
void SetSPIRoute(uint32_t id, uint64_t affinity, GICDIROUTERBits_t mode);
/*
* GetSPIRoute - read ARE-enabled interrupt routing information
*
* Inputs:
*
* id - interrupt identifier
*
* Returns:
*
* routing configuration
*/
uint64_t GetSPIRoute(uint32_t id);
/*
* SetSPITarget - configure the set of processor targets for an interrupt
*
* Inputs
*
* id - interrupt identifier
*
* target - 8-bit target bitmap
*
* Returns
*
* <nothing>
*/
void SetSPITarget(uint32_t id, uint32_t target);
/*
* GetSPITarget - read the set of processor targets for an interrupt
*
* Inputs
*
* id - interrupt identifier
*
* Returns
*
* 8-bit target bitmap
*/
uint32_t GetSPITarget(uint32_t id);
/*
* ConfigureSPI - setup an interrupt as edge- or level-triggered
*
* Inputs
*
* id - interrupt identifier
*
* config - desired configuration
*
* Returns
*
* <nothing>
*/
void ConfigureSPI(uint32_t id, GICDICFGRBits_t config);
/*
* SetSPIPending - mark an interrupt as pending
*
* Inputs
*
* id - interrupt identifier
*
* Returns
*
* <nothing>
*/
void SetSPIPending(uint32_t id);
/*
* ClearSPIPending - mark an interrupt as not pending
*
* Inputs
*
* id - interrupt identifier
*
* Returns
*
* <nothing>
*/
void ClearSPIPending(uint32_t id);
/*
* GetSPIPending - query whether an interrupt is pending
*
* Inputs
*
* id - interrupt identifier
*
* Returns
*
* pending status
*/
uint32_t GetSPIPending(uint32_t id);
/*
* SetSPISecurity - mark a shared peripheral interrupt as
* security <group>
*
* Inputs
*
* id - which interrupt to mark
*
* group - the group for the interrupt
*
* Returns
*
* <nothing>
*/
void SetSPISecurity(uint32_t id, GICIGROUPRBits_t group);
/*
* SetSPISecurityBlock - mark a block of 32 shared peripheral
* interrupts as security <group>
*
* Inputs:
*
* block - which block to mark (e.g. 1 = Ints 32-63)
*
* group - the group for the interrupts
*
* Returns:
*
* <nothing>
*/
void SetSPISecurityBlock(uint32_t block, GICIGROUPRBits_t group);
/*
* SetSPISecurityAll - mark all shared peripheral interrupts
* as security <group>
*
* Inputs:
*
* group - the group for the interrupts
*
* Returns:
*
* <nothing>
*/
void SetSPISecurityAll(GICIGROUPRBits_t group);
/**********************************************************************/
/*
* GIC Re-Distributor Function Prototypes
*
* The model for calling Redistributor functions is that, rather than
* identifying the target redistributor with every function call, the
* SelectRedistributor() function is used to identify which redistributor
* is to be used for all functions until a different redistributor is
* explicitly selected
*/
/*
* WakeupGICR - wake up a Redistributor
*
* Inputs:
*
* gicr - which Redistributor to wakeup
*
* Returns:
*
* <nothing>
*/
void WakeupGICR(uint32_t gicr);
/*
* EnablePrivateInt - enable a private (SGI/PPI) interrupt
*
* Inputs:
*
* gicr - which Redistributor to program
*
* id - which interrupt to enable
*
* Returns:
*
* <nothing>
*/
void EnablePrivateInt(uint32_t gicr, uint32_t id);
/*
* DisablePrivateInt - disable a private (SGI/PPI) interrupt
*
* Inputs:
*
* gicr - which Redistributor to program
*
* id - which interrupt to disable
*
* Returns:
*
* <nothing>
*/
void DisablePrivateInt(uint32_t gicr, uint32_t id);
/*
* SetPrivateIntPriority - configure the priority for a private
* (SGI/PPI) interrupt
*
* Inputs:
*
* gicr - which Redistributor to program
*
* id - interrupt identifier
*
* priority - 8-bit priority to program (see note below)
*
* Returns:
*
* <nothing>
*
* Note:
*
* The GICv3 architecture makes this function sensitive to the Security
* context in terms of what effect it has on the programmed priority: no
* attempt is made to adjust for the reduced priority range available
* when making Non-Secure accesses to the GIC
*/
void SetPrivateIntPriority(uint32_t gicr, uint32_t id, uint32_t priority);
/*
* GetPrivateIntPriority - configure the priority for a private
* (SGI/PPI) interrupt
*
* Inputs:
*
* gicr - which Redistributor to program
*
* id - interrupt identifier
*
* Returns:
*
* Int priority
*/
uint32_t GetPrivateIntPriority(uint32_t gicr, uint32_t id);
/*
* SetPrivateIntPending - mark a private (SGI/PPI) interrupt as pending
*
* Inputs
*
* gicr - which Redistributor to program
*
* id - interrupt identifier
*
* Returns
*
* <nothing>
*/
void SetPrivateIntPending(uint32_t gicr, uint32_t id);
/*
* ClearPrivateIntPending - mark a private (SGI/PPI) interrupt as not pending
*
* Inputs
*
* gicr - which Redistributor to program
*
* id - interrupt identifier
*
* Returns
*
* <nothing>
*/
void ClearPrivateIntPending(uint32_t gicr, uint32_t id);
/*
* GetPrivateIntPending - query whether a private (SGI/PPI) interrupt is pending
*
* Inputs
*
* gicr - which Redistributor to program
*
* id - interrupt identifier
*
* Returns
*
* pending status
*/
uint32_t GetPrivateIntPending(uint32_t gicr, uint32_t id);
/*
* SetPrivateIntSecurity - mark a private (SGI/PPI) interrupt as
* security <group>
*
* Inputs
*
* gicr - which Redistributor to program
*
* id - which interrupt to mark
*
* group - the group for the interrupt
*
* Returns
*
* <nothing>
*/
void SetPrivateIntSecurity(uint32_t gicr, uint32_t id, GICIGROUPRBits_t group);
/*
* SetPrivateIntSecurityBlock - mark all 32 private (SGI/PPI)
* interrupts as security <group>
*
* Inputs:
*
* gicr - which Redistributor to program
*
* group - the group for the interrupt
*
* Returns:
*
* <nothing>
*/
void SetPrivateIntSecurityBlock(uint32_t gicr, GICIGROUPRBits_t group);
#endif /* ndef GICV3_h */
/* EOF GICv3.h */

113
ports_arch/ARMv8-A/threadx_smp/ports/ac6/example_build/sample_threadx/GICv3_aliases.h Normal file
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//
// Aliases for GICv3 registers
//
// Copyright (c) 2016-2017 Arm Limited (or its affiliates). All rights reserved.
// Use, modification and redistribution of this file is subject to your possession of a
// valid End User License Agreement for the Arm Product of which these examples are part of
// and your compliance with all applicable terms and conditions of such licence agreement.
//
#ifndef GICV3_ALIASES_H
#define GICV3_ALIASES_H
#ifndef __clang__
/*
* Mapping of MSR and MRS to physical and virtual CPU interface registers
*
* Arm Generic Interrupt Controller Architecture Specification
* GIC architecture version 3.0 and version 4.0
* Table 8-5
*/
#define ICC_AP0R0_EL1 S3_0_C12_C8_4
#define ICC_AP0R1_EL1 S3_0_C12_C8_5
#define ICC_AP0R2_EL1 S3_0_C12_C8_6
#define ICC_AP0R3_EL1 S3_0_C12_C8_7
#define ICC_AP1R0_EL1 S3_0_C12_C9_0
#define ICC_AP1R1_EL1 S3_0_C12_C9_1
#define ICC_AP1R2_EL1 S3_0_C12_C9_2
#define ICC_AP1R3_EL1 S3_0_C12_C9_3
#define ICC_ASGI1R_EL1 S3_0_C12_C11_6
#define ICC_BPR0_EL1 S3_0_C12_C8_3
#define ICC_BPR1_EL1 S3_0_C12_C12_3
#define ICC_CTLR_EL1 S3_0_C12_C12_4
#define ICC_CTLR_EL3 S3_6_C12_C12_4
#define ICC_DIR_EL1 S3_0_C12_C11_1
#define ICC_EOIR0_EL1 S3_0_C12_C8_1
#define ICC_EOIR1_EL1 S3_0_C12_C12_1
#define ICC_HPPIR0_EL1 S3_0_C12_C8_2
#define ICC_HPPIR1_EL1 S3_0_C12_C12_2
#define ICC_IAR0_EL1 S3_0_C12_C8_0
#define ICC_IAR1_EL1 S3_0_C12_C12_0
#define ICC_IGRPEN0_EL1 S3_0_C12_C12_6
#define ICC_IGRPEN1_EL1 S3_0_C12_C12_7
#define ICC_IGRPEN1_EL3 S3_6_C12_C12_7
#define ICC_PMR_EL1 S3_0_C4_C6_0
#define ICC_RPR_EL1 S3_0_C12_C11_3
#define ICC_SGI0R_EL1 S3_0_C12_C11_7
#define ICC_SGI1R_EL1 S3_0_C12_C11_5
#define ICC_SRE_EL1 S3_0_C12_C12_5
#define ICC_SRE_EL2 S3_4_C12_C9_5
#define ICC_SRE_EL3 S3_6_C12_C12_5
/*
* Mapping of MSR and MRS to virtual interface control registers
*
* Arm Generic Interrupt Controller Architecture Specification
* GIC architecture version 3.0 and version 4.0
* Table 8-6
*/
#define ICH_AP0R0_EL2 S3_4_C12_C8_0
#define ICH_AP0R1_EL2 S3_4_C12_C8_1
#define ICH_AP0R2_EL2 S3_4_C12_C8_2
#define ICH_AP0R3_EL2 S3_4_C12_C8_3
#define ICH_AP1R0_EL2 S3_4_C12_C9_0
#define ICH_AP1R1_EL2 S3_4_C12_C9_1
#define ICH_AP1R2_EL2 S3_4_C12_C9_2
#define ICH_AP1R3_EL2 S3_4_C12_C9_3
#define ICH_HCR_EL2 S3_4_C12_C11_0
#define ICH_VTR_EL2 S3_4_C12_C11_1
#define ICH_MISR_EL2 S3_4_C12_C11_2
#define ICH_EISR_EL2 S3_4_C12_C11_3
#define ICH_ELRSR_EL2 S3_4_C12_C11_5
#define ICH_VMCR_EL2 S3_4_C12_C11_7
#define ICH_LR0_EL2 S3_4_C12_C12_0
#define ICH_LR1_EL2 S3_4_C12_C12_1
#define ICH_LR2_EL2 S3_4_C12_C12_2
#define ICH_LR3_EL2 S3_4_C12_C12_3
#define ICH_LR4_EL2 S3_4_C12_C12_4
#define ICH_LR5_EL2 S3_4_C12_C12_5
#define ICH_LR6_EL2 S3_4_C12_C12_6
#define ICH_LR7_EL2 S3_4_C12_C12_7
#define ICH_LR8_EL2 S3_4_C12_C13_0
#define ICH_LR9_EL2 S3_4_C12_C13_1
#define ICH_LR10_EL2 S3_4_C12_C13_2
#define ICH_LR11_EL2 S3_4_C12_C13_3
#define ICH_LR12_EL2 S3_4_C12_C13_4
#define ICH_LR13_EL2 S3_4_C12_C13_5
#define ICH_LR14_EL2 S3_4_C12_C13_6
#define ICH_LR15_EL2 S3_4_C12_C13_7
#endif /* not __clang__ */
#endif /* GICV3_ALIASES */

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/*
* GICv3_gicc.h - prototypes and inline functions for GICC system register operations
*
* Copyright (c) 2014-2017 Arm Limited (or its affiliates). All rights reserved.
* Use, modification and redistribution of this file is subject to your possession of a
* valid End User License Agreement for the Arm Product of which these examples are part of
* and your compliance with all applicable terms and conditions of such licence agreement.
*/
#ifndef GICV3_gicc_h
#define GICV3_gicc_h
#include "GICv3_aliases.h"
#define stringify_no_expansion(x) #x
#define stringify(x) stringify_no_expansion(x)
/**********************************************************************/
typedef enum
{
sreSRE = (1 << 0),
sreDFB = (1 << 1),
sreDIB = (1 << 2),
sreEnable = (1 << 3)
} ICC_SREBits_t;
static inline void setICC_SRE_EL1(ICC_SREBits_t mode)
{
asm("msr "stringify(ICC_SRE_EL1)", %0\n; isb" :: "r" ((uint64_t)mode));
}
static inline uint64_t getICC_SRE_EL1(void)
{
uint64_t retc;
asm("mrs %0, "stringify(ICC_SRE_EL1)"\n" : "=r" (retc));
return retc;
}
static inline void setICC_SRE_EL2(ICC_SREBits_t mode)
{
asm("msr "stringify(ICC_SRE_EL2)", %0\n; isb" :: "r" ((uint64_t)mode));
}
static inline uint64_t getICC_SRE_EL2(void)
{
uint64_t retc;
asm("mrs %0, "stringify(ICC_SRE_EL2)"\n" : "=r" (retc));
return retc;
}
static inline void setICC_SRE_EL3(ICC_SREBits_t mode)
{
asm("msr "stringify(ICC_SRE_EL3)", %0\n; isb" :: "r" ((uint64_t)mode));
}
static inline uint64_t getICC_SRE_EL3(void)
{
uint64_t retc;
asm("mrs %0, "stringify(ICC_SRE_EL3)"\n" : "=r" (retc));
return retc;
}
/**********************************************************************/
typedef enum
{
igrpEnable = (1 << 0),
igrpEnableGrp1NS = (1 << 0),
igrpEnableGrp1S = (1 << 2)
} ICC_IGRPBits_t;
static inline void setICC_IGRPEN0_EL1(ICC_IGRPBits_t mode)
{
asm("msr "stringify(ICC_IGRPEN0_EL1)", %0\n; isb" :: "r" ((uint64_t)mode));
}
static inline void setICC_IGRPEN1_EL1(ICC_IGRPBits_t mode)
{
asm("msr "stringify(ICC_IGRPEN1_EL1)", %0\n; isb" :: "r" ((uint64_t)mode));
}
static inline void setICC_IGRPEN1_EL3(ICC_IGRPBits_t mode)
{
asm("msr "stringify(ICC_IGRPEN1_EL3)", %0\n; isb" :: "r" ((uint64_t)mode));
}
/**********************************************************************/
typedef enum
{
ctlrCBPR = (1 << 0),
ctlrCBPR_EL1S = (1 << 0),
ctlrEOImode = (1 << 1),
ctlrCBPR_EL1NS = (1 << 1),
ctlrEOImode_EL3 = (1 << 2),
ctlrEOImode_EL1S = (1 << 3),
ctlrEOImode_EL1NS = (1 << 4),
ctlrRM = (1 << 5),
ctlrPMHE = (1 << 6)
} ICC_CTLRBits_t;
static inline void setICC_CTLR_EL1(ICC_CTLRBits_t mode)
{
asm("msr "stringify(ICC_CTLR_EL1)", %0\n; isb" :: "r" ((uint64_t)mode));
}
static inline uint64_t getICC_CTLR_EL1(void)
{
uint64_t retc;
asm("mrs %0, "stringify(ICC_CTLR_EL1)"\n" : "=r" (retc));
return retc;
}
static inline void setICC_CTLR_EL3(ICC_CTLRBits_t mode)
{
asm("msr "stringify(ICC_CTLR_EL3)", %0\n; isb" :: "r" ((uint64_t)mode));
}
static inline uint64_t getICC_CTLR_EL3(void)
{
uint64_t retc;
asm("mrs %0, "stringify(ICC_CTLR_EL3)"\n" : "=r" (retc));
return retc;
}
/**********************************************************************/
static inline uint64_t getICC_IAR0(void)
{
uint64_t retc;
asm("mrs %0, "stringify(ICC_IAR0_EL1)"\n" : "=r" (retc));
return retc;
}
static inline uint64_t getICC_IAR1(void)
{
uint64_t retc;
asm("mrs %0, "stringify(ICC_IAR1_EL1)"\n" : "=r" (retc));
return retc;
}
static inline void setICC_EOIR0(uint32_t interrupt)
{
asm("msr "stringify(ICC_EOIR0_EL1)", %0\n; isb" :: "r" ((uint64_t)interrupt));
}
static inline void setICC_EOIR1(uint32_t interrupt)
{
asm("msr "stringify(ICC_EOIR1_EL1)", %0\n; isb" :: "r" ((uint64_t)interrupt));
}
static inline void setICC_DIR(uint32_t interrupt)
{
asm("msr "stringify(ICC_DIR_EL1)", %0\n; isb" :: "r" ((uint64_t)interrupt));
}
static inline void setICC_PMR(uint32_t priority)
{
asm("msr "stringify(ICC_PMR_EL1)", %0\n; isb" :: "r" ((uint64_t)priority));
}
static inline void setICC_BPR0(uint32_t binarypoint)
{
asm("msr "stringify(ICC_BPR0_EL1)", %0\n; isb" :: "r" ((uint64_t)binarypoint));
}
static inline void setICC_BPR1(uint32_t binarypoint)
{
asm("msr "stringify(ICC_BPR1_EL1)", %0\n; isb" :: "r" ((uint64_t)binarypoint));
}
static inline uint64_t getICC_BPR0(void)
{
uint64_t retc;
asm("mrs %0, "stringify(ICC_BPR0_EL1)"\n" : "=r" (retc));
return retc;
}
static inline uint64_t getICC_BPR1(void)
{
uint64_t retc;
asm("mrs %0, "stringify(ICC_BPR1_EL1)"\n" : "=r" (retc));
return retc;
}
static inline uint64_t getICC_RPR(void)
{
uint64_t retc;
asm("mrs %0, "stringify(ICC_RPR_EL1)"\n" : "=r" (retc));
return retc;
}
/**********************************************************************/
typedef enum
{
sgirIRMTarget = 0,
sgirIRMAll = (1ull << 40)
} ICC_SGIRBits_t;
static inline void setICC_SGI0R(uint8_t aff3, uint8_t aff2,
uint8_t aff1, ICC_SGIRBits_t irm,
uint16_t targetlist, uint8_t intid)
{
uint64_t packedbits = (((uint64_t)aff3 << 48) | ((uint64_t)aff2 << 32) | \
((uint64_t)aff1 << 16) | irm | targetlist | \
((uint64_t)(intid & 0x0f) << 24));
asm("msr "stringify(ICC_SGI0R_EL1)", %0\n; isb" :: "r" (packedbits));
}
static inline void setICC_SGI1R(uint8_t aff3, uint8_t aff2,
uint8_t aff1, ICC_SGIRBits_t irm,
uint16_t targetlist, uint8_t intid)
{
uint64_t packedbits = (((uint64_t)aff3 << 48) | ((uint64_t)aff2 << 32) | \
((uint64_t)aff1 << 16) | irm | targetlist | \
((uint64_t)(intid & 0x0f) << 24));
asm("msr "stringify(ICC_SGI1R_EL1)", %0\n; isb" :: "r" (packedbits));
}
static inline void setICC_ASGI1R(uint8_t aff3, uint8_t aff2,
uint8_t aff1, ICC_SGIRBits_t irm,
uint16_t targetlist, uint8_t intid)
{
uint64_t packedbits = (((uint64_t)aff3 << 48) | ((uint64_t)aff2 << 32) | \
((uint64_t)aff1 << 16) | irm | targetlist | \
((uint64_t)(intid & 0x0f) << 24));
asm("msr "stringify(ICC_ASGI1R_EL1)", %0\n; isb" :: "r" (packedbits));
}
#endif /* ndef GICV3_gicc_h */

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/*
* GICv3_gicd.c - generic driver code for GICv3 distributor
*
* Copyright (c) 2014-2017 Arm Limited (or its affiliates). All rights reserved.
* Use, modification and redistribution of this file is subject to your possession of a
* valid End User License Agreement for the Arm Product of which these examples are part of
* and your compliance with all applicable terms and conditions of such licence agreement.
*/
#include <stdint.h>
#include "GICv3.h"
typedef struct
{
volatile uint32_t GICD_CTLR; // +0x0000
const volatile uint32_t GICD_TYPER; // +0x0004
const volatile uint32_t GICD_IIDR; // +0x0008
const volatile uint32_t padding0; // +0x000c
volatile uint32_t GICD_STATUSR; // +0x0010
const volatile uint32_t padding1[3]; // +0x0014
volatile uint32_t IMP_DEF[8]; // +0x0020
volatile uint32_t GICD_SETSPI_NSR; // +0x0040
const volatile uint32_t padding2; // +0x0044
volatile uint32_t GICD_CLRSPI_NSR; // +0x0048
const volatile uint32_t padding3; // +0x004c
volatile uint32_t GICD_SETSPI_SR; // +0x0050
const volatile uint32_t padding4; // +0x0054
volatile uint32_t GICD_CLRSPI_SR; // +0x0058
const volatile uint32_t padding5[3]; // +0x005c
volatile uint32_t GICD_SEIR; // +0x0068
const volatile uint32_t padding6[5]; // +0x006c
volatile uint32_t GICD_IGROUPR[32]; // +0x0080
volatile uint32_t GICD_ISENABLER[32]; // +0x0100
volatile uint32_t GICD_ICENABLER[32]; // +0x0180
volatile uint32_t GICD_ISPENDR[32]; // +0x0200
volatile uint32_t GICD_ICPENDR[32]; // +0x0280
volatile uint32_t GICD_ISACTIVER[32]; // +0x0300
volatile uint32_t GICD_ICACTIVER[32]; // +0x0380
volatile uint8_t GICD_IPRIORITYR[1024]; // +0x0400
volatile uint8_t GICD_ITARGETSR[1024]; // +0x0800
volatile uint32_t GICD_ICFGR[64]; // +0x0c00
volatile uint32_t GICD_IGRPMODR[32]; // +0x0d00
const volatile uint32_t padding7[32]; // +0x0d80
volatile uint32_t GICD_NSACR[64]; // +0x0e00
volatile uint32_t GICD_SGIR; // +0x0f00
const volatile uint32_t padding8[3]; // +0x0f04
volatile uint32_t GICD_CPENDSGIR[4]; // +0x0f10
volatile uint32_t GICD_SPENDSGIR[4]; // +0x0f20
const volatile uint32_t padding9[52]; // +0x0f30
const volatile uint32_t padding10[5120]; // +0x1000
volatile uint64_t GICD_IROUTER[1024]; // +0x6000
} GICv3_distributor;
/*
* use the scatter file to place GICD
*/
static GICv3_distributor __attribute__((section(".bss.distributor"))) gicd;
void ConfigGICD(GICDCTLRFlags_t flags)
{
gicd.GICD_CTLR = flags;
}
void EnableGICD(GICDCTLRFlags_t flags)
{
gicd.GICD_CTLR |= flags;
}
void DisableGICD(GICDCTLRFlags_t flags)
{
gicd.GICD_CTLR &= ~flags;
}
void SyncAREinGICD(GICDCTLRFlags_t flags, uint32_t dosync)
{
if (dosync)
{
const uint32_t tmask = gicdctlr_ARE_S | gicdctlr_ARE_NS;
const uint32_t tval = flags & tmask;
while ((gicd.GICD_CTLR & tmask) != tval)
continue;
}
else
gicd.GICD_CTLR = flags;
}
void EnableSPI(uint32_t id)
{
uint32_t bank;
/*
* GICD_ISENABLER has 32 interrupts per register
*/
bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ISENABLER);
id &= 32 - 1;
gicd.GICD_ISENABLER[bank] = 1 << id;
return;
}
void DisableSPI(uint32_t id)
{
uint32_t bank;
/*
* GICD_ISENABLER has 32 interrupts per register
*/
bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ICENABLER);
id &= 32 - 1;
gicd.GICD_ICENABLER[bank] = 1 << id;
return;
}
void SetSPIPriority(uint32_t id, uint32_t priority)
{
uint32_t bank;
/*
* GICD_IPRIORITYR has one byte-wide entry per interrupt
*/
bank = id & RANGE_LIMIT(gicd.GICD_IPRIORITYR);
gicd.GICD_IPRIORITYR[bank] = priority;
}
uint32_t GetSPIPriority(uint32_t id)
{
uint32_t bank;
/*
* GICD_IPRIORITYR has one byte-wide entry per interrupt
*/
bank = id & RANGE_LIMIT(gicd.GICD_IPRIORITYR);
return (uint32_t)(gicd.GICD_IPRIORITYR[bank]);
}
void SetSPIRoute(uint32_t id, uint64_t affinity, GICDIROUTERBits_t mode)
{
uint32_t bank;
/*
* GICD_IROUTER has one doubleword-wide entry per interrupt
*/
bank = id & RANGE_LIMIT(gicd.GICD_IROUTER);
gicd.GICD_IROUTER[bank] = affinity | (uint64_t)mode;
}
uint64_t GetSPIRoute(uint32_t id)
{
uint32_t bank;
/*
* GICD_IROUTER has one doubleword-wide entry per interrupt
*/
bank = id & RANGE_LIMIT(gicd.GICD_IROUTER);
return gicd.GICD_IROUTER[bank];
}
void SetSPITarget(uint32_t id, uint32_t target)
{
uint32_t bank;
/*
* GICD_ITARGETSR has one byte-wide entry per interrupt
*/
bank = id & RANGE_LIMIT(gicd.GICD_ITARGETSR);
gicd.GICD_ITARGETSR[bank] = target;
}
uint32_t GetSPITarget(uint32_t id)
{
uint32_t bank;
/*
* GICD_ITARGETSR has one byte-wide entry per interrupt
*/
/*
* GICD_ITARGETSR has 4 interrupts per register, i.e. 8-bits of
* target bitmap per register
*/
bank = id & RANGE_LIMIT(gicd.GICD_ITARGETSR);
return (uint32_t)(gicd.GICD_ITARGETSR[bank]);
}
void ConfigureSPI(uint32_t id, GICDICFGRBits_t config)
{
uint32_t bank, tmp;
/*
* GICD_ICFGR has 16 interrupts per register, i.e. 2-bits of
* configuration per register
*/
bank = (id >> 4) & RANGE_LIMIT(gicd.GICD_ICFGR);
config &= 3;
id = (id & 0xf) << 1;
tmp = gicd.GICD_ICFGR[bank];
tmp &= ~(3 << id);
tmp |= config << id;
gicd.GICD_ICFGR[bank] = tmp;
}
void SetSPIPending(uint32_t id)
{
uint32_t bank;
/*
* GICD_ISPENDR has 32 interrupts per register
*/
bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ISPENDR);
id &= 0x1f;
gicd.GICD_ISPENDR[bank] = 1 << id;
}
void ClearSPIPending(uint32_t id)
{
uint32_t bank;
/*
* GICD_ICPENDR has 32 interrupts per register
*/
bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ICPENDR);
id &= 0x1f;
gicd.GICD_ICPENDR[bank] = 1 << id;
}
uint32_t GetSPIPending(uint32_t id)
{
uint32_t bank;
/*
* GICD_ICPENDR has 32 interrupts per register
*/
bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ICPENDR);
id &= 0x1f;
return (gicd.GICD_ICPENDR[bank] >> id) & 1;
}
void SetSPISecurity(uint32_t id, GICIGROUPRBits_t group)
{
uint32_t bank, groupmod;
/*
* GICD_IGROUPR has 32 interrupts per register
*/
bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_IGROUPR);
id &= 0x1f;
/*
* the single group argument is split into two separate
* registers, so filter out and remove the (new to gicv3)
* group modifier bit
*/
groupmod = (group >> 1) & 1;
group &= 1;
/*
* either set or clear the Group bit for the interrupt as appropriate
*/
if (group)
gicd.GICD_IGROUPR[bank] |= 1 << id;
else
gicd.GICD_IGROUPR[bank] &= ~(1 << id);
/*
* now deal with groupmod
*/
if (groupmod)
gicd.GICD_IGRPMODR[bank] |= 1 << id;
else
gicd.GICD_IGRPMODR[bank] &= ~(1 << id);
}
void SetSPISecurityBlock(uint32_t block, GICIGROUPRBits_t group)
{
uint32_t groupmod;
const uint32_t nbits = (sizeof group * 8) - 1;
/*
* GICD_IGROUPR has 32 interrupts per register
*/
block &= RANGE_LIMIT(gicd.GICD_IGROUPR);
/*
* get each bit of group config duplicated over all 32-bits in a word
*/
groupmod = (uint32_t)(((int32_t)group << (nbits - 1)) >> 31);
group = (uint32_t)(((int32_t)group << nbits) >> 31);
/*
* set the security state for this block of SPIs
*/
gicd.GICD_IGROUPR[block] = group;
gicd.GICD_IGRPMODR[block] = groupmod;
}
void SetSPISecurityAll(GICIGROUPRBits_t group)
{
uint32_t block;
/*
* GICD_TYPER.ITLinesNumber gives (No. SPIS / 32) - 1, and we
* want to iterate over all blocks excluding 0 (which are the
* SGI/PPI interrupts, and not relevant here)
*/
for (block = (gicd.GICD_TYPER & ((1 << 5) - 1)); block > 0; --block)
SetSPISecurityBlock(block, group);
}
/* EOF GICv3_gicd.c */

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/*
* GICv3_gicr.c - generic driver code for GICv3 redistributor
*
* Copyright (c) 2014-2019 Arm Limited (or its affiliates). All rights reserved.
* Use, modification and redistribution of this file is subject to your possession of a
* valid End User License Agreement for the Arm Product of which these examples are part of
* and your compliance with all applicable terms and conditions of such licence agreement.
*/
#include "GICv3.h"
/*
* physical LPI Redistributor register map
*/
typedef struct
{
volatile uint32_t GICR_CTLR; // +0x0000 - RW - Redistributor Control Register
const volatile uint32_t GICR_IIDR; // +0x0004 - RO - Implementer Identification Register
const volatile uint32_t GICR_TYPER[2]; // +0x0008 - RO - Redistributor Type Register
volatile uint32_t GICR_STATUSR; // +0x0010 - RW - Error Reporting Status Register, optional
volatile uint32_t GICR_WAKER; // +0x0014 - RW - Redistributor Wake Register
const volatile uint32_t padding1[2]; // +0x0018 - RESERVED
#ifndef USE_GIC600
volatile uint32_t IMPDEF1[8]; // +0x0020 - ?? - IMPLEMENTATION DEFINED
#else
volatile uint32_t GICR_FCTLR; // +0x0020 - RW - Function Control Register
volatile uint32_t GICR_PWRR; // +0x0024 - RW - Power Management Control Register
volatile uint32_t GICR_CLASS; // +0x0028 - RW - Class Register
const volatile uint32_t padding2[5]; // +0x002C - RESERVED
#endif
volatile uint64_t GICR_SETLPIR; // +0x0040 - WO - Set LPI Pending Register
volatile uint64_t GICR_CLRLPIR; // +0x0048 - WO - Clear LPI Pending Register
const volatile uint32_t padding3[8]; // +0x0050 - RESERVED
volatile uint64_t GICR_PROPBASER; // +0x0070 - RW - Redistributor Properties Base Address Register
volatile uint64_t GICR_PENDBASER; // +0x0078 - RW - Redistributor LPI Pending Table Base Address Register
const volatile uint32_t padding4[8]; // +0x0080 - RESERVED
volatile uint64_t GICR_INVLPIR; // +0x00A0 - WO - Redistributor Invalidate LPI Register
const volatile uint32_t padding5[2]; // +0x00A8 - RESERVED
volatile uint64_t GICR_INVALLR; // +0x00B0 - WO - Redistributor Invalidate All Register
const volatile uint32_t padding6[2]; // +0x00B8 - RESERVED
volatile uint64_t GICR_SYNCR; // +0x00C0 - RO - Redistributor Synchronize Register
const volatile uint32_t padding7[2]; // +0x00C8 - RESERVED
const volatile uint32_t padding8[12]; // +0x00D0 - RESERVED
volatile uint64_t IMPDEF2; // +0x0100 - WO - IMPLEMENTATION DEFINED
const volatile uint32_t padding9[2]; // +0x0108 - RESERVED
volatile uint64_t IMPDEF3; // +0x0110 - WO - IMPLEMENTATION DEFINED
const volatile uint32_t padding10[2]; // +0x0118 - RESERVED
} GICv3_redistributor_RD;
/*
* SGI and PPI Redistributor register map
*/
typedef struct
{
const volatile uint32_t padding1[32]; // +0x0000 - RESERVED
volatile uint32_t GICR_IGROUPR0; // +0x0080 - RW - Interrupt Group Registers (Security Registers in GICv1)
const volatile uint32_t padding2[31]; // +0x0084 - RESERVED
volatile uint32_t GICR_ISENABLER; // +0x0100 - RW - Interrupt Set-Enable Registers
const volatile uint32_t padding3[31]; // +0x0104 - RESERVED
volatile uint32_t GICR_ICENABLER; // +0x0180 - RW - Interrupt Clear-Enable Registers
const volatile uint32_t padding4[31]; // +0x0184 - RESERVED
volatile uint32_t GICR_ISPENDR; // +0x0200 - RW - Interrupt Set-Pending Registers
const volatile uint32_t padding5[31]; // +0x0204 - RESERVED
volatile uint32_t GICR_ICPENDR; // +0x0280 - RW - Interrupt Clear-Pending Registers
const volatile uint32_t padding6[31]; // +0x0284 - RESERVED
volatile uint32_t GICR_ISACTIVER; // +0x0300 - RW - Interrupt Set-Active Register
const volatile uint32_t padding7[31]; // +0x0304 - RESERVED
volatile uint32_t GICR_ICACTIVER; // +0x0380 - RW - Interrupt Clear-Active Register
const volatile uint32_t padding8[31]; // +0x0184 - RESERVED
volatile uint8_t GICR_IPRIORITYR[32]; // +0x0400 - RW - Interrupt Priority Registers
const volatile uint32_t padding9[504]; // +0x0420 - RESERVED
volatile uint32_t GICR_ICnoFGR[2]; // +0x0C00 - RW - Interrupt Configuration Registers
const volatile uint32_t padding10[62]; // +0x0C08 - RESERVED
volatile uint32_t GICR_IGRPMODR0; // +0x0D00 - RW - ????
const volatile uint32_t padding11[63]; // +0x0D04 - RESERVED
volatile uint32_t GICR_NSACR; // +0x0E00 - RW - Non-Secure Access Control Register
} GICv3_redistributor_SGI;
/*
* We have a multiplicity of GIC Redistributors; on the GIC-AEM and
* GIC-500 they are arranged as one 128KB region per redistributor: one
* 64KB page of GICR LPI registers, and one 64KB page of GICR Private
* Int registers
*/
typedef struct
{
union
{
GICv3_redistributor_RD RD_base;
uint8_t padding[64 * 1024];
} RDblock;
union
{
GICv3_redistributor_SGI SGI_base;
uint8_t padding[64 * 1024];
} SGIblock;
} GICv3_GICR;
/*
* use the scatter file to place GIC Redistributor base address
*
* although this code doesn't know how many Redistributor banks
* a particular system will have, we declare gicrbase as an array
* to avoid unwanted compiler optimisations when calculating the
* base of a particular Redistributor bank
*/
static const GICv3_GICR gicrbase[2] __attribute__((section (".bss.redistributor")));
/**********************************************************************/
/*
* utility functions to calculate base of a particular
* Redistributor bank
*/
static inline GICv3_redistributor_RD *const getgicrRD(uint32_t gicr)
{
GICv3_GICR *const arraybase = (GICv3_GICR *const)&gicrbase;
return &((arraybase + gicr)->RDblock.RD_base);
}
static inline GICv3_redistributor_SGI *const getgicrSGI(uint32_t gicr)
{
GICv3_GICR *arraybase = (GICv3_GICR *)(&gicrbase);
return &(arraybase[gicr].SGIblock.SGI_base);
}
/**********************************************************************/
// This function walks a block of RDs to find one with the matching affinity
uint32_t GetGICR(uint32_t affinity)
{
GICv3_redistributor_RD* gicr;
uint32_t index = 0;
do
{
gicr = getgicrRD(index);
if (gicr->GICR_TYPER[1] == affinity)
return index;
index++;
}
while((gicr->GICR_TYPER[0] & (1<<4)) == 0); // Keep looking until GICR_TYPER.Last reports no more RDs in block
return 0xFFFFFFFF; // return -1 to signal not RD found
}
void WakeupGICR(uint32_t gicr)
{
GICv3_redistributor_RD *const gicrRD = getgicrRD(gicr);
#ifdef USE_GIC600
//Power up Re-distributor for GIC-600
gicrRD->GICR_PWRR = 0x2;
#endif
/*
* step 1 - ensure GICR_WAKER.ProcessorSleep is off
*/
gicrRD->GICR_WAKER &= ~gicrwaker_ProcessorSleep;
/*
* step 2 - wait for children asleep to be cleared
*/
while ((gicrRD->GICR_WAKER & gicrwaker_ChildrenAsleep) != 0)
continue;
/*
* OK, GICR is go
*/
return;
}
void EnablePrivateInt(uint32_t gicr, uint32_t id)
{
GICv3_redistributor_SGI *const gicrSGI = getgicrSGI(gicr);
id &= 0x1f;
gicrSGI->GICR_ISENABLER = 1 << id;
}
void DisablePrivateInt(uint32_t gicr, uint32_t id)
{
GICv3_redistributor_SGI *const gicrSGI = getgicrSGI(gicr);
id &= 0x1f;
gicrSGI->GICR_ICENABLER = 1 << id;
}
void SetPrivateIntPriority(uint32_t gicr, uint32_t id, uint32_t priority)
{
GICv3_redistributor_SGI *const gicrSGI = getgicrSGI(gicr);
/*
* GICD_IPRIORITYR has one byte-wide entry per interrupt
*/
id &= RANGE_LIMIT(gicrSGI->GICR_IPRIORITYR);
gicrSGI->GICR_IPRIORITYR[id] = priority;
}
uint32_t GetPrivateIntPriority(uint32_t gicr, uint32_t id)
{
GICv3_redistributor_SGI *const gicrSGI = getgicrSGI(gicr);
/*
* GICD_IPRIORITYR has one byte-wide entry per interrupt
*/
id &= RANGE_LIMIT(gicrSGI->GICR_IPRIORITYR);
return (uint32_t)(gicrSGI->GICR_IPRIORITYR[id]);
}
void SetPrivateIntPending(uint32_t gicr, uint32_t id)
{
GICv3_redistributor_SGI *const gicrSGI = getgicrSGI(gicr);
/*
* GICR_ISPENDR is one 32-bit register
*/
id &= 0x1f;
gicrSGI->GICR_ISPENDR = 1 << id;
}
void ClearPrivateIntPending(uint32_t gicr, uint32_t id)
{
GICv3_redistributor_SGI *const gicrSGI = getgicrSGI(gicr);
/*
* GICR_ICPENDR is one 32-bit register
*/
id &= 0x1f;
gicrSGI->GICR_ICPENDR = 1 << id;
}
uint32_t GetPrivateIntPending(uint32_t gicr, uint32_t id)
{
GICv3_redistributor_SGI *const gicrSGI = getgicrSGI(gicr);
/*
* GICR_ISPENDR is one 32-bit register
*/
id &= 0x1f;
return (gicrSGI->GICR_ISPENDR >> id) & 0x01;
}
void SetPrivateIntSecurity(uint32_t gicr, uint32_t id, GICIGROUPRBits_t group)
{
GICv3_redistributor_SGI *const gicrSGI = getgicrSGI(gicr);
uint32_t groupmod;
/*
* GICR_IGROUPR0 is one 32-bit register
*/
id &= 0x1f;
/*
* the single group argument is split into two separate
* registers, so filter out and remove the (new to gicv3)
* group modifier bit
*/
groupmod = (group >> 1) & 1;
group &= 1;
/*
* either set or clear the Group bit for the interrupt as appropriate
*/
if (group)
gicrSGI->GICR_IGROUPR0 |= 1 << id;
else
gicrSGI->GICR_IGROUPR0 &= ~(1 << id);
/*
* now deal with groupmod
*/
if (groupmod)
gicrSGI->GICR_IGRPMODR0 |= 1 << id;
else
gicrSGI->GICR_IGRPMODR0 &= ~(1 << id);
}
void SetPrivateIntSecurityBlock(uint32_t gicr, GICIGROUPRBits_t group)
{
GICv3_redistributor_SGI *const gicrSGI = getgicrSGI(gicr);
const uint32_t nbits = (sizeof group * 8) - 1;
uint32_t groupmod;
/*
* get each bit of group config duplicated over all 32-bits
*/
groupmod = (uint32_t)(((int32_t)group << (nbits - 1)) >> 31);
group = (uint32_t)(((int32_t)group << nbits) >> 31);
/*
* set the security state for this block of SPIs
*/
gicrSGI->GICR_IGROUPR0 = group;
gicrSGI->GICR_IGRPMODR0 = groupmod;
}
/* EOF GICv3_gicr.c */

133
ports_arch/ARMv8-A/threadx_smp/ports/ac6/example_build/sample_threadx/MP_Mutexes.S Normal file
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//
// Armv8-A AArch64 - Basic Mutex Example
// Includes the option (USE_LSE_ATOMIC) to use Large System Extension (LSE) atomics introduced in Armv8.1-A
//
// Copyright (c) 2012-2019 Arm Limited (or its affiliates). All rights reserved.
// Use, modification and redistribution of this file is subject to your possession of a
// valid End User License Agreement for the Arm Product of which these examples are part of
// and your compliance with all applicable terms and conditions of such licence agreement.
//
.text
.cfi_sections .debug_frame // put stack frame info into .debug_frame instead of .eh_frame
.global _mutex_initialize
.global _mutex_acquire
.global _mutex_release
//
// These routines implement the mutex management functions required for running
// the Arm C library in a multi-threaded environment.
//
// They use a value of 0 to represent an unlocked mutex, and 1 for a locked mutex
//
// **********************************************************************
//
.type _mutex_initialize, "function"
.cfi_startproc
_mutex_initialize:
//
// mark the mutex as unlocked
//
mov w1, #0
str w1, [x0]
//
// we are running multi-threaded, so set a non-zero return
// value (function prototype says use 1)
//
mov w0, #1
ret
.cfi_endproc
#if !defined(USE_LSE_ATOMIC)
.type _mutex_acquire, "function"
.cfi_startproc
_mutex_acquire:
//
// send ourselves an event, so we don't stick on the wfe at the
// top of the loop
//
sevl
//
// wait until the mutex is available
//
loop:
wfe
ldaxr w1, [x0]
cbnz w1, loop
//
// mutex is (at least, it was) available - try to claim it
//
mov w1, #1
stxr w2, w1, [x0]
cbnz w2, loop
//
// OK, we have the mutex, our work is done here
//
ret
.cfi_endproc
.type _mutex_release, "function"
.cfi_startproc
_mutex_release:
mov w1, #0
stlr w1, [x0]
ret
.cfi_endproc
#else // LSE version
.type _mutex_acquire, "function"
.cfi_startproc
_mutex_acquire:
// This uses a "ticket lock". The lock is stored as a 32-bit value:
// - the upper 16-bits record the thread's ticket number ("take a ticket")
// - the lower 16-bits record the ticket being served ("now serving")
// atomically load then increment the thread's ticket number ("take a ticket")
mov w3, #(1 << 16)
ldadda w3, w1, [x0]
// is the ticket now being served?
eor w2, w1, w1, ror #16
cbz w2, loop_exit
// no, so wait for the ticket to be served
// send a local event to avoid missing an unlock before the exclusive load
sevl
loop:
wfe
ldaxrh w3, [x0]
eor w2, w3, w1, lsr #16
cbnz w2, loop
//
// OK, we have the mutex, our work is done here
//
loop_exit:
ret
.cfi_endproc
.type _mutex_release, "function"
.cfi_startproc
_mutex_release:
mov w1, #1
staddlh w1, [x0]
ret
.cfi_endproc
#endif

66
ports_arch/ARMv8-A/threadx_smp/ports/ac6/example_build/sample_threadx/MP_Mutexes.h Normal file
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/*
* Armv8-A AArch64 - Basic Mutex Example
*
* Copyright (c) 2012-2014 Arm Limited (or its affiliates). All rights reserved.
* Use, modification and redistribution of this file is subject to your possession of a
* valid End User License Agreement for the Arm Product of which these examples are part of
* and your compliance with all applicable terms and conditions of such licence agreement.
*/
#ifndef MP_MUTEX_H
#define MP_MUTEX_H
/*
* The Arm C library calls-out to these functions to manage multithreading.
* They can also be called by user application code.
*
* Mutex type is specified by the Arm C library
*
* Declare function prototypes for libc mutex routines
*/
typedef signed int *mutex;
/*
* int _mutex_initialize(mutex *m)
*
* Inputs
* mutex *m - pointer to the 32-bit word associated with the mutex
*
* Returns
* 0 - application is non-threaded
* 1 - application is threaded
* The C library uses the return result to indicate whether it is being used in a multithreaded environment.
*/
int _mutex_initialize(mutex *m);
/*
* void _mutex_acquire(mutex *m)
*
* Inputs
* mutex *m - pointer to the 32-bit word associated with the mutex
*
* Returns
* <nothing>
*
* Side Effects
* Routine does not return until the mutex has been claimed. A load-acquire
* is used to guarantee that the mutex claim is properly ordered with
* respect to any accesses to the resource protected by the mutex
*/
void _mutex_acquire(mutex *m);
/*
* void _mutex_release(mutex *m)
*
* Inputs
* mutex *m - pointer to the 32-bit word associated with the mutex
*
* Returns
* <nothing>
*
* Side Effects
* A store-release is used to guarantee that the mutex release is properly
* ordered with respect any accesses to the resource protected by the mutex
*/
void _mutex_release(mutex *m);
#endif

66
ports_arch/ARMv8-A/threadx_smp/ports/ac6/example_build/sample_threadx/PPM_AEM.h Normal file
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//
// Private Peripheral Map for the v8 Architecture Envelope Model
//
// Copyright (c) 2012-2017 Arm Limited (or its affiliates). All rights reserved.
// Use, modification and redistribution of this file is subject to your possession of a
// valid End User License Agreement for the Arm Product of which these examples are part of
// and your compliance with all applicable terms and conditions of such licence agreement.
//
#ifndef PPM_AEM_H
#define PPM_AEM_H
//
// Distributor layout
//
#define GICD_CTLR 0x0000
#define GICD_TYPER 0x0004
#define GICD_IIDR 0x0008
#define GICD_IGROUP 0x0080
#define GICD_ISENABLE 0x0100
#define GICD_ICENABLE 0x0180
#define GICD_ISPEND 0x0200
#define GICD_ICPEND 0x0280
#define GICD_ISACTIVE 0x0300
#define GICD_ICACTIVE 0x0380
#define GICD_IPRIORITY 0x0400
#define GICD_ITARGETS 0x0800
#define GICD_ICFG 0x0c00
#define GICD_PPISR 0x0d00
#define GICD_SPISR 0x0d04
#define GICD_SGIR 0x0f00
#define GICD_CPENDSGI 0x0f10
#define GICD_SPENDSGI 0x0f20
#define GICD_PIDR4 0x0fd0
#define GICD_PIDR5 0x0fd4
#define GICD_PIDR6 0x0fd8
#define GICD_PIDR7 0x0fdc
#define GICD_PIDR0 0x0fe0
#define GICD_PIDR1 0x0fe4
#define GICD_PIDR2 0x0fe8
#define GICD_PIDR3 0x0fec
#define GICD_CIDR0 0x0ff0
#define GICD_CIDR1 0x0ff4
#define GICD_CIDR2 0x0ff8
#define GICD_CIDR3 0x0ffc
//
// CPU Interface layout
//
#define GICC_CTLR 0x0000
#define GICC_PMR 0x0004
#define GICC_BPR 0x0008
#define GICC_IAR 0x000c
#define GICC_EOIR 0x0010
#define GICC_RPR 0x0014
#define GICC_HPPIR 0x0018
#define GICC_ABPR 0x001c
#define GICC_AIAR 0x0020
#define GICC_AEOIR 0x0024
#define GICC_AHPPIR 0x0028
#define GICC_APR0 0x00d0
#define GICC_NSAPR0 0x00e0
#define GICC_IIDR 0x00fc
#define GICC_DIR 0x1000
#endif // PPM_AEM_H

413
ports_arch/ARMv8-A/threadx_smp/ports/ac6/example_build/sample_threadx/sample_threadx.launch Normal file
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<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<launchConfiguration type="com.arm.debugger.launcher2">
<stringAttribute key="ANDROID_ACTIVITY_NAME" value=""/>
<stringAttribute key="ANDROID_APPLICATION" value=""/>
<stringAttribute key="ANDROID_APP_DIR" value=""/>
<stringAttribute key="ANDROID_PROCESS_NAME" value=""/>
<mapAttribute key="AverageDurationTracker">
<mapEntry key="*Fetching Data" value="34126331"/>
<mapEntry key="*Fetching Data Model" value="1887986"/>
<mapEntry key="*FunctionLoader" value="137168653"/>
<mapEntry key="*list global low level symbols" value="3163826"/>
<mapEntry key="*loading memory from target" value="2367919"/>
<mapEntry key="*loading values from target" value="8665557"/>
<mapEntry key="*trace" value="1527238"/>
<mapEntry key="*updating expressions" value="25251903"/>
<mapEntry key="*updating local_variables" value="836905"/>
<mapEntry key="*updating registers" value="97090462"/>
<mapEntry key="*updating variables" value="877039"/>
<mapEntry key="AddEventObserver" value="5292071"/>
<mapEntry key="Evaluate" value="1689813"/>
<mapEntry key="ResumeToHere" value="20159012"/>
<mapEntry key="Retrieving globals list" value="21298708"/>
<mapEntry key="areCachesAvailable" value="474743"/>
<mapEntry key="backtrace" value="21505977"/>
<mapEntry key="break" value="9764564"/>
<mapEntry key="checking tracepoints" value="372731"/>
<mapEntry key="compute execution mode" value="835755"/>
<mapEntry key="console" value="11946310"/>
<mapEntry key="continue" value="21247618"/>
<mapEntry key="core" value="5451456"/>
<mapEntry key="directory" value="4479981"/>
<mapEntry key="disable" value="2444670"/>
<mapEntry key="disassemble" value="64135505"/>
<mapEntry key="enable" value="5445745"/>
<mapEntry key="evaluate" value="5333036"/>
<mapEntry key="evaluate address" value="1056014"/>
<mapEntry key="finish" value="20115248"/>
<mapEntry key="get byte order" value="633302"/>
<mapEntry key="get capabilities" value="382078"/>
<mapEntry key="get execution addresss" value="403253"/>
<mapEntry key="get source lines" value="951928"/>
<mapEntry key="get substitute paths" value="523052"/>
<mapEntry key="getValidEncodings" value="1202320"/>
<mapEntry key="initialize command help" value="63855085"/>
<mapEntry key="interrupt" value="11210435"/>
<mapEntry key="list breakpoint options" value="2030851"/>
<mapEntry key="list breakpoints" value="1627224"/>
<mapEntry key="list instruction sets" value="1847125"/>
<mapEntry key="list signals" value="1953020"/>
<mapEntry key="list source files" value="573423"/>
<mapEntry key="list watchpoint options" value="6057468"/>
<mapEntry key="list watchpoints" value="970059"/>
<mapEntry key="loadfile" value="386648009"/>
<mapEntry key="next" value="24266800"/>
<mapEntry key="query supports threads" value="215433"/>
<mapEntry key="remove" value="7663692"/>
<mapEntry key="run script" value="44460661"/>
<mapEntry key="set CWD" value="5180571"/>
<mapEntry key="set breakpoint properties" value="10666013"/>
<mapEntry key="set debug-from" value="1157012"/>
<mapEntry key="set substitute-path" value="27245163"/>
<mapEntry key="source use_model_semihosting.ds" value="8849881"/>
<mapEntry key="start" value="50528177"/>
<mapEntry key="step" value="26461127"/>
<mapEntry key="stepi" value="29574773"/>
<mapEntry key="synchronizing trace ranges" value="21582"/>
<mapEntry key="target reset" value="32992642"/>
<mapEntry key="toggleBreakpoint" value="19462208"/>
<mapEntry key="updateBreakpointLocation" value="1868000"/>
<mapEntry key="waitForTargetToStop" value="52570549"/>
<mapEntry key="write expression" value="21220700"/>
</mapAttribute>
<stringAttribute key="CLOCK_SPEED" value="Auto"/>
<listAttribute key="DEBUG_TAB."/>
<stringAttribute key="DEBUG_TAB..RESOURCES.0.TYPE" value="SOURCE_DIR"/>
<stringAttribute key="DEBUG_TAB..RESOURCES.0.VALUE" value="${workspace_loc:/sample_threadx}"/>
<stringAttribute key="DEBUG_TAB..RESOURCES.1.TYPE" value="SOURCE_DIR"/>
<stringAttribute key="DEBUG_TAB..RESOURCES.1.VALUE" value="${workspace_loc:/tx}"/>
<intAttribute key="DEBUG_TAB..RESOURCES.COUNT" value="2"/>
<booleanAttribute key="EVENT_VIEWER_ENABLED" value="false"/>
<stringAttribute key="EVENT_VIEWER_MAX_DEPTH" value="1Mb"/>
<stringAttribute key="EVENT_VIEWER_MAX_DEPTH_NUMBER" value="1048576"/>
<booleanAttribute key="EVENT_VIEWER_STM_ENABLED" value="false"/>
<stringAttribute key="EVENT_VIEWER_STM_MAX_DEPTH" value=""/>
<stringAttribute key="EVENT_VIEWER_STM_MAX_DEPTH_NUMBER" value="0"/>
<intAttribute key="FILES.CONNECT_TO_GDB_SERVER.RESOURCES.COUNT" value="0"/>
<intAttribute key="FILES.DEBUG_EXISTING_ANDROID.RESOURCES.COUNT" value="0"/>
<listAttribute key="FILES.DEBUG_RESIDENT_ANDROID"/>
<stringAttribute key="FILES.DEBUG_RESIDENT_ANDROID.RESOURCES.0.TYPE" value="TARGET_WORKING_DIR"/>
<stringAttribute key="FILES.DEBUG_RESIDENT_ANDROID.RESOURCES.0.VALUE" value=""/>
<intAttribute key="FILES.DEBUG_RESIDENT_ANDROID.RESOURCES.COUNT" value="1"/>
<listAttribute key="FILES.DEBUG_RESIDENT_APP"/>
<stringAttribute key="FILES.DEBUG_RESIDENT_APP.RESOURCES.0.TYPE" value="APPLICATION_ON_TARGET"/>
<stringAttribute key="FILES.DEBUG_RESIDENT_APP.RESOURCES.0.VALUE" value=""/>
<stringAttribute key="FILES.DEBUG_RESIDENT_APP.RESOURCES.1.TYPE" value="TARGET_WORKING_DIR"/>
<stringAttribute key="FILES.DEBUG_RESIDENT_APP.RESOURCES.1.VALUE" value=""/>
<intAttribute key="FILES.DEBUG_RESIDENT_APP.RESOURCES.COUNT" value="2"/>
<listAttribute key="FILES.DOWNLOAD_AND_DEBUG"/>
<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.0.OPTION.ALSO_LOAD_SYMBOLS" value="false"/>
<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.0.OPTION.ON_DEMAND_LOAD" value="true"/>
<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.0.TYPE" value="TARGET_DOWNLOAD_DIR"/>
<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.0.VALUE" value=""/>
<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.1.OPTION.ALSO_LOAD_SYMBOLS" value="false"/>
<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.1.OPTION.ON_DEMAND_LOAD" value="true"/>
<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.1.TYPE" value="APP_ON_HOST_TO_DOWNLOAD"/>
<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.1.VALUE" value=""/>
<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.2.OPTION.ALSO_LOAD_SYMBOLS" value="false"/>
<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.2.OPTION.ON_DEMAND_LOAD" value="true"/>
<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.2.TYPE" value="TARGET_WORKING_DIR"/>
<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.2.VALUE" value=""/>
<intAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.COUNT" value="3"/>
<listAttribute key="FILES.DOWNLOAD_DEBUG"/>
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<mapEntry key="C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports_smp\cortex_a35_smp\ac6\example_build\sample_threadx\use_model_semihosting.ds" value=""/>
<mapEntry key="C:\Users\nisohack\Documents\work\x-ware_libs\threadx_github\ports\cortex_a5x_smp\ac6\example_build\sample_threadx\use_model_semihosting.ds" value=""/>
</mapAttribute>
<listAttribute key="setup">
<listEntry value="CDB://Scripts/rtsm_launcher.py"/>
<listEntry value="&quot;FVP_Base_Cortex-A35x4&quot;"/>
</listAttribute>
<stringAttribute key="stopAtExpression" value="*$ENTRYPOINT"/>
<stringAttribute key="substitutePath" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot;?&gt;&#10;&lt;tuplelist&gt;&#10;&#9;&lt;tuple&gt;&#10;&#9;&#9;&lt;ta&gt;C:/release/threadx/sample_threadx&lt;/ta&gt;&#10;&#9;&#9;&lt;tb&gt;C:\release\threadx\sample_threadx\&lt;/tb&gt;&#10;&#9;&lt;/tuple&gt;&#10;&#9;&lt;tuple&gt;&#10;&#9;&#9;&lt;ta&gt;C:/release/threadx/tx&lt;/ta&gt;&#10;&#9;&#9;&lt;tb&gt;C:\release\threadx\sample_threadx\&lt;/tb&gt;&#10;&#9;&lt;/tuple&gt;&#10;&lt;/tuplelist&gt;&#10;"/>
<stringAttribute key="watchpoints" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot;?&gt;&#10;&lt;watchpoints&gt;&#10;&lt;/watchpoints&gt;&#10;"/>
</launchConfiguration>

262
ports_arch/ARMv8-A/threadx_smp/ports/ac6/example_build/sample_threadx/sample_threadx.scat Normal file
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@@ -0,0 +1,262 @@
;********************************************************
; Scatter file for Armv8-A Startup code on FVP Base model
; Copyright (c) 2014-2017 Arm Limited (or its affiliates). All rights reserved.
; Use, modification and redistribution of this file is subject to your
; possession of a valid DS-5 end user licence agreement and your compliance
; with all applicable terms and conditions of such licence agreement.
;********************************************************
LOAD 0x80000000
{
EXEC +0
{
startup.o (StartUp, +FIRST)
* (+RO, +RW, +ZI)
}
;XTABLES +0 ALIGN 0x1000
;{
; xtables.o (*)
;}
SYS_STACK +0 ALIGN 8 EMPTY 0x1000
{
}
;
; Separate heap - import symbol __use_two_region_memory
; in source code for this to work correctly
;
ARM_LIB_HEAP +0 ALIGN 64 EMPTY 0xA0000 {}
;
; App stacks for all CPUs
; All stacks and heap are aligned to a cache-line boundary
;
ARM_LIB_STACK +0 ALIGN 64 EMPTY 4 * 0x4000 {}
;
; Handler stacks for all CPUs
; All stacks and heap are aligned to a cache-line boundary
;
HANDLER_STACK +0 ALIGN 64 EMPTY 4 * 0x4000 {}
;
; Stacks for EL3
;
EL3_STACKS +0 ALIGN 64 EMPTY 4 * 0x1000 {}
;
; Strictly speaking, the L1 tables don't need to
; be so strongly aligned, but no matter
;
TTB0_L1 +0 ALIGN 4096 EMPTY 0x1000 {}
;
; Various sets of L2 tables
;
; Alignment is 4KB, since the code uses a 4K page
; granularity - larger granularities would require
; correspondingly stricter alignment
;
TTB0_L2_RAM +0 ALIGN 4096 EMPTY 0x1000 {}
TTB0_L2_PRIVATE +0 ALIGN 4096 EMPTY 0x1000 {}
TTB0_L2_PERIPH +0 ALIGN 4096 EMPTY 0x1000 {}
;
; The startup code uses the end of this region to calculate
; the top of memory - don't place any RAM regions after it
;
TOP_OF_RAM +0 EMPTY 4 {}
;
; CS3 Peripherals is a 64MB region from 0x1c000000
; that includes the following:
; System Registers at 0x1C010000
; UART0 (PL011) at 0x1C090000
; Color LCD Controller (PL111) at 0x1C1F0000
; plus a number of others.
; CS3_PERIPHERALS is used by the startup code for page-table generation
; This region is not truly empty, but we have no
; predefined objects that live within it
;
CS3_PERIPHERALS 0x1c000000 EMPTY 0x90000 {}
;
; Place the UART peripheral registers data structure
; This is only really needed if USE_SERIAL_PORT is defined, but
; the linker will remove unused sections if not needed
; PL011 0x1c090000 UNINIT 0x1000
; {
; uart.o (+ZI)
; }
; Note that some other CS3_PERIPHERALS follow this
;
; GICv3 distributor
;
GICD 0x2f000000 UNINIT 0x8000
{
GICv3_gicd.o (.bss.distributor)
}
;
; GICv3 redistributors
; 128KB for each redistributor in the system
;
GICR 0x2f100000 UNINIT 0x80000
{
GICv3_gicr.o (.bss.redistributor)
}
}
; Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
;
; Redistributions of source code must retain the above copyright notice, this
; list of conditions and the following disclaimer.
;
; Redistributions in binary form must reproduce the above copyright notice,
; this list of conditions and the following disclaimer in the documentation
; and/or other materials provided with the distribution.
;
; Neither the name of ARM nor the names of its contributors may be used
; to endorse or promote products derived from this software without specific
; prior written permission.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
; ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
; POSSIBILITY OF SUCH DAMAGE.
;RO AlignExpr(0x80000000, 0x1000)
;{
; C_SYNCH_SP0 +0 ALIGN 0x80
; {
; vectors.o (_c_synch_sp0)
; }
; C_IRQ_SP0 +0 ALIGN 0x80
; {
; vectors.o (_c_irq_sp0)
; }
; C_FIQ_SP0 +0 ALIGN 0x80
; {
; vectors.o (_c_fiq_sp0)
; }
; C_SERROR_SP0 +0 ALIGN 0x80
; {
; vectors.o (_c_serror_sp0)
; }
;
; C_SYNCH_SPX +0 ALIGN 0x80
; {
; vectors.o (_c_synch_spx)
; }
; C_IRQ_SPX +0 ALIGN 0x80
; {
; vectors.o (_c_irq_spx)
; }
; C_FIQ_SPX +0 ALIGN 0x80
; {
; vectors.o (_c_fiq_spx)
; }
; C_SERROR_SPX +0 ALIGN 0x80
; {
; vectors.o (_c_serror_spx)
; }
;
; L64_SYNCH +0 ALIGN 0x80
; {
; vectors.o (_l64_synch)
; }
; L64_IRQ +0 ALIGN 0x80
; {
; vectors.o (_l64_irq)
; }
; L64_FIQ +0 ALIGN 0x80
; {
; vectors.o (_l64_fiq)
; }
; L64_SERROR +0 ALIGN 0x80
; {
; vectors.o (_l64_serror)
; }
;
; L32_SYNCH +0 ALIGN 0x80
; {
; vectors.o (_l32_synch)
; }
; L32_IRQ +0 ALIGN 0x80
; {
; vectors.o (_l32_irq)
; }
; L32_FIQ +0 ALIGN 0x80
; {
; vectors.o (_l32_fiq)
; }
; L32_SERROR +0 ALIGN 0x80
; {
; vectors.o (_l32_serror)
; }
;
; ROSEC +0 ALIGN 8
; {
; *( +RO )
; }
;
; XTABLES +0 ALIGN 0x1000
; {
; xtables.o (*)
; }
;}
;
;RW AlignExpr(ImageLimit(XTABLES), 0x1000)
;{
; RWSEC +0
; {
; *( +RW )
; }
;
; ZISEC +0
; {
; *( +ZI )
; }
;
; SYS_STACK +0 ALIGN 8 EMPTY 0x1000
; {
; }
;
; ; 512 MiB heap
; HEAP +0 ALIGN 8 EMPTY 0x10000000
; {
; }
;
; ; Free Memory section
; FREE_MEMORY +0 ALIGN 8 EMPTY 0x10000000
; {
; }
;
; ; Per-CPU 128 MiB task stacks
; TASK_STACKS +0 ALIGN 16 EMPTY (4 * 0x8000000)
; {
; }
;
; ; Per-CPU 128 MiB handler stacks
; HANDLER_STACKS +0 ALIGN 16 EMPTY (4 * 0x8000000)
; {
; }
;}

122
ports_arch/ARMv8-A/threadx_smp/ports/ac6/example_build/sample_threadx/sp804_timer.c Normal file
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// ------------------------------------------------------------
// SP804 Dual Timer
//
// Copyright (c) 2009-2017 Arm Limited (or its affiliates). All rights reserved.
// Use, modification and redistribution of this file is subject to your possession of a
// valid End User License Agreement for the Arm Product of which these examples are part of
// and your compliance with all applicable terms and conditions of such licence agreement.
// ------------------------------------------------------------
#include "sp804_timer.h"
#define TIMER_SP804_CTRL_TIMEREN (1 << 7)
#define TIMER_SP804_CTRL_TIMERMODE (1 << 6) // Bit 6:
#define TIMER_SP804_CTRL_INTENABLE (1 << 5)
#define TIMER_SP804_CTRL_TIMERSIZE (1 << 1) // Bit 1: 0=16-bit, 1=32-bit
#define TIMER_SP804_CTRL_ONESHOT (1 << 0) // Bit 0: 0=wrapping, 1=one-shot
#define TIMER_SP804_CTRL_PRESCALE_1 (0 << 2) // clk/1
#define TIMER_SP804_CTRL_PRESCALE_4 (1 << 2) // clk/4
#define TIMER_SP804_CTRL_PRESCALE_8 (2 << 2) // clk/8
struct sp804_timer
{
volatile uint32_t Time1Load; // +0x00
const volatile uint32_t Time1Value; // +0x04 - RO
volatile uint32_t Timer1Control; // +0x08
volatile uint32_t Timer1IntClr; // +0x0C - WO
const volatile uint32_t Timer1RIS; // +0x10 - RO
const volatile uint32_t Timer1MIS; // +0x14 - RO
volatile uint32_t Timer1BGLoad; // +0x18
volatile uint32_t Time2Load; // +0x20
volatile uint32_t Time2Value; // +0x24
volatile uint8_t Timer2Control; // +0x28
volatile uint32_t Timer2IntClr; // +0x2C - WO
const volatile uint32_t Timer2RIS; // +0x30 - RO
const volatile uint32_t Timer2MIS; // +0x34 - RO
volatile uint32_t Timer2BGLoad; // +0x38
// Not including ID registers
};
// Instance of the dual timer, will be placed using the scatter file
struct sp804_timer* dual_timer;
// Set base address of timer
// address - virtual address of SP804 timer
void setTimerBaseAddress(uint64_t address)
{
dual_timer = (struct sp804_timer*)address;
return;
}
// Sets up the private timer
// load_value - Initial value of timer
// auto_reload - Periodic (SP804_AUTORELOAD) or one shot (SP804_SINGLESHOT)
// interrupt - Whether to generate an interrupt
void initTimer(uint32_t load_value, uint32_t auto_reload, uint32_t interrupt)
{
uint32_t tmp = 0;
dual_timer->Time1Load = load_value;
// Fixed setting: 32-bit, no prescaling
tmp = TIMER_SP804_CTRL_TIMERSIZE | TIMER_SP804_CTRL_PRESCALE_1 | TIMER_SP804_CTRL_TIMERMODE;
// Settings from parameters: interrupt generation & reload
tmp = tmp | interrupt | auto_reload;
// Write control register
dual_timer->Timer1Control = tmp;
return;
}
// Starts the timer
void startTimer(void)
{
uint32_t tmp;
tmp = dual_timer->Timer1Control;
tmp = tmp | TIMER_SP804_CTRL_TIMEREN; // Set TimerEn (bit 7)
dual_timer->Timer1Control = tmp;
return;
}
// Stops the timer
void stopTimer(void)
{
uint32_t tmp;
tmp = dual_timer->Timer1Control;
tmp = tmp & ~TIMER_SP804_CTRL_TIMEREN; // Clear TimerEn (bit 7)
dual_timer->Timer1Control = tmp;
return;
}
// Returns the current timer count
uint32_t getTimerCount(void)
{
return dual_timer->Time1Value;
}
void clearTimerIrq(void)
{
// A write to this register, of any value, clears the interrupt
dual_timer->Timer1IntClr = 1;
}
// ------------------------------------------------------------
// End of sp804_timer.c
// ------------------------------------------------------------

53
ports_arch/ARMv8-A/threadx_smp/ports/ac6/example_build/sample_threadx/sp804_timer.h Normal file
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// ------------------------------------------------------------
// SP804 Dual Timer
// Header Filer
//
// Copyright (c) 2009-2017 Arm Limited (or its affiliates). All rights reserved.
// Use, modification and redistribution of this file is subject to your possession of a
// valid End User License Agreement for the Arm Product of which these examples are part of
// and your compliance with all applicable terms and conditions of such licence agreement.
// ------------------------------------------------------------
#ifndef _SP804_TIMER_
#define _SP804_TIMER_
#include <stdint.h>
// Set base address of timer
// address - virtual address of SP804 timer
void setTimerBaseAddress(uint64_t address);
// Sets up the private timer
// load_value - Initial value of timer
// auto_reload - Periodic (SP804_AUTORELOAD) or one shot (SP804_SINGLESHOT)
// interrupt - Whether to generate an interrupt
#define SP804_AUTORELOAD (0)
#define SP804_SINGLESHOT (1)
#define SP804_GENERATE_IRQ (1 << 5)
#define SP804_NO_IRQ (0)
void initTimer(uint32_t load_value, uint32_t auto_reload, uint32_t interrupt);
// Starts the timer
void startTimer(void);
// Stops the timer
void stopTimer(void);
// Returns the current timer count
uint32_t getTimerCount(void);
// Clears the timer interrupt
void clearTimerIrq(void);
#endif
// ------------------------------------------------------------
// End of sp804_timer.h
// ------------------------------------------------------------

803
ports_arch/ARMv8-A/threadx_smp/ports/ac6/example_build/sample_threadx/startup.S Normal file
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// ------------------------------------------------------------
// Armv8-A MPCore EL3 AArch64 Startup Code
//
// Basic Vectors, MMU, caches and GICv3 initialization
//
// Exits in EL1 AArch64
//
// Copyright (c) 2014-2019 Arm Limited (or its affiliates). All rights reserved.
// Use, modification and redistribution of this file is subject to your possession of a
// valid End User License Agreement for the Arm Product of which these examples are part of
// and your compliance with all applicable terms and conditions of such licence agreement.
// ------------------------------------------------------------
#include "v8_mmu.h"
#include "v8_system.h"
#include "GICv3_aliases.h"
.section StartUp, "ax"
.balign 4
.cfi_sections .debug_frame // put stack frame info into .debug_frame instead of .eh_frame
.global el1_vectors
.global el2_vectors
.global el3_vectors
.global InvalidateUDCaches
.global ZeroBlock
.global SetPrivateIntSecurityBlock
.global SetSPISecurityAll
.global SetPrivateIntPriority
.global GetGICR
.global WakeupGICR
.global SyncAREinGICD
.global EnableGICD
.global EnablePrivateInt
.global GetPrivateIntPending
.global ClearPrivateIntPending
.global __main
.global Image$$EXEC$$RO$$Base
.global Image$$TTB0_L1$$ZI$$Base
.global Image$$TTB0_L2_RAM$$ZI$$Base
.global Image$$TTB0_L2_PERIPH$$ZI$$Base
.global Image$$TOP_OF_RAM$$ZI$$Base
.global Image$$GICD$$ZI$$Base
.global Image$$ARM_LIB_STACK$$ZI$$Limit
.global Image$$EL3_STACKS$$ZI$$Limit
.global Image$$CS3_PERIPHERALS$$ZI$$Base
// use separate stack and heap, as anticipated by scatter.scat
.global __use_two_region_memory
is_mmu_ready:
.word 0
// ------------------------------------------------------------
.global start64
.type start64, "function"
start64:
//
// program the VBARs
//
ldr x1, =el1_vectors
msr VBAR_EL1, x1
ldr x1, =el2_vectors
msr VBAR_EL2, x1
ldr x1, =el3_vectors
msr VBAR_EL3, x1
// GIC-500 comes out of reset in GICv2 compatibility mode - first set
// system register enables for all relevant exception levels, and
// select GICv3 operating mode
//
msr SCR_EL3, xzr // Ensure NS bit is initially clear, so secure copy of ICC_SRE_EL1 can be configured
isb
mov x0, #15
msr ICC_SRE_EL3, x0
isb
msr ICC_SRE_EL1, x0 // Secure copy of ICC_SRE_EL1
//
// set lower exception levels as non-secure, with no access
// back to EL2 or EL3, and are AArch64 capable
//
mov x3, #(SCR_EL3_RW | \
SCR_EL3_SMD | \
SCR_EL3_NS) // Set NS bit, to access Non-secure registers
msr SCR_EL3, x3
isb
mov x0, #15
msr ICC_SRE_EL2, x0
isb
msr ICC_SRE_EL1, x0 // Non-secure copy of ICC_SRE_EL1
//
// no traps or VM modifications from the Hypervisor, EL1 is AArch64
//
mov x2, #HCR_EL2_RW
msr HCR_EL2, x2
//
// VMID is still significant, even when virtualisation is not
// being used, so ensure VTTBR_EL2 is properly initialised
//
msr VTTBR_EL2, xzr
//
// VMPIDR_EL2 holds the value of the Virtualization Multiprocessor ID. This is the value returned by Non-secure EL1 reads of MPIDR_EL1.
// VPIDR_EL2 holds the value of the Virtualization Processor ID. This is the value returned by Non-secure EL1 reads of MIDR_EL1.
// Both of these registers are architecturally UNKNOWN at reset, and so they must be set to the correct value
// (even if EL2/virtualization is not being used), otherwise non-secure EL1 reads of MPIDR_EL1/MIDR_EL1 will return garbage values.
// This guarantees that any future reads of MPIDR_EL1 and MIDR_EL1 from Non-secure EL1 will return the correct value.
//
mrs x0, MPIDR_EL1
msr VMPIDR_EL2, x0
mrs x0, MIDR_EL1
msr VPIDR_EL2, x0
// extract the core number from MPIDR_EL1 and store it in
// x19 (defined by the AAPCS as callee-saved), so we can re-use
// the number later
//
bl GetCPUID
mov x19, x0
//
// neither EL3 nor EL2 trap floating point or accesses to CPACR
//
msr CPTR_EL3, xzr
msr CPTR_EL2, xzr
//
// SCTLR_ELx may come out of reset with UNKNOWN values so we will
// set the fields to 0 except, possibly, the endianess field(s).
// Note that setting SCTLR_EL2 or the EL0 related fields of SCTLR_EL1
// is not strictly needed, since we're never in EL2 or EL0
//
#ifdef __ARM_BIG_ENDIAN
mov x0, #(SCTLR_ELx_EE | SCTLR_EL1_E0E)
#else
mov x0, #0
#endif
msr SCTLR_EL3, x0
msr SCTLR_EL2, x0
msr SCTLR_EL1, x0
#ifdef CORTEXA
//
// Configure ACTLR_EL[23]
// ----------------------
//
// These bits are IMPLEMENTATION DEFINED, so are different for
// different processors
//
// For Cortex-A57, the controls we set are:
//
// Enable lower level access to CPUACTLR_EL1
// Enable lower level access to CPUECTLR_EL1
// Enable lower level access to L2CTLR_EL1
// Enable lower level access to L2ECTLR_EL1
// Enable lower level access to L2ACTLR_EL1
//
mov x0, #((1 << 0) | \
(1 << 1) | \
(1 << 4) | \
(1 << 5) | \
(1 << 6))
msr ACTLR_EL3, x0
msr ACTLR_EL2, x0
//
// configure CPUECTLR_EL1
//
// These bits are IMP DEF, so need to different for different
// processors
//
// SMPEN - bit 6 - Enables the processor to receive cache
// and TLB maintenance operations
//
// Note: For Cortex-A57/53 SMPEN should be set before enabling
// the caches and MMU, or performing any cache and TLB
// maintenance operations.
//
// This register has a defined reset value, so we use a
// read-modify-write sequence to set SMPEN
//
mrs x0, S3_1_c15_c2_1 // Read EL1 CPU Extended Control Register
orr x0, x0, #(1 << 6) // Set the SMPEN bit
msr S3_1_c15_c2_1, x0 // Write EL1 CPU Extended Control Register
isb
#endif
//
// That's the last of the control settings for now
//
// Note: no ISB after all these changes, as registers won't be
// accessed until after an exception return, which is itself a
// context synchronisation event
//
//
// Setup some EL3 stack space, ready for calling some subroutines, below.
//
// Stack space allocation is CPU-specific, so use CPU
// number already held in x19
//
// 2^12 bytes per CPU for the EL3 stacks
//
ldr x0, =Image$$EL3_STACKS$$ZI$$Limit
sub x0, x0, x19, lsl #12
mov sp, x0
//
// we need to configure the GIC while still in secure mode, specifically
// all PPIs and SPIs have to be programmed as Group1 interrupts
//
//
// Before the GIC can be reliably programmed, we need to
// enable Affinity Routing, as this affects where the configuration
// registers are (with Affinity Routing enabled, some registers are
// in the Redistributor, whereas those same registers are in the
// Distributor with Affinity Routing disabled (i.e. when in GICv2
// compatibility mode).
//
mov x0, #(1 << 4) | (1 << 5) // gicdctlr_ARE_S | gicdctlr_ARE_NS
mov x1, x19
bl SyncAREinGICD
//
// The Redistributor comes out of reset assuming the processor is
// asleep - correct that assumption
//
mov w0, w19
bl WakeupGICR
//
// Now we're ready to set security and other initialisations
//
// This is a per-CPU configuration for these interrupts
//
// for the first cluster, CPU number is the redistributor index
//
mov w0, w19
mov w1, #1 // gicigroupr_G1NS
bl SetPrivateIntSecurityBlock
//
// While we're in the Secure World, set the priority mask low enough
// for it to be writable in the Non-Secure World
//
//mov x0, #16 << 3 // 5 bits of priority in the Secure world
mov x0, #0xFF // for Non-Secure interrupts
msr ICC_PMR_EL1, x0
//
// there's more GIC setup to do, but only for the primary CPU
//
cbnz x19, drop_to_el1
//
// There's more to do to the GIC - call the utility routine to set
// all SPIs to Group1
//
mov w0, #1 // gicigroupr_G1NS
bl SetSPISecurityAll
//
// Set up EL1 entry point and "dummy" exception return information,
// then perform exception return to enter EL1
//
.global drop_to_el1
drop_to_el1:
adr x1, el1_entry_aarch64
msr ELR_EL3, x1
mov x1, #(AARCH64_SPSR_EL1h | \
AARCH64_SPSR_F | \
AARCH64_SPSR_I | \
AARCH64_SPSR_A)
msr SPSR_EL3, x1
eret
// ------------------------------------------------------------
// EL1 - Common start-up code
// ------------------------------------------------------------
.global el1_entry_aarch64
.type el1_entry_aarch64, "function"
el1_entry_aarch64:
//
// Now we're in EL1, setup the application stack
// the scatter file allocates 2^14 bytes per app stack
//
ldr x0, =Image$$HANDLER_STACK$$ZI$$Limit
sub x0, x0, x19, lsl #14
mov sp, x0
MSR SPSel, #0
ISB
ldr x0, =Image$$ARM_LIB_STACK$$ZI$$Limit
sub x0, x0, x19, lsl #14
mov sp, x0
//
// Enable floating point
//
mov x0, #CPACR_EL1_FPEN
msr CPACR_EL1, x0
//
// Invalidate caches and TLBs for all stage 1
// translations used at EL1
//
// Cortex-A processors automatically invalidate their caches on reset
// (unless suppressed with the DBGL1RSTDISABLE or L2RSTDISABLE pins).
// It is therefore not necessary for software to invalidate the caches
// on startup, however, this is done here in case of a warm reset.
bl InvalidateUDCaches
tlbi VMALLE1
//
// Set TTBR0 Base address
//
// The CPUs share one set of translation tables that are
// generated by CPU0 at run-time
//
// TTBR1_EL1 is not used in this example
//
ldr x1, =Image$$TTB0_L1$$ZI$$Base
msr TTBR0_EL1, x1
//
// Set up memory attributes
//
// These equate to:
//
// 0 -> 0b01000100 = 0x00000044 = Normal, Inner/Outer Non-Cacheable
// 1 -> 0b11111111 = 0x0000ff00 = Normal, Inner/Outer WriteBack Read/Write Allocate
// 2 -> 0b00000100 = 0x00040000 = Device-nGnRE
//
mov x1, #0xff44
movk x1, #4, LSL #16 // equiv to: movk x1, #0x0000000000040000
msr MAIR_EL1, x1
//
// Set up TCR_EL1
//
// We're using only TTBR0 (EPD1 = 1), and the page table entries:
// - are using an 8-bit ASID from TTBR0
// - have a 4K granularity (TG0 = 0b00)
// - are outer-shareable (SH0 = 0b10)
// - are using Inner & Outer WBWA Normal memory ([IO]RGN0 = 0b01)
// - map
// + 32 bits of VA space (T0SZ = 0x20)
// + into a 32-bit PA space (IPS = 0b000)
//
// 36 32 28 24 20 16 12 8 4 0
// -----+----+----+----+----+----+----+----+----+----+
// | | |OOII| | | |OOII| | |
// TT | | |RRRR|E T | T| |RRRR|E T | T|
// BB | I I|TTSS|GGGG|P 1 | 1|TTSS|GGGG|P 0 | 0|
// IIA| P P|GGHH|NNNN|DAS | S|GGHH|NNNN|D S | S|
// 10S| S-S|1111|1111|11Z-|---Z|0000|0000|0 Z-|---Z|
//
// 000 0000 0000 0000 1000 0000 0010 0101 0010 0000
//
// 0x 8 0 2 5 2 0
//
// Note: the ISB is needed to ensure the changes to system
// context are before the write of SCTLR_EL1.M to enable
// the MMU. It is likely on a "real" implementation that
// this setup would work without an ISB, due to the
// amount of code that gets executed before enabling the
// MMU, but that would not be architecturally correct.
//
ldr x1, =0x0000000000802520
msr TCR_EL1, x1
isb
//
// the primary CPU is going to use SGI 15 as a wakeup event
// to let us know when it is OK to proceed, so prepare for
// receiving that interrupt
//
// NS interrupt priorities run from 0 to 15, with 15 being
// too low a priority to ever raise an interrupt, so let's
// use 14
//
mov w0, w19
mov w1, #0
mov w2, #14 << 4 // we're in NS world, so 4 bits of priority,
// 8-bit field, - 4 = 4-bit shift
bl SetPrivateIntPriority
mov w0, w19
mov w1, #0
bl EnablePrivateInt
//
// set priority mask as low as possible; although,being in the
// NS World, we can't set bit[7] of the priority, we still
// write all 8-bits of priority to an ICC register
//
mov x0, #31 << 3
msr ICC_PMR_EL1, x0
//
// set global enable and wait for our interrupt to arrive
//
mov x0, #1
msr ICC_IGRPEN1_EL1, x0
isb
//
// x19 already contains the CPU number, so branch to secondary
// code if we're not on CPU0
//
cbnz x19, el1_secondary
//
// Fall through to primary code
//
//
// ------------------------------------------------------------
//
// EL1 - primary CPU init code
//
// This code is run on CPU0, while the other CPUs are in the
// holding pen
//
.global el1_primary
.type el1_primary, "function"
el1_primary:
//
// Turn on the banked GIC distributor enable,
// ready for individual CPU enables later
//
mov w0, #(1 << 1) // gicdctlr_EnableGrp1A
bl EnableGICD
//
// Generate TTBR0 L1
//
// at 4KB granularity, 32-bit VA space, table lookup starts at
// L1, with 1GB regions
//
// we are going to create entries pointing to L2 tables for a
// couple of these 1GB regions, the first of which is the
// RAM on the VE board model - get the table addresses and
// start by emptying out the L1 page tables (4 entries at L1
// for a 4K granularity)
//
// x21 = address of L1 tables
//
ldr x21, =Image$$TTB0_L1$$ZI$$Base
mov x0, x21
mov x1, #(4 << 3)
bl ZeroBlock
//
// time to start mapping the RAM regions - clear out the
// L2 tables and point to them from the L1 tables
//
// x22 = address of L2 tables, needs to be remembered in case
// we want to re-use the tables for mapping peripherals
//
ldr x22, =Image$$TTB0_L2_RAM$$ZI$$Base
mov x1, #(512 << 3)
mov x0, x22
bl ZeroBlock
//
// Get the start address of RAM (the EXEC region) into x4
// and calculate the offset into the L1 table (1GB per region,
// max 4GB)
//
// x23 = L1 table offset, saved for later comparison against
// peripheral offset
//
ldr x4, =Image$$EXEC$$RO$$Base
ubfx x23, x4, #30, #2
orr x1, x22, #TT_S1_ATTR_PAGE
str x1, [x21, x23, lsl #3]
//
// we've already used the RAM start address in x4 - we now need
// to get this in terms of an offset into the L2 page tables,
// where each entry covers 2MB
//
ubfx x2, x4, #21, #9
//
// TOP_OF_RAM in the scatter file marks the end of the
// Execute region in RAM: convert the end of this region to an
// offset too, being careful to round up, then calculate the
// number of entries to write
//
ldr x5, =Image$$TOP_OF_RAM$$ZI$$Base
sub x3, x5, #1
ubfx x3, x3, #21, #9
add x3, x3, #1
sub x3, x3, x2
//
// set x1 to the required page table attributes, then orr
// in the start address (modulo 2MB)
//
// L2 tables in our configuration cover 2MB per entry - map
// memory as Shared, Normal WBWA (MAIR[1]) with a flat
// VA->PA translation
//
bic x4, x4, #((1 << 21) - 1)
ldr x1, =(TT_S1_ATTR_BLOCK | \
(1 << TT_S1_ATTR_MATTR_LSB) | \
TT_S1_ATTR_NS | \
TT_S1_ATTR_AP_RW_PL1 | \
TT_S1_ATTR_SH_INNER | \
TT_S1_ATTR_AF | \
TT_S1_ATTR_nG)
orr x1, x1, x4
//
// factor the offset into the page table address and then write
// the entries
//
add x0, x22, x2, lsl #3
loop1:
subs x3, x3, #1
str x1, [x0], #8
add x1, x1, #0x200, LSL #12 // equiv to add x1, x1, #(1 << 21) // 2MB per entry
bne loop1
//
// now mapping the Peripheral regions - clear out the
// L2 tables and point to them from the L1 tables
//
// The assumption here is that all peripherals live within
// a common 1GB region (i.e. that there's a single set of
// L2 pages for all the peripherals). We only use a UART
// and the GIC in this example, so the assumption is sound
//
// x24 = address of L2 peripheral tables
//
ldr x24, =Image$$TTB0_L2_PERIPH$$ZI$$Base
//
// get the GICD address into x4 and calculate
// the offset into the L1 table
//
// x25 = L1 table offset
//
ldr x4, =Image$$GICD$$ZI$$Base
ubfx x25, x4, #30, #2
//
// here's the tricky bit: it's possible that the peripherals are
// in the same 1GB region as the RAM, in which case we don't need
// to prime a separate set of L2 page tables, nor add them to the
// L1 tables
//
// if we're going to re-use the TTB0_L2_RAM tables, get their
// address into x24, which is used later on to write the PTEs
//
cmp x25, x23
csel x24, x22, x24, EQ
b.eq nol2setup
//
// Peripherals are in a separate 1GB region, and so have their own
// set of L2 tables - clean out the tables and add them to the L1
// table
//
mov x0, x24
mov x1, #512 << 3
bl ZeroBlock
orr x1, x24, #TT_S1_ATTR_PAGE
str x1, [x21, x25, lsl #3]
//
// there's only going to be a single 2MB region for GICD (in
// x4) - get this in terms of an offset into the L2 page tables
//
// with larger systems, it is possible that the GIC redistributor
// registers require extra 2MB pages, in which case extra code
// would be required here
//
nol2setup:
ubfx x2, x4, #21, #9
//
// set x1 to the required page table attributes, then orr
// in the start address (modulo 2MB)
//
// L2 tables in our configuration cover 2MB per entry - map
// memory as NS Device-nGnRE (MAIR[2]) with a flat VA->PA
// translation
//
bic x4, x4, #((1 << 21) - 1) // start address mod 2MB
ldr x1, =(TT_S1_ATTR_BLOCK | \
(2 << TT_S1_ATTR_MATTR_LSB) | \
TT_S1_ATTR_NS | \
TT_S1_ATTR_AP_RW_PL1 | \
TT_S1_ATTR_AF | \
TT_S1_ATTR_nG)
orr x1, x1, x4
//
// only a single L2 entry for this, so no loop as we have for RAM, above
//
str x1, [x24, x2, lsl #3]
//
// we have CS3_PERIPHERALS that include the UART controller
//
// Again, the code is making assumptions - this time that the CS3_PERIPHERALS
// region uses the same 1GB portion of the address space as the GICD,
// and thus shares the same set of L2 page tables
//
// Get CS3_PERIPHERALS address into x4 and calculate the offset into the
// L2 tables
//
ldr x4, =Image$$CS3_PERIPHERALS$$ZI$$Base
ubfx x2, x4, #21, #9
//
// set x1 to the required page table attributes, then orr
// in the start address (modulo 2MB)
//
// L2 tables in our configuration cover 2MB per entry - map
// memory as NS Device-nGnRE (MAIR[2]) with a flat VA->PA
// translation
//
bic x4, x4, #((1 << 21) - 1) // start address mod 2MB
ldr x1, =(TT_S1_ATTR_BLOCK | \
(2 << TT_S1_ATTR_MATTR_LSB) | \
TT_S1_ATTR_NS | \
TT_S1_ATTR_AP_RW_PL1 | \
TT_S1_ATTR_AF | \
TT_S1_ATTR_nG)
orr x1, x1, x4
//
// only a single L2 entry again - write it
//
str x1, [x24, x2, lsl #3]
//
// issue a barrier to ensure all table entry writes are complete
//
dsb ish
ldr x1, =is_mmu_ready
mov x2, #1
str x2, [x1]
//
// Enable the MMU. Caches will be enabled later, after scatterloading.
//
mrs x1, SCTLR_EL1
orr x1, x1, #SCTLR_ELx_M
bic x1, x1, #SCTLR_ELx_A // Disable alignment fault checking. To enable, change bic to orr
msr SCTLR_EL1, x1
isb
//
// Branch to C library init code
//
b __main
// ------------------------------------------------------------
// AArch64 Arm C library startup add-in:
// The Arm Architecture Reference Manual for Armv8-A states:
//
// Instruction accesses to Non-cacheable Normal memory can be held in instruction caches.
// Correspondingly, the sequence for ensuring that modifications to instructions are available
// for execution must include invalidation of the modified locations from the instruction cache,
// even if the instructions are held in Normal Non-cacheable memory.
// This includes cases where the instruction cache is disabled.
//
// To invalidate the AArch64 instruction cache after scatter-loading and before initialization of the stack and heap,
// it is necessary for the user to:
//
// * Implement instruction cache invalidation code in _platform_pre_stackheap_init.
// * Ensure all code on the path from the program entry up to and including _platform_pre_stackheap_init is located in a root region.
//
// In this example, this function is only called once, by the primary core
.global _platform_pre_stackheap_init
.type _platform_pre_stackheap_init, "function"
.cfi_startproc
_platform_pre_stackheap_init:
dsb ish // ensure all previous stores have completed before invalidating
ic ialluis // I cache invalidate all inner shareable to PoU (which includes secondary cores)
dsb ish // ensure completion on inner shareable domain (which includes secondary cores)
isb
// Scatter-loading is complete, so enable the caches here, so that the C-library's mutex initialization later will work
mrs x1, SCTLR_EL1
orr x1, x1, #SCTLR_ELx_C
orr x1, x1, #SCTLR_ELx_I
msr SCTLR_EL1, x1
isb
ret
.cfi_endproc
// ------------------------------------------------------------
// EL1 - secondary CPU init code
//
// This code is run on CPUs 1, 2, 3 etc....
// ------------------------------------------------------------
.global el1_secondary
.type el1_secondary, "function"
el1_secondary:
wait_for_mmu_ready:
ldr x1, =is_mmu_ready
ldr x1, [x1]
cmp x1, #1
b.ne wait_for_mmu_ready
//
// Enable the MMU and caches
//
mrs x1, SCTLR_EL1
orr x1, x1, #SCTLR_ELx_M
orr x1, x1, #SCTLR_ELx_C
orr x1, x1, #SCTLR_ELx_I
bic x1, x1, #SCTLR_ELx_A // Disable alignment fault checking. To enable, change bic to orr
msr SCTLR_EL1, x1
isb
/* EL: Secondary core entrance. */
B _tx_thread_smp_initialize_wait
loop_wfi:
dsb SY // Clear all pending data accesses
wfi // Go to sleep
//
// something woke us from our wait, was it the required interrupt?
//
mov w0, w19
mov w1, #15
bl GetPrivateIntPending
cbz w0, loop_wfi
//
// it was - there's no need to actually take the interrupt,
// so just clear it
//
mov w0, w19
mov w1, #15
bl ClearPrivateIntPending
//
// Branch to thread start
//
// B MainApp
/**
* Retargeted to prevent the C library from doing its own stack and heap
* initialisation.
*/
.type __user_setup_stackheap, @function
__user_setup_stackheap:
ADRP X0, Image$$SYS_STACK$$ZI$$Limit
MOV SP, X0
ADRP X0, Image$$ARM_LIB_HEAP$$ZI$$Base
ADRP X2, Image$$ARM_LIB_HEAP$$ZI$$Limit
RET

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ports_arch/ARMv8-A/threadx_smp/ports/ac6/example_build/sample_threadx/timer_interrupts.c Normal file
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/* Bare-metal example for Armv8-A FVP Base model */
/* Timer and interrupts */
/* Copyright (c) 2016-2018 Arm Limited (or its affiliates). All rights reserved. */
/* Use, modification and redistribution of this file is subject to your possession of a */
/* valid End User License Agreement for the Arm Product of which these examples are part of */
/* and your compliance with all applicable terms and conditions of such licence agreement. */
#include <stdio.h>
#include "GICv3.h"
#include "GICv3_gicc.h"
#include "sp804_timer.h"
void _tx_timer_interrupt(void);
// LED Base address
#define LED_BASE (volatile unsigned int *)0x1C010008
void nudge_leds(void) // Move LEDs along
{
static int state = 1;
static int value = 1;
if (state)
{
int max = (1 << 7);
value <<= 1;
if (value == max)
state = 0;
}
else
{
value >>= 1;
if (value == 1)
state = 1;
}
*LED_BASE = value; // Update LEDs hardware
}
// Initialize Timer 0 and Interrupt Controller
void init_timer(void)
{
// Enable interrupts
__asm("MSR DAIFClr, #0xF");
setICC_IGRPEN1_EL1(igrpEnable);
// Configure the SP804 timer to generate an interrupt
setTimerBaseAddress(0x1C110000);
initTimer(0x200, SP804_AUTORELOAD, SP804_GENERATE_IRQ);
startTimer();
// The SP804 timer generates SPI INTID 34. Enable
// this ID, and route it to core 0.0.0.0 (this one!)
SetSPIRoute(34, 0, gicdirouter_ModeSpecific); // Route INTID 34 to 0.0.0.0 (this core)
SetSPIPriority(34, 0); // Set INTID 34 to priority to 0
ConfigureSPI(34, gicdicfgr_Level); // Set INTID 34 as level-sensitive
EnableSPI(34); // Enable INTID 34
}
// --------------------------------------------------------
void irqHandler(void)
{
unsigned int ID;
ID = getICC_IAR1(); // readIntAck();
// Check for reserved IDs
if ((1020 <= ID) && (ID <= 1023))
{
//printf("irqHandler() - Reserved INTID %d\n\n", ID);
return;
}
switch(ID)
{
case 34:
// Dual-Timer 0 (SP804)
//printf("irqHandler() - External timer interrupt\n\n");
nudge_leds();
clearTimerIrq();
/* Call ThreadX timer interrupt processing. */
_tx_timer_interrupt();
break;
default:
// Unexpected ID value
//printf("irqHandler() - Unexpected INTID %d\n\n", ID);
break;
}
// Write the End of Interrupt register to tell the GIC
// we've finished handling the interrupt
setICC_EOIR1(ID); // writeAliasedEOI(ID);
}
// --------------------------------------------------------
// Not actually used in this example, but provided for completeness
void fiqHandler(void)
{
unsigned int ID;
unsigned int aliased = 0;
ID = getICC_IAR0(); // readIntAck();
//printf("fiqHandler() - Read %d from IAR0\n", ID);
// Check for reserved IDs
if ((1020 <= ID) && (ID <= 1023))
{
//printf("fiqHandler() - Reserved INTID %d\n\n", ID);
ID = getICC_IAR1(); // readAliasedIntAck();
//printf("fiqHandler() - Read %d from AIAR\n", ID);
aliased = 1;
// If still spurious then simply return
if ((1020 <= ID) && (ID <= 1023))
return;
}
switch(ID)
{
case 34:
// Dual-Timer 0 (SP804)
//printf("fiqHandler() - External timer interrupt\n\n");
clearTimerIrq();
break;
default:
// Unexpected ID value
//printf("fiqHandler() - Unexpected INTID %d\n\n", ID);
break;
}
// Write the End of Interrupt register to tell the GIC
// we've finished handling the interrupt
// NOTE: If the ID was read from the Aliased IAR, then
// the aliased EOI register must be used
if (aliased == 0)
setICC_EOIR0(ID); // writeEOI(ID);
else
setICC_EOIR1(ID); // writeAliasedEOI(ID);
}

1
ports_arch/ARMv8-A/threadx_smp/ports/ac6/example_build/sample_threadx/use_model_semihosting.ds Normal file
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set semihosting enabled off

179
ports_arch/ARMv8-A/threadx_smp/ports/ac6/example_build/sample_threadx/v8_aarch64.S Normal file
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// ------------------------------------------------------------
// Armv8-A AArch64 - Common helper functions
//
// Copyright (c) 2012-2019 Arm Limited (or its affiliates). All rights reserved.
// Use, modification and redistribution of this file is subject to your possession of a
// valid End User License Agreement for the Arm Product of which these examples are part of
// and your compliance with all applicable terms and conditions of such licence agreement.
// ------------------------------------------------------------
#include "v8_system.h"
.text
.cfi_sections .debug_frame // put stack frame info into .debug_frame instead of .eh_frame
.global EnableCachesEL1
.global DisableCachesEL1
.global InvalidateUDCaches
.global GetMIDR
.global GetMPIDR
.global GetAffinity
.global GetCPUID
// ------------------------------------------------------------
//
// void EnableCachesEL1(void)
//
// enable Instruction and Data caches
//
.type EnableCachesEL1, "function"
.cfi_startproc
EnableCachesEL1:
mrs x0, SCTLR_EL1
orr x0, x0, #SCTLR_ELx_I
orr x0, x0, #SCTLR_ELx_C
msr SCTLR_EL1, x0
isb
ret
.cfi_endproc
// ------------------------------------------------------------
.type DisableCachesEL1, "function"
.cfi_startproc
DisableCachesEL1:
mrs x0, SCTLR_EL1
bic x0, x0, #SCTLR_ELx_I
bic x0, x0, #SCTLR_ELx_C
msr SCTLR_EL1, x0
isb
ret
.cfi_endproc
// ------------------------------------------------------------
//
// void InvalidateUDCaches(void)
//
// Invalidate data and unified caches
//
.type InvalidateUDCaches, "function"
.cfi_startproc
InvalidateUDCaches:
// From the Armv8-A Architecture Reference Manual
dmb ish // ensure all prior inner-shareable accesses have been observed
mrs x0, CLIDR_EL1
and w3, w0, #0x07000000 // get 2 x level of coherence
lsr w3, w3, #23
cbz w3, finished
mov w10, #0 // w10 = 2 x cache level
mov w8, #1 // w8 = constant 0b1
loop_level:
add w2, w10, w10, lsr #1 // calculate 3 x cache level
lsr w1, w0, w2 // extract 3-bit cache type for this level
and w1, w1, #0x7
cmp w1, #2
b.lt next_level // no data or unified cache at this level
msr CSSELR_EL1, x10 // select this cache level
isb // synchronize change of csselr
mrs x1, CCSIDR_EL1 // read ccsidr
and w2, w1, #7 // w2 = log2(linelen)-4
add w2, w2, #4 // w2 = log2(linelen)
ubfx w4, w1, #3, #10 // w4 = max way number, right aligned
clz w5, w4 // w5 = 32-log2(ways), bit position of way in dc operand
lsl w9, w4, w5 // w9 = max way number, aligned to position in dc operand
lsl w16, w8, w5 // w16 = amount to decrement way number per iteration
loop_way:
ubfx w7, w1, #13, #15 // w7 = max set number, right aligned
lsl w7, w7, w2 // w7 = max set number, aligned to position in dc operand
lsl w17, w8, w2 // w17 = amount to decrement set number per iteration
loop_set:
orr w11, w10, w9 // w11 = combine way number and cache number ...
orr w11, w11, w7 // ... and set number for dc operand
dc isw, x11 // do data cache invalidate by set and way
subs w7, w7, w17 // decrement set number
b.ge loop_set
subs x9, x9, x16 // decrement way number
b.ge loop_way
next_level:
add w10, w10, #2 // increment 2 x cache level
cmp w3, w10
b.gt loop_level
dsb sy // ensure completion of previous cache maintenance operation
isb
finished:
ret
.cfi_endproc
// ------------------------------------------------------------
//
// ID Register functions
//
.type GetMIDR, "function"
.cfi_startproc
GetMIDR:
mrs x0, MIDR_EL1
ret
.cfi_endproc
.type GetMPIDR, "function"
.cfi_startproc
GetMPIDR:
mrs x0, MPIDR_EL1
ret
.cfi_endproc
.type GetAffinity, "function"
.cfi_startproc
GetAffinity:
mrs x0, MPIDR_EL1
ubfx x1, x0, #32, #8
bfi w0, w1, #24, #8
ret
.cfi_endproc
.type GetCPUID, "function"
.cfi_startproc
GetCPUID:
mrs x0, MIDR_EL1
ubfx x0, x0, #4, #12 // extract PartNum
cmp x0, #0xD0D // Cortex-A77
b.eq DynamIQ
cmp x0, #0xD0B // Cortex-A76
b.eq DynamIQ
cmp x0, #0xD0A // Cortex-A75
b.eq DynamIQ
cmp x0, #0xD05 // Cortex-A55
b.eq DynamIQ
b Others
DynamIQ:
mrs x0, MPIDR_EL1
ubfx x0, x0, #MPIDR_EL1_AFF1_LSB, #MPIDR_EL1_AFF_WIDTH
ret
Others:
mrs x0, MPIDR_EL1
ubfx x1, x0, #MPIDR_EL1_AFF0_LSB, #MPIDR_EL1_AFF_WIDTH
ubfx x2, x0, #MPIDR_EL1_AFF1_LSB, #MPIDR_EL1_AFF_WIDTH
add x0, x1, x2, LSL #2
ret
.cfi_endproc

103
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/*
*
* Armv8-A AArch64 common helper functions
*
* Copyright (c) 2012-2014 Arm Limited (or its affiliates). All rights reserved.
* Use, modification and redistribution of this file is subject to your possession of a
* valid End User License Agreement for the Arm Product of which these examples are part of
* and your compliance with all applicable terms and conditions of such licence agreement.
*/
#ifndef V8_AARCH64_H
#define V8_AARCH64_H
/*
* Parameters for data barriers
*/
#define OSHLD 1
#define OSHST 2
#define OSH 3
#define NSHLD 5
#define NSHST 6
#define NSH 7
#define ISHLD 9
#define ISHST 10
#define ISH 11
#define LD 13
#define ST 14
#define SY 15
/**********************************************************************/
/*
* function prototypes
*/
/*
* void InvalidateUDCaches(void)
* invalidates all Unified and Data Caches
*
* Inputs
* <none>
*
* Returns
* <nothing>
*
* Side Effects
* guarantees that all levels of cache will be invalidated before
* returning to caller
*/
void InvalidateUDCaches(void);
/*
* unsigned long long EnableCachesEL1(void)
* enables I- and D- caches at EL1
*
* Inputs
* <none>
*
* Returns
* New value of SCTLR_EL1
*
* Side Effects
* context will be synchronised before returning to caller
*/
unsigned long long EnableCachesEL1(void);
/*
* unsigned long long GetMIDR(void)
* returns the contents of MIDR_EL0
*
* Inputs
* <none>
*
* Returns
* MIDR_EL0
*/
unsigned long long GetMIDR(void);
/*
* unsigned long long GetMPIDR(void)
* returns the contents of MPIDR_EL0
*
* Inputs
* <none>
*
* Returns
* MPIDR_EL0
*/
unsigned long long GetMPIDR(void);
/*
* unsigned int GetCPUID(void)
* returns the Aff0 field of MPIDR_EL0
*
* Inputs
* <none>
*
* Returns
* MPIDR_EL0[7:0]
*/
unsigned int GetCPUID(void);
#endif

128
ports_arch/ARMv8-A/threadx_smp/ports/ac6/example_build/sample_threadx/v8_mmu.h Normal file
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//
// Defines for v8 Memory Model
//
// Copyright (c) 2012-2019 Arm Limited (or its affiliates). All rights reserved.
// Use, modification and redistribution of this file is subject to your possession of a
// valid End User License Agreement for the Arm Product of which these examples are part of
// and your compliance with all applicable terms and conditions of such licence agreement.
//
#ifndef V8_MMU_H
#define V8_MMU_H
//
// Translation Control Register fields
//
// RGN field encodings
//
#define TCR_RGN_NC 0b00
#define TCR_RGN_WBWA 0b01
#define TCR_RGN_WT 0b10
#define TCR_RGN_WBRA 0b11
//
// Shareability encodings
//
#define TCR_SHARE_NONE 0b00
#define TCR_SHARE_OUTER 0b10
#define TCR_SHARE_INNER 0b11
//
// Granule size encodings
//
#define TCR_GRANULE_4K 0b00
#define TCR_GRANULE_64K 0b01
#define TCR_GRANULE_16K 0b10
//
// Physical Address sizes
//
#define TCR_SIZE_4G 0b000
#define TCR_SIZE_64G 0b001
#define TCR_SIZE_1T 0b010
#define TCR_SIZE_4T 0b011
#define TCR_SIZE_16T 0b100
#define TCR_SIZE_256T 0b101
//
// Translation Control Register fields
//
#define TCR_EL1_T0SZ_SHIFT 0
#define TCR_EL1_EPD0 (1 << 7)
#define TCR_EL1_IRGN0_SHIFT 8
#define TCR_EL1_ORGN0_SHIFT 10
#define TCR_EL1_SH0_SHIFT 12
#define TCR_EL1_TG0_SHIFT 14
#define TCR_EL1_T1SZ_SHIFT 16
#define TCR_EL1_A1 (1 << 22)
#define TCR_EL1_EPD1 (1 << 23)
#define TCR_EL1_IRGN1_SHIFT 24
#define TCR_EL1_ORGN1_SHIFT 26
#define TCR_EL1_SH1_SHIFT 28
#define TCR_EL1_TG1_SHIFT 30
#define TCR_EL1_IPS_SHIFT 32
#define TCR_EL1_AS (1 << 36)
#define TCR_EL1_TBI0 (1 << 37)
#define TCR_EL1_TBI1 (1 << 38)
//
// Stage 1 Translation Table descriptor fields
//
#define TT_S1_ATTR_FAULT (0b00 << 0)
#define TT_S1_ATTR_BLOCK (0b01 << 0) // Level 1/2
#define TT_S1_ATTR_TABLE (0b11 << 0) // Level 0/1/2
#define TT_S1_ATTR_PAGE (0b11 << 0) // Level 3
#define TT_S1_ATTR_MATTR_LSB 2
#define TT_S1_ATTR_NS (1 << 5)
#define TT_S1_ATTR_AP_RW_PL1 (0b00 << 6)
#define TT_S1_ATTR_AP_RW_ANY (0b01 << 6)
#define TT_S1_ATTR_AP_RO_PL1 (0b10 << 6)
#define TT_S1_ATTR_AP_RO_ANY (0b11 << 6)
#define TT_S1_ATTR_SH_NONE (0b00 << 8)
#define TT_S1_ATTR_SH_OUTER (0b10 << 8)
#define TT_S1_ATTR_SH_INNER (0b11 << 8)
#define TT_S1_ATTR_AF (1 << 10)
#define TT_S1_ATTR_nG (1 << 11)
// OA bits [15:12] - If Armv8.2-LPA is implemented, bits[15:12] are bits[51:48]
// and bits[47:16] are bits[47:16] of the output address for a page of memory
#define TT_S1_ATTR_nT (1 << 16) // Present if Armv8.4-TTRem is implemented, otherwise RES0
#define TT_S1_ATTR_DBM (1 << 51) // Present if Armv8.1-TTHM is implemented, otherwise RES0
#define TT_S1_ATTR_CONTIG (1 << 52)
#define TT_S1_ATTR_PXN (1 << 53)
#define TT_S1_ATTR_UXN (1 << 54)
// PBHA bits[62:59] - If Armv8.2-TTPBHA is implemented, hardware can use these bits
// for IMPLEMENTATIONDEFINED purposes, otherwise IGNORED
#define TT_S1_MAIR_DEV_nGnRnE 0b00000000
#define TT_S1_MAIR_DEV_nGnRE 0b00000100
#define TT_S1_MAIR_DEV_nGRE 0b00001000
#define TT_S1_MAIR_DEV_GRE 0b00001100
//
// Inner and Outer Normal memory attributes use the same bit patterns
// Outer attributes just need to be shifted up
//
#define TT_S1_MAIR_OUTER_SHIFT 4
#define TT_S1_MAIR_WT_TRANS_RA 0b0010
#define TT_S1_MAIR_WB_TRANS_RA 0b0110
#define TT_S1_MAIR_WB_TRANS_RWA 0b0111
#define TT_S1_MAIR_WT_RA 0b1010
#define TT_S1_MAIR_WB_RA 0b1110
#define TT_S1_MAIR_WB_RWA 0b1111
#endif // V8_MMU_H

115
ports_arch/ARMv8-A/threadx_smp/ports/ac6/example_build/sample_threadx/v8_system.h Normal file
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//
// Defines for v8 System Registers
//
// Copyright (c) 2012-2016 Arm Limited (or its affiliates). All rights reserved.
// Use, modification and redistribution of this file is subject to your possession of a
// valid End User License Agreement for the Arm Product of which these examples are part of
// and your compliance with all applicable terms and conditions of such licence agreement.
//
#ifndef V8_SYSTEM_H
#define V8_SYSTEM_H
//
// AArch64 SPSR
//
#define AARCH64_SPSR_EL3h 0b1101
#define AARCH64_SPSR_EL3t 0b1100
#define AARCH64_SPSR_EL2h 0b1001
#define AARCH64_SPSR_EL2t 0b1000
#define AARCH64_SPSR_EL1h 0b0101
#define AARCH64_SPSR_EL1t 0b0100
#define AARCH64_SPSR_EL0t 0b0000
#define AARCH64_SPSR_RW (1 << 4)
#define AARCH64_SPSR_F (1 << 6)
#define AARCH64_SPSR_I (1 << 7)
#define AARCH64_SPSR_A (1 << 8)
#define AARCH64_SPSR_D (1 << 9)
#define AARCH64_SPSR_IL (1 << 20)
#define AARCH64_SPSR_SS (1 << 21)
#define AARCH64_SPSR_V (1 << 28)
#define AARCH64_SPSR_C (1 << 29)
#define AARCH64_SPSR_Z (1 << 30)
#define AARCH64_SPSR_N (1 << 31)
//
// Multiprocessor Affinity Register
//
#define MPIDR_EL1_AFF3_LSB 32
#define MPIDR_EL1_U (1 << 30)
#define MPIDR_EL1_MT (1 << 24)
#define MPIDR_EL1_AFF2_LSB 16
#define MPIDR_EL1_AFF1_LSB 8
#define MPIDR_EL1_AFF0_LSB 0
#define MPIDR_EL1_AFF_WIDTH 8
//
// Data Cache Zero ID Register
//
#define DCZID_EL0_BS_LSB 0
#define DCZID_EL0_BS_WIDTH 4
#define DCZID_EL0_DZP_LSB 5
#define DCZID_EL0_DZP (1 << 5)
//
// System Control Register
//
#define SCTLR_EL1_UCI (1 << 26)
#define SCTLR_ELx_EE (1 << 25)
#define SCTLR_EL1_E0E (1 << 24)
#define SCTLR_ELx_WXN (1 << 19)
#define SCTLR_EL1_nTWE (1 << 18)
#define SCTLR_EL1_nTWI (1 << 16)
#define SCTLR_EL1_UCT (1 << 15)
#define SCTLR_EL1_DZE (1 << 14)
#define SCTLR_ELx_I (1 << 12)
#define SCTLR_EL1_UMA (1 << 9)
#define SCTLR_EL1_SED (1 << 8)
#define SCTLR_EL1_ITD (1 << 7)
#define SCTLR_EL1_THEE (1 << 6)
#define SCTLR_EL1_CP15BEN (1 << 5)
#define SCTLR_EL1_SA0 (1 << 4)
#define SCTLR_ELx_SA (1 << 3)
#define SCTLR_ELx_C (1 << 2)
#define SCTLR_ELx_A (1 << 1)
#define SCTLR_ELx_M (1 << 0)
//
// Architectural Feature Access Control Register
//
#define CPACR_EL1_TTA (1 << 28)
#define CPACR_EL1_FPEN (3 << 20)
//
// Architectural Feature Trap Register
//
#define CPTR_ELx_TCPAC (1 << 31)
#define CPTR_ELx_TTA (1 << 20)
#define CPTR_ELx_TFP (1 << 10)
//
// Secure Configuration Register
//
#define SCR_EL3_TWE (1 << 13)
#define SCR_EL3_TWI (1 << 12)
#define SCR_EL3_ST (1 << 11)
#define SCR_EL3_RW (1 << 10)
#define SCR_EL3_SIF (1 << 9)
#define SCR_EL3_HCE (1 << 8)
#define SCR_EL3_SMD (1 << 7)
#define SCR_EL3_EA (1 << 3)
#define SCR_EL3_FIQ (1 << 2)
#define SCR_EL3_IRQ (1 << 1)
#define SCR_EL3_NS (1 << 0)
//
// Hypervisor Configuration Register
//
#define HCR_EL2_ID (1 << 33)
#define HCR_EL2_CD (1 << 32)
#define HCR_EL2_RW (1 << 31)
#define HCR_EL2_TRVM (1 << 30)
#define HCR_EL2_HVC (1 << 29)
#define HCR_EL2_TDZ (1 << 28)
#endif // V8_SYSTEM_H

69
ports_arch/ARMv8-A/threadx_smp/ports/ac6/example_build/sample_threadx/v8_utils.S Normal file
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//
// Simple utility routines for baremetal v8 code
//
// Copyright (c) 2013-2017 Arm Limited (or its affiliates). All rights reserved.
// Use, modification and redistribution of this file is subject to your possession of a
// valid End User License Agreement for the Arm Product of which these examples are part of
// and your compliance with all applicable terms and conditions of such licence agreement.
//
#include "v8_system.h"
.text
.cfi_sections .debug_frame // put stack frame info into .debug_frame instead of .eh_frame
//
// void *ZeroBlock(void *blockPtr, unsigned int nBytes)
//
// Zero fill a block of memory
// Fill memory pages or similar structures with zeros.
// The byte count must be a multiple of the block fill size (16 bytes)
//
// Inputs:
// blockPtr - base address of block to fill
// nBytes - block size, in bytes
//
// Returns:
// pointer to just filled block, NULL if nBytes is
// incompatible with block fill size
//
.global ZeroBlock
.type ZeroBlock, "function"
.cfi_startproc
ZeroBlock:
//
// we fill data by steam, 16 bytes at a time: check that
// blocksize is a multiple of that
//
ubfx x2, x1, #0, #4
cbnz x2, incompatible
//
// we already have one register full of zeros, get another
//
mov x3, x2
//
// OK, set temporary pointer and away we go
//
add x0, x0, x1
loop0:
subs x1, x1, #16
stp x2, x3, [x0, #-16]!
b.ne loop0
//
// that's all - x0 will be back to its start value
//
ret
//
// parameters are incompatible with block size - return
// an indication that this is so
//
incompatible:
mov x0,#0
ret
.cfi_endproc

252
ports_arch/ARMv8-A/threadx_smp/ports/ac6/example_build/sample_threadx/vectors.S Normal file
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// ------------------------------------------------------------
// Armv8-A Vector tables
//
// Copyright (c) 2014-2016 Arm Limited (or its affiliates). All rights reserved.
// Use, modification and redistribution of this file is subject to your possession of a
// valid End User License Agreement for the Arm Product of which these examples are part of
// and your compliance with all applicable terms and conditions of such licence agreement.
// ------------------------------------------------------------
.global el1_vectors
.global el2_vectors
.global el3_vectors
.global c0sync1
.global irqHandler
.global fiqHandler
.global irqFirstLevelHandler
.global fiqFirstLevelHandler
.section EL1VECTORS, "ax"
.align 11
//
// Current EL with SP0
//
el1_vectors:
c0sync1: B c0sync1
.balign 0x80
c0irq1: B irqFirstLevelHandler
.balign 0x80
c0fiq1: B fiqFirstLevelHandler
.balign 0x80
c0serr1: B c0serr1
//
// Current EL with SPx
//
.balign 0x80
cxsync1: B cxsync1
.balign 0x80
cxirq1: B irqFirstLevelHandler
.balign 0x80
cxfiq1: B fiqFirstLevelHandler
.balign 0x80
cxserr1: B cxserr1
//
// Lower EL using AArch64
//
.balign 0x80
l64sync1: B l64sync1
.balign 0x80
l64irq1: B irqFirstLevelHandler
.balign 0x80
l64fiq1: B fiqFirstLevelHandler
.balign 0x80
l64serr1: B l64serr1
//
// Lower EL using AArch32
//
.balign 0x80
l32sync1: B l32sync1
.balign 0x80
l32irq1: B irqFirstLevelHandler
.balign 0x80
l32fiq1: B fiqFirstLevelHandler
.balign 0x80
l32serr1: B l32serr1
//----------------------------------------------------------------
.section EL2VECTORS, "ax"
.align 11
//
// Current EL with SP0
//
el2_vectors:
c0sync2: B c0sync2
.balign 0x80
c0irq2: B irqFirstLevelHandler
.balign 0x80
c0fiq2: B fiqFirstLevelHandler
.balign 0x80
c0serr2: B c0serr2
//
// Current EL with SPx
//
.balign 0x80
cxsync2: B cxsync2
.balign 0x80
cxirq2: B irqFirstLevelHandler
.balign 0x80
cxfiq2: B fiqFirstLevelHandler
.balign 0x80
cxserr2: B cxserr2
//
// Lower EL using AArch64
//
.balign 0x80
l64sync2: B l64sync2
.balign 0x80
l64irq2: B irqFirstLevelHandler
.balign 0x80
l64fiq2: B fiqFirstLevelHandler
.balign 0x80
l64serr2: B l64serr2
//
// Lower EL using AArch32
//
.balign 0x80
l32sync2: B l32sync2
.balign 0x80
l32irq2: B irqFirstLevelHandler
.balign 0x80
l32fiq2: B fiqFirstLevelHandler
.balign 0x80
l32serr2: B l32serr2
//----------------------------------------------------------------
.section EL3VECTORS, "ax"
.align 11
//
// Current EL with SP0
//
el3_vectors:
c0sync3: B c0sync3
.balign 0x80
c0irq3: B irqFirstLevelHandler
.balign 0x80
c0fiq3: B fiqFirstLevelHandler
.balign 0x80
c0serr3: B c0serr3
//
// Current EL with SPx
//
.balign 0x80
cxsync3: B cxsync3
.balign 0x80
cxirq3: B irqFirstLevelHandler
.balign 0x80
cxfiq3: B fiqFirstLevelHandler
.balign 0x80
cxserr3: B cxserr3
//
// Lower EL using AArch64
//
.balign 0x80
l64sync3: B l64sync3
.balign 0x80
l64irq3: B irqFirstLevelHandler
.balign 0x80
l64fiq3: B fiqFirstLevelHandler
.balign 0x80
l64serr3: B l64serr3
//
// Lower EL using AArch32
//
.balign 0x80
l32sync3: B l32sync3
.balign 0x80
l32irq3: B irqFirstLevelHandler
.balign 0x80
l32fiq3: B fiqFirstLevelHandler
.balign 0x80
l32serr3: B l32serr3
.section InterruptHandlers, "ax"
.balign 4
.type irqFirstLevelHandler, "function"
irqFirstLevelHandler:
MSR SPSel, 0
STP x29, x30, [sp, #-16]!
BL _tx_thread_context_save
BL irqHandler
B _tx_thread_context_restore
.type fiqFirstLevelHandler, "function"
fiqFirstLevelHandler:
STP x29, x30, [sp, #-16]!
STP x18, x19, [sp, #-16]!
STP x16, x17, [sp, #-16]!
STP x14, x15, [sp, #-16]!
STP x12, x13, [sp, #-16]!
STP x10, x11, [sp, #-16]!
STP x8, x9, [sp, #-16]!
STP x6, x7, [sp, #-16]!
STP x4, x5, [sp, #-16]!
STP x2, x3, [sp, #-16]!
STP x0, x1, [sp, #-16]!
BL fiqHandler
LDP x0, x1, [sp], #16
LDP x2, x3, [sp], #16
LDP x4, x5, [sp], #16
LDP x6, x7, [sp], #16
LDP x8, x9, [sp], #16
LDP x10, x11, [sp], #16
LDP x12, x13, [sp], #16
LDP x14, x15, [sp], #16
LDP x16, x17, [sp], #16
LDP x18, x19, [sp], #16
LDP x29, x30, [sp], #16
ERET

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ports_arch/ARMv8-A/threadx_smp/ports/ac6/example_build/tx/.cproject Normal file
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<?xml version="1.0" encoding="UTF-8" standalone="no"?>
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<cconfiguration id="com.arm.eclipse.build.config.v6.lib.debug.base.1470528944">
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<externalSettings>
<externalSetting>
<entry flags="VALUE_WORKSPACE_PATH" kind="includePath" name="/tx"/>
<entry flags="VALUE_WORKSPACE_PATH" kind="libraryPath" name="/tx/Debug"/>
<entry flags="RESOLVED" kind="libraryFile" name="tx" srcPrefixMapping="" srcRootPath=""/>
</externalSetting>
</externalSettings>
<extensions>
<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="com.arm.eclipse.builder.armcc.error" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
</extensions>
</storageModule>
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
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<builder autoBuildTarget="all" buildPath="${workspace_loc:/tx}/Debug" cleanBuildTarget="clean" enableAutoBuild="false" enableCleanBuild="true" enabledIncrementalBuild="true" id="com.arm.toolchain.v6.builder.218588332" incrementalBuildTarget="all" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" parallelBuildOn="true" parallelizationNumber="8" superClass="com.arm.toolchain.v6.builder"/>
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<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/inc_port}&quot;"/>
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48
ports_arch/ARMv8-A/threadx_smp/ports/ac6/example_build/tx/.project Normal file
View File

@@ -0,0 +1,48 @@
<?xml version="1.0" encoding="UTF-8"?>
<projectDescription>
<name>tx</name>
<comment></comment>
<projects>
</projects>
<buildSpec>
<buildCommand>
<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
<triggers>clean,full,incremental,</triggers>
<arguments>
</arguments>
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<triggers>full,incremental,</triggers>
<arguments>
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<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
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</natures>
<linkedResources>
<link>
<name>inc_generic</name>
<type>2</type>
<locationURI>$%7BPARENT-5-PROJECT_LOC%7D/common_smp/inc</locationURI>
</link>
<link>
<name>inc_port</name>
<type>2</type>
<locationURI>$%7BPARENT-2-PROJECT_LOC%7D/inc</locationURI>
</link>
<link>
<name>src_generic</name>
<type>2</type>
<locationURI>$%7BPARENT-5-PROJECT_LOC%7D/common_smp/src</locationURI>
</link>
<link>
<name>src_port</name>
<type>2</type>
<locationURI>$%7BPARENT-2-PROJECT_LOC%7D/src</locationURI>
</link>
</linkedResources>
</projectDescription>

104
ports_arch/ARMv8-A/threadx_smp/ports/ac6/src/tx_initialize_low_level.S Normal file
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@@ -0,0 +1,104 @@
/**************************************************************************/
/* */
/* Copyright (c) Microsoft Corporation. All rights reserved. */
/* */
/* This software is licensed under the Microsoft Software License */
/* Terms for Microsoft Azure RTOS. Full text of the license can be */
/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
/* and in the root directory of this software. */
/* */
/**************************************************************************/
/**************************************************************************/
/**************************************************************************/
/** */
/** ThreadX Component */
/** */
/** Initialize */
/** */
/**************************************************************************/
/**************************************************************************/
.text
.align 3
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_initialize_low_level ARMv8-A-SMP */
/* 6.1.10 */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
/* */
/* DESCRIPTION */
/* */
/* This function is responsible for any low-level processor */
/* initialization, including setting up interrupt vectors, setting */
/* up a periodic timer interrupt source, saving the system stack */
/* pointer for use in ISR processing later, and finding the first */
/* available RAM memory address for tx_application_define. */
/* */
/* INPUT */
/* */
/* None */
/* */
/* OUTPUT */
/* */
/* None */
/* */
/* CALLS */
/* */
/* None */
/* */
/* CALLED BY */
/* */
/* _tx_initialize_kernel_enter ThreadX entry function */
/* */
/* RELEASE HISTORY */
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 01-31-2022 Andres Mlinar Updated comments, */
/* resulting in version 6.1.10 */
/* */
/**************************************************************************/
// VOID _tx_initialize_low_level(VOID)
// {
.global _tx_initialize_low_level
.type _tx_initialize_low_level, @function
_tx_initialize_low_level:
MSR DAIFSet, 0x3 // Lockout interrupts
/* Save the system stack pointer. */
// _tx_thread_system_stack_ptr = (VOID_PTR) (sp);
LDR x0, =_tx_thread_system_stack_ptr // Pickup address of system stack ptr
MOV x1, sp // Pickup SP
SUB x1, x1, #15 //
BIC x1, x1, #0xF // Get 16-bit alignment
STR x1, [x0] // Store system stack
/* Save the first available memory address. */
// _tx_initialize_unused_memory = (VOID_PTR) Image$$HEAP$$ZI$$Limit;
LDR x0, =_tx_initialize_unused_memory // Pickup address of unused memory ptr
LDR x1, =heap_limit // Pickup unused memory address - A free
LDR x1, [x1] // memory section must be setup after the
// heap section.
STR x1, [x0] // Store unused memory address
/* Done, return to caller. */
RET // Return to caller
// }
.align 3
heap_limit:
.quad (Image$$TOP_OF_RAM$$ZI$$Limit)