add ARM11
This commit is contained in:
Scott Larson
183
ports/arm11/iar/src/tx_thread_schedule.s
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183
ports/arm11/iar/src/tx_thread_schedule.s
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;/**************************************************************************/
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;/* */
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;/* Copyright (c) 1996-2018 by Express Logic Inc. */
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;/* */
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;/* This software is copyrighted by and is the sole property of Express */
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;/* Logic, Inc. All rights, title, ownership, or other interests */
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;/* in the software remain the property of Express Logic, Inc. This */
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;/* software may only be used in accordance with the corresponding */
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;/* license agreement. Any unauthorized use, duplication, transmission, */
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;/* distribution, or disclosure of this software is expressly forbidden. */
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;/* */
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;/* This Copyright notice may not be removed or modified without prior */
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;/* written consent of Express Logic, Inc. */
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;/* */
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;/* Express Logic, Inc. reserves the right to modify this software */
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;/* without notice. */
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;/* */
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;/* Express Logic, Inc. info@expresslogic.com */
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;/* 11423 West Bernardo Court http://www.expresslogic.com */
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;/* San Diego, CA 92127 */
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;/* */
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;/**************************************************************************/
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;
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;
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;/**************************************************************************/
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;/**************************************************************************/
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;/** */
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;/** ThreadX Component */
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;/** */
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;/** Thread */
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;/** */
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;/**************************************************************************/
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;/**************************************************************************/
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;
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;
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;#define TX_SOURCE_CODE
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;
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;
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;/* Include necessary system files. */
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;
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;#include "tx_api.h"
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;#include "tx_thread.h"
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;#include "tx_timer.h"
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;
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#ifdef TX_ENABLE_FIQ_SUPPORT
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ENABLE_INTS DEFINE 0xC0 ; IRQ & FIQ Interrupts enabled mask
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#else
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ENABLE_INTS DEFINE 0x80 ; IRQ Interrupts enabled mask
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#endif
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;
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;
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EXTERN _tx_thread_execute_ptr
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EXTERN _tx_thread_current_ptr
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EXTERN _tx_timer_time_slice
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EXTERN _tx_execution_thread_enter
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;
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;
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;
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;/**************************************************************************/
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;/* */
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;/* FUNCTION RELEASE */
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;/* */
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;/* _tx_thread_schedule ARM11/IAR */
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;/* 6.0.1 */
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;/* AUTHOR */
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;/* */
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;/* William E. Lamie, Express Logic, Inc. */
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;/* */
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;/* DESCRIPTION */
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;/* */
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;/* This function waits for a thread control block pointer to appear in */
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;/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */
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;/* in the variable, the corresponding thread is resumed. */
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;/* */
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;/* INPUT */
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;/* */
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;/* None */
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;/* */
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;/* OUTPUT */
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;/* */
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;/* None */
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;/* */
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;/* CALLS */
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;/* */
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;/* None */
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;/* */
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;/* CALLED BY */
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;/* */
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;/* _tx_initialize_kernel_enter ThreadX entry function */
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;/* _tx_thread_system_return Return to system from thread */
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;/* _tx_thread_context_restore Restore thread's context */
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;/* */
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;/* RELEASE HISTORY */
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;/* */
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;/* DATE NAME DESCRIPTION */
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;/* */
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;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
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;/* */
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;/**************************************************************************/
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;VOID _tx_thread_schedule(VOID)
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;{
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RSEG .text:CODE:NOROOT(2)
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PUBLIC _tx_thread_schedule
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CODE32
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_tx_thread_schedule??rA
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_tx_thread_schedule
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;
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; /* Enable interrupts. */
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;
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MRS r2, CPSR ; Pickup CPSR
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BIC r0, r2, #ENABLE_INTS ; Clear the disable bit(s)
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MSR CPSR_cxsf, r0 ; Enable interrupts
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;
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; /* Wait for a thread to execute. */
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; do
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; {
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LDR r1, =_tx_thread_execute_ptr ; Address of thread execute ptr
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;
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__tx_thread_schedule_loop
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;
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LDR r0, [r1, #0] ; Pickup next thread to execute
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CMP r0, #0 ; Is it NULL?
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BEQ __tx_thread_schedule_loop ; If so, keep looking for a thread
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;
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; }
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; while(_tx_thread_execute_ptr == TX_NULL);
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;
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; /* Yes! We have a thread to execute. Lockout interrupts and
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; transfer control to it. */
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;
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MSR CPSR_cxsf, r2 ; Disable interrupts
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;
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; /* Setup the current thread pointer. */
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; _tx_thread_current_ptr = _tx_thread_execute_ptr;
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;
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LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread
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STR r0, [r1, #0] ; Setup current thread pointer
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;
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; /* Increment the run count for this thread. */
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; _tx_thread_current_ptr -> tx_thread_run_count++;
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;
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LDR r2, [r0, #4] ; Pickup run counter
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LDR r3, [r0, #24] ; Pickup time-slice for this thread
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ADD r2, r2, #1 ; Increment thread run-counter
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STR r2, [r0, #4] ; Store the new run counter
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;
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; /* Setup time-slice, if present. */
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; _tx_timer_time_slice = _tx_thread_current_ptr -> tx_thread_time_slice;
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;
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LDR r2, =_tx_timer_time_slice ; Pickup address of time slice
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; variable
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LDR sp, [r0, #8] ; Switch stack pointers
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STR r3, [r2, #0] ; Setup time-slice
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;
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; /* Switch to the thread's stack. */
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; sp = _tx_thread_execute_ptr -> tx_thread_stack_ptr;
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;
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#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
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;
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; /* Call the thread entry function to indicate the thread is executing. */
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;
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BL _tx_execution_thread_enter ; Call the thread execution enter function
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#endif
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;
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; /* Determine if an interrupt frame or a synchronous task suspension frame
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; is present. */
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;
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LDMIA sp!, {r0, r1} ; Pickup the stack type and saved CPSR
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CMP r0, #0 ; Check for synchronous context switch
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MSRNE SPSR_cxsf, r1 ; Setup SPSR for return
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LDMNEIA sp!, {r0-r12, lr, pc}^ ; Return to point of thread interrupt
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LDMIA sp!, {r4-r11, lr} ; Return to thread synchronously
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MSR CPSR_cxsf, r1 ; Recover CPSR
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#ifdef TX_THUMB
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BX lr ; Return to caller
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#else
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MOV pc, lr ; Return to caller
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#endif
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;
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;}
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;
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END
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