add SMP, Modules, and more processor/tools releases
This commit is contained in:
Scott Larson
95
ports/cortex_m7/ac6/src/tx_thread_context_restore.S
Normal file
95
ports/cortex_m7/ac6/src/tx_thread_context_restore.S
Normal file
@@ -0,0 +1,95 @@
|
||||
@/**************************************************************************/
|
||||
@/* */
|
||||
@/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
@/* */
|
||||
@/* This software is licensed under the Microsoft Software License */
|
||||
@/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
@/* and in the root directory of this software. */
|
||||
@/* */
|
||||
@/**************************************************************************/
|
||||
@
|
||||
@
|
||||
@/**************************************************************************/
|
||||
@/**************************************************************************/
|
||||
@/** */
|
||||
@/** ThreadX Component */
|
||||
@/** */
|
||||
@/** Thread */
|
||||
@/** */
|
||||
@/**************************************************************************/
|
||||
@/**************************************************************************/
|
||||
@
|
||||
@
|
||||
@#define TX_SOURCE_CODE
|
||||
@
|
||||
@
|
||||
@/* Include necessary system files. */
|
||||
@
|
||||
@#include "tx_api.h"
|
||||
@#include "tx_thread.h"
|
||||
@#include "tx_timer.h"
|
||||
@
|
||||
@
|
||||
.global _tx_thread_system_state
|
||||
.global _tx_thread_current_ptr
|
||||
.global _tx_thread_system_stack_ptr
|
||||
.global _tx_thread_execute_ptr
|
||||
.global _tx_timer_time_slice
|
||||
.global _tx_thread_schedule
|
||||
.global _tx_thread_preempt_disable
|
||||
@
|
||||
@
|
||||
.text
|
||||
.align 4
|
||||
.syntax unified
|
||||
@/**************************************************************************/
|
||||
@/* */
|
||||
@/* FUNCTION RELEASE */
|
||||
@/* */
|
||||
@/* _tx_thread_context_restore Cortex-M7/AC6 */
|
||||
@/* 6.0.1 */
|
||||
@/* AUTHOR */
|
||||
@/* */
|
||||
@/* William E. Lamie, Microsoft Corporation */
|
||||
@/* */
|
||||
@/* DESCRIPTION */
|
||||
@/* */
|
||||
@/* This function restores the interrupt context if it is processing a */
|
||||
@/* nested interrupt. If not, it returns to the interrupt thread if no */
|
||||
@/* preemption is necessary. Otherwise, if preemption is necessary or */
|
||||
@/* if no thread was running, the function returns to the scheduler. */
|
||||
@/* */
|
||||
@/* INPUT */
|
||||
@/* */
|
||||
@/* None */
|
||||
@/* */
|
||||
@/* OUTPUT */
|
||||
@/* */
|
||||
@/* None */
|
||||
@/* */
|
||||
@/* CALLS */
|
||||
@/* */
|
||||
@/* _tx_thread_schedule Thread scheduling routine */
|
||||
@/* */
|
||||
@/* CALLED BY */
|
||||
@/* */
|
||||
@/* ISRs Interrupt Service Routines */
|
||||
@/* */
|
||||
@/* RELEASE HISTORY */
|
||||
@/* */
|
||||
@/* DATE NAME DESCRIPTION */
|
||||
@/* */
|
||||
@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
|
||||
@/* */
|
||||
@/**************************************************************************/
|
||||
@VOID _tx_thread_context_restore(VOID)
|
||||
@{
|
||||
.global _tx_thread_context_restore
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||||
.thumb_func
|
||||
_tx_thread_context_restore:
|
||||
@
|
||||
@ /* Not needed for this port - just return! */
|
||||
BX lr
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||||
@}
|
||||
|
||||
88
ports/cortex_m7/ac6/src/tx_thread_context_save.S
Normal file
88
ports/cortex_m7/ac6/src/tx_thread_context_save.S
Normal file
@@ -0,0 +1,88 @@
|
||||
@/**************************************************************************/
|
||||
@/* */
|
||||
@/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
@/* */
|
||||
@/* This software is licensed under the Microsoft Software License */
|
||||
@/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
@/* and in the root directory of this software. */
|
||||
@/* */
|
||||
@/**************************************************************************/
|
||||
@
|
||||
@
|
||||
@/**************************************************************************/
|
||||
@/**************************************************************************/
|
||||
@/** */
|
||||
@/** ThreadX Component */
|
||||
@/** */
|
||||
@/** Thread */
|
||||
@/** */
|
||||
@/**************************************************************************/
|
||||
@/**************************************************************************/
|
||||
@
|
||||
@
|
||||
@#define TX_SOURCE_CODE
|
||||
@
|
||||
@
|
||||
@/* Include necessary system files. */
|
||||
@
|
||||
@#include "tx_api.h"
|
||||
@#include "tx_thread.h"
|
||||
@#include "tx_timer.h"
|
||||
@
|
||||
@
|
||||
.global _tx_thread_system_state
|
||||
.global _tx_thread_current_ptr
|
||||
@
|
||||
@
|
||||
.text
|
||||
.align 4
|
||||
.syntax unified
|
||||
@/**************************************************************************/
|
||||
@/* */
|
||||
@/* FUNCTION RELEASE */
|
||||
@/* */
|
||||
@/* _tx_thread_context_save Cortex-M7/AC6 */
|
||||
@/* 6.0.1 */
|
||||
@/* AUTHOR */
|
||||
@/* */
|
||||
@/* William E. Lamie, Microsoft Corporation */
|
||||
@/* */
|
||||
@/* DESCRIPTION */
|
||||
@/* */
|
||||
@/* This function saves the context of an executing thread in the */
|
||||
@/* beginning of interrupt processing. The function also ensures that */
|
||||
@/* the system stack is used upon return to the calling ISR. */
|
||||
@/* */
|
||||
@/* INPUT */
|
||||
@/* */
|
||||
@/* None */
|
||||
@/* */
|
||||
@/* OUTPUT */
|
||||
@/* */
|
||||
@/* None */
|
||||
@/* */
|
||||
@/* CALLS */
|
||||
@/* */
|
||||
@/* None */
|
||||
@/* */
|
||||
@/* CALLED BY */
|
||||
@/* */
|
||||
@/* ISRs */
|
||||
@/* */
|
||||
@/* RELEASE HISTORY */
|
||||
@/* */
|
||||
@/* DATE NAME DESCRIPTION */
|
||||
@/* */
|
||||
@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
|
||||
@/* */
|
||||
@/**************************************************************************/
|
||||
@VOID _tx_thread_context_save(VOID)
|
||||
@{
|
||||
.global _tx_thread_context_save
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||||
.thumb_func
|
||||
_tx_thread_context_save:
|
||||
@
|
||||
@ /* Not needed for this port - just return! */
|
||||
BX lr
|
||||
@}
|
||||
92
ports/cortex_m7/ac6/src/tx_thread_interrupt_control.S
Normal file
92
ports/cortex_m7/ac6/src/tx_thread_interrupt_control.S
Normal file
@@ -0,0 +1,92 @@
|
||||
@/**************************************************************************/
|
||||
@/* */
|
||||
@/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
@/* */
|
||||
@/* This software is licensed under the Microsoft Software License */
|
||||
@/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
@/* and in the root directory of this software. */
|
||||
@/* */
|
||||
@/**************************************************************************/
|
||||
|
||||
|
||||
@/**************************************************************************/
|
||||
@/**************************************************************************/
|
||||
@/** */
|
||||
@/** ThreadX Component */
|
||||
@/** */
|
||||
@/** Thread */
|
||||
@/** */
|
||||
@/**************************************************************************/
|
||||
@/**************************************************************************/
|
||||
|
||||
@/* #define TX_SOURCE_CODE */
|
||||
|
||||
|
||||
@/* Include necessary system files. */
|
||||
|
||||
@/* #include "tx_api.h"
|
||||
#include "tx_thread.h" */
|
||||
|
||||
|
||||
.text 32
|
||||
.align 4
|
||||
.syntax unified
|
||||
@/**************************************************************************/
|
||||
@/* */
|
||||
@/* FUNCTION RELEASE */
|
||||
@/* */
|
||||
@/* _tx_thread_interrupt_control Cortex-M7/AC6 */
|
||||
@/* 6.0.1 */
|
||||
@/* AUTHOR */
|
||||
@/* */
|
||||
@/* William E. Lamie, Microsoft Corporation */
|
||||
@/* */
|
||||
@/* DESCRIPTION */
|
||||
@/* */
|
||||
@/* This function is responsible for changing the interrupt lockout */
|
||||
@/* posture of the system. */
|
||||
@/* */
|
||||
@/* INPUT */
|
||||
@/* */
|
||||
@/* new_posture New interrupt lockout posture */
|
||||
@/* */
|
||||
@/* OUTPUT */
|
||||
@/* */
|
||||
@/* old_posture Old interrupt lockout posture */
|
||||
@/* */
|
||||
@/* CALLS */
|
||||
@/* */
|
||||
@/* None */
|
||||
@/* */
|
||||
@/* CALLED BY */
|
||||
@/* */
|
||||
@/* Application Code */
|
||||
@/* */
|
||||
@/* RELEASE HISTORY */
|
||||
@/* */
|
||||
@/* DATE NAME DESCRIPTION */
|
||||
@/* */
|
||||
@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
|
||||
@/* */
|
||||
@/**************************************************************************/
|
||||
@/* UINT _tx_thread_interrupt_control(UINT new_posture)
|
||||
{ */
|
||||
.global _tx_thread_interrupt_control
|
||||
.thumb_func
|
||||
_tx_thread_interrupt_control:
|
||||
|
||||
@/* Pickup current interrupt lockout posture. */
|
||||
|
||||
MRS r1, PRIMASK @ Pickup current interrupt lockout
|
||||
|
||||
@/* Apply the new interrupt posture. */
|
||||
|
||||
MSR PRIMASK, r0 @ Apply the new interrupt lockout
|
||||
MOV r0, r1 @ Transfer old to return register
|
||||
BX lr @ Return to caller
|
||||
|
||||
@/* } */
|
||||
|
||||
|
||||
|
||||
294
ports/cortex_m7/ac6/src/tx_thread_schedule.S
Normal file
294
ports/cortex_m7/ac6/src/tx_thread_schedule.S
Normal file
@@ -0,0 +1,294 @@
|
||||
@/**************************************************************************/
|
||||
@/* */
|
||||
@/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
@/* */
|
||||
@/* This software is licensed under the Microsoft Software License */
|
||||
@/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
@/* and in the root directory of this software. */
|
||||
@/* */
|
||||
@/**************************************************************************/
|
||||
@
|
||||
@
|
||||
@/**************************************************************************/
|
||||
@/**************************************************************************/
|
||||
@/** */
|
||||
@/** ThreadX Component */
|
||||
@/** */
|
||||
@/** Thread */
|
||||
@/** */
|
||||
@/**************************************************************************/
|
||||
@/**************************************************************************/
|
||||
@
|
||||
@
|
||||
@#define TX_SOURCE_CODE
|
||||
@
|
||||
@
|
||||
@/* Include necessary system files. */
|
||||
@
|
||||
@#include "tx_api.h"
|
||||
@#include "tx_thread.h"
|
||||
@#include "tx_timer.h"
|
||||
@
|
||||
.global _tx_thread_current_ptr
|
||||
.global _tx_thread_execute_ptr
|
||||
.global _tx_timer_time_slice
|
||||
.global _tx_thread_system_stack_ptr
|
||||
@
|
||||
@
|
||||
.text
|
||||
.align 4
|
||||
.syntax unified
|
||||
@/**************************************************************************/
|
||||
@/* */
|
||||
@/* FUNCTION RELEASE */
|
||||
@/* */
|
||||
@/* _tx_thread_schedule Cortex-M7/AC6 */
|
||||
@/* 6.0.1 */
|
||||
@/* AUTHOR */
|
||||
@/* */
|
||||
@/* William E. Lamie, Microsoft Corporation */
|
||||
@/* */
|
||||
@/* DESCRIPTION */
|
||||
@/* */
|
||||
@/* This function waits for a thread control block pointer to appear in */
|
||||
@/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */
|
||||
@/* in the variable, the corresponding thread is resumed. */
|
||||
@/* */
|
||||
@/* INPUT */
|
||||
@/* */
|
||||
@/* None */
|
||||
@/* */
|
||||
@/* OUTPUT */
|
||||
@/* */
|
||||
@/* None */
|
||||
@/* */
|
||||
@/* CALLS */
|
||||
@/* */
|
||||
@/* None */
|
||||
@/* */
|
||||
@/* CALLED BY */
|
||||
@/* */
|
||||
@/* _tx_initialize_kernel_enter ThreadX entry function */
|
||||
@/* _tx_thread_system_return Return to system from thread */
|
||||
@/* _tx_thread_context_restore Restore thread's context */
|
||||
@/* */
|
||||
@/* RELEASE HISTORY */
|
||||
@/* */
|
||||
@/* DATE NAME DESCRIPTION */
|
||||
@/* */
|
||||
@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
|
||||
@/* */
|
||||
@/**************************************************************************/
|
||||
@VOID _tx_thread_schedule(VOID)
|
||||
@{
|
||||
.global _tx_thread_schedule
|
||||
.thumb_func
|
||||
_tx_thread_schedule:
|
||||
@
|
||||
@ /* This function should only ever be called on Cortex-M7
|
||||
@ from the first schedule request. Subsequent scheduling occurs
|
||||
@ from the PendSV handling routines below. */
|
||||
@
|
||||
@ /* Clear the preempt-disable flag to enable rescheduling after initialization on Cortex-M targets. */
|
||||
@
|
||||
MOV r0, #0 @ Build value for TX_FALSE
|
||||
LDR r2, =_tx_thread_preempt_disable @ Build address of preempt disable flag
|
||||
STR r0, [r2, #0] @ Clear preempt disable flag
|
||||
@
|
||||
@ /* Clear CONTROL.FPCA bit so VFP registers aren't unnecessarily stacked. */
|
||||
@
|
||||
#ifdef TX_ENABLE_FPU_SUPPORT
|
||||
MRS r0, CONTROL @ Pickup current CONTROL register
|
||||
BIC r0, r0, #4 @ Clear the FPCA bit
|
||||
MSR CONTROL, r0 @ Setup new CONTROL register
|
||||
#endif
|
||||
@
|
||||
@ /* Enable interrupts */
|
||||
@
|
||||
CPSIE i
|
||||
@
|
||||
@ /* Enter the scheduler for the first time. */
|
||||
@
|
||||
MOV r0, #0x10000000 @ Load PENDSVSET bit
|
||||
MOV r1, #0xE000E000 @ Load NVIC base
|
||||
STR r0, [r1, #0xD04] @ Set PENDSVBIT in ICSR
|
||||
DSB @ Complete all memory accesses
|
||||
ISB @ Flush pipeline
|
||||
@
|
||||
@ /* Wait here for the PendSV to take place. */
|
||||
@
|
||||
__tx_wait_here:
|
||||
B __tx_wait_here @ Wait for the PendSV to happen
|
||||
@}
|
||||
@
|
||||
@ /* Generic context switch-out switch-in handler... Note that this handler is
|
||||
@ common for both PendSV and SVCall. */
|
||||
@
|
||||
.global PendSV_Handler
|
||||
.global __tx_PendSVHandler
|
||||
.thumb_func
|
||||
PendSV_Handler:
|
||||
.thumb_func
|
||||
__tx_PendSVHandler:
|
||||
@
|
||||
@ /* Get current thread value and new thread pointer. */
|
||||
@
|
||||
__tx_ts_handler:
|
||||
|
||||
#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
|
||||
@
|
||||
@ /* Call the thread exit function to indicate the thread is no longer executing. */
|
||||
@
|
||||
CPSID i @ Disable interrupts
|
||||
PUSH {r0, lr} @ Save LR (and r0 just for alignment)
|
||||
BL _tx_execution_thread_exit @ Call the thread exit function
|
||||
POP {r0, lr} @ Recover LR
|
||||
CPSIE i @ Enable interrupts
|
||||
#endif
|
||||
LDR r0, =_tx_thread_current_ptr @ Build current thread pointer address
|
||||
LDR r2, =_tx_thread_execute_ptr @ Build execute thread pointer address
|
||||
MOV r3, #0 @ Build NULL value
|
||||
LDR r1, [r0] @ Pickup current thread pointer
|
||||
@
|
||||
@ /* Determine if there is a current thread to finish preserving. */
|
||||
@
|
||||
CBZ r1, __tx_ts_new @ If NULL, skip preservation
|
||||
@
|
||||
@ /* Recover PSP and preserve current thread context. */
|
||||
@
|
||||
STR r3, [r0] @ Set _tx_thread_current_ptr to NULL
|
||||
MRS r12, PSP @ Pickup PSP pointer (thread's stack pointer)
|
||||
STMDB r12!, {r4-r11} @ Save its remaining registers
|
||||
#ifdef TX_ENABLE_FPU_SUPPORT
|
||||
TST LR, #0x10 @ Determine if the VFP extended frame is present
|
||||
BNE _skip_vfp_save
|
||||
VSTMDB r12!,{s16-s31} @ Yes, save additional VFP registers
|
||||
_skip_vfp_save:
|
||||
#endif
|
||||
LDR r4, =_tx_timer_time_slice @ Build address of time-slice variable
|
||||
STMDB r12!, {LR} @ Save LR on the stack
|
||||
@
|
||||
@ /* Determine if time-slice is active. If it isn't, skip time handling processing. */
|
||||
@
|
||||
LDR r5, [r4] @ Pickup current time-slice
|
||||
STR r12, [r1, #8] @ Save the thread stack pointer
|
||||
CBZ r5, __tx_ts_new @ If not active, skip processing
|
||||
@
|
||||
@ /* Time-slice is active, save the current thread's time-slice and clear the global time-slice variable. */
|
||||
@
|
||||
STR r5, [r1, #24] @ Save current time-slice
|
||||
@
|
||||
@ /* Clear the global time-slice. */
|
||||
@
|
||||
STR r3, [r4] @ Clear time-slice
|
||||
@
|
||||
@
|
||||
@ /* Executing thread is now completely preserved!!! */
|
||||
@
|
||||
__tx_ts_new:
|
||||
@
|
||||
@ /* Now we are looking for a new thread to execute! */
|
||||
@
|
||||
CPSID i @ Disable interrupts
|
||||
LDR r1, [r2] @ Is there another thread ready to execute?
|
||||
CBZ r1, __tx_ts_wait @ No, skip to the wait processing
|
||||
@
|
||||
@ /* Yes, another thread is ready for else, make the current thread the new thread. */
|
||||
@
|
||||
STR r1, [r0] @ Setup the current thread pointer to the new thread
|
||||
CPSIE i @ Enable interrupts
|
||||
@
|
||||
@ /* Increment the thread run count. */
|
||||
@
|
||||
__tx_ts_restore:
|
||||
LDR r7, [r1, #4] @ Pickup the current thread run count
|
||||
LDR r4, =_tx_timer_time_slice @ Build address of time-slice variable
|
||||
LDR r5, [r1, #24] @ Pickup thread's current time-slice
|
||||
ADD r7, r7, #1 @ Increment the thread run count
|
||||
STR r7, [r1, #4] @ Store the new run count
|
||||
@
|
||||
@ /* Setup global time-slice with thread's current time-slice. */
|
||||
@
|
||||
STR r5, [r4] @ Setup global time-slice
|
||||
|
||||
#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
|
||||
@
|
||||
@ /* Call the thread entry function to indicate the thread is executing. */
|
||||
@
|
||||
PUSH {r0, r1} @ Save r0/r1
|
||||
BL _tx_execution_thread_enter @ Call the thread execution enter function
|
||||
POP {r0, r1} @ Recover r3
|
||||
#endif
|
||||
@
|
||||
@ /* Restore the thread context and PSP. */
|
||||
@
|
||||
LDR r12, [r1, #8] @ Pickup thread's stack pointer
|
||||
LDMIA r12!, {LR} @ Pickup LR
|
||||
#ifdef TX_ENABLE_FPU_SUPPORT
|
||||
TST LR, #0x10 @ Determine if the VFP extended frame is present
|
||||
BNE _skip_vfp_restore @ If not, skip VFP restore
|
||||
VLDMIA r12!, {s16-s31} @ Yes, restore additional VFP registers
|
||||
_skip_vfp_restore:
|
||||
#endif
|
||||
LDMIA r12!, {r4-r11} @ Recover thread's registers
|
||||
MSR PSP, r12 @ Setup the thread's stack pointer
|
||||
@
|
||||
@ /* Return to thread. */
|
||||
@
|
||||
BX lr @ Return to thread!
|
||||
@
|
||||
@ /* The following is the idle wait processing... in this case, no threads are ready for execution and the
|
||||
@ system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts
|
||||
@ are disabled to allow use of WFI for waiting for a thread to arrive. */
|
||||
@
|
||||
__tx_ts_wait:
|
||||
CPSID i @ Disable interrupts
|
||||
LDR r1, [r2] @ Pickup the next thread to execute pointer
|
||||
STR r1, [r0] @ Store it in the current pointer
|
||||
CBNZ r1, __tx_ts_ready @ If non-NULL, a new thread is ready!
|
||||
#ifdef TX_ENABLE_WFI
|
||||
DSB @ Ensure no outstanding memory transactions
|
||||
WFI @ Wait for interrupt
|
||||
ISB @ Ensure pipeline is flushed
|
||||
#endif
|
||||
CPSIE i @ Enable interrupts
|
||||
B __tx_ts_wait @ Loop to continue waiting
|
||||
@
|
||||
@ /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are
|
||||
@ already in the handler! */
|
||||
@
|
||||
__tx_ts_ready:
|
||||
MOV r7, #0x08000000 @ Build clear PendSV value
|
||||
MOV r8, #0xE000E000 @ Build base NVIC address
|
||||
STR r7, [r8, #0xD04] @ Clear any PendSV
|
||||
@
|
||||
@ /* Re-enable interrupts and restore new thread. */
|
||||
@
|
||||
CPSIE i @ Enable interrupts
|
||||
B __tx_ts_restore @ Restore the thread
|
||||
|
||||
|
||||
#ifdef TX_ENABLE_FPU_SUPPORT
|
||||
|
||||
.global tx_thread_fpu_enable
|
||||
.thumb_func
|
||||
tx_thread_fpu_enable:
|
||||
@
|
||||
@ /* Automatic VPF logic is supported, this function is present only for
|
||||
@ backward compatibility purposes and therefore simply returns. */
|
||||
@
|
||||
BX LR @ Return to caller
|
||||
|
||||
.global tx_thread_fpu_disable
|
||||
.thumb_func
|
||||
tx_thread_fpu_disable:
|
||||
@
|
||||
@ /* Automatic VPF logic is supported, this function is present only for
|
||||
@ backward compatibility purposes and therefore simply returns. */
|
||||
@
|
||||
BX LR @ Return to caller
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
146
ports/cortex_m7/ac6/src/tx_thread_stack_build.S
Normal file
146
ports/cortex_m7/ac6/src/tx_thread_stack_build.S
Normal file
@@ -0,0 +1,146 @@
|
||||
@/**************************************************************************/
|
||||
@/* */
|
||||
@/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
@/* */
|
||||
@/* This software is licensed under the Microsoft Software License */
|
||||
@/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
@/* and in the root directory of this software. */
|
||||
@/* */
|
||||
@/**************************************************************************/
|
||||
@
|
||||
@
|
||||
@/**************************************************************************/
|
||||
@/**************************************************************************/
|
||||
@/** */
|
||||
@/** ThreadX Component */
|
||||
@/** */
|
||||
@/** Thread */
|
||||
@/** */
|
||||
@/**************************************************************************/
|
||||
@/**************************************************************************/
|
||||
@
|
||||
@
|
||||
@#define TX_SOURCE_CODE
|
||||
@
|
||||
@
|
||||
@/* Include necessary system files. */
|
||||
@
|
||||
@#include "tx_api.h"
|
||||
@#include "tx_thread.h"
|
||||
@
|
||||
@
|
||||
.text
|
||||
.align 4
|
||||
.syntax unified
|
||||
@/**************************************************************************/
|
||||
@/* */
|
||||
@/* FUNCTION RELEASE */
|
||||
@/* */
|
||||
@/* _tx_thread_stack_build Cortex-M7/AC6 */
|
||||
@/* 6.0.1 */
|
||||
@/* AUTHOR */
|
||||
@/* */
|
||||
@/* William E. Lamie, Microsoft Corporation */
|
||||
@/* */
|
||||
@/* DESCRIPTION */
|
||||
@/* */
|
||||
@/* This function builds a stack frame on the supplied thread's stack. */
|
||||
@/* The stack frame results in a fake interrupt return to the supplied */
|
||||
@/* function pointer. */
|
||||
@/* */
|
||||
@/* INPUT */
|
||||
@/* */
|
||||
@/* thread_ptr Pointer to thread control blk */
|
||||
@/* function_ptr Pointer to return function */
|
||||
@/* */
|
||||
@/* OUTPUT */
|
||||
@/* */
|
||||
@/* None */
|
||||
@/* */
|
||||
@/* CALLS */
|
||||
@/* */
|
||||
@/* None */
|
||||
@/* */
|
||||
@/* CALLED BY */
|
||||
@/* */
|
||||
@/* _tx_thread_create Create thread service */
|
||||
@/* */
|
||||
@/* RELEASE HISTORY */
|
||||
@/* */
|
||||
@/* DATE NAME DESCRIPTION */
|
||||
@/* */
|
||||
@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
|
||||
@/* */
|
||||
@/**************************************************************************/
|
||||
@VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID))
|
||||
@{
|
||||
.global _tx_thread_stack_build
|
||||
.thumb_func
|
||||
_tx_thread_stack_build:
|
||||
@
|
||||
@
|
||||
@ /* Build a fake interrupt frame. The form of the fake interrupt stack
|
||||
@ on the Cortex-M7 should look like the following after it is built:
|
||||
@
|
||||
@ Stack Top:
|
||||
@ LR Interrupted LR (LR at time of PENDSV)
|
||||
@ r4 Initial value for r4
|
||||
@ r5 Initial value for r5
|
||||
@ r6 Initial value for r6
|
||||
@ r7 Initial value for r7
|
||||
@ r8 Initial value for r8
|
||||
@ r9 Initial value for r9
|
||||
@ r10 Initial value for r10
|
||||
@ r11 Initial value for r11
|
||||
@ r0 Initial value for r0 (Hardware stack starts here!!)
|
||||
@ r1 Initial value for r1
|
||||
@ r2 Initial value for r2
|
||||
@ r3 Initial value for r3
|
||||
@ r12 Initial value for r12
|
||||
@ lr Initial value for lr
|
||||
@ pc Initial value for pc
|
||||
@ xPSR Initial value for xPSR
|
||||
@
|
||||
@ Stack Bottom: (higher memory address) */
|
||||
@
|
||||
LDR r2, [r0, #16] @ Pickup end of stack area
|
||||
BIC r2, r2, #0x7 @ Align frame
|
||||
SUB r2, r2, #68 @ Subtract frame size
|
||||
LDR r3, =0xFFFFFFFD @ Build initial LR value
|
||||
STR r3, [r2, #0] @ Save on the stack
|
||||
@
|
||||
@ /* Actually build the stack frame. */
|
||||
@
|
||||
MOV r3, #0 @ Build initial register value
|
||||
STR r3, [r2, #4] @ Store initial r4
|
||||
STR r3, [r2, #8] @ Store initial r5
|
||||
STR r3, [r2, #12] @ Store initial r6
|
||||
STR r3, [r2, #16] @ Store initial r7
|
||||
STR r3, [r2, #20] @ Store initial r8
|
||||
STR r3, [r2, #24] @ Store initial r9
|
||||
STR r3, [r2, #28] @ Store initial r10
|
||||
STR r3, [r2, #32] @ Store initial r11
|
||||
@
|
||||
@ /* Hardware stack follows. */
|
||||
@
|
||||
STR r3, [r2, #36] @ Store initial r0
|
||||
STR r3, [r2, #40] @ Store initial r1
|
||||
STR r3, [r2, #44] @ Store initial r2
|
||||
STR r3, [r2, #48] @ Store initial r3
|
||||
STR r3, [r2, #52] @ Store initial r12
|
||||
MOV r3, #0xFFFFFFFF @ Poison EXC_RETURN value
|
||||
STR r3, [r2, #56] @ Store initial lr
|
||||
STR r1, [r2, #60] @ Store initial pc
|
||||
MOV r3, #0x01000000 @ Only T-bit need be set
|
||||
STR r3, [r2, #64] @ Store initial xPSR
|
||||
@
|
||||
@ /* Setup stack pointer. */
|
||||
@ thread_ptr -> tx_thread_stack_ptr = r2;
|
||||
@
|
||||
STR r2, [r0, #8] @ Save stack pointer in thread's
|
||||
@ control block
|
||||
BX lr @ Return to caller
|
||||
@}
|
||||
|
||||
|
||||
98
ports/cortex_m7/ac6/src/tx_thread_system_return.S
Normal file
98
ports/cortex_m7/ac6/src/tx_thread_system_return.S
Normal file
@@ -0,0 +1,98 @@
|
||||
@/**************************************************************************/
|
||||
@/* */
|
||||
@/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
@/* */
|
||||
@/* This software is licensed under the Microsoft Software License */
|
||||
@/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
@/* and in the root directory of this software. */
|
||||
@/* */
|
||||
@/**************************************************************************/
|
||||
@
|
||||
@
|
||||
@/**************************************************************************/
|
||||
@/**************************************************************************/
|
||||
@/** */
|
||||
@/** ThreadX Component */
|
||||
@/** */
|
||||
@/** Thread */
|
||||
@/** */
|
||||
@/**************************************************************************/
|
||||
@/**************************************************************************/
|
||||
@
|
||||
@/* #define TX_SOURCE_CODE */
|
||||
@
|
||||
@
|
||||
@/* Include necessary system files. */
|
||||
@
|
||||
@/* #include "tx_api.h"
|
||||
@ #include "tx_thread.h"
|
||||
@ #include "tx_timer.h" */
|
||||
|
||||
|
||||
.text 32
|
||||
.align 4
|
||||
.syntax unified
|
||||
@/**************************************************************************/
|
||||
@/* */
|
||||
@/* FUNCTION RELEASE */
|
||||
@/* */
|
||||
@/* _tx_thread_system_return Cortex-M7/AC6 */
|
||||
@/* 6.0.1 */
|
||||
@/* AUTHOR */
|
||||
@/* */
|
||||
@/* William E. Lamie, Microsoft Corporation */
|
||||
@/* */
|
||||
@/* DESCRIPTION */
|
||||
@/* */
|
||||
@/* This function is target processor specific. It is used to transfer */
|
||||
@/* control from a thread back to the ThreadX system. Only a */
|
||||
@/* minimal context is saved since the compiler assumes temp registers */
|
||||
@/* are going to get slicked by a function call anyway. */
|
||||
@/* */
|
||||
@/* INPUT */
|
||||
@/* */
|
||||
@/* None */
|
||||
@/* */
|
||||
@/* OUTPUT */
|
||||
@/* */
|
||||
@/* None */
|
||||
@/* */
|
||||
@/* CALLS */
|
||||
@/* */
|
||||
@/* _tx_thread_schedule Thread scheduling loop */
|
||||
@/* */
|
||||
@/* CALLED BY */
|
||||
@/* */
|
||||
@/* ThreadX components */
|
||||
@/* */
|
||||
@/* RELEASE HISTORY */
|
||||
@/* */
|
||||
@/* DATE NAME DESCRIPTION */
|
||||
@/* */
|
||||
@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
|
||||
@/* */
|
||||
@/**************************************************************************/
|
||||
@/* VOID _tx_thread_system_return(VOID)
|
||||
@{ */
|
||||
.thumb_func
|
||||
.global _tx_thread_system_return
|
||||
_tx_thread_system_return:
|
||||
@
|
||||
@ /* Return to real scheduler via PendSV. Note that this routine is often
|
||||
@ replaced with in-line assembly in tx_port.h to improved performance. */
|
||||
@
|
||||
MOV r0, #0x10000000 @ Load PENDSVSET bit
|
||||
MOV r1, #0xE000E000 @ Load NVIC base
|
||||
STR r0, [r1, #0xD04] @ Set PENDSVBIT in ICSR
|
||||
MRS r0, IPSR @ Pickup IPSR
|
||||
CMP r0, #0 @ Is it a thread returning?
|
||||
BNE _isr_context @ If ISR, skip interrupt enable
|
||||
MRS r1, PRIMASK @ Thread context returning, pickup PRIMASK
|
||||
CPSIE i @ Enable interrupts
|
||||
MSR PRIMASK, r1 @ Restore original interrupt posture
|
||||
_isr_context:
|
||||
BX lr @ Return to caller
|
||||
|
||||
@/* } */
|
||||
|
||||
270
ports/cortex_m7/ac6/src/tx_timer_interrupt.S
Normal file
270
ports/cortex_m7/ac6/src/tx_timer_interrupt.S
Normal file
@@ -0,0 +1,270 @@
|
||||
@/**************************************************************************/
|
||||
@/* */
|
||||
@/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
@/* */
|
||||
@/* This software is licensed under the Microsoft Software License */
|
||||
@/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
@/* and in the root directory of this software. */
|
||||
@/* */
|
||||
@/**************************************************************************/
|
||||
@
|
||||
@
|
||||
@/**************************************************************************/
|
||||
@/**************************************************************************/
|
||||
@/** */
|
||||
@/** ThreadX Component */
|
||||
@/** */
|
||||
@/** Timer */
|
||||
@/** */
|
||||
@/**************************************************************************/
|
||||
@/**************************************************************************/
|
||||
@
|
||||
@#define TX_SOURCE_CODE
|
||||
@
|
||||
@
|
||||
@/* Include necessary system files. */
|
||||
@
|
||||
@#include "tx_api.h"
|
||||
@#include "tx_timer.h"
|
||||
@#include "tx_thread.h"
|
||||
@
|
||||
@
|
||||
@Define Assembly language external references...
|
||||
@
|
||||
.global _tx_timer_time_slice
|
||||
.global _tx_timer_system_clock
|
||||
.global _tx_timer_current_ptr
|
||||
.global _tx_timer_list_start
|
||||
.global _tx_timer_list_end
|
||||
.global _tx_timer_expired_time_slice
|
||||
.global _tx_timer_expired
|
||||
.global _tx_thread_time_slice
|
||||
.global _tx_timer_expiration_process
|
||||
@
|
||||
@
|
||||
.text
|
||||
.align 4
|
||||
.syntax unified
|
||||
@/**************************************************************************/
|
||||
@/* */
|
||||
@/* FUNCTION RELEASE */
|
||||
@/* */
|
||||
@/* _tx_timer_interrupt Cortex-M7/AC6 */
|
||||
@/* 6.0.1 */
|
||||
@/* AUTHOR */
|
||||
@/* */
|
||||
@/* William E. Lamie, Microsoft Corporation */
|
||||
@/* */
|
||||
@/* DESCRIPTION */
|
||||
@/* */
|
||||
@/* This function processes the hardware timer interrupt. This */
|
||||
@/* processing includes incrementing the system clock and checking for */
|
||||
@/* time slice and/or timer expiration. If either is found, the */
|
||||
@/* interrupt context save/restore functions are called along with the */
|
||||
@/* expiration functions. */
|
||||
@/* */
|
||||
@/* INPUT */
|
||||
@/* */
|
||||
@/* None */
|
||||
@/* */
|
||||
@/* OUTPUT */
|
||||
@/* */
|
||||
@/* None */
|
||||
@/* */
|
||||
@/* CALLS */
|
||||
@/* */
|
||||
@/* _tx_timer_expiration_process Timer expiration processing */
|
||||
@/* _tx_thread_time_slice Time slice interrupted thread */
|
||||
@/* */
|
||||
@/* CALLED BY */
|
||||
@/* */
|
||||
@/* interrupt vector */
|
||||
@/* */
|
||||
@/* RELEASE HISTORY */
|
||||
@/* */
|
||||
@/* DATE NAME DESCRIPTION */
|
||||
@/* */
|
||||
@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
|
||||
@/* */
|
||||
@/**************************************************************************/
|
||||
@VOID _tx_timer_interrupt(VOID)
|
||||
@{
|
||||
.global _tx_timer_interrupt
|
||||
.thumb_func
|
||||
_tx_timer_interrupt:
|
||||
@
|
||||
@ /* Upon entry to this routine, it is assumed that context save has already
|
||||
@ been called, and therefore the compiler scratch registers are available
|
||||
@ for use. */
|
||||
@
|
||||
@ /* Increment the system clock. */
|
||||
@ _tx_timer_system_clock++;
|
||||
@
|
||||
LDR r1, =_tx_timer_system_clock @ Pickup address of system clock
|
||||
LDR r0, [r1, #0] @ Pickup system clock
|
||||
ADD r0, r0, #1 @ Increment system clock
|
||||
STR r0, [r1, #0] @ Store new system clock
|
||||
@
|
||||
@ /* Test for time-slice expiration. */
|
||||
@ if (_tx_timer_time_slice)
|
||||
@ {
|
||||
@
|
||||
LDR r3, =_tx_timer_time_slice @ Pickup address of time-slice
|
||||
LDR r2, [r3, #0] @ Pickup time-slice
|
||||
CMP r2, #0 @ Is it non-active?
|
||||
BEQ __tx_timer_no_time_slice @ Yes, skip time-slice processing
|
||||
@
|
||||
@ /* Decrement the time_slice. */
|
||||
@ _tx_timer_time_slice--;
|
||||
@
|
||||
SUB r2, r2, #1 @ Decrement the time-slice
|
||||
STR r2, [r3, #0] @ Store new time-slice value
|
||||
@
|
||||
@ /* Check for expiration. */
|
||||
@ if (__tx_timer_time_slice == 0)
|
||||
@
|
||||
CMP r2, #0 @ Has it expired?
|
||||
BNE __tx_timer_no_time_slice @ No, skip expiration processing
|
||||
@
|
||||
@ /* Set the time-slice expired flag. */
|
||||
@ _tx_timer_expired_time_slice = TX_TRUE;
|
||||
@
|
||||
LDR r3, =_tx_timer_expired_time_slice @ Pickup address of expired flag
|
||||
MOV r0, #1 @ Build expired value
|
||||
STR r0, [r3, #0] @ Set time-slice expiration flag
|
||||
@
|
||||
@ }
|
||||
@
|
||||
__tx_timer_no_time_slice:
|
||||
@
|
||||
@ /* Test for timer expiration. */
|
||||
@ if (*_tx_timer_current_ptr)
|
||||
@ {
|
||||
@
|
||||
LDR r1, =_tx_timer_current_ptr @ Pickup current timer pointer address
|
||||
LDR r0, [r1, #0] @ Pickup current timer
|
||||
LDR r2, [r0, #0] @ Pickup timer list entry
|
||||
CMP r2, #0 @ Is there anything in the list?
|
||||
BEQ __tx_timer_no_timer @ No, just increment the timer
|
||||
@
|
||||
@ /* Set expiration flag. */
|
||||
@ _tx_timer_expired = TX_TRUE;
|
||||
@
|
||||
LDR r3, =_tx_timer_expired @ Pickup expiration flag address
|
||||
MOV r2, #1 @ Build expired value
|
||||
STR r2, [r3, #0] @ Set expired flag
|
||||
B __tx_timer_done @ Finished timer processing
|
||||
@
|
||||
@ }
|
||||
@ else
|
||||
@ {
|
||||
__tx_timer_no_timer:
|
||||
@
|
||||
@ /* No timer expired, increment the timer pointer. */
|
||||
@ _tx_timer_current_ptr++;
|
||||
@
|
||||
ADD r0, r0, #4 @ Move to next timer
|
||||
@
|
||||
@ /* Check for wrap-around. */
|
||||
@ if (_tx_timer_current_ptr == _tx_timer_list_end)
|
||||
@
|
||||
LDR r3, =_tx_timer_list_end @ Pickup addr of timer list end
|
||||
LDR r2, [r3, #0] @ Pickup list end
|
||||
CMP r0, r2 @ Are we at list end?
|
||||
BNE __tx_timer_skip_wrap @ No, skip wrap-around logic
|
||||
@
|
||||
@ /* Wrap to beginning of list. */
|
||||
@ _tx_timer_current_ptr = _tx_timer_list_start;
|
||||
@
|
||||
LDR r3, =_tx_timer_list_start @ Pickup addr of timer list start
|
||||
LDR r0, [r3, #0] @ Set current pointer to list start
|
||||
@
|
||||
__tx_timer_skip_wrap:
|
||||
@
|
||||
STR r0, [r1, #0] @ Store new current timer pointer
|
||||
@ }
|
||||
@
|
||||
__tx_timer_done:
|
||||
@
|
||||
@
|
||||
@ /* See if anything has expired. */
|
||||
@ if ((_tx_timer_expired_time_slice) || (_tx_timer_expired))
|
||||
@ {
|
||||
@
|
||||
LDR r3, =_tx_timer_expired_time_slice @ Pickup addr of expired flag
|
||||
LDR r2, [r3, #0] @ Pickup time-slice expired flag
|
||||
CMP r2, #0 @ Did a time-slice expire?
|
||||
BNE __tx_something_expired @ If non-zero, time-slice expired
|
||||
LDR r1, =_tx_timer_expired @ Pickup addr of other expired flag
|
||||
LDR r0, [r1, #0] @ Pickup timer expired flag
|
||||
CMP r0, #0 @ Did a timer expire?
|
||||
BEQ __tx_timer_nothing_expired @ No, nothing expired
|
||||
@
|
||||
__tx_something_expired:
|
||||
@
|
||||
@
|
||||
STMDB sp!, {r0, lr} @ Save the lr register on the stack
|
||||
@ and save r0 just to keep 8-byte alignment
|
||||
@
|
||||
@ /* Did a timer expire? */
|
||||
@ if (_tx_timer_expired)
|
||||
@ {
|
||||
@
|
||||
LDR r1, =_tx_timer_expired @ Pickup addr of expired flag
|
||||
LDR r0, [r1, #0] @ Pickup timer expired flag
|
||||
CMP r0, #0 @ Check for timer expiration
|
||||
BEQ __tx_timer_dont_activate @ If not set, skip timer activation
|
||||
@
|
||||
@ /* Process timer expiration. */
|
||||
@ _tx_timer_expiration_process();
|
||||
@
|
||||
BL _tx_timer_expiration_process @ Call the timer expiration handling routine
|
||||
@
|
||||
@ }
|
||||
__tx_timer_dont_activate:
|
||||
@
|
||||
@ /* Did time slice expire? */
|
||||
@ if (_tx_timer_expired_time_slice)
|
||||
@ {
|
||||
@
|
||||
LDR r3, =_tx_timer_expired_time_slice @ Pickup addr of time-slice expired
|
||||
LDR r2, [r3, #0] @ Pickup the actual flag
|
||||
CMP r2, #0 @ See if the flag is set
|
||||
BEQ __tx_timer_not_ts_expiration @ No, skip time-slice processing
|
||||
@
|
||||
@ /* Time slice interrupted thread. */
|
||||
@ _tx_thread_time_slice();
|
||||
@
|
||||
BL _tx_thread_time_slice @ Call time-slice processing
|
||||
LDR r0, =_tx_thread_preempt_disable @ Build address of preempt disable flag
|
||||
LDR r1, [r0] @ Is the preempt disable flag set?
|
||||
CBNZ r1, __tx_timer_skip_time_slice @ Yes, skip the PendSV logic
|
||||
LDR r0, =_tx_thread_current_ptr @ Build current thread pointer address
|
||||
LDR r1, [r0] @ Pickup the current thread pointer
|
||||
LDR r2, =_tx_thread_execute_ptr @ Build execute thread pointer address
|
||||
LDR r3, [r2] @ Pickup the execute thread pointer
|
||||
LDR r0, =0xE000ED04 @ Build address of control register
|
||||
LDR r2, =0x10000000 @ Build value for PendSV bit
|
||||
CMP r1, r3 @ Are they the same?
|
||||
BEQ __tx_timer_skip_time_slice @ If the same, there was no time-slice performed
|
||||
STR r2, [r0] @ Not the same, issue the PendSV for preemption
|
||||
__tx_timer_skip_time_slice:
|
||||
@
|
||||
@ }
|
||||
@
|
||||
__tx_timer_not_ts_expiration:
|
||||
@
|
||||
LDMIA sp!, {r0, lr} @ Recover lr register (r0 is just there for
|
||||
@ the 8-byte stack alignment
|
||||
@
|
||||
@ }
|
||||
@
|
||||
__tx_timer_nothing_expired:
|
||||
|
||||
DSB @ Complete all memory access
|
||||
BX lr @ Return to caller
|
||||
@
|
||||
@}
|
||||
|
||||
|
||||
Reference in New Issue
Block a user