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add SMP, Modules, and more processor/tools releases

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This commit is contained in:
Scott Larson
2020-08-07 16:56:45 -07:00
parent 49e3c27f3f
commit 6f61053f2a
1858 changed files with 617131 additions and 4 deletions
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313
ports_smp/arc_hs_smp/metaware/src/tx_thread_context_restore.s Normal file
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;/**************************************************************************/
;/* */
;/* Copyright (c) Microsoft Corporation. All rights reserved. */
;/* */
;/* This software is licensed under the Microsoft Software License */
;/* Terms for Microsoft Azure RTOS. Full text of the license can be */
;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
;/* and in the root directory of this software. */
;/* */
;/**************************************************************************/
;
;
;/**************************************************************************/
;/**************************************************************************/
;/** */
;/** ThreadX Component */
;/** */
;/** Thread */
;/** */
;/**************************************************************************/
;/**************************************************************************/
;
;
;#define TX_SOURCE_CODE
;
.equ BTA, 0x412
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_thread.h"
;#include "tx_timer.h"
;
;
;/**************************************************************************/
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_context_restore SMP/ARC_HS/MetaWare */
;/* 6.0.1 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
;/* */
;/* DESCRIPTION */
;/* */
;/* This function restores the interrupt context if it is processing a */
;/* nested interrupt. If not, it returns to the interrupt thread if no */
;/* preemption is necessary. Otherwise, if preemption is necessary or */
;/* if no thread was running, the function returns to the scheduler. */
;/* */
;/* INPUT */
;/* */
;/* None */
;/* */
;/* OUTPUT */
;/* */
;/* None */
;/* */
;/* CALLS */
;/* */
;/* _tx_thread_schedule Thread scheduling routine */
;/* */
;/* CALLED BY */
;/* */
;/* ISRs Interrupt Service Routines */
;/* */
;/* RELEASE HISTORY */
;/* */
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* */
;/**************************************************************************/
;VOID _tx_thread_context_restore(VOID)
;{
.global _tx_thread_context_restore
.type _tx_thread_context_restore, @function
_tx_thread_context_restore:
;
; /* Note: it is assumed that the stack pointer is in the same position now as
; it was after the last context save call. */
;
; /* Lockout interrupts. */
;
clri ; Disable interrupts
nop ; Delay for interrupts to really be disabled
.ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
;
; /* Call the ISR exit function to indicate an ISR is complete. */
;
bl.d _tx_execution_isr_exit ; Call the ISR exit function
sub sp, sp, 16 ; ..allocating some space on the stack
add sp, sp, 16 ; Recover the stack space
.endif
;
; /* Determine if interrupts are nested. */
; if (--_tx_thread_system_state)
; {
;
lr r3, [IDENTITY] ; Pickup core ID
xbfu r3, r3, 8, 8 ; Shift down and isolate core ID
.ifndef TX_ZERO_BASED_CORE_ID
sub r3, r3, 1 ; Subtract 1 to make 0-based
.endif
asl r3, r3, 2 ; Build index into core arrays
mov r0, _tx_thread_system_state ; Build address of system state
add r1, r0, r3 ;
ld r0, [r1] ; Pickup system state
sub r0, r0, 1 ; Decrement the system state
st r0, [r1] ; Store the new system state
breq r0, 0, __tx_thread_not_nested_restore ; If zero, not a nested interrupt
;
; /* Interrupts are nested. */
;
; /* Just recover the saved registers and return to the point of
; interrupt. */
;
__tx_thread_nested_restore:
.ifndef TX_DISABLE_LP
ld r0, [sp, 4] ; Recover LP_START
sr r0, [LP_START] ; Restore LP_START
ld r4, [sp, 8] ; Recover LP_END
sr r4, [LP_END] ; Restore LP_END
ld r2, [sp, 12] ; Recover LP_COUNT
mov LP_COUNT, r2
.endif
ld r2, [sp, 156] ; Pickup BTA
sr r2, [BTA] ; Recover BTA
.ifdef TX_ENABLE_ACC
ld r58, [sp, 140] ; Recover r58
ld r59, [sp, 144] ; Recover r59
.endif
ld blink, [sp, 16] ; Recover blink
ld r12, [sp, 84] ; Recover r12
ld r11, [sp, 88] ; Recover r11
ld r10, [sp, 92] ; Recover r10
ld r9, [sp, 96] ; Recover r9
ld r8, [sp, 100] ; Recover r8
ld r7, [sp, 104] ; Recover r7
ld r6, [sp, 108] ; Recover r6
ld r5, [sp, 112] ; Recover r5
ld r4, [sp, 116] ; Recover r4
ld r3, [sp, 120] ; Recover r3
ld r2, [sp, 124] ; Recover r2
ld r1, [sp, 128] ; Recover r1
ld r0, [sp, 132] ; Recover r0
add sp, sp, 160 ; Recover interrupt stack frame
rtie ; Return from interrupt
;
;
; }
__tx_thread_not_nested_restore:
;
; /* Determine if a thread was interrupted and no preemption is required. */
; else if (((_tx_thread_current_ptr[core]) && (_tx_thread_current_ptr[core] == _tx_thread_execute_ptr[core])
; || (_tx_thread_preempt_disable))
; {
;
mov r1, _tx_thread_current_ptr ; Build current thread pointer address
add r1, r1, r3 ;
ld r0, [r1] ; Pickup current thread pointer
mov r2, _tx_thread_smp_protection ; Build protection address
sub.f 0, r0, 0 ; Set condition codes
beq.d __tx_thread_idle_system_restore ; If NULL, idle system was interrupted
lr r4, [AUX_IRQ_ACT] ; Pickup the interrupt active register
neg r5, r4 ; Negate
and r5, r4, r5 ; See if there are any other interrupts present
brne r4, r5, __tx_thread_no_preempt_restore ; If more interrupts, just return to the point of interrupt
mov r4, _tx_thread_execute_ptr ; Build address of next thread to execute for this core
add r4, r4, r3 ;
ld r4, [r4] ; Pickup next thread to execute
ld r2, [r2, 8] ; Pickup core that has protection
breq r0, r4, __tx_thread_no_preempt_restore ; If equal, simply restore executing thread
ld r5, [gp, _tx_thread_preempt_disable@sda] ; Pickup preempt disable flag
asr r4, r3, 2 ; Shift core index back down for core ID
brne r2, r4, __tx_thread_preempt_restore ; If the core doesn't have protection, preempt thread without looking at preempt disable flag
breq r5, 0, __tx_thread_preempt_restore ; If preempt disable not set, preempt executing thread
;
;
__tx_thread_no_preempt_restore:
;
; /* Restore interrupted thread or ISR. */
;
; /* Pickup the saved stack pointer. */
; sp = _tx_thread_current_ptr[core] -> tx_thread_stack_ptr;
;
; /* Recover the saved context and return to the point of interrupt. */
;
ld sp, [r0, 8] ; Switch back to thread's stack
.ifndef TX_DISABLE_LP
ld r0, [sp, 4] ; Recover LP_START
sr r0, [LP_START] ; Restore LP_START
ld r4, [sp, 8] ; Recover LP_END
sr r4, [LP_END] ; Restore LP_END
ld r2, [sp, 12] ; Recover LP_COUNT
mov LP_COUNT, r2
.endif
ld r2, [sp, 156] ; Pickup BTA
sr r2, [BTA] ; Recover BTA
.ifdef TX_ENABLE_ACC
ld r58, [sp, 140] ; Recover r58
ld r59, [sp, 144] ; Recover r59
.endif
ld blink, [sp, 16] ; Recover blink
ld r12, [sp, 84] ; Recover r12
ld r11, [sp, 88] ; Recover r11
ld r10, [sp, 92] ; Recover r10
ld r9, [sp, 96] ; Recover r9
ld r8, [sp, 100] ; Recover r8
ld r7, [sp, 104] ; Recover r7
ld r6, [sp, 108] ; Recover r6
ld r5, [sp, 112] ; Recover r5
ld r4, [sp, 116] ; Recover r4
ld r3, [sp, 120] ; Recover r3
ld r2, [sp, 124] ; Recover r2
ld r1, [sp, 128] ; Recover r1
ld r0, [sp, 132] ; Recover r0
add sp, sp, 160 ; Recover interrupt stack frame
rtie ; Return from interrupt
;
; }
; else
; {
__tx_thread_preempt_restore:
;
ld r7, [r0, 8] ; Pickup stack pointer
mov r6, 1 ; Build interrupt stack type
st r6, [r7, 0] ; Setup interrupt stack type
st fp, [r7, 24] ; Save fp
st gp, [r7, 28] ; Save gp
st r25, [r7, 32] ; Save r25
st r24, [r7, 36] ; Save r24
st r23, [r7, 40] ; Save r23
st r22, [r7, 44] ; Save r22
st r21, [r7, 48] ; Save r21
st r20, [r7, 52] ; Save r20
st r19, [r7, 56] ; Save r19
st r18, [r7, 60] ; Save r18
st r17, [r7, 64] ; Save r17
st r16, [r7, 68] ; Save r16
st r15, [r7, 72] ; Save r15
st r14, [r7, 76] ; Save r14
st r13, [r7, 80] ; Save r13
st r30, [r7, 136] ; Save r30
__tx_preempt_save_done:
;
; /* Save the remaining time-slice and disable it. */
; if (_tx_timer_time_slice)
; {
;
mov r5, _tx_timer_time_slice ; Build time-slice address
add r5, r5, r3 ;
ld r2, [r5] ; Pickup time-slice contents
mov r7, 0 ; Build clear/NULL value
breq r2, 0, __tx_thread_dont_save_ts ; No time-slice, don't need to save it
;
; _tx_thread_current_ptr[core] -> tx_thread_time_slice = _tx_timer_time_slice[core];
; _tx_timer_time_slice = 0;
;
st r2, [r0, 24] ; If set, save remaining time-slice
st r7, [r5] ; If set, clear time slice
;
; }
__tx_thread_dont_save_ts:
;
;
; /* Clear the current thread pointer. */
; _tx_thread_current_ptr[core] = TX_NULL;
;
st r7, [r1] ; Set current thread ptr to NULL
;
; /* Set bit indicating this thread is ready for execution. */
;
dmb 3 ; Data memory barrier
st 1, [r0, 164] ; Set ready bit
sub sp, sp, 8 ; Allocate a small stack frame on the system stack
lr r0, [STATUS32] ; Pickup STATUS32
st r0, [sp, 4] ; Place on stack
mov r0, _tx_thread_schedule ; Build address of scheduler
st r0, [sp, 0] ; Write over the point of interrupt
rtie ; Return from interrupt to scheduler
;
; }
;
; /* Return to the scheduler. */
; _tx_thread_schedule();
;
__tx_thread_idle_system_restore:
lr r4, [AUX_IRQ_ACT] ; Pickup the interrupt active register
neg r5, r4 ; Negate
and r5, r4, r5 ; See if there are any other interrupts present
sub.f 0, r4, r5 ; Set condition codes
bne __tx_thread_nested_restore ; If more interrupts, just return to the point of interrupt
lr r0, [STATUS32] ; Pickup STATUS32
st r0, [sp, 4] ; Place on stack
mov r0, _tx_thread_schedule ; Build address of scheduler
st r0, [sp, 0] ; Write over the point of interrupt
rtie ; Return from interrupt to scheduler
;
;}
.end

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ports_smp/arc_hs_smp/metaware/src/tx_thread_context_save.s Normal file
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;/**************************************************************************/
;/* */
;/* Copyright (c) Microsoft Corporation. All rights reserved. */
;/* */
;/* This software is licensed under the Microsoft Software License */
;/* Terms for Microsoft Azure RTOS. Full text of the license can be */
;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
;/* and in the root directory of this software. */
;/* */
;/**************************************************************************/
;
;
;/**************************************************************************/
;/**************************************************************************/
;/** */
;/** ThreadX Component */
;/** */
;/** Thread */
;/** */
;/**************************************************************************/
;/**************************************************************************/
;
;
;#define TX_SOURCE_CODE
;
.equ BTA, 0x412
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_thread.h"
;#include "tx_timer.h"
;
;
;/**************************************************************************/
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_context_save SMP/ARC_HS/MetaWare */
;/* 6.0.1 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
;/* */
;/* DESCRIPTION */
;/* */
;/* This function saves the context of an executing thread in the */
;/* beginning of interrupt processing. The function also ensures that */
;/* the system stack is used upon return to the calling ISR. */
;/* */
;/* INPUT */
;/* */
;/* None */
;/* */
;/* OUTPUT */
;/* */
;/* None */
;/* */
;/* CALLS */
;/* */
;/* None */
;/* */
;/* CALLED BY */
;/* */
;/* ISRs */
;/* */
;/* RELEASE HISTORY */
;/* */
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* */
;/**************************************************************************/
;VOID _tx_thread_context_save(VOID)
;{
.global _tx_thread_context_save
.type _tx_thread_context_save, @function
_tx_thread_context_save:
;
; /* Upon entry to this routine, it is assumed that an interrupt stack frame
; has already been allocated, and the interrupted blink register is already saved. */
;
clri ; Disable interrupts
st r1, [sp, 128] ; Save r1
st r0, [sp, 132] ; Save r0
st r3, [sp, 120] ; Save r3
st r2, [sp, 124] ; Save r2
;
; /* Check for a nested interrupt condition. */
; if (_tx_thread_system_state++)
; {
;
lr r3, [IDENTITY] ; Pickup core ID
xbfu r3, r3, 8, 8 ; Shift down and isolate core ID
.ifndef TX_ZERO_BASED_CORE_ID
sub r3, r3, 1 ; Subtract 1 to make 0-based
.endif
asl r3, r3, 2 ; Build index into core arrays
mov r0, _tx_thread_system_state ; Build address of system state
add r1, r0, r3 ;
ld r0, [r1] ; Pickup system state
breq r0, 0, __tx_thread_not_nested_save ; If 0, we are not in a nested
; condition
;
; /* Nested interrupt condition. */
;
add r0, r0, 1 ; Increment the nested interrupt count
st r0, [r1] ; Update system state
;
; /* Save the rest of the scratch registers on the stack and return to the
; calling ISR. */
;
__tx_thread_nested_save: ; Label is for special nested interrupt case from idle system save below
st r12, [sp, 84] ; Save r12
st r11, [sp, 88] ; Save r11
st r10, [sp, 92] ; Save r10
st r9, [sp, 96] ; Save r9
st r8, [sp, 100] ; Save r8
st r7, [sp, 104] ; Save r7
st r6, [sp, 108] ; Save r6
st r5, [sp, 112] ; Save r5
st r4, [sp, 116] ; Save r6
lr r10, [LP_START] ; Pickup LP_START
lr r9, [LP_END] ; Pickup LP_END
st LP_COUNT, [sp, 12] ; Save LP_COUNT
st r10, [sp, 4] ; Save LP_START
st r9, [sp, 8] ; Save LP_END
.ifdef TX_ENABLE_ACC
st r58, [sp, 140] ; Save r58
st r59, [sp, 144] ; Save r59
.endif
lr r0, [BTA] ; Pickup BTA
st r0, [sp, 156] ; Save BTA
;
; /* Return to the ISR. */
;
.ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
;
; /* Call the ISR enter function to indicate an ISR is executing. */
;
sub sp, sp, 32 ; Allocating some space on the stack
st blink, [sp, 16] ; Save blink
bl.d _tx_execution_isr_enter ; Call the ISR enter function
nop ; Delay slot
ld blink, [sp, 16] ; Recover blink
add sp, sp, 32 ; Recover the stack space
.endif
;
j.d [blink] ; Return to Level 1 ISR
st ilink, [sp, 20] ; Save ilink
;
__tx_thread_not_nested_save:
; }
;
; /* Otherwise, not nested, check to see if a thread was running. */
; else if (_tx_thread_current_ptr[core])
; {
;
add r0, r0, 1 ; Increment the nested interrupt count
st r0, [r1] ; Update system state
mov r2, _tx_thread_current_ptr ; Build address of current thread pointer
add r2, r2, r3 ;
ld r1, [r2] ; Pickup current thread pointer
st r12, [sp, 84] ; Save r12
st r11, [sp, 88] ; Save r11
breq r1, 0, __tx_thread_idle_system_save ; If no thread is running, idle system was
; interrupted.
;
; /* Save minimal context of interrupted thread. */
;
st r10, [sp, 92] ; Save r10
st r9, [sp, 96] ; Save r9
st r8, [sp, 100] ; Save r8
st r7, [sp, 104] ; Save r7
st r6, [sp, 108] ; Save r6
st r5, [sp, 112] ; Save r5
st r4, [sp, 116] ; Save r4
lr r10, [LP_START] ; Pickup LP_START
lr r9, [LP_END] ; Pickup LP_END
st LP_COUNT, [sp, 12] ; Save LP_COUNT
st r10, [sp, 4] ; Save LP_START
st r9, [sp, 8] ; Save LP_END
st ilink, [sp, 20] ; Save ilink
.ifdef TX_ENABLE_ACC
st r58, [sp, 140] ; Save r58
st r59, [sp, 144] ; Save r59
.endif
lr r0, [BTA] ; Pickup BTA
st r0, [sp, 156] ; Save BTA
;
; /* Save the current stack pointer in the thread's control block. */
; _tx_thread_current_ptr[core] -> tx_thread_stack_ptr = sp;
;
st sp, [r1, 8] ; Save thread's stack pointer
.ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
;
; /* Call the ISR enter function to indicate an ISR is executing. */
;
sub sp, sp, 32 ; Allocating some space on the stack
st blink, [sp, 16] ; Save blink
bl.d _tx_execution_isr_enter ; Call the ISR enter function
nop ; Delay slot
ld blink, [sp, 16] ; Recover blink
add sp, sp, 32 ; Recover the stack space
.endif
;
; /* Switch to the system stack. */
; sp = _tx_thread_system_stack_ptr[core];
;
mov r1, _tx_thread_system_stack_ptr ; Build address of system stack pointer
add r1, r1, r3 ;
j_s.d [blink] ; Return to calling ISR
ld sp, [r1] ; Switch to system stack
;
; }
; else
; {
;
__tx_thread_idle_system_save:
;
; /* Interrupt occurred in the scheduling loop. */
;
.ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
;
; /* Call the ISR enter function to indicate an ISR is executing. */
;
sub sp, sp, 32 ; Allocating some space on the stack
st blink, [sp, 16] ; Save blink
bl.d _tx_execution_isr_enter ; Call the ISR enter function
nop ; Delay slot
ld blink, [sp, 16] ; Recover blink
add sp, sp, 32 ; Recover the stack space
.endif
;
; /* See if we have a special nesting condition. This happens when the higher priority
; interrupt occurs before the nested interrupt logic is valid. */
;
lr r0, [AUX_IRQ_ACT] ; Pickup the interrupt active register
neg r1, r0 ; Negate
and r1, r0, r1 ; See if there are any other interrupts present
brne r0, r1, __tx_thread_nested_save ; If more interrupts, go into the nested interrupt save logic
;
; /* Not much to do here, just adjust the stack pointer, and return to
; ISR processing. */
;
j_s.d [blink] ; Return to ISR
add sp, sp, 160 ; Recover stack space
;
; }
;}
.end

87
ports_smp/arc_hs_smp/metaware/src/tx_thread_interrupt_control.s Normal file
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;/**************************************************************************/
;/* */
;/* Copyright (c) Microsoft Corporation. All rights reserved. */
;/* */
;/* This software is licensed under the Microsoft Software License */
;/* Terms for Microsoft Azure RTOS. Full text of the license can be */
;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
;/* and in the root directory of this software. */
;/* */
;/**************************************************************************/
;
;
;/**************************************************************************/
;/**************************************************************************/
;/** */
;/** ThreadX Component */
;/** */
;/** Thread */
;/** */
;/**************************************************************************/
;/**************************************************************************/
;
;#define TX_SOURCE_CODE
;
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_thread.h"
;
;
;/**************************************************************************/
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_interrupt_control SMP/ARC_HS/MetaWare */
;/* 6.0.1 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
;/* */
;/* DESCRIPTION */
;/* */
;/* This function is responsible for changing the interrupt lockout */
;/* posture of the system. */
;/* */
;/* INPUT */
;/* */
;/* new_posture New interrupt lockout posture */
;/* */
;/* OUTPUT */
;/* */
;/* old_posture Old interrupt lockout posture */
;/* */
;/* CALLS */
;/* */
;/* None */
;/* */
;/* CALLED BY */
;/* */
;/* Application Code */
;/* */
;/* RELEASE HISTORY */
;/* */
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* */
;/**************************************************************************/
;UINT _tx_thread_interrupt_control(UINT new_posture)
;{
.global _tx_thread_interrupt_control
.type _tx_thread_interrupt_control, @function
_tx_thread_interrupt_control:
;
; /* Pickup current interrupt lockout posture. */
;
clri r1 ; Get current interrupt state
;
; /* Apply the new interrupt posture. */
;
seti r0 ; Set desired interrupt state
j_s.d [blink] ; Return to caller with delay slot
mov r0, r1 ; Return previous mask value. Return value is TX_INT_DISABLE or TX_INT_ENABLE.
;
;}
.end

297
ports_smp/arc_hs_smp/metaware/src/tx_thread_schedule.s Normal file
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;/**************************************************************************/
;/* */
;/* Copyright (c) Microsoft Corporation. All rights reserved. */
;/* */
;/* This software is licensed under the Microsoft Software License */
;/* Terms for Microsoft Azure RTOS. Full text of the license can be */
;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
;/* and in the root directory of this software. */
;/* */
;/**************************************************************************/
;
;
;/**************************************************************************/
;/**************************************************************************/
;/** */
;/** ThreadX Component */
;/** */
;/** Thread */
;/** */
;/**************************************************************************/
;/**************************************************************************/
;
;
;#define TX_SOURCE_CODE
;
;
.equ BTA, 0x412
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_thread.h"
;#include "tx_timer.h"
;
;
; /* Define the lock for the ARC simulator workaround. The ARC HS SMP
; simulator does not execute cores in a lock-step fashion, i.e., a
; core can stall for many cycles while the other core executes. This
; does not happen on actual hardware and thus the need for a schedule
; lock is not required since: 1) ThreadX SMP will not load the same
; thread into two places on the _tx_thread_execute_list, and moving
; a thread from one entry on the _tx_thread_execute_list to another
; is more than the 5 instructions executed between examination of the
; the _tx_thread_execute_list thread and clearing its ready bit in
; preparation for scheduling. */
;
.ifdef TX_ARC_SIMULATOR_WORKAROUND
.globl _tx_thread_schedule_lock
.size _tx_thread_schedule_lock, 4
.type _tx_thread_schedule_lock,@object
_tx_thread_schedule_lock:
.word 0
.endif
;
;
;/**************************************************************************/
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_schedule SMP/ARC_HS/MetaWare */
;/* 6.0.1 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
;/* */
;/* DESCRIPTION */
;/* */
;/* This function waits for a thread control block pointer to appear in */
;/* the _tx_thread_execute_ptr array. Once a thread pointer appears */
;/* in the variable, the corresponding thread is resumed. */
;/* */
;/* INPUT */
;/* */
;/* None */
;/* */
;/* OUTPUT */
;/* */
;/* None */
;/* */
;/* CALLS */
;/* */
;/* None */
;/* */
;/* CALLED BY */
;/* */
;/* _tx_initialize_kernel_enter ThreadX entry function */
;/* _tx_thread_system_return Return to system from thread */
;/* _tx_thread_context_restore Restore thread's context */
;/* */
;/* RELEASE HISTORY */
;/* */
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* */
;/**************************************************************************/
;VOID _tx_thread_schedule(VOID)
;{
.global _tx_thread_schedule_restart
_tx_thread_schedule_restart:
.ifdef TX_ARC_SIMULATOR_WORKAROUND
mov r7, _tx_thread_schedule_lock
dmb 3
mov r3, 0
st r3, [r7]
dmb 3
.endif
.global _tx_thread_schedule
.type _tx_thread_schedule, @function
_tx_thread_schedule:
;
;
; /* Enable interrupts. */
;
mov r0, 0x1F ; Build enable interrupt value
seti r0 ; Enable interrupts
;
; /* Wait for a thread to execute. */
; do
; {
;
lr r1, [IDENTITY] ; Pickup core ID
xbfu r1, r1, 8, 8 ; Shift down and isolate core ID
.ifndef TX_ZERO_BASED_CORE_ID
sub r1, r1, 1 ; Subtract 1 to make 0-based
.endif
asl r4, r1, 2 ; Build index into core arrays
mov r7, _tx_thread_execute_ptr ; Pickup base of the execute thread pointer
add r7, r7, r4 ; Build address of current thread pointer
__tx_thread_schedule_loop:
;
clri ; Lockout interrupts
nop ; Delay for interrupts to really be disabled
.ifdef TX_ARC_SIMULATOR_WORKAROUND
mov r0, _tx_thread_schedule_lock
llock r5, [r0]
breq r5, 0, _continue
b _tx_thread_schedule
_continue:
add r5, r1, 1
scond r5, [r0]
beq_s _got_lock
b _tx_thread_schedule
_got_lock:
.endif
ld r0, [r7] ; Pickup next thread to execute
breq r0, 0, _tx_thread_schedule_restart ; If NULL, keep looking
;
; }
; while(_tx_thread_execute_ptr[core] == TX_NULL);
;
;
; /* Now make sure the thread's ready bit is set. */
;
ld r5, [r0, 164] ; Pickup the ready bit for this thread to see if it can be executed
breq r5, 0, _tx_thread_schedule_restart ; If not set, start over
st 0, [r0, 164] ; Clear the ready bit now that this thread is being executed
dmb 3 ; Data memory barrier
.ifdef TX_ARC_SIMULATOR_WORKAROUND
mov r7, _tx_thread_schedule_lock
dmb 3
mov r3, 0
st r3, [r7]
dmb 3
.endif
;
; /* Yes! We have a thread to execute - transfer control to it. */
;
; /* Setup the current thread pointer. */
; _tx_thread_current_ptr[core] = _tx_thread_execute_ptr[core];
;
mov r7, _tx_thread_current_ptr ; Build address of current thread pointer
add r7, r7, r4 ;
st r0, [r7] ; Setup current thread pointer
;
; /* Increment the run count for this thread. */
; _tx_thread_current_ptr[core] -> tx_thread_run_count++;
;
ld r3, [r0, 4] ; Pickup run counter
ld r5, [r0, 24] ; Pickup time-slice for this thread
add r3, r3, 1 ; Increment run counter
st r3, [r0, 4] ; Store the new run counter
;
; /* Setup time-slice, if present. */
; _tx_timer_time_slice[core] = _tx_thread_current_ptr -> tx_thread_time_slice;
;
mov r6, _tx_timer_time_slice ; Build address of time-slice for this core
add r6, r6, r4 ;
st r5, [r6] ; Setup time-slice
;
.ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
;
; /* Call the thread entry function to indicate the thread is executing. */
;
mov r13, r0 ; Save thread control block pointer
bl.d _tx_execution_thread_enter ; Call the thread execution enter function
sub sp, sp, 16 ; ..allocating some space on the stack
add sp, sp, 16 ; Recover the stack space
mov r0, r13 ; Recover thread control block pointer
.endif
;
; /* Switch to the thread's stack. */
; sp = _tx_thread_execute_ptr[core] -> tx_thread_stack_ptr;
;
ld sp, [r0, 8] ; Switch to thread's stack
;
; /* Determine if an interrupt frame or a synchronous task suspension frame
; is present. */
;
ld r1, [sp, 0] ; Pickup the stack type
brne r1, 0, __tx_thread_schedule_int_ret ; Compare to solicited stack type. If not, thread was interrupted
ld blink, [sp, 4] ; Recover blink
ld fp, [sp, 8] ; Recover fp
ld gp, [sp, 12] ; Recover gp
ld r25, [sp, 16] ; Recover r25
ld r24, [sp, 20] ; Recover r24
ld r23, [sp, 24] ; Recover r23
ld r22, [sp, 28] ; Recover r22
ld r21, [sp, 32] ; Recover r21
ld r20, [sp, 36] ; Recover r20
ld r19, [sp, 40] ; Recover r19
ld r18, [sp, 44] ; Recover r18
ld r17, [sp, 48] ; Recover r17
ld r16, [sp, 52] ; Recover r16
ld r15, [sp, 56] ; Recover r15
ld r14, [sp, 60] ; Recover r14
ld r13, [sp, 64] ; Recover r13
ld r1, [sp, 68] ; Pickup status32
ld r30, [sp, 72] ; Recover r30
add sp, sp, 76 ; Recover solicited stack frame
j_s.d [blink] ; Return to thread and restore flags
seti r1 ; Recover STATUS32
;
__tx_thread_schedule_int_ret:
;
mov r0, 0x2 ; Pretend level 1 interrupt is returning
sr r0, [AUX_IRQ_ACT] ;
.ifndef TX_DISABLE_LP
ld r0, [sp, 4] ; Recover LP_START
sr r0, [LP_START] ; Restore LP_START
ld r1, [sp, 8] ; Recover LP_END
sr r1, [LP_END] ; Restore LP_END
ld r2, [sp, 12] ; Recover LP_COUNT
mov LP_COUNT, r2
.endif
ld r0, [sp, 156] ; Pickup saved BTA
sr r0, [BTA] ; Recover BTA
ld blink, [sp, 16] ; Recover blink
ld ilink, [sp, 20] ; Recover ilink
ld fp, [sp, 24] ; Recover fp
ld gp, [sp, 28] ; Recover gp
ld r25, [sp, 32] ; Recover r25
ld r24, [sp, 36] ; Recover r24
ld r23, [sp, 40] ; Recover r23
ld r22, [sp, 44] ; Recover r22
ld r21, [sp, 48] ; Recover r21
ld r20, [sp, 52] ; Recover r20
ld r19, [sp, 56] ; Recover r19
ld r18, [sp, 60] ; Recover r18
ld r17, [sp, 64] ; Recover r17
ld r16, [sp, 68] ; Recover r16
ld r15, [sp, 72] ; Recover r15
ld r14, [sp, 76] ; Recover r14
ld r13, [sp, 80] ; Recover r13
ld r12, [sp, 84] ; Recover r12
ld r11, [sp, 88] ; Recover r11
ld r10, [sp, 92] ; Recover r10
ld r9, [sp, 96] ; Recover r9
ld r8, [sp, 100] ; Recover r8
ld r7, [sp, 104] ; Recover r7
ld r6, [sp, 108] ; Recover r6
ld r5, [sp, 112] ; Recover r5
ld r4, [sp, 116] ; Recover r4
ld r3, [sp, 120] ; Recover r3
ld r2, [sp, 124] ; Recover r2
ld r1, [sp, 128] ; Recover r1
ld r0, [sp, 132] ; Recover r0
ld r30, [sp, 136] ; Recover r30
.ifdef TX_ENABLE_ACC
ld r58, [sp, 140] ; Recover r58
ld r59, [sp, 144] ; Recover r59
.endif
add sp, sp, 160 ; Recover interrupt stack frame
rtie ; Return to point of interrupt
;
;}
;
.end

86
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;/**************************************************************************/
;/* */
;/* Copyright (c) Microsoft Corporation. All rights reserved. */
;/* */
;/* This software is licensed under the Microsoft Software License */
;/* Terms for Microsoft Azure RTOS. Full text of the license can be */
;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
;/* and in the root directory of this software. */
;/* */
;/**************************************************************************/
;
;
;/**************************************************************************/
;/**************************************************************************/
;/** */
;/** ThreadX Component */
;/** */
;/** Thread - Low Level SMP Support */
;/** */
;/**************************************************************************/
;/**************************************************************************/
;
;
;#define TX_SOURCE_CODE
;#define TX_THREAD_SMP_SOURCE_CODE
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_thread.h"
;#include "tx_timer.h" */
;
;
;/**************************************************************************/
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_smp_core_get SMP/ARC_HS/MetaWare */
;/* 6.0.1 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
;/* */
;/* DESCRIPTION */
;/* */
;/* This function gets the currently running core number and returns it.*/
;/* */
;/* INPUT */
;/* */
;/* None */
;/* */
;/* OUTPUT */
;/* */
;/* Core ID */
;/* */
;/* CALLS */
;/* */
;/* None */
;/* */
;/* CALLED BY */
;/* */
;/* ThreadX Source */
;/* */
;/* RELEASE HISTORY */
;/* */
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* */
;/**************************************************************************/
.global _tx_thread_smp_core_get
.type _tx_thread_smp_core_get, @function
_tx_thread_smp_core_get:
;
; /* Pickup core ID. */
;
lr r0, [IDENTITY] ; Pickup core ID
xbfu r0, r0, 8, 8 ; Shift down and isolate core ID
j_s.d [blink] ; Return to caller with delay slot
.ifndef TX_ZERO_BASED_CORE_ID
sub r0, r0, 1 ; Subtract 1 to make 0-based
.else
nop ;
.endif
.end

88
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;/**************************************************************************/
;/* */
;/* Copyright (c) Microsoft Corporation. All rights reserved. */
;/* */
;/* This software is licensed under the Microsoft Software License */
;/* Terms for Microsoft Azure RTOS. Full text of the license can be */
;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
;/* and in the root directory of this software. */
;/* */
;/**************************************************************************/
;
;
;/**************************************************************************/
;/**************************************************************************/
;/** */
;/** ThreadX Component */
;/** */
;/** Thread - Low Level SMP Support */
;/** */
;/**************************************************************************/
;/**************************************************************************/
;
;
;#define TX_SOURCE_CODE
;#define TX_THREAD_SMP_SOURCE_CODE
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_thread.h"
;#include "tx_timer.h" */
;
;
;/**************************************************************************/
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_smp_core_preempt SMP/ARC_HS/MetaWare */
;/* 6.0.1 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
;/* */
;/* DESCRIPTION */
;/* */
;/* This function preempts the specified core in situations where the */
;/* thread corresponding to this core is no longer ready or when the */
;/* core must be used for a higher-priority thread. If the specified is */
;/* the current core, this processing is skipped since the will give up */
;/* control subsequently on its own. */
;/* */
;/* INPUT */
;/* */
;/* core The core to preempt */
;/* */
;/* OUTPUT */
;/* */
;/* None */
;/* */
;/* CALLS */
;/* */
;/* None */
;/* */
;/* CALLED BY */
;/* */
;/* ThreadX Source */
;/* */
;/* RELEASE HISTORY */
;/* */
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* */
;/**************************************************************************/
.global _tx_thread_smp_core_preempt
.type _tx_thread_smp_core_preempt, @function
_tx_thread_smp_core_preempt:
sub sp, sp, 16 ; Allocate some stack space
st blink, [sp] ; Save return address
bl.d arc_ici_send ; Call ARC inter-core interrupt routine
sub sp, sp, 16 ; Allocate stack space (delay slot)
add sp, sp, 16 ; Recover stack space
ld blink, [sp] ; Recover return address
j_s.d [blink] ; Return to caller with delay slot
add sp, sp, 16 ; Recover stack space
.end

89
ports_smp/arc_hs_smp/metaware/src/tx_thread_smp_current_state_get.s Normal file
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;/**************************************************************************/
;/* */
;/* Copyright (c) Microsoft Corporation. All rights reserved. */
;/* */
;/* This software is licensed under the Microsoft Software License */
;/* Terms for Microsoft Azure RTOS. Full text of the license can be */
;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
;/* and in the root directory of this software. */
;/* */
;/**************************************************************************/
;
;
;/**************************************************************************/
;/**************************************************************************/
;/** */
;/** ThreadX Component */
;/** */
;/** Thread - Low Level SMP Support */
;/** */
;/**************************************************************************/
;/**************************************************************************/
;
;
;#define TX_SOURCE_CODE
;#define TX_THREAD_SMP_SOURCE_CODE
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_thread.h"
;#include "tx_timer.h" */
;
;
;/**************************************************************************/
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_smp_current_state_get SMP/ARC_HS/MetaWare */
;/* 6.0.1 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
;/* */
;/* DESCRIPTION */
;/* */
;/* This function is gets the current state of the calling core. */
;/* */
;/* INPUT */
;/* */
;/* None */
;/* */
;/* OUTPUT */
;/* */
;/* None */
;/* */
;/* CALLS */
;/* */
;/* None */
;/* */
;/* CALLED BY */
;/* */
;/* ThreadX Components */
;/* */
;/* RELEASE HISTORY */
;/* */
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* */
;/**************************************************************************/
.global _tx_thread_smp_current_state_get
.type _tx_thread_smp_current_state_get, @function
_tx_thread_smp_current_state_get:
clri r2 ; Disable interrupts
lr r0, [IDENTITY] ; Pickup core ID
xbfu r0, r0, 8, 8 ; Shift down and isolate core ID
.ifndef TX_ZERO_BASED_CORE_ID
sub r0, r0, 1 ; Subtract 1 to make 0-based
.endif
asl r0, r0, 2 ; Build index into _tx_thread_system_state
mov r1, _tx_thread_system_state ; Build address of _tx_thread_system_state
add r1, r1, r0 ;
ld r0, [r1] ; Pickup current system state for this core
j_s.d [blink] ; Return to caller with delay slot
seti r2 ; Restore previous interrupt state
.end

90
ports_smp/arc_hs_smp/metaware/src/tx_thread_smp_current_thread_get.s Normal file
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;/**************************************************************************/
;/* */
;/* Copyright (c) Microsoft Corporation. All rights reserved. */
;/* */
;/* This software is licensed under the Microsoft Software License */
;/* Terms for Microsoft Azure RTOS. Full text of the license can be */
;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
;/* and in the root directory of this software. */
;/* */
;/**************************************************************************/
;
;
;/**************************************************************************/
;/**************************************************************************/
;/** */
;/** ThreadX Component */
;/** */
;/** Thread - Low Level SMP Support */
;/** */
;/**************************************************************************/
;/**************************************************************************/
;
;
;#define TX_SOURCE_CODE
;#define TX_THREAD_SMP_SOURCE_CODE
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_thread.h"
;#include "tx_timer.h" */
;
;
;/**************************************************************************/
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_smp_current_thread_get SMP/ARC_HS/MetaWare */
;/* 6.0.1 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
;/* */
;/* DESCRIPTION */
;/* */
;/* This function is gets the current thread of the calling core. */
;/* */
;/* INPUT */
;/* */
;/* None */
;/* */
;/* OUTPUT */
;/* */
;/* None */
;/* */
;/* CALLS */
;/* */
;/* None */
;/* */
;/* CALLED BY */
;/* */
;/* ThreadX Components */
;/* */
;/* RELEASE HISTORY */
;/* */
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* */
;/**************************************************************************/
.global _tx_thread_smp_current_thread_get
.type _tx_thread_smp_current_thread_get, @function
_tx_thread_smp_current_thread_get:
clri r2 ; Disable interrupts
lr r0, [IDENTITY] ; Pickup core ID
xbfu r0, r0, 8, 8 ; Shift down and isolate core ID
.ifndef TX_ZERO_BASED_CORE_ID
sub r0, r0, 1 ; Subtract 1 to make 0-based
.endif
asl r0, r0, 2 ; Build index into _tx_thread_current_ptr
mov r1, _tx_thread_current_ptr ; Build address of _tx_thread_current_ptr
add r1, r1, r0 ;
ld r0, [r1] ; Pickup current thread for this core
j_s.d [blink] ; Return to caller with delay slot
seti r2 ; Restore previous interrupt state
.end

126
ports_smp/arc_hs_smp/metaware/src/tx_thread_smp_initialize_wait.s Normal file
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;/**************************************************************************/
;/* */
;/* Copyright (c) Microsoft Corporation. All rights reserved. */
;/* */
;/* This software is licensed under the Microsoft Software License */
;/* Terms for Microsoft Azure RTOS. Full text of the license can be */
;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
;/* and in the root directory of this software. */
;/* */
;/**************************************************************************/
;
;
;/**************************************************************************/
;/**************************************************************************/
;/** */
;/** ThreadX Component */
;/** */
;/** Thread - Low Level SMP Support */
;/** */
;/**************************************************************************/
;/**************************************************************************/
;
;
;#define TX_SOURCE_CODE
;#define TX_THREAD_SMP_SOURCE_CODE
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_thread.h"
;#include "tx_timer.h" */
;
;
;/**************************************************************************/
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_smp_initialize_wait SMP/ARC_HS/MetaWare */
;/* 6.0.1 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
;/* */
;/* DESCRIPTION */
;/* */
;/* This function is the place where additional cores wait until */
;/* initialization is complete before they enter the thread scheduling */
;/* loop. */
;/* */
;/* INPUT */
;/* */
;/* None */
;/* */
;/* OUTPUT */
;/* */
;/* None */
;/* */
;/* CALLS */
;/* */
;/* _tx_thread_schedule Thread scheduling loop */
;/* */
;/* CALLED BY */
;/* */
;/* Hardware */
;/* */
;/* RELEASE HISTORY */
;/* */
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* */
;/**************************************************************************/
.global _tx_thread_smp_initialize_wait
.type _tx_thread_smp_initialize_wait, @function
_tx_thread_smp_initialize_wait:
;
; /* Lockout interrupts. */
;
clri r2 ; Disable interrupts
;
; /* Pickup the CPU ID. */
;
lr r0, [IDENTITY] ; Pickup core ID
xbfu r0, r0, 8, 8 ; Shift down and isolate core ID
.ifndef TX_ZERO_BASED_CORE_ID
sub r0, r0, 1 ; Subtract 1 to make 0-based
.endif
asl r0, r0, 2 ; Build index into _tx_thread_system_state
mov r1, _tx_thread_system_stack_ptr ; Build system stack pointer address
add r1, r1, r0 ;
st sp, [r1] ; Save this core's system address
mov r1, _tx_thread_system_state ; Build system state pointer address
add r1, r1, r0 ;
mov r3, 0xF0F0F0F0 ; Build TX_INITIALIZE_IN_PROGRESS flag
wait_for_initialize:
ld r0, [r1] ; Pickup current system state for this core
; Has the TX_INITIALIZE_IN_PROGRESS flag been set yet?
brne r3, r0, wait_for_initialize ; No, simply wait here until this value is set
;
; /* Pickup the release cores flag. */
;
mov r3, 0 ; Build clear value
wait_for_release:
ld r0, [gp, _tx_thread_smp_release_cores_flag@sda] ; Pickup the release cores flag
breq r3, r0, wait_for_release ; No, simply wait here until this flag is set
;
; /* Core 0 has released this core. */
;
; /* Clear this core's system state variable. */
;
st r3, [r1] ; Clear this core's state value
;
; /* Now wait for core 0 to finish it's initialization. */
;
core_0_wait_loop:
ld r0, [gp, _tx_thread_system_state@sda] ; Pickup core 0's state value
brne r3, r0, core_0_wait_loop ; If set, continue to wait here
;
; /* Initialize is complete, enter the scheduling loop! */
;
b _tx_thread_schedule ; Return to scheduler..
.end

79
ports_smp/arc_hs_smp/metaware/src/tx_thread_smp_low_level_initialize.s Normal file
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;/**************************************************************************/
;/* */
;/* Copyright (c) Microsoft Corporation. All rights reserved. */
;/* */
;/* This software is licensed under the Microsoft Software License */
;/* Terms for Microsoft Azure RTOS. Full text of the license can be */
;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
;/* and in the root directory of this software. */
;/* */
;/**************************************************************************/
;
;
;/**************************************************************************/
;/**************************************************************************/
;/** */
;/** ThreadX Component */
;/** */
;/** Thread - Low Level SMP Support */
;/** */
;/**************************************************************************/
;/**************************************************************************/
;
;
;#define TX_SOURCE_CODE
;#define TX_THREAD_SMP_SOURCE_CODE
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_thread.h"
;#include "tx_timer.h" */
;
;
;/**************************************************************************/
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_smp_low_level_initialize SMP/ARC_HS/MetaWare */
;/* 6.0.1 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
;/* */
;/* DESCRIPTION */
;/* */
;/* This function performs low-level initialization of the booting */
;/* core. */
;/* */
;/* INPUT */
;/* */
;/* number_of_cores Number of cores */
;/* */
;/* OUTPUT */
;/* */
;/* None */
;/* */
;/* CALLS */
;/* */
;/* None */
;/* */
;/* CALLED BY */
;/* */
;/* _tx_initialize_high_level ThreadX high-level init */
;/* */
;/* RELEASE HISTORY */
;/* */
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* */
;/**************************************************************************/
.global _tx_thread_smp_low_level_initialize
.type _tx_thread_smp_low_level_initialize, @function
_tx_thread_smp_low_level_initialize:
j_s.d [blink] ; Return to caller with delay slot
nop ;
.end

117
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;/**************************************************************************/
;/* */
;/* Copyright (c) Microsoft Corporation. All rights reserved. */
;/* */
;/* This software is licensed under the Microsoft Software License */
;/* Terms for Microsoft Azure RTOS. Full text of the license can be */
;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
;/* and in the root directory of this software. */
;/* */
;/**************************************************************************/
;
;
;/**************************************************************************/
;/**************************************************************************/
;/** */
;/** ThreadX Component */
;/** */
;/** Thread - Low Level SMP Support */
;/** */
;/**************************************************************************/
;/**************************************************************************/
;
;
;#define TX_SOURCE_CODE
;#define TX_THREAD_SMP_SOURCE_CODE
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_thread.h"
;#include "tx_timer.h" */
;
;
;/**************************************************************************/
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_smp_protect SMP/ARC_HS/MetaWare */
;/* 6.0.1 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
;/* */
;/* DESCRIPTION */
;/* */
;/* This function gets protection for running inside the ThreadX */
;/* source. This is acomplished by a combination of a test-and-set */
;/* flag and periodically disabling interrupts. */
;/* */
;/* INPUT */
;/* */
;/* None */
;/* */
;/* OUTPUT */
;/* */
;/* Previous Status Register */
;/* */
;/* CALLS */
;/* */
;/* None */
;/* */
;/* CALLED BY */
;/* */
;/* ThreadX Source */
;/* */
;/* RELEASE HISTORY */
;/* */
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* */
;/**************************************************************************/
.global _tx_thread_smp_protect
.type _tx_thread_smp_protect, @function
_tx_thread_smp_protect:
clri r0 ; Disable interrupts
lr r1, [IDENTITY] ; Pickup core ID
xbfu r1, r1, 8, 8 ; Shift down and isolate core ID
.ifndef TX_ZERO_BASED_CORE_ID
sub r1, r1, 1 ; Subtract 1 to make 0-based
.endif
mov r2, 1 ; Build protection flag
mov r3, 0 ; Build clear value
mov r4, _tx_thread_smp_protection ; Build address of the protection structure
ld r5, [r4, 8] ; Pickup the owning core
breq r1, r5, _owned ; Check if the core already owns the protection
llock r6, [r4] ; Attempt to get the inter-core lock
breq r3, r6, _continue ; If the lock is available, continue
b.d _tx_thread_smp_protect ; Attempt to get the lock again
seti r0 ; Restore original interrupt posture
_continue:
scond r2, [r4] ; Attempt to set the lock
beq_s _got_lock ; If STATUS32[Z] flag is set, we got the lock!
b.d _tx_thread_smp_protect ; Attempt to get the lock again
seti r0 ; Restore original interrupt posture
_got_lock:
dmb 3 ; Data memory barrier
st r1, [r4, 8] ; Store the owning core
.ifdef TX_SMP_DEBUG_ENABLE
asl r0, r1, 2 ; Build index into _tx_thread_system_state
mov r7, _tx_thread_current_ptr ; Pickup base of the current thread pointer
add r7, r7, r0 ; Build address of current thread pointer
ld r8, [r7] ; Pickup the current thread pointer
st r8, [r4, 4] ; Save the current thread pointer
st blink, [r4, 16] ; Save last caller's return address
st r0, [r4, 20] ; Save STATUS32
.endif
_owned:
ld r6, [r4, 12] ; Pickup ownership count
add r6, r6, 1 ; Increment ownership count
j_s.d [blink] ; Return to caller with delay slot
st r6, [r4, 12] ; Store new ownership count
.end

80
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;/**************************************************************************/
;/* */
;/* Copyright (c) Microsoft Corporation. All rights reserved. */
;/* */
;/* This software is licensed under the Microsoft Software License */
;/* Terms for Microsoft Azure RTOS. Full text of the license can be */
;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
;/* and in the root directory of this software. */
;/* */
;/**************************************************************************/
;
;
;/**************************************************************************/
;/**************************************************************************/
;/** */
;/** ThreadX Component */
;/** */
;/** Thread - Low Level SMP Support */
;/** */
;/**************************************************************************/
;/**************************************************************************/
;
;
;#define TX_SOURCE_CODE
;#define TX_THREAD_SMP_SOURCE_CODE
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_thread.h"
;#include "tx_timer.h" */
;
;
;/**************************************************************************/
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_smp_time_get SMP/ARC_HS/MetaWare */
;/* 6.0.1 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
;/* */
;/* DESCRIPTION */
;/* */
;/* This function gets the global time value that is used for debug */
;/* information and event tracing. */
;/* */
;/* INPUT */
;/* */
;/* None */
;/* */
;/* OUTPUT */
;/* */
;/* 32-bit time stamp */
;/* */
;/* CALLS */
;/* */
;/* None */
;/* */
;/* CALLED BY */
;/* */
;/* ThreadX Source */
;/* */
;/* RELEASE HISTORY */
;/* */
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* */
;/**************************************************************************/
.global _tx_thread_smp_time_get
.type _tx_thread_smp_time_get, @function
_tx_thread_smp_time_get:
j_s.d [blink] ; Return to caller with delay slot
lr r0, [COUNT0] ; Return count 0 value
.end

107
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;/**************************************************************************/
;/* */
;/* Copyright (c) Microsoft Corporation. All rights reserved. */
;/* */
;/* This software is licensed under the Microsoft Software License */
;/* Terms for Microsoft Azure RTOS. Full text of the license can be */
;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
;/* and in the root directory of this software. */
;/* */
;/**************************************************************************/
;
;
;/**************************************************************************/
;/**************************************************************************/
;/** */
;/** ThreadX Component */
;/** */
;/** Thread - Low Level SMP Support */
;/** */
;/**************************************************************************/
;/**************************************************************************/
;
;
;#define TX_SOURCE_CODE
;#define TX_THREAD_SMP_SOURCE_CODE
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_thread.h"
;#include "tx_timer.h" */
;
;
;/**************************************************************************/
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_smp_unprotect SMP/ARC_HS/MetaWare */
;/* 6.0.1 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
;/* */
;/* DESCRIPTION */
;/* */
;/* This function releases previously obtained protection. The supplied */
;/* previous SR is restored. If the value of _tx_thread_system_state */
;/* and _tx_thread_preempt_disable are both zero, then multithreading */
;/* is enabled as well. */
;/* */
;/* INPUT */
;/* */
;/* Previous Status Register */
;/* */
;/* OUTPUT */
;/* */
;/* None */
;/* */
;/* CALLS */
;/* */
;/* None */
;/* */
;/* CALLED BY */
;/* */
;/* ThreadX Source */
;/* */
;/* RELEASE HISTORY */
;/* */
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* */
;/**************************************************************************/
.global _tx_thread_smp_unprotect
.type _tx_thread_smp_unprotect, @function
_tx_thread_smp_unprotect:
clri ; Disable interrupts
lr r1, [IDENTITY] ; Pickup core ID
xbfu r1, r1, 8, 8 ; Shift down and isolate core ID
.ifndef TX_ZERO_BASED_CORE_ID
sub r1, r1, 1 ; Subtract 1 to make 0-based
.endif
mov r4, _tx_thread_smp_protection ; Build address of the protection structure
ld r5, [r4, 8] ; Pickup the owning core
brne r1, r5, _still_protected ; If not the owning core, protection is in force elsewhere
ld r6, [r4, 12] ; Pickup ownership count
breq r6, 0, _still_protected ; If zero, protection is still active
sub r6, r6, 1 ; Decrement the ownership count
st r6, [r4, 12] ; Store the ownership count
brne r6, 0, _still_protected ; If non-zero, protection is still active
ld r6, [gp, _tx_thread_preempt_disable@sda] ; Pickup preempt disable flag
brne r6, 0, _still_protected ; If non-zero, don't release the protection
mov r2, 0xFFFFFFFF ; Build invalid value
st r2, [r4, 8] ; Set the owning core to an invalid value
.ifdef TX_SMP_DEBUG_ENABLE
st blink, [r4, 24] ; Save caller of unprotect
.endif
mov r2, 0 ; Build clear value
dmb 3 ; Data memory barrier
st r2, [r4] ; Release the protection
dmb 3 ; Data memory barrier
_still_protected:
j_s.d [blink] ; Return to caller with delay slot
seti r0 ; Set desired interrupt state
.end

209
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;/**************************************************************************/
;/* */
;/* Copyright (c) Microsoft Corporation. All rights reserved. */
;/* */
;/* This software is licensed under the Microsoft Software License */
;/* Terms for Microsoft Azure RTOS. Full text of the license can be */
;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
;/* and in the root directory of this software. */
;/* */
;/**************************************************************************/
;
;
;/**************************************************************************/
;/**************************************************************************/
;/** */
;/** ThreadX Component */
;/** */
;/** Thread */
;/** */
;/**************************************************************************/
;/**************************************************************************/
;
;
;#define TX_SOURCE_CODE
;
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_thread.h"
;
;
.equ LONG_ALIGN_MASK, 0xFFFFFFFC
.equ INT_ENABLE_BITS, 0x8000001E
;
;
;/**************************************************************************/
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_stack_build SMP/ARC_HS/MetaWare */
;/* 6.0.1 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
;/* */
;/* DESCRIPTION */
;/* */
;/* This function builds a stack frame on the supplied thread's stack. */
;/* The stack frame results in a fake interrupt return to the supplied */
;/* function pointer. */
;/* */
;/* INPUT */
;/* */
;/* thread_ptr Pointer to thread control blk */
;/* function_ptr Pointer to return function */
;/* */
;/* OUTPUT */
;/* */
;/* None */
;/* */
;/* CALLS */
;/* */
;/* None */
;/* */
;/* CALLED BY */
;/* */
;/* _tx_thread_create Create thread service */
;/* */
;/* RELEASE HISTORY */
;/* */
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* */
;/**************************************************************************/
;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID))
;{
.global _tx_thread_stack_build
.type _tx_thread_stack_build, @function
_tx_thread_stack_build:
;
;
; /* Build a fake interrupt frame. The form of the fake interrupt stack
; on the ARC HS should look like the following after it is built.
; Note that the extension registers are always assigned space here.
;
; Stack Top: 1 Interrupt stack frame type
; LP_START Initial loop start
; LP_END Initial loop end
; LP_COUNT Initial loop count
; blink Initial blink value
; ilink Initial ilink (point of interrupt)
; fp (r27) Initial fp (0)
; gp Initial gp
; r25 Initial r25
; r24 Initial r24
; r23 Initial r23
; r22 Initial r22
; r21 Initial r21
; r20 Initial r20
; r19 Initial r19
; r18 Initial r18
; r17 Initial r17
; r16 Initial r16
; r15 Initial r15
; r14 Initial r14
; r13 Initial r13
; r12 Initial r12
; r11 Initial r11
; r10 Initial r10
; r9 Initial r9
; r8 Initial r8
; r7 Initial r7
; r6 Initial r6
; r5 Initial r5
; r4 Initial r4
; r3 Initial r3
; r2 Initial r2
; r1 Initial r1
; r0 Initial r0
; r30 Initial r30
; r58 Initial r58
; r59 Initial r59
; 0 Reserved
; 0 Reserved
; 0 Initial BTA
; 0 Point of Interrupt (thread entry point)
; 0 Initial STATUS32
; 0 Backtrace
; 0 Backtrace
; 0 Backtrace
; 0 Backtrace
;
; *: these registers will only be saved and restored if flag -Xxmac_d16 is passed to hcac
;
; Stack Bottom: (higher memory address) */
;
ld r3, [r0, 16] ; Pickup end of stack area
and r3, r3, LONG_ALIGN_MASK ; Ensure long-word alignment
sub r3, r3, 196 ; Allocate an interrupt stack frame (ARC HS)
;
; /* Actually build the stack frame. */
;
st 1, [r3, 0] ; Store interrupt stack type on the
; top of the stack
mov r5, 0 ; Build initial clear value
st r5, [r3, 4] ; Store initial LP_START
st r5, [r3, 8] ; Store initial LP_END
st r5, [r3, 12] ; Store initial LP_COUNT
st r5, [r3, 16] ; Store initial blink
st r1, [r3, 20] ; Store initial ilink
st r5, [r3, 24] ; Store initial fp (0 for backtrace)
st gp, [r3, 28] ; Store current gp
st r5, [r3, 32] ; Store initial r25
st r5, [r3, 36] ; Store initial r24
st r5, [r3, 40] ; Store initial r23
st r5, [r3, 44] ; Store initial r22
st r5, [r3, 48] ; Store initial r21
st r5, [r3, 52] ; Store initial r20
st r5, [r3, 56] ; Store initial r19
st r5, [r3, 60] ; Store initial r18
st r5, [r3, 64] ; Store initial r17
st r5, [r3, 68] ; Store initial r16
st r5, [r3, 72] ; Store initial r15
st r5, [r3, 76] ; Store initial r14
st r5, [r3, 80] ; Store initial r13
st r5, [r3, 84] ; Store initial r12
st r5, [r3, 88] ; Store initial r11
st r5, [r3, 92] ; Store initial r10
st r5, [r3, 96] ; Store initial r9
st r5, [r3, 100] ; Store initial r8
st r5, [r3, 104] ; Store initial r7
st r5, [r3, 108] ; Store initial r6
st r5, [r3, 112] ; Store initial r5
st r5, [r3, 116] ; Store initial r4
st r5, [r3, 120] ; Store initial r3
st r5, [r3, 124] ; Store initial r2
st r5, [r3, 128] ; Store initial r1
st r5, [r3, 132] ; Store initial r0
st r5, [r3, 136] ; Store initial r30
st r5, [r3, 140] ; Store initial r58
st r5, [r3, 144] ; Store initial r59
st r5, [r3, 148] ; Reserved
st r5, [r3, 152] ; Reserved
st r5, [r3, 156] ; Store initial BTA
st r1, [r3, 160] ; Store initial point of entry
lr r6, [status32] ; Pickup STATUS32
or r6, r6, INT_ENABLE_BITS ; Make sure interrupts are enabled
st r6, [r3, 164] ; Store initial STATUS32
st r5, [r3, 168] ; Backtrace 0
st r5, [r3, 172] ; Backtrace 0
st r5, [r3, 176] ; Backtrace 0
st r5, [r3, 180] ; Backtrace 0
;
; /* Set ready bit in thread control block. */
;
st 1, [r0, 164] ; Set ready bit in thread's control block
;
; /* Setup stack pointer. */
; thread_ptr -> tx_thread_stack_ptr = r3;
;
j_s.d [blink] ; Return to caller
st r3, [r0, 8] ; Save stack pointer in thread's
; control block
;}
.end

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;/**************************************************************************/
;/* */
;/* Copyright (c) Microsoft Corporation. All rights reserved. */
;/* */
;/* This software is licensed under the Microsoft Software License */
;/* Terms for Microsoft Azure RTOS. Full text of the license can be */
;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
;/* and in the root directory of this software. */
;/* */
;/**************************************************************************/
;
;
;/**************************************************************************/
;/**************************************************************************/
;/** */
;/** ThreadX Component */
;/** */
;/** Thread */
;/** */
;/**************************************************************************/
;/**************************************************************************/
;
;#define TX_SOURCE_CODE
;
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_thread.h"
;#include "tx_timer.h"
;
;
;/**************************************************************************/
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_system_return SMP/ARC_HS/MetaWare */
;/* 6.0.1 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
;/* */
;/* DESCRIPTION */
;/* */
;/* This function is target processor specific. It is used to transfer */
;/* control from a thread back to the ThreadX system. Only a */
;/* minimal context is saved since the compiler assumes temp registers */
;/* are going to get slicked by a function call anyway. */
;/* */
;/* INPUT */
;/* */
;/* None */
;/* */
;/* OUTPUT */
;/* */
;/* None */
;/* */
;/* CALLS */
;/* */
;/* _tx_thread_schedule Thread scheduling loop */
;/* */
;/* CALLED BY */
;/* */
;/* ThreadX components */
;/* */
;/* RELEASE HISTORY */
;/* */
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* */
;/**************************************************************************/
;VOID _tx_thread_system_return(VOID)
;{
.global _tx_thread_system_return
.type _tx_thread_system_return, @function
_tx_thread_system_return:
;
; /* Save minimal context on the stack. */
;
; /* Lockout interrupts. */
;
clri r2 ; Disable interrupts
lr r1, [IDENTITY] ; Pickup core ID
xbfu r1, r1, 8, 8 ; Shift down and isolate core ID
.ifndef TX_ZERO_BASED_CORE_ID
sub r1, r1, 1 ; Subtract 1 to make 0-based
.endif
asl r4, r1, 2 ; Build index into core arrays
mov r7, _tx_thread_current_ptr ; Pickup base of the current thread pointer
add r7, r7, r4 ; Build address of current thread pointer
ld r0, [r7] ; Pickup current thread ptr
sub sp, sp, 76 ; Allocate a solicited stack frame
mov r3, 0 ; Build a solicited stack type
st r3, [sp, 0] ; Store stack type on the top
st blink, [sp, 4] ; Save return address and flags
st fp, [sp, 8] ; Save fp
st r26, [sp, 12] ; Save r26
st r25, [sp, 16] ; Save r25
st r24, [sp, 20] ; Save r24
st r23, [sp, 24] ; Save r23
st r22, [sp, 28] ; Save r22
st r21, [sp, 32] ; Save r21
st r20, [sp, 36] ; Save r20
st r19, [sp, 40] ; Save r19
st r18, [sp, 44] ; Save r18
st r17, [sp, 48] ; Save r17
st r16, [sp, 52] ; Save r16
st r15, [sp, 56] ; Save r15
st r14, [sp, 60] ; Save r14
st r13, [sp, 64] ; Save r13
st r2, [sp, 68] ; Save status32
st r30, [sp, 72] ; Save r30
;
; /* Save current stack and switch to system stack. */
; _tx_thread_current_ptr[core] -> tx_thread_stack_ptr = sp;
; sp = _tx_thread_system_stack_ptr[core];
;
;
st sp, [r0, 8] ; Save thread's stack pointer
mov r6, _tx_thread_system_stack_ptr ; Pickup address of system stack pointer
add r6, r6, r4 ; Build address of this core's entry
ld sp, [r6] ; Switch to system stack
;
.ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
;
; /* Call the thread exit function to indicate the thread is no longer executing. */
;
mov r13, r0 ; Save thread control block pointer
mov r14, r1 ; Save core executing
mov r15, r7 ; Save current thread pointer for core
mov r16, blink ; Save blink
bl.d _tx_execution_thread_exit ; Call the thread exit function
sub sp, sp, 16 ; ..allocating some space on the stack
add sp, sp, 16 ; Recover the stack space
ld r0, [gp, _tx_thread_current_ptr@sda] ; Pickup current thread ptr
mov r3, 0 ; Build clear value
mov r0, r13 ; Recover thread control block
mov r1, r14 ; Recover current core executing
mov r7, r15 ; Recover current thread pointer for core
mov blink, r16 ; Recover blink
asl r4, r1, 2 ; Build index into core arrays
.endif
;
; /* Determine if the time-slice is active. */
; if (_tx_timer_time_slice)
; {
;
mov r6, _tx_timer_time_slice ; Build address of current time-slice
add r6, r6, r4 ;
ld r5, [r6] ; Pickup current time-slice
breq r5, 0, __tx_thread_dont_save_ts ; If not, skip save processing
;
; /* Save time-slice for the thread and clear the current time-slice. */
; _tx_thread_current_ptr[core] -> tx_thread_time_slice = _tx_timer_time_slice[core];
; _tx_timer_time_slice = 0;
;
st r3, [r6] ; Clear time-slice variable
st r5, [r0, 24] ; Save current time-slice
;
; }
__tx_thread_dont_save_ts:
;
; /* Clear the current thread pointer. */
; _tx_thread_current_ptr[core] = TX_NULL;
;
st r3, [r7] ; Clear current thread pointer
;
; /* Set ready bit in thread control block. */
;
dmb 3 ; Data memory barrier
st 1, [r0, 164] ; Set ready bit for this thread
;
; /* Now clear protection. It is assumed that protection is in force whenever this routine is called. */
;
mov r6, _tx_thread_smp_protection ; Pickup address of protection structure
.ifdef TX_SMP_DEBUG_ENABLE
st blink, [r6, 24] ; Save last caller
ld r5, [r6, 4] ; Pickup last core owner
__error_loop:
brne r1, r5, __error_loop ; Check for an error - if found stay here!
.endif
st r3, [gp, _tx_thread_preempt_disable@sda] ; Clear the preempt disable flag
st r3, [r6, 12] ; Clear the protection count
mov r5, 0xFFFFFFFF ; Build invalid core value
st r5, [r6, 8] ; Set core to an invalid value
dmb 3 ; Data memory barrier
st r3, [r6] ; Clear protection
dmb 3 ; Data memory barrier
b _tx_thread_schedule ; Return to scheduler..
;
;}
.end

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;/**************************************************************************/
;/* */
;/* Copyright (c) Microsoft Corporation. All rights reserved. */
;/* */
;/* This software is licensed under the Microsoft Software License */
;/* Terms for Microsoft Azure RTOS. Full text of the license can be */
;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
;/* and in the root directory of this software. */
;/* */
;/**************************************************************************/
;
;
;/**************************************************************************/
;/**************************************************************************/
;/** */
;/** ThreadX Component */
;/** */
;/** Timer */
;/** */
;/**************************************************************************/
;/**************************************************************************/
;
;#define TX_SOURCE_CODE
;
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_timer.h"
;#include "tx_thread.h"
;
;
;/**************************************************************************/
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* _tx_timer_interrupt SMP/ARC_HS/MetaWare */
;/* 6.0.1 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
;/* */
;/* DESCRIPTION */
;/* */
;/* This function processes the hardware timer interrupt. This */
;/* processing includes incrementing the system clock and checking for */
;/* time slice and/or timer expiration. If either is found, the */
;/* interrupt context save/restore functions are called along with the */
;/* expiration functions. */
;/* */
;/* INPUT */
;/* */
;/* None */
;/* */
;/* OUTPUT */
;/* */
;/* None */
;/* */
;/* CALLS */
;/* */
;/* _tx_timer_expiration_process Process timer expiration */
;/* _tx_thread_time_slice Time slice interrupted thread */
;/* _tx_thread_context_save Save interrupt context */
;/* _tx_thread_context_restore Restore interrupt context */
;/* */
;/* CALLED BY */
;/* */
;/* interrupt vector */
;/* */
;/* RELEASE HISTORY */
;/* */
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* */
;/**************************************************************************/
;VOID _tx_timer_interrupt(VOID)
;{
.global _tx_timer_interrupt
.type _tx_timer_interrupt, @function
_tx_timer_interrupt:
;
; /* Upon entry to this routine, it is assumed that context save has already
; been called, and therefore the compiler scratch registers are available
; for use. */
;
lr r1, [IDENTITY] ; Pickup core ID
xbfu r1, r1, 8, 8 ; Shift down and isolate core ID
.ifndef TX_ZERO_BASED_CORE_ID
sub r1, r1, 1 ; Subtract 1 to make 0-based
.endif
breq r1, 0, __tx_process_timer ; By default if core 0, process timer
j_s.d [blink] ; Return to caller with delay
nop ;
__tx_process_timer:
sub sp, sp, 16 ; Allocate some stack space
st blink, [sp] ; Save return address
bl.d _tx_thread_smp_protect ; Get SMP protecton
sub sp, sp, 16 ; ..allocating some space on the stack
add sp, sp, 16 ; Recover the stack space
st r0, [sp, 4] ; Save returned interrupt posture on stack
ld r0, [gp,_tx_timer_interrupt_active@sda] ; Pickup current timer active count
add r0, r0, 1 ; Increment the active count
st r0, [gp,_tx_timer_interrupt_active@sda] ; Store the new timer active count
dmb 3 ; Data memory barrier
;
; /* Increment the system clock. */
; _tx_timer_system_clock++;
;
ld r0, [gp,_tx_timer_system_clock@sda] ; Pickup current system clock
add r0, r0, 1 ; Increment the system clock
st r0, [gp,_tx_timer_system_clock@sda] ; Store system clock back in memory
;
; /* Test for timer expiration. */
; if (*_tx_timer_current_ptr)
; {
;
ld r0, [gp, _tx_timer_current_ptr@sda] ; Pickup current timer pointer
ld r2, [r0, 0] ; Pickup examine actual list entry
breq r2, 0, __tx_timer_no_timer ;
; If NULL, no timer has expired, just move to the next entry
;
; /* Set expiration flag. */
; _tx_timer_expired = TX_TRUE;
;
mov r1, 1 ; Build expiration value
b.d __tx_timer_done ; Skip moving the timer pointer
st r1, [gp, _tx_timer_expired@sda] ; Set the expired value
;
; }
; else
; {
__tx_timer_no_timer:
;
; /* No timer expired, increment the timer pointer. */
; _tx_timer_current_ptr++;
;
ld r2, [gp, _tx_timer_list_end@sda] ; Pickup end of list
add r0, r0, 4 ; Move to next timer entry
;
; /* Check for wrap-around. */
; if (_tx_timer_current_ptr == _tx_timer_list_end)
;
st r0, [gp, _tx_timer_current_ptr@sda] ; Store the current timer
brne r0, r2, __tx_timer_skip_wrap ; If not equal, don't wrap the list
;
; /* Wrap to beginning of list. */
; _tx_timer_current_ptr = _tx_timer_list_start;
;
ld r2, [gp, _tx_timer_list_start@sda] ; Pickup start of timer list
st r2, [gp, _tx_timer_current_ptr@sda] ; Set current timer to the start
;
__tx_timer_skip_wrap:
;
; }
;
__tx_timer_done:
;
;
; /* See if anything has expired. */
; if (_tx_timer_expired)
; {
;
breq r1, 0, __tx_timer_nothing_expired ; If 0, nothing has expired
;
__tx_something_expired:
;
;
; /* Process the timer expiration. */
; /* _tx_timer_expiration_process(); */
bl.d _tx_timer_expiration_process ; Call the timer expiration handling routine
sub sp, sp, 16 ; ..allocating some space on the stack
add sp, sp, 16 ; Recover the stack space
;
; }
__tx_timer_nothing_expired:
;
; /* Call time-slice processing. */
; /* _tx_thread_time_slice(); */
bl.d _tx_thread_time_slice ; Call time-slice processing
sub sp, sp, 16 ; ..allocating some stack space
add sp, sp, 16 ; Recover stack space
;
; }
;
ld r0, [gp,_tx_timer_interrupt_active@sda] ; Pickup current timer active count
sub r0, r0, 1 ; Decrement the active count
st r0, [gp,_tx_timer_interrupt_active@sda] ; Store the new timer active count
dmb 3 ; Data memory barrier
ld r0, [sp, 4] ; Recover previous interrupt posture
bl.d _tx_thread_smp_unprotect ; Get SMP protecton
sub sp, sp, 16 ; ..allocating some space on the stack
add sp, sp, 16 ; Recover the stack space
ld blink, [sp] ; Recover original blink
;
;
j_s.d [blink] ; Return to caller with delay slot
add sp, sp, 16 ; Recover temporary stack space
;
;}
.end