patch release 6.1.2
This commit is contained in:
Scott Larson
@@ -1,240 +1,235 @@
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del tx.a
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armasm -g --cpu=cortex-m4 --fpu=softvfp --apcs=/interwork tx_initialize_low_level.S
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armasm -g --cpu=cortex-m4 --fpu=softvfp --apcs=/interwork ../module_manager/src/tx_thread_stack_build.S
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armasm -g --cpu=cortex-m4 --fpu=softvfp --apcs=/interwork ../module_manager/src/tx_thread_schedule.S --diag_suppress=A1581W
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armasm -g --cpu=cortex-m4 --fpu=softvfp --apcs=/interwork ../module_manager/src/tx_thread_system_return.S
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armasm -g --cpu=cortex-m4 --fpu=softvfp --apcs=/interwork ../module_manager/src/tx_thread_context_save.S
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armasm -g --cpu=cortex-m4 --fpu=softvfp --apcs=/interwork ../module_manager/src/tx_thread_context_restore.S
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armasm -g --cpu=cortex-m4 --fpu=softvfp --apcs=/interwork ../module_manager/src/tx_thread_interrupt_control.S
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armasm -g --cpu=cortex-m4 --fpu=softvfp --apcs=/interwork ../module_manager/src/tx_timer_interrupt.S
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armasm -g --cpu=cortex-m4 --fpu=softvfp --apcs=/interwork ../module_manager/src/tx_thread_interrupt_disable.S
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armasm -g --cpu=cortex-m4 --fpu=softvfp --apcs=/interwork ../module_manager/src/tx_thread_interrupt_restore.S
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armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_block_allocate.c
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armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_block_pool_cleanup.c
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armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_block_pool_create.c
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armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_block_pool_delete.c
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armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_block_pool_info_get.c
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armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_block_pool_initialize.c
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armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_block_pool_performance_info_get.c
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armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_block_pool_performance_system_info_get.c
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armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_block_pool_prioritize.c
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armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_block_release.c
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armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_byte_allocate.c
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armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_byte_pool_cleanup.c
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armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_byte_pool_create.c
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armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_byte_pool_delete.c
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armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_byte_pool_info_get.c
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armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_byte_pool_initialize.c
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armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_byte_pool_performance_info_get.c
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armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_byte_pool_performance_system_info_get.c
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armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_byte_pool_prioritize.c
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armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_byte_pool_search.c
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armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_byte_release.c
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armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_event_flags_cleanup.c
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armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_event_flags_create.c
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armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_event_flags_delete.c
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armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_event_flags_get.c
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armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_event_flags_info_get.c
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armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_event_flags_initialize.c
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armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_event_flags_performance_info_get.c
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armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_event_flags_performance_system_info_get.c
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armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_event_flags_set.c
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armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_event_flags_set_notify.c
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armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_initialize_high_level.c
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armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_initialize_kernel_enter.c
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armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_initialize_kernel_setup.c
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armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_mutex_cleanup.c
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armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_mutex_create.c
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armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_mutex_delete.c
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armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_mutex_get.c
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armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_mutex_info_get.c
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armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_mutex_initialize.c
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armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_mutex_performance_info_get.c
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armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_mutex_performance_system_info_get.c
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armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_mutex_prioritize.c
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armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_mutex_priority_change.c
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armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_mutex_put.c
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armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_queue_cleanup.c
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armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_queue_create.c
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armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_queue_delete.c
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armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_queue_flush.c
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armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_queue_front_send.c
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armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_queue_info_get.c
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armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_queue_initialize.c
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armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_queue_performance_info_get.c
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armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_queue_performance_system_info_get.c
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armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_queue_prioritize.c
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armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_queue_receive.c
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armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_queue_send.c
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armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_queue_send_notify.c
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armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_semaphore_ceiling_put.c
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armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_semaphore_cleanup.c
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armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_semaphore_create.c
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armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_semaphore_delete.c
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armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_semaphore_get.c
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armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_semaphore_info_get.c
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armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_semaphore_initialize.c
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armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_semaphore_performance_info_get.c
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armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_semaphore_performance_system_info_get.c
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armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_semaphore_prioritize.c
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armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_semaphore_put.c
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armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_semaphore_put_notify.c
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armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_create.c
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armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_delete.c
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armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_entry_exit_notify.c
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armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_identify.c
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armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_info_get.c
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armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_initialize.c
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armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_performance_info_get.c
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armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_performance_system_info_get.c
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armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_preemption_change.c
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armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_priority_change.c
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armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_relinquish.c
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armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_reset.c
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armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_resume.c
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armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_shell_entry.c
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armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_sleep.c
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armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_stack_analyze.c
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armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_stack_error_handler.c
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armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_stack_error_notify.c
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armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_suspend.c
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armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_system_preempt_check.c
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armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_system_resume.c
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armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_system_suspend.c
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armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_terminate.c
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armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_time_slice.c
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armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_time_slice_change.c
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armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_timeout.c
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armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_wait_abort.c
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armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_time_get.c
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armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_time_set.c
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armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_timer_activate.c
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armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_timer_change.c
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armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_timer_create.c
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armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_timer_deactivate.c
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armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_timer_delete.c
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armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_timer_expiration_process.c
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armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_timer_info_get.c
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armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_timer_initialize.c
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armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_timer_performance_info_get.c
|
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armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_timer_performance_system_info_get.c
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armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_timer_system_activate.c
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armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_timer_system_deactivate.c
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armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_timer_thread_entry.c
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armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_trace_enable.c
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armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_trace_disable.c
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armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_trace_initialize.c
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armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_trace_interrupt_control.c
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armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_trace_isr_enter_insert.c
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armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_trace_isr_exit_insert.c
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armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_trace_object_register.c
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armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_trace_object_unregister.c
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armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_trace_user_event_insert.c
|
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armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_trace_buffer_full_notify.c
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armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_trace_event_filter.c
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armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_trace_event_unfilter.c
|
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armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_block_allocate.c
|
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armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_block_pool_create.c
|
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armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_block_pool_delete.c
|
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armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_block_pool_info_get.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_block_pool_prioritize.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_block_release.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_byte_allocate.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_byte_pool_create.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_byte_pool_delete.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_byte_pool_info_get.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_byte_pool_prioritize.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_byte_release.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_event_flags_create.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_event_flags_delete.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_event_flags_get.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_event_flags_info_get.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_event_flags_set.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_event_flags_set_notify.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_mutex_create.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_mutex_delete.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_mutex_get.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_mutex_info_get.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_mutex_prioritize.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_mutex_put.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_queue_create.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_queue_delete.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_queue_flush.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_queue_front_send.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_queue_info_get.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_queue_prioritize.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_queue_receive.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_queue_send.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_queue_send_notify.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_semaphore_ceiling_put.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_semaphore_create.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_semaphore_delete.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_semaphore_get.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_semaphore_info_get.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_semaphore_prioritize.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_semaphore_put.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_semaphore_put_notify.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_thread_create.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_thread_delete.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_thread_entry_exit_notify.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_thread_info_get.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_thread_preemption_change.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_thread_priority_change.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_thread_relinquish.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_thread_reset.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_thread_resume.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_thread_suspend.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_thread_terminate.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_thread_time_slice_change.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_thread_wait_abort.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_timer_activate.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_timer_change.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_timer_create.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_timer_deactivate.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_timer_delete.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_timer_info_get.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_application_request.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_callback_request.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_event_flags_notify_trampoline.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_file_load.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_in_place_load.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_internal_load.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_initialize.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_kernel_dispatch.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_maximum_module_priority_set.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_memory_load.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_object_allocate.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_object_deallocate.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_object_pointer_get.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_object_pointer_get_extended.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_object_pool_create.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_properties_get.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_queue_notify_trampoline.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_semaphore_notify_trampoline.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_start.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_stop.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_thread_create.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_thread_notify_trampoline.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_thread_reset.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_timer_notify_trampoline.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_unload.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_util.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../module_manager/src/txm_module_manager_alignment_adjust.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../module_manager/src/txm_module_manager_external_memory_enable.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../module_manager/src/txm_module_manager_memory_fault_handler.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../module_manager/src/txm_module_manager_memory_fault_notify.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../module_manager/src/txm_module_manager_mm_register_setup.c
|
||||
armasm -g --cpu=cortex-m4 --fpu=softvfp --apcs=/interwork ../module_manager/src/txm_module_manager_thread_stack_build.S
|
||||
armasm -g --cpu=cortex-m4 --fpu=softvfp --apcs=/interwork ../module_manager/src/txm_module_manager_user_mode_entry.S
|
||||
armasm -g --cpreproc --cpu=cortex-m4 --fpu=vfpv4 --apcs=/interwork tx_initialize_low_level.S
|
||||
armasm -g --cpreproc --cpu=cortex-m4 --fpu=vfpv4 --apcs=/interwork ../module_manager/src/tx_thread_stack_build.S
|
||||
armasm -g --cpreproc --cpu=cortex-m4 --fpu=vfpv4 --apcs=/interwork ../module_manager/src/tx_thread_schedule.S --diag_suppress=A1581W
|
||||
armasm -g --cpreproc --cpu=cortex-m4 --fpu=vfpv4 --apcs=/interwork ../module_manager/src/tx_thread_system_return.S
|
||||
armasm -g --cpreproc --cpu=cortex-m4 --fpu=vfpv4 --apcs=/interwork ../module_manager/src/tx_thread_context_save.S
|
||||
armasm -g --cpreproc --cpu=cortex-m4 --fpu=vfpv4 --apcs=/interwork ../module_manager/src/tx_thread_context_restore.S
|
||||
armasm -g --cpreproc --cpu=cortex-m4 --fpu=vfpv4 --apcs=/interwork ../module_manager/src/tx_thread_interrupt_control.S
|
||||
armasm -g --cpreproc --cpu=cortex-m4 --fpu=vfpv4 --apcs=/interwork ../module_manager/src/tx_timer_interrupt.S
|
||||
armasm -g --cpreproc --cpu=cortex-m4 --fpu=vfpv4 --apcs=/interwork ../module_manager/src/tx_thread_interrupt_disable.S
|
||||
armasm -g --cpreproc --cpu=cortex-m4 --fpu=vfpv4 --apcs=/interwork ../module_manager/src/tx_thread_interrupt_restore.S
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_block_allocate.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_block_pool_cleanup.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_block_pool_create.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_block_pool_delete.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_block_pool_info_get.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_block_pool_initialize.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_block_pool_performance_info_get.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_block_pool_performance_system_info_get.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_block_pool_prioritize.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_block_release.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_byte_allocate.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_byte_pool_cleanup.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_byte_pool_create.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_byte_pool_delete.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_byte_pool_info_get.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_byte_pool_initialize.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_byte_pool_performance_info_get.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_byte_pool_performance_system_info_get.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_byte_pool_prioritize.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_byte_pool_search.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_byte_release.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_event_flags_cleanup.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_event_flags_create.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_event_flags_delete.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_event_flags_get.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_event_flags_info_get.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_event_flags_initialize.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_event_flags_performance_info_get.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_event_flags_performance_system_info_get.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_event_flags_set.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_event_flags_set_notify.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_initialize_high_level.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_initialize_kernel_enter.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_initialize_kernel_setup.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_mutex_cleanup.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_mutex_create.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_mutex_delete.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_mutex_get.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_mutex_info_get.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_mutex_initialize.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_mutex_performance_info_get.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_mutex_performance_system_info_get.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_mutex_prioritize.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_mutex_priority_change.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_mutex_put.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_queue_cleanup.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_queue_create.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_queue_delete.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_queue_flush.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_queue_front_send.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_queue_info_get.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_queue_initialize.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_queue_performance_info_get.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_queue_performance_system_info_get.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_queue_prioritize.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_queue_receive.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_queue_send.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_queue_send_notify.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_semaphore_ceiling_put.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_semaphore_cleanup.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_semaphore_create.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_semaphore_delete.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_semaphore_get.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_semaphore_info_get.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_semaphore_initialize.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_semaphore_performance_info_get.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_semaphore_performance_system_info_get.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_semaphore_prioritize.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_semaphore_put.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_semaphore_put_notify.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_create.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_delete.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_entry_exit_notify.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_identify.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_info_get.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_initialize.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_performance_info_get.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_performance_system_info_get.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_preemption_change.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_priority_change.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_relinquish.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_reset.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_resume.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_shell_entry.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_sleep.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_stack_analyze.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_stack_error_handler.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_stack_error_notify.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_suspend.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_system_preempt_check.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_system_resume.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_system_suspend.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_terminate.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_time_slice.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_time_slice_change.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_timeout.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_wait_abort.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_time_get.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_time_set.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_timer_activate.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_timer_change.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_timer_create.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_timer_deactivate.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_timer_delete.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_timer_expiration_process.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_timer_info_get.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_timer_initialize.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_timer_performance_info_get.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_timer_performance_system_info_get.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_timer_system_activate.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_timer_system_deactivate.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_timer_thread_entry.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_trace_enable.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_trace_disable.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_trace_initialize.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_trace_interrupt_control.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_trace_isr_enter_insert.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_trace_isr_exit_insert.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_trace_object_register.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_trace_object_unregister.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_trace_user_event_insert.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_trace_buffer_full_notify.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_trace_event_filter.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_trace_event_unfilter.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_block_allocate.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_block_pool_create.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_block_pool_delete.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_block_pool_info_get.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_block_pool_prioritize.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_block_release.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_byte_allocate.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_byte_pool_create.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_byte_pool_delete.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_byte_pool_info_get.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_byte_pool_prioritize.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_byte_release.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_event_flags_create.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_event_flags_delete.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_event_flags_get.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_event_flags_info_get.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_event_flags_set.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_event_flags_set_notify.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_mutex_create.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_mutex_delete.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_mutex_get.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_mutex_info_get.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_mutex_prioritize.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_mutex_put.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_queue_create.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_queue_delete.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_queue_flush.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_queue_front_send.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_queue_info_get.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_queue_prioritize.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_queue_receive.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_queue_send.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_queue_send_notify.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_semaphore_ceiling_put.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_semaphore_create.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_semaphore_delete.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_semaphore_get.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_semaphore_info_get.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_semaphore_prioritize.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_semaphore_put.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_semaphore_put_notify.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_thread_create.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_thread_delete.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_thread_entry_exit_notify.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_thread_info_get.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_thread_preemption_change.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_thread_priority_change.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_thread_relinquish.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_thread_reset.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_thread_resume.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_thread_suspend.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_thread_terminate.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_thread_time_slice_change.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_thread_wait_abort.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_timer_activate.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_timer_change.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_timer_create.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_timer_deactivate.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_timer_delete.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_timer_info_get.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_application_request.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_callback_request.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_event_flags_notify_trampoline.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_file_load.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_in_place_load.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_internal_load.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_initialize.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_kernel_dispatch.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_maximum_module_priority_set.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_memory_load.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_object_allocate.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_object_deallocate.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_object_pointer_get.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_object_pointer_get_extended.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_object_pool_create.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_properties_get.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_queue_notify_trampoline.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_semaphore_notify_trampoline.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_start.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_stop.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_thread_create.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_thread_notify_trampoline.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_thread_reset.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_timer_notify_trampoline.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_unload.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_util.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../module_manager/src/txm_module_manager_alignment_adjust.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../module_manager/src/txm_module_manager_external_memory_enable.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../module_manager/src/txm_module_manager_memory_fault_handler.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../module_manager/src/txm_module_manager_memory_fault_notify.c
|
||||
armcc -g -O0 --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../module_manager/src/txm_module_manager_mm_register_setup.c
|
||||
armasm -g --cpreproc --cpu=cortex-m4 --fpu=vfpv4 --apcs=/interwork ../module_manager/src/txm_module_manager_thread_stack_build.S
|
||||
armasm -g --cpreproc --cpu=cortex-m4 --fpu=vfpv4 --apcs=/interwork ../module_manager/src/txm_module_manager_user_mode_entry.S
|
||||
|
||||
armar --create tx.a tx_thread_stack_build.o tx_thread_schedule.o tx_thread_system_return.o tx_thread_context_save.o tx_thread_context_restore.o tx_timer_interrupt.o tx_thread_interrupt_control.o tx_initialize_low_level.o tx_thread_interrupt_disable.o tx_thread_interrupt_restore.o tx_block_allocate.o tx_block_pool_cleanup.o tx_block_pool_create.o tx_block_pool_delete.o tx_block_pool_info_get.o tx_block_pool_initialize.o tx_block_pool_performance_info_get.o tx_block_pool_performance_system_info_get.o tx_block_pool_prioritize.o tx_block_release.o tx_byte_allocate.o tx_byte_pool_cleanup.o tx_byte_pool_create.o tx_byte_pool_delete.o tx_byte_pool_info_get.o tx_byte_pool_initialize.o tx_byte_pool_performance_info_get.o tx_byte_pool_performance_system_info_get.o tx_byte_pool_prioritize.o tx_byte_pool_search.o tx_byte_release.o tx_event_flags_cleanup.o tx_event_flags_create.o tx_event_flags_delete.o tx_event_flags_get.o tx_event_flags_info_get.o tx_event_flags_initialize.o tx_event_flags_performance_info_get.o
|
||||
|
||||
armar -r tx.a tx_event_flags_performance_system_info_get.o tx_event_flags_set.o tx_event_flags_set_notify.o tx_initialize_high_level.o tx_initialize_kernel_enter.o tx_initialize_kernel_setup.o tx_mutex_cleanup.o tx_mutex_create.o tx_mutex_delete.o tx_mutex_get.o tx_mutex_info_get.o tx_mutex_initialize.o tx_mutex_performance_info_get.o tx_mutex_performance_system_info_get.o tx_mutex_prioritize.o tx_mutex_priority_change.o tx_mutex_put.o tx_queue_cleanup.o tx_queue_create.o tx_queue_delete.o tx_queue_flush.o tx_queue_front_send.o tx_queue_info_get.o tx_queue_initialize.o tx_queue_performance_info_get.o tx_queue_performance_system_info_get.o tx_queue_prioritize.o tx_queue_receive.o tx_queue_send.o tx_queue_send_notify.o tx_semaphore_ceiling_put.o tx_semaphore_cleanup.o tx_semaphore_create.o tx_semaphore_delete.o tx_semaphore_get.o tx_semaphore_info_get.o tx_semaphore_initialize.o tx_semaphore_performance_info_get.o tx_semaphore_performance_system_info_get.o tx_semaphore_prioritize.o tx_semaphore_put.o
|
||||
|
||||
armar -r tx.a tx_semaphore_put_notify.o tx_thread_create.o tx_thread_delete.o tx_thread_entry_exit_notify.o tx_thread_identify.o tx_thread_info_get.o tx_thread_initialize.o tx_thread_performance_info_get.o tx_thread_performance_system_info_get.o tx_thread_preemption_change.o tx_thread_priority_change.o tx_thread_relinquish.o tx_thread_reset.o tx_thread_resume.o tx_thread_shell_entry.o tx_thread_sleep.o tx_thread_stack_analyze.o tx_thread_stack_error_handler.o tx_thread_stack_error_notify.o tx_thread_suspend.o tx_thread_system_preempt_check.o tx_thread_system_resume.o tx_thread_system_suspend.o tx_thread_terminate.o tx_thread_time_slice.o tx_thread_time_slice_change.o tx_thread_timeout.o tx_thread_wait_abort.o tx_time_get.o tx_time_set.o tx_timer_activate.o tx_timer_change.o tx_timer_create.o tx_timer_deactivate.o tx_timer_delete.o tx_timer_expiration_process.o tx_timer_info_get.o tx_timer_initialize.o tx_timer_performance_info_get.o tx_timer_performance_system_info_get.o tx_timer_system_activate.o
|
||||
|
||||
armar -r tx.a tx_timer_system_deactivate.o tx_timer_thread_entry.o tx_trace_enable.o tx_trace_disable.o tx_trace_initialize.o tx_trace_interrupt_control.o tx_trace_isr_enter_insert.o tx_trace_isr_exit_insert.o tx_trace_object_register.o tx_trace_object_unregister.o tx_trace_user_event_insert.o tx_trace_buffer_full_notify.o tx_trace_event_filter.o tx_trace_event_unfilter.o txe_block_allocate.o txe_block_pool_create.o txe_block_pool_delete.o txe_block_pool_info_get.o txe_block_pool_prioritize.o txe_block_release.o txe_byte_allocate.o txe_byte_pool_create.o txe_byte_pool_delete.o txe_byte_pool_info_get.o txe_byte_pool_prioritize.o txe_byte_release.o txe_event_flags_create.o txe_event_flags_delete.o txe_event_flags_get.o txe_event_flags_info_get.o txe_event_flags_set.o txe_event_flags_set_notify.o txe_mutex_create.o txe_mutex_delete.o txe_mutex_get.o txe_mutex_info_get.o txe_mutex_prioritize.o txe_mutex_put.o txe_queue_create.o txe_queue_delete.o txe_queue_flush.o txe_queue_front_send.o txe_queue_info_get.o
|
||||
|
||||
armar -r tx.a txe_queue_prioritize.o txe_queue_receive.o txe_queue_send.o txe_queue_send_notify.o txe_semaphore_ceiling_put.o txe_semaphore_create.o txe_semaphore_delete.o txe_semaphore_get.o txe_semaphore_info_get.o txe_semaphore_prioritize.o txe_semaphore_put.o txe_semaphore_put_notify.o txe_thread_create.o txe_thread_delete.o txe_thread_entry_exit_notify.o txe_thread_info_get.o txe_thread_preemption_change.o txe_thread_priority_change.o txe_thread_relinquish.o txe_thread_reset.o txe_thread_resume.o txe_thread_suspend.o txe_thread_terminate.o txe_thread_time_slice_change.o txe_thread_wait_abort.o txe_timer_activate.o txe_timer_change.o txe_timer_create.o txe_timer_deactivate.o txe_timer_delete.o txe_timer_info_get.o txm_module_manager_alignment_adjust.o txm_module_manager_application_request.o txm_module_manager_callback_request.o txm_module_manager_event_flags_notify_trampoline.o txm_module_manager_external_memory_enable.o txm_module_manager_file_load.o txm_module_manager_in_place_load.o
|
||||
|
||||
armar -r tx.a txm_module_manager_initialize.o txm_module_manager_kernel_dispatch.o txm_module_manager_maximum_module_priority_set.o txm_module_manager_memory_fault_handler.o txm_module_manager_memory_fault_notify.o txm_module_manager_memory_load.o txm_module_manager_object_pointer_get.o txm_module_manager_object_pool_create.o txm_module_manager_queue_notify_trampoline.o txm_module_manager_semaphore_notify_trampoline.o txm_module_manager_mm_register_setup.o txm_module_manager_start.o txm_module_manager_stop.o txm_module_manager_thread_create.o txm_module_manager_thread_notify_trampoline.o txm_module_manager_thread_reset.o txm_module_manager_timer_notify_trampoline.o txm_module_manager_unload.o txm_module_manager_thread_stack_build.o txm_module_manager_internal_load.o txm_module_manager_object_allocate.o txm_module_manager_object_deallocate.o txm_module_manager_object_pointer_get_extended.o txm_module_manager_properties_get.o txm_module_manager_util.o txm_module_manager_user_mode_entry.o
|
||||
|
||||
@@ -1,4 +1,4 @@
|
||||
armasm -g --cpu=cortex-m4 --apcs=interwork tx_initialize_low_level.S
|
||||
armasm -g --cpreproc --cpu=cortex-m4 --apcs=/interwork tx_initialize_low_level.S
|
||||
armcc -c -g --cpu=cortex-m4 -O2 -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc sample_threadx.c
|
||||
armlink -d -o sample_threadx.axf --elf --map --ro-base=0x00000000 --rw-base=0x20000000 --first __tx_vectors --datacompressor=off --inline --info=inline --callgraph --list sample_threadx.map tx_initialize_low_level.o sample_threadx.o tx.a
|
||||
|
||||
|
||||
@@ -1,3 +1,3 @@
|
||||
armasm -g --cpu=cortex-m4 --fpu=softvfp --apcs=/interwork/ropi/rwpi txm_module_preamble.S
|
||||
armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi --lower_ropi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc sample_threadx_module.c
|
||||
armasm -g --cpreproc --cpu=cortex-m4 --fpu=vfpv4 --apcs=/interwork/ropi/rwpi txm_module_preamble.S
|
||||
armcc -g --cpu=cortex-m4 --fpu=vfpv4 -c --apcs=/interwork/ropi/rwpi --lower_ropi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc sample_threadx_module.c
|
||||
armlink -d -o sample_threadx_module.axf --elf --ro=0x30000 --rw=0x40000 --first txm_module_preamble.o(Init) --entry=_txm_module_thread_shell_entry --ropi --rwpi --remove --map --symbols --list sample_threadx_module.map txm_module_preamble.o sample_threadx_module.o txm.a
|
||||
|
||||
@@ -1,106 +1,104 @@
|
||||
del txm.a
|
||||
|
||||
armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_block_allocate.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_block_pool_create.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_block_pool_delete.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_block_pool_info_get.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_block_pool_performance_info_get.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_block_pool_performance_system_info_get.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_block_pool_prioritize.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_block_release.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_byte_allocate.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_byte_pool_create.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_byte_pool_delete.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_byte_pool_info_get.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_byte_pool_performance_info_get.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_byte_pool_performance_system_info_get.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_byte_pool_prioritize.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_byte_release.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_event_flags_create.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_event_flags_delete.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_event_flags_get.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_event_flags_info_get.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_event_flags_performance_info_get.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_event_flags_performance_system_info_get.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_event_flags_set.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_event_flags_set_notify.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_module_application_request.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_module_callback_request_thread_entry.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_module_object_allocate.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_module_object_deallocate.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_module_object_pointer_get.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_module_thread_system_suspend.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_mutex_create.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_mutex_delete.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_mutex_get.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_mutex_info_get.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_mutex_performance_info_get.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_mutex_performance_system_info_get.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_mutex_prioritize.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_mutex_put.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_queue_create.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_queue_delete.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_queue_flush.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_queue_front_send.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_queue_info_get.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_queue_performance_info_get.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_queue_performance_system_info_get.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_queue_prioritize.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_queue_receive.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_queue_send.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_queue_send_notify.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_semaphore_ceiling_put.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_semaphore_create.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_semaphore_delete.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_semaphore_get.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_semaphore_info_get.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_semaphore_performance_info_get.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_semaphore_performance_system_info_get.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_semaphore_prioritize.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_semaphore_put.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_semaphore_put_notify.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_thread_create.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_thread_delete.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_thread_entry_exit_notify.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_thread_identify.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_thread_info_get.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_thread_interrupt_control.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_thread_performance_info_get.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_thread_performance_system_info_get.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_thread_preemption_change.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_thread_priority_change.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_thread_relinquish.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_thread_reset.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_thread_resume.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_thread_sleep.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_thread_stack_error_notify.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_thread_suspend.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_thread_terminate.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_thread_time_slice_change.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_thread_wait_abort.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_time_get.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_time_set.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_timer_activate.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_timer_change.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_timer_create.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_timer_deactivate.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_timer_delete.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_timer_info_get.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_timer_performance_info_get.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_timer_performance_system_info_get.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_trace_buffer_full_notify.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_trace_disable.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_trace_enable.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_trace_event_filter.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_trace_event_unfilter.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_trace_isr_enter_insert.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_trace_isr_exit_insert.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_trace_user_event_insert.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ..//module_lib/src/txm_module_thread_shell_entry.c
|
||||
armasm -g --cpu=cortex-m4 --fpu=softvfp --apcs=/interwork/ropi/rwpi --cpreproc --cpreproc_opts=-D,TXM_ASSEMBLY --cpreproc_opts=-D,TXM_MODULE_HEAP_SIZE=512 -I../inc ../module_lib/src/txm_module_initialize.S
|
||||
armcc -g --cpu=cortex-m4 --fpu=vfpv4 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_block_allocate.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=vfpv4 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_block_pool_create.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=vfpv4 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_block_pool_delete.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=vfpv4 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_block_pool_info_get.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=vfpv4 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_block_pool_performance_info_get.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=vfpv4 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_block_pool_performance_system_info_get.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=vfpv4 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_block_pool_prioritize.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=vfpv4 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_block_release.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=vfpv4 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_byte_allocate.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=vfpv4 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_byte_pool_create.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=vfpv4 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_byte_pool_delete.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=vfpv4 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_byte_pool_info_get.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=vfpv4 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_byte_pool_performance_info_get.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=vfpv4 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_byte_pool_performance_system_info_get.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=vfpv4 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_byte_pool_prioritize.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=vfpv4 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_byte_release.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=vfpv4 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_event_flags_create.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=vfpv4 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_event_flags_delete.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=vfpv4 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_event_flags_get.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=vfpv4 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_event_flags_info_get.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=vfpv4 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_event_flags_performance_info_get.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=vfpv4 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_event_flags_performance_system_info_get.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=vfpv4 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_event_flags_set.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=vfpv4 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_event_flags_set_notify.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=vfpv4 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_module_application_request.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=vfpv4 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_module_callback_request_thread_entry.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=vfpv4 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_module_object_allocate.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=vfpv4 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_module_object_deallocate.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=vfpv4 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_module_object_pointer_get.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=vfpv4 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_module_thread_system_suspend.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=vfpv4 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_mutex_create.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=vfpv4 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_mutex_delete.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=vfpv4 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_mutex_get.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=vfpv4 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_mutex_info_get.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=vfpv4 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_mutex_performance_info_get.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=vfpv4 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_mutex_performance_system_info_get.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=vfpv4 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_mutex_prioritize.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=vfpv4 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_mutex_put.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=vfpv4 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_queue_create.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=vfpv4 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_queue_delete.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=vfpv4 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_queue_flush.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=vfpv4 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_queue_front_send.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=vfpv4 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_queue_info_get.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=vfpv4 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_queue_performance_info_get.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=vfpv4 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_queue_performance_system_info_get.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=vfpv4 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_queue_prioritize.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=vfpv4 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_queue_receive.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=vfpv4 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_queue_send.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=vfpv4 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_queue_send_notify.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=vfpv4 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_semaphore_ceiling_put.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=vfpv4 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_semaphore_create.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=vfpv4 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_semaphore_delete.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=vfpv4 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_semaphore_get.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=vfpv4 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_semaphore_info_get.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=vfpv4 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_semaphore_performance_info_get.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=vfpv4 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_semaphore_performance_system_info_get.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=vfpv4 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_semaphore_prioritize.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=vfpv4 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_semaphore_put.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=vfpv4 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_semaphore_put_notify.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=vfpv4 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_thread_create.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=vfpv4 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_thread_delete.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=vfpv4 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_thread_entry_exit_notify.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=vfpv4 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_thread_identify.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=vfpv4 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_thread_info_get.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=vfpv4 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_thread_interrupt_control.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=vfpv4 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_thread_performance_info_get.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=vfpv4 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_thread_performance_system_info_get.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=vfpv4 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_thread_preemption_change.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=vfpv4 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_thread_priority_change.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=vfpv4 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_thread_relinquish.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=vfpv4 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_thread_reset.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=vfpv4 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_thread_resume.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=vfpv4 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_thread_sleep.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=vfpv4 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_thread_stack_error_notify.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=vfpv4 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_thread_suspend.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=vfpv4 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_thread_terminate.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=vfpv4 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_thread_time_slice_change.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=vfpv4 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_thread_wait_abort.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=vfpv4 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_time_get.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=vfpv4 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_time_set.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=vfpv4 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_timer_activate.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=vfpv4 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_timer_change.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=vfpv4 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_timer_create.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=vfpv4 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_timer_deactivate.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=vfpv4 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_timer_delete.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=vfpv4 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_timer_info_get.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=vfpv4 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_timer_performance_info_get.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=vfpv4 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_timer_performance_system_info_get.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=vfpv4 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_trace_buffer_full_notify.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=vfpv4 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_trace_disable.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=vfpv4 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_trace_enable.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=vfpv4 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_trace_event_filter.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=vfpv4 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_trace_event_unfilter.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=vfpv4 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_trace_isr_enter_insert.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=vfpv4 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_trace_isr_exit_insert.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=vfpv4 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_trace_user_event_insert.c
|
||||
armcc -g --cpu=cortex-m4 --fpu=vfpv4 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ..//module_lib/src/txm_module_thread_shell_entry.c
|
||||
armasm -g --cpreproc --cpu=cortex-m4 --fpu=vfpv4 --apcs=/interwork/ropi/rwpi --cpreproc --cpreproc_opts=-D,TXM_ASSEMBLY --cpreproc_opts=-D,TXM_MODULE_HEAP_SIZE=512 -I../inc ../module_lib/src/txm_module_initialize.S
|
||||
|
||||
armar --create txm.a txm_block_allocate.o txm_block_pool_create.o txm_block_pool_delete.o txm_block_pool_info_get.o txm_block_pool_performance_info_get.o txm_block_pool_performance_system_info_get.o txm_block_pool_prioritize.o txm_block_release.o txm_byte_allocate.o txm_byte_pool_create.o txm_byte_pool_delete.o txm_byte_pool_info_get.o txm_byte_pool_performance_info_get.o txm_byte_pool_performance_system_info_get.o txm_byte_pool_prioritize.o txm_byte_release.o txm_event_flags_create.o txm_event_flags_delete.o txm_event_flags_get.o txm_event_flags_info_get.o txm_event_flags_performance_info_get.o txm_event_flags_performance_system_info_get.o txm_event_flags_set.o txm_event_flags_set_notify.o txm_module_application_request.o txm_module_callback_request_thread_entry.o txm_module_initialize.o txm_module_object_allocate.o txm_module_object_deallocate.o txm_module_object_pointer_get.o txm_module_thread_shell_entry.o txm_module_thread_system_suspend.o txm_mutex_create.o txm_mutex_delete.o txm_mutex_get.o
|
||||
|
||||
armar -r txm.a txm_mutex_info_get.o txm_mutex_performance_info_get.o txm_mutex_performance_system_info_get.o txm_mutex_prioritize.o txm_mutex_put.o txm_queue_create.o txm_queue_delete.o txm_queue_flush.o txm_queue_front_send.o txm_queue_info_get.o txm_queue_performance_info_get.o txm_queue_performance_system_info_get.o txm_queue_prioritize.o txm_queue_receive.o txm_queue_send.o txm_queue_send_notify.o txm_semaphore_ceiling_put.o txm_semaphore_create.o txm_semaphore_delete.o txm_semaphore_get.o txm_semaphore_info_get.o txm_semaphore_performance_info_get.o txm_semaphore_performance_system_info_get.o txm_semaphore_prioritize.o txm_semaphore_put.o txm_semaphore_put_notify.o txm_thread_create.o txm_thread_delete.o txm_thread_entry_exit_notify.o txm_thread_identify.o txm_thread_info_get.o txm_thread_interrupt_control.o txm_thread_performance_info_get.o txm_thread_performance_system_info_get.o txm_thread_preemption_change.o txm_thread_priority_change.o txm_thread_relinquish.o txm_thread_reset.o txm_thread_resume.o
|
||||
|
||||
armar -r txm.a txm_thread_sleep.o txm_thread_stack_error_notify.o txm_thread_suspend.o txm_thread_terminate.o txm_thread_time_slice_change.o txm_thread_wait_abort.o txm_time_get.o txm_time_set.o txm_timer_activate.o txm_timer_change.o txm_timer_create.o txm_timer_deactivate.o txm_timer_delete.o txm_timer_info_get.o txm_timer_performance_info_get.o txm_timer_performance_system_info_get.o txm_trace_buffer_full_notify.o txm_trace_disable.o txm_trace_enable.o txm_trace_event_filter.o txm_trace_event_unfilter.o txm_trace_isr_enter_insert.o txm_trace_isr_exit_insert.o txm_trace_user_event_insert.o
|
||||
|
||||
@@ -1,3 +1,3 @@
|
||||
armasm -g --cpu=cortex-m4 --fpu=softvfp --apcs=interwork tx_initialize_low_level.S
|
||||
armcc -g --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc sample_threadx_module_manager.c
|
||||
armasm -g --cpreproc --cpu=cortex-m4 --fpu=vfpv4 --apcs=/interwork tx_initialize_low_level.S
|
||||
armcc -g --cpu=cortex-m4 --fpu=vfpv4 -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc sample_threadx_module_manager.c
|
||||
armlink -d -o sample_threadx_module_manager.axf --elf --ro 0x00000000 --first tx_initialize_low_level.o(RESET) --remove --map --symbols --list sample_threadx_module_manager.map tx_initialize_low_level.o sample_threadx_module_manager.o tx.a
|
||||
|
||||
@@ -1,36 +1,25 @@
|
||||
;/**************************************************************************/
|
||||
;/* */
|
||||
;/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
;/* */
|
||||
;/* This software is licensed under the Microsoft Software License */
|
||||
;/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
;/* and in the root directory of this software. */
|
||||
;/* */
|
||||
;/**************************************************************************/
|
||||
;
|
||||
;
|
||||
;/**************************************************************************/
|
||||
;/**************************************************************************/
|
||||
;/** */
|
||||
;/** ThreadX Component */
|
||||
;/** */
|
||||
;/** Initialize */
|
||||
;/** */
|
||||
;/**************************************************************************/
|
||||
;/**************************************************************************/
|
||||
;
|
||||
;#define TX_SOURCE_CODE
|
||||
;
|
||||
;
|
||||
;/* Include necessary system files. */
|
||||
;
|
||||
;#include "tx_api.h"
|
||||
;#include "tx_initialize.h"
|
||||
;#include "tx_thread.h"
|
||||
;#include "tx_timer.h"
|
||||
;
|
||||
;
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
/* */
|
||||
/* This software is licensed under the Microsoft Software License */
|
||||
/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
/* and in the root directory of this software. */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
/** */
|
||||
/** ThreadX Component */
|
||||
/** */
|
||||
/** Initialize */
|
||||
/** */
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
|
||||
IMPORT _tx_thread_system_stack_ptr
|
||||
IMPORT _tx_initialize_unused_memory
|
||||
IMPORT _tx_thread_context_save
|
||||
@@ -44,14 +33,12 @@
|
||||
IMPORT __tx_PendSVHandler
|
||||
IMPORT __tx_SVCallHandler
|
||||
IMPORT MemManage_Handler
|
||||
;
|
||||
;
|
||||
|
||||
SYSTEM_CLOCK EQU 6000000
|
||||
SYSTICK_CYCLES EQU ((SYSTEM_CLOCK / 100) -1)
|
||||
;
|
||||
;
|
||||
;/* Setup the stack and heap areas. */
|
||||
;
|
||||
|
||||
/* Setup the stack and heap areas. */
|
||||
|
||||
STACK_SIZE EQU 0x00000400
|
||||
HEAP_SIZE EQU 0x00000000
|
||||
|
||||
@@ -69,156 +56,156 @@ __heap_limit
|
||||
|
||||
|
||||
AREA RESET, CODE, READONLY
|
||||
;
|
||||
|
||||
EXPORT __tx_vectors
|
||||
EXPORT __vector_table
|
||||
__vector_table
|
||||
__tx_vectors
|
||||
DCD __initial_sp ; Reset and system stack ptr
|
||||
DCD Reset_Handler ; Reset goes to startup function
|
||||
DCD __tx_NMIHandler ; NMI
|
||||
DCD __tx_BadHandler ; HardFault
|
||||
DCD MemManage_Handler ; MemManage
|
||||
DCD 0 ; BusFault
|
||||
DCD 0 ; UsageFault
|
||||
DCD 0 ; 7
|
||||
DCD 0 ; 8
|
||||
DCD 0 ; 9
|
||||
DCD 0 ; 10
|
||||
DCD __tx_SVCallHandler ; SVCall
|
||||
DCD __tx_DBGHandler ; Monitor
|
||||
DCD 0 ; 13
|
||||
DCD __tx_PendSVHandler ; PendSV
|
||||
DCD __tx_SysTickHandler ; SysTick
|
||||
DCD __tx_IntHandler ; Int 0
|
||||
DCD __tx_IntHandler ; Int 1
|
||||
DCD __tx_IntHandler ; Int 2
|
||||
DCD __tx_IntHandler ; Int 3
|
||||
|
||||
;
|
||||
;
|
||||
DCD __initial_sp // Reset and system stack ptr
|
||||
DCD Reset_Handler // Reset goes to startup function
|
||||
DCD __tx_NMIHandler // NMI
|
||||
DCD __tx_BadHandler // HardFault
|
||||
DCD MemManage_Handler // MemManage
|
||||
DCD 0 // BusFault
|
||||
DCD 0 // UsageFault
|
||||
DCD 0 // 7
|
||||
DCD 0 // 8
|
||||
DCD 0 // 9
|
||||
DCD 0 // 10
|
||||
DCD __tx_SVCallHandler // SVCall
|
||||
DCD __tx_DBGHandler // Monitor
|
||||
DCD 0 // 13
|
||||
DCD __tx_PendSVHandler // PendSV
|
||||
DCD __tx_SysTickHandler // SysTick
|
||||
DCD __tx_IntHandler // Int 0
|
||||
DCD __tx_IntHandler // Int 1
|
||||
DCD __tx_IntHandler // Int 2
|
||||
DCD __tx_IntHandler // Int 3
|
||||
|
||||
AREA ||.text||, CODE, READONLY
|
||||
EXPORT Reset_Handler
|
||||
Reset_Handler
|
||||
CPSID i
|
||||
IF {TARGET_FPU_VFP} = {TRUE}
|
||||
LDR r0, =0xE000ED88 ; Pickup address of CPACR
|
||||
LDR r1, [r0] ; Pickup CPACR
|
||||
MOV32 r2, 0x00F00000 ; Build enable value
|
||||
ORR r1, r1, r2 ; Or in enable value
|
||||
STR r1, [r0] ; Setup CPACR
|
||||
LDR r0, =0xE000ED88 // Pickup address of CPACR
|
||||
LDR r1, [r0] // Pickup CPACR
|
||||
MOV32 r2, 0x00F00000 // Build enable value
|
||||
ORR r1, r1, r2 // Or in enable value
|
||||
STR r1, [r0] // Setup CPACR
|
||||
ENDIF
|
||||
LDR r0, =__main
|
||||
BX r0
|
||||
|
||||
|
||||
;/**************************************************************************/
|
||||
;/* */
|
||||
;/* FUNCTION RELEASE */
|
||||
;/* */
|
||||
;/* _tx_initialize_low_level Cortex-M4/MPU/AC5 */
|
||||
;/* 6.1 */
|
||||
;/* AUTHOR */
|
||||
;/* */
|
||||
;/* Scott Larson, Microsoft Corporation */
|
||||
;/* */
|
||||
;/* DESCRIPTION */
|
||||
;/* */
|
||||
;/* This function is responsible for any low-level processor */
|
||||
;/* initialization, including setting up interrupt vectors, setting */
|
||||
;/* up a periodic timer interrupt source, saving the system stack */
|
||||
;/* pointer for use in ISR processing later, and finding the first */
|
||||
;/* available RAM memory address for tx_application_define. */
|
||||
;/* */
|
||||
;/* INPUT */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* OUTPUT */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* CALLS */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* CALLED BY */
|
||||
;/* */
|
||||
;/* _tx_initialize_kernel_enter ThreadX entry function */
|
||||
;/* */
|
||||
;/* RELEASE HISTORY */
|
||||
;/* */
|
||||
;/* DATE NAME DESCRIPTION */
|
||||
;/* */
|
||||
;/* 09-30-2020 Scott Larson Initial Version 6.1 */
|
||||
;/* */
|
||||
;/**************************************************************************/
|
||||
;VOID _tx_initialize_low_level(VOID)
|
||||
;{
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* FUNCTION RELEASE */
|
||||
/* */
|
||||
/* _tx_initialize_low_level Cortex-M4/MPU/AC5 */
|
||||
/* 6.1.2 */
|
||||
/* AUTHOR */
|
||||
/* */
|
||||
/* Scott Larson, Microsoft Corporation */
|
||||
/* */
|
||||
/* DESCRIPTION */
|
||||
/* */
|
||||
/* This function is responsible for any low-level processor */
|
||||
/* initialization, including setting up interrupt vectors, setting */
|
||||
/* up a periodic timer interrupt source, saving the system stack */
|
||||
/* pointer for use in ISR processing later, and finding the first */
|
||||
/* available RAM memory address for tx_application_define. */
|
||||
/* */
|
||||
/* INPUT */
|
||||
/* */
|
||||
/* None */
|
||||
/* */
|
||||
/* OUTPUT */
|
||||
/* */
|
||||
/* None */
|
||||
/* */
|
||||
/* CALLS */
|
||||
/* */
|
||||
/* None */
|
||||
/* */
|
||||
/* CALLED BY */
|
||||
/* */
|
||||
/* _tx_initialize_kernel_enter ThreadX entry function */
|
||||
/* */
|
||||
/* RELEASE HISTORY */
|
||||
/* */
|
||||
/* DATE NAME DESCRIPTION */
|
||||
/* */
|
||||
/* 09-30-2020 Scott Larson Initial Version 6.1 */
|
||||
/* 11-09-2020 Scott Larson Modified comment(s), */
|
||||
/* resulting in version 6.1.2 */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
// VOID _tx_initialize_low_level(VOID)
|
||||
// {
|
||||
EXPORT _tx_initialize_low_level
|
||||
_tx_initialize_low_level
|
||||
;
|
||||
; /* Disable interrupts during ThreadX initialization. */
|
||||
;
|
||||
|
||||
/* Disable interrupts during ThreadX initialization. */
|
||||
|
||||
CPSID i
|
||||
;
|
||||
; /* Set base of available memory to end of non-initialised RAM area. */
|
||||
;
|
||||
LDR r0, =_tx_initialize_unused_memory ; Build address of unused memory pointer
|
||||
LDR r1, =|Image$$ZI$$Limit| ; Build first free address
|
||||
ADD r1, r1, #4 ;
|
||||
STR r1, [r0] ; Setup first unused memory pointer
|
||||
;
|
||||
; /* Setup Vector Table Offset Register. */
|
||||
;
|
||||
MOV r0, #0xE000E000 ; Build address of NVIC registers
|
||||
LDR r1, =__tx_vectors ; Pickup address of vector table
|
||||
STR r1, [r0, #0xD08] ; Set vector table address
|
||||
;
|
||||
; /* Enable the cycle count register. */
|
||||
;
|
||||
; LDR r0, =0xE0001000 ; Build address of DWT register
|
||||
; LDR r1, [r0] ; Pickup the current value
|
||||
; ORR r1, r1, #1 ; Set the CYCCNTENA bit
|
||||
; STR r1, [r0] ; Enable the cycle count register
|
||||
;
|
||||
; /* Set system stack pointer from vector value. */
|
||||
;
|
||||
LDR r0, =_tx_thread_system_stack_ptr ; Build address of system stack pointer
|
||||
LDR r1, =__tx_vectors ; Pickup address of vector table
|
||||
LDR r1, [r1] ; Pickup reset stack pointer
|
||||
STR r1, [r0] ; Save system stack pointer
|
||||
;
|
||||
; /* Configure SysTick. */
|
||||
;
|
||||
MOV r0, #0xE000E000 ; Build address of NVIC registers
|
||||
|
||||
/* Set base of available memory to end of non-initialised RAM area. */
|
||||
|
||||
LDR r0, =_tx_initialize_unused_memory // Build address of unused memory pointer
|
||||
LDR r1, =|Image$$ZI$$Limit| // Build first free address
|
||||
ADD r1, r1, #4 //
|
||||
STR r1, [r0] // Setup first unused memory pointer
|
||||
|
||||
/* Setup Vector Table Offset Register. */
|
||||
|
||||
MOV r0, #0xE000E000 // Build address of NVIC registers
|
||||
LDR r1, =__tx_vectors // Pickup address of vector table
|
||||
STR r1, [r0, #0xD08] // Set vector table address
|
||||
|
||||
/* Enable the cycle count register. */
|
||||
|
||||
// LDR r0, =0xE0001000 // Build address of DWT register
|
||||
// LDR r1, [r0] // Pickup the current value
|
||||
// ORR r1, r1, #1 // Set the CYCCNTENA bit
|
||||
// STR r1, [r0] // Enable the cycle count register
|
||||
|
||||
/* Set system stack pointer from vector value. */
|
||||
|
||||
LDR r0, =_tx_thread_system_stack_ptr // Build address of system stack pointer
|
||||
LDR r1, =__tx_vectors // Pickup address of vector table
|
||||
LDR r1, [r1] // Pickup reset stack pointer
|
||||
STR r1, [r0] // Save system stack pointer
|
||||
|
||||
/* Configure SysTick. */
|
||||
|
||||
MOV r0, #0xE000E000 // Build address of NVIC registers
|
||||
LDR r1, =SYSTICK_CYCLES
|
||||
STR r1, [r0, #0x14] ; Setup SysTick Reload Value
|
||||
MOV r1, #0x7 ; Build SysTick Control Enable Value
|
||||
STR r1, [r0, #0x10] ; Setup SysTick Control
|
||||
;
|
||||
; /* Configure handler priorities. */
|
||||
;
|
||||
LDR r1, =0x00000000 ; Rsrv, UsgF, BusF, MemM
|
||||
STR r1, [r0, #0xD18] ; Setup System Handlers 4-7 Priority Registers
|
||||
STR r1, [r0, #0x14] // Setup SysTick Reload Value
|
||||
MOV r1, #0x7 // Build SysTick Control Enable Value
|
||||
STR r1, [r0, #0x10] // Setup SysTick Control
|
||||
|
||||
LDR r1, =0xFF000000 ; SVCl, Rsrv, Rsrv, Rsrv
|
||||
STR r1, [r0, #0xD1C] ; Setup System Handlers 8-11 Priority Registers
|
||||
; Note: SVC must be lowest priority, which is 0xFF
|
||||
/* Configure handler priorities. */
|
||||
|
||||
LDR r1, =0x00000000 // Rsrv, UsgF, BusF, MemM
|
||||
STR r1, [r0, #0xD18] // Setup System Handlers 4-7 Priority Registers
|
||||
|
||||
LDR r1, =0xFF000000 // SVCl, Rsrv, Rsrv, Rsrv
|
||||
STR r1, [r0, #0xD1C] // Setup System Handlers 8-11 Priority Registers
|
||||
// Note: SVC must be lowest priority, which is 0xFF
|
||||
|
||||
LDR r1, =0x40FF0000 // SysT, PnSV, Rsrv, DbgM
|
||||
STR r1, [r0, #0xD20] // Setup System Handlers 12-15 Priority Registers
|
||||
// Note: PnSV must be lowest priority, which is 0xFF
|
||||
|
||||
/* Return to caller. */
|
||||
|
||||
LDR r1, =0x40FF0000 ; SysT, PnSV, Rsrv, DbgM
|
||||
STR r1, [r0, #0xD20] ; Setup System Handlers 12-15 Priority Registers
|
||||
; Note: PnSV must be lowest priority, which is 0xFF
|
||||
;
|
||||
; /* Return to caller. */
|
||||
;
|
||||
BX lr
|
||||
;}
|
||||
;
|
||||
;
|
||||
;/* Define initial heap/stack routine for the ARM RVCT startup code.
|
||||
; This routine will set the initial stack and heap locations */
|
||||
;
|
||||
// }
|
||||
|
||||
|
||||
/* Define initial heap/stack routine for the ARM RVCT startup code.
|
||||
This routine will set the initial stack and heap locations */
|
||||
|
||||
EXPORT __user_initial_stackheap
|
||||
__user_initial_stackheap
|
||||
LDR r0, =HeapMem
|
||||
@@ -226,41 +213,40 @@ __user_initial_stackheap
|
||||
LDR r2, =(HeapMem + HEAP_SIZE)
|
||||
LDR r3, =StackMem
|
||||
BX lr
|
||||
;
|
||||
;
|
||||
;/* Define shells for each of the unused vectors. */
|
||||
;
|
||||
|
||||
/* Define shells for each of the unused vectors. */
|
||||
|
||||
EXPORT __tx_BadHandler
|
||||
__tx_BadHandler
|
||||
B __tx_BadHandler
|
||||
|
||||
; EXPORT __tx_SVCallHandler
|
||||
;__tx_SVCallHandler
|
||||
; B __tx_SVCallHandler
|
||||
// EXPORT __tx_SVCallHandler
|
||||
//__tx_SVCallHandler
|
||||
// B __tx_SVCallHandler
|
||||
|
||||
EXPORT __tx_IntHandler
|
||||
__tx_IntHandler
|
||||
; VOID InterruptHandler (VOID)
|
||||
; {
|
||||
PUSH {lr}
|
||||
|
||||
; /* Do interrupt handler work here */
|
||||
; /* .... */
|
||||
// VOID InterruptHandler (VOID)
|
||||
// {
|
||||
PUSH {r0, lr}
|
||||
|
||||
POP {lr}
|
||||
/* Do interrupt handler work here */
|
||||
/* .... */
|
||||
|
||||
POP {r0, lr}
|
||||
BX LR
|
||||
; }
|
||||
// }
|
||||
|
||||
EXPORT __tx_SysTickHandler
|
||||
__tx_SysTickHandler
|
||||
; VOID TimerInterruptHandler (VOID)
|
||||
; {
|
||||
;
|
||||
PUSH {lr}
|
||||
// VOID TimerInterruptHandler (VOID)
|
||||
// {
|
||||
|
||||
PUSH {r0, lr}
|
||||
BL _tx_timer_interrupt
|
||||
POP {lr}
|
||||
POP {r0, lr}
|
||||
BX LR
|
||||
; }
|
||||
// }
|
||||
|
||||
EXPORT __tx_NMIHandler
|
||||
__tx_NMIHandler
|
||||
@@ -281,5 +267,3 @@ _tx_execution_thread_exit
|
||||
ALIGN
|
||||
LTORG
|
||||
END
|
||||
|
||||
|
||||
|
||||
@@ -2,7 +2,7 @@
|
||||
|
||||
PRESERVE8
|
||||
|
||||
; Define public symbols
|
||||
/* Define public symbols. */
|
||||
|
||||
EXPORT __txm_module_preamble
|
||||
|
||||
@@ -12,7 +12,7 @@
|
||||
EXTERN demo_module_start
|
||||
|
||||
|
||||
; Define common external references
|
||||
/* Define common external references. */
|
||||
|
||||
IMPORT _txm_module_thread_shell_entry
|
||||
IMPORT _txm_module_callback_request_thread_entry
|
||||
@@ -23,47 +23,48 @@
|
||||
IMPORT |Image$$ER_ZI$$ZI$$Length|
|
||||
|
||||
__txm_module_preamble
|
||||
DCD 0x4D4F4455 ; Module ID
|
||||
DCD 0x6 ; Module Major Version
|
||||
DCD 0x1 ; Module Minor Version
|
||||
DCD 32 ; Module Preamble Size in 32-bit words
|
||||
DCD 0x12345678 ; Module ID (application defined)
|
||||
DCD 0x01000007 ; Module Properties where:
|
||||
; Bits 31-24: Compiler ID
|
||||
; 0 -> IAR
|
||||
; 1 -> ARM
|
||||
; 2 -> GNU
|
||||
; Bit 0: 0 -> Privileged mode execution
|
||||
; 1 -> User mode execution
|
||||
; Bit 1: 0 -> No MPU protection
|
||||
; 1 -> MPU protection (must have user mode selected)
|
||||
; Bit 2: 0 -> Disable shared/external memory access
|
||||
; 1 -> Enable shared/external memory access
|
||||
DCD _txm_module_thread_shell_entry - __txm_module_preamble ; Module Shell Entry Point
|
||||
DCD demo_module_start - __txm_module_preamble ; Module Start Thread Entry Point
|
||||
DCD 0 ; Module Stop Thread Entry Point
|
||||
DCD 1 ; Module Start/Stop Thread Priority
|
||||
DCD 1024 ; Module Start/Stop Thread Stack Size
|
||||
DCD _txm_module_callback_request_thread_entry - __txm_module_preamble ; Module Callback Thread Entry
|
||||
DCD 1 ; Module Callback Thread Priority
|
||||
DCD 1024 ; Module Callback Thread Stack Size
|
||||
DCD |Image$$ER_RO$$Length| + |Image$$ER_RW$$Length| ; Module Code Size
|
||||
DCD |Image$$ER_RW$$Length| + |Image$$ER_ZI$$ZI$$Length| ; Module Data Size
|
||||
DCD 0 ; Reserved 0
|
||||
DCD 0 ; Reserved 1
|
||||
DCD 0 ; Reserved 2
|
||||
DCD 0 ; Reserved 3
|
||||
DCD 0 ; Reserved 4
|
||||
DCD 0 ; Reserved 5
|
||||
DCD 0 ; Reserved 6
|
||||
DCD 0 ; Reserved 7
|
||||
DCD 0 ; Reserved 8
|
||||
DCD 0 ; Reserved 9
|
||||
DCD 0 ; Reserved 10
|
||||
DCD 0 ; Reserved 11
|
||||
DCD 0 ; Reserved 12
|
||||
DCD 0 ; Reserved 13
|
||||
DCD 0 ; Reserved 14
|
||||
DCD 0 ; Reserved 15
|
||||
DCD 0x4D4F4455 // Module ID
|
||||
DCD 0x6 // Module Major Version
|
||||
DCD 0x1 // Module Minor Version
|
||||
DCD 32 // Module Preamble Size in 32-bit words
|
||||
DCD 0x12345678 // Module ID (application defined)
|
||||
DCD 0x01000007 // Module Properties where:
|
||||
// Bits 31-24: Compiler ID
|
||||
// 0 -> IAR
|
||||
// 1 -> ARM
|
||||
// 2 -> GNU
|
||||
// Bits 23-3: Reserved
|
||||
// Bit 2: 0 -> Disable shared/external memory access
|
||||
// 1 -> Enable shared/external memory access
|
||||
// Bit 1: 0 -> No MPU protection
|
||||
// 1 -> MPU protection (must have user mode selected)
|
||||
// Bit 0: 0 -> Privileged mode execution
|
||||
// 1 -> User mode execution
|
||||
DCD _txm_module_thread_shell_entry - __txm_module_preamble // Module Shell Entry Point
|
||||
DCD demo_module_start - __txm_module_preamble // Module Start Thread Entry Point
|
||||
DCD 0 // Module Stop Thread Entry Point
|
||||
DCD 1 // Module Start/Stop Thread Priority
|
||||
DCD 1024 // Module Start/Stop Thread Stack Size
|
||||
DCD _txm_module_callback_request_thread_entry - __txm_module_preamble // Module Callback Thread Entry
|
||||
DCD 1 // Module Callback Thread Priority
|
||||
DCD 1024 // Module Callback Thread Stack Size
|
||||
DCD |Image$$ER_RO$$Length| + |Image$$ER_RW$$Length| // Module Code Size
|
||||
DCD |Image$$ER_RW$$Length| + |Image$$ER_ZI$$ZI$$Length| // Module Data Size
|
||||
DCD 0 // Reserved 0
|
||||
DCD 0 // Reserved 1
|
||||
DCD 0 // Reserved 2
|
||||
DCD 0 // Reserved 3
|
||||
DCD 0 // Reserved 4
|
||||
DCD 0 // Reserved 5
|
||||
DCD 0 // Reserved 6
|
||||
DCD 0 // Reserved 7
|
||||
DCD 0 // Reserved 8
|
||||
DCD 0 // Reserved 9
|
||||
DCD 0 // Reserved 10
|
||||
DCD 0 // Reserved 11
|
||||
DCD 0 // Reserved 12
|
||||
DCD 0 // Reserved 13
|
||||
DCD 0 // Reserved 14
|
||||
DCD 0 // Reserved 15
|
||||
|
||||
END
|
||||
|
||||
@@ -26,7 +26,7 @@
|
||||
/* APPLICATION INTERFACE DEFINITION RELEASE */
|
||||
/* */
|
||||
/* txm_module_port.h Cortex-M4/MPU/AC5 */
|
||||
/* 6.1 */
|
||||
/* 6.1.2 */
|
||||
/* AUTHOR */
|
||||
/* */
|
||||
/* Scott Larson, Microsoft Corporation */
|
||||
@@ -41,6 +41,9 @@
|
||||
/* DATE NAME DESCRIPTION */
|
||||
/* */
|
||||
/* 09-30-2020 Scott Larson Initial Version 6.1 */
|
||||
/* 11-09-2020 Scott Larson Modified comment(s), */
|
||||
/* increase kernel stack size, */
|
||||
/* resulting in version 6.1.2 */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
|
||||
@@ -98,19 +101,9 @@ The following extensions must also be defined in tx_port.h:
|
||||
|
||||
/* Define the kernel stack size for a module thread. */
|
||||
#ifndef TXM_MODULE_KERNEL_STACK_SIZE
|
||||
#define TXM_MODULE_KERNEL_STACK_SIZE 512
|
||||
#define TXM_MODULE_KERNEL_STACK_SIZE 768
|
||||
#endif
|
||||
|
||||
/* For the following 3 access control settings, change TEX and C, B, S (bits 21 through 16 of MPU_RASR)
|
||||
* to reflect your system memory attributes (cache, shareable, memory type). */
|
||||
/* Code region access control: privileged read-only, outer & inner write-back, normal memory, shareable. */
|
||||
#define TXM_MODULE_MPU_CODE_ACCESS_CONTROL 0x06070000
|
||||
/* Data region access control: execute never, read/write, outer & inner write-back, normal memory, shareable. */
|
||||
#define TXM_MODULE_MPU_DATA_ACCESS_CONTROL 0x13070000
|
||||
/* Shared region access control: execute never, read-only, outer & inner write-back, normal memory, shareable. */
|
||||
#define TXM_MODULE_MPU_SHARED_ACCESS_CONTROL 0x12070000
|
||||
|
||||
|
||||
/* Define constants specific to the tools the module can be built with for this particular modules port. */
|
||||
|
||||
#define TXM_MODULE_IAR_COMPILER 0x00000000
|
||||
@@ -165,9 +158,9 @@ The following extensions must also be defined in tx_port.h:
|
||||
|
||||
#define INLINE_DECLARE inline
|
||||
|
||||
/* Define the number of MPU entries assigned to the code and data sections. On Cortex-M parts, there can only be 7 total
|
||||
entries, since ThreadX uses one for access to the kernel dispatch function. */
|
||||
|
||||
/* Define the number of MPU entries assigned to the code and data sections.
|
||||
On Cortex-M4 parts, there are 8 total entries. ThreadX uses one for access
|
||||
to the kernel entry function, thus 7 remain for code and data protection. */
|
||||
#define TXM_MODULE_MANAGER_CODE_MPU_ENTRIES 4
|
||||
#define TXM_MODULE_MANAGER_DATA_MPU_ENTRIES 3
|
||||
#define TXM_MODULE_MANAGER_SHARED_MPU_INDEX 8
|
||||
@@ -333,6 +326,6 @@ ULONG _txm_module_manager_region_size_get(ULONG block_size);
|
||||
|
||||
#define TXM_MODULE_MANAGER_VERSION_ID \
|
||||
CHAR _txm_module_manager_version_id[] = \
|
||||
"Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M4/MPU/AC5 Version 6.1 *";
|
||||
"Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M4/MPU/AC5 Version 6.1.2 *";
|
||||
|
||||
#endif
|
||||
|
||||
@@ -1,97 +1,96 @@
|
||||
;/**************************************************************************/
|
||||
;/* */
|
||||
;/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
;/* */
|
||||
;/* This software is licensed under the Microsoft Software License */
|
||||
;/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
;/* and in the root directory of this software. */
|
||||
;/* */
|
||||
;/**************************************************************************/
|
||||
;
|
||||
;
|
||||
;/**************************************************************************/
|
||||
;/**************************************************************************/
|
||||
;/** */
|
||||
;/** ThreadX Component */
|
||||
;/** */
|
||||
;/** Module */
|
||||
;/** */
|
||||
;/**************************************************************************/
|
||||
;/**************************************************************************/
|
||||
;
|
||||
;
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
/* */
|
||||
/* This software is licensed under the Microsoft Software License */
|
||||
/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
/* and in the root directory of this software. */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
/** */
|
||||
/** ThreadX Component */
|
||||
/** */
|
||||
/** Module */
|
||||
/** */
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
|
||||
IMPORT __use_two_region_memory
|
||||
IMPORT __scatterload
|
||||
IMPORT txm_heap
|
||||
|
||||
AREA ||.text||, CODE, READONLY
|
||||
;/**************************************************************************/
|
||||
;/* */
|
||||
;/* FUNCTION RELEASE */
|
||||
;/* */
|
||||
;/* _txm_module_initialize Cortex-M4/MPU/AC5 */
|
||||
;/* 6.1 */
|
||||
;/* AUTHOR */
|
||||
;/* */
|
||||
;/* Scott Larson, Microsoft Corporation */
|
||||
;/* */
|
||||
;/* DESCRIPTION */
|
||||
;/* */
|
||||
;/* This function initializes the module c runtime. */
|
||||
;/* */
|
||||
;/* INPUT */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* OUTPUT */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* CALLS */
|
||||
;/* */
|
||||
;/* __scatterload Initialize C runtime */
|
||||
;/* */
|
||||
;/* CALLED BY */
|
||||
;/* */
|
||||
;/* _txm_module_thread_shell_entry Start module thread */
|
||||
;/* */
|
||||
;/* RELEASE HISTORY */
|
||||
;/* */
|
||||
;/* DATE NAME DESCRIPTION */
|
||||
;/* */
|
||||
;/* 09-30-2020 Scott Larson Initial Version 6.1 */
|
||||
;/* */
|
||||
;/**************************************************************************/
|
||||
;VOID _txm_module_initialize(VOID)
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* FUNCTION RELEASE */
|
||||
/* */
|
||||
/* _txm_module_initialize Cortex-M4/MPU/AC5 */
|
||||
/* 6.1.2 */
|
||||
/* AUTHOR */
|
||||
/* */
|
||||
/* Scott Larson, Microsoft Corporation */
|
||||
/* */
|
||||
/* DESCRIPTION */
|
||||
/* */
|
||||
/* This function initializes the module c runtime. */
|
||||
/* */
|
||||
/* INPUT */
|
||||
/* */
|
||||
/* None */
|
||||
/* */
|
||||
/* OUTPUT */
|
||||
/* */
|
||||
/* None */
|
||||
/* */
|
||||
/* CALLS */
|
||||
/* */
|
||||
/* __scatterload Initialize C runtime */
|
||||
/* */
|
||||
/* CALLED BY */
|
||||
/* */
|
||||
/* _txm_module_thread_shell_entry Start module thread */
|
||||
/* */
|
||||
/* RELEASE HISTORY */
|
||||
/* */
|
||||
/* DATE NAME DESCRIPTION */
|
||||
/* */
|
||||
/* 09-30-2020 Scott Larson Initial Version 6.1 */
|
||||
/* 11-09-2020 Scott Larson Modified comment(s), */
|
||||
/* resulting in version 6.1.2 */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
// VOID _txm_module_initialize(VOID)
|
||||
|
||||
EXPORT _txm_module_initialize
|
||||
_txm_module_initialize
|
||||
PUSH {r4-r12,lr} ; Save dregs and LR
|
||||
PUSH {r4-r12,lr} // Save dregs and LR
|
||||
|
||||
B __scatterload ; Call ARM func to initialize variables
|
||||
B __scatterload // Call ARM func to initialize variables
|
||||
|
||||
|
||||
/* Override __rt_exit function. */
|
||||
|
||||
;
|
||||
;/* Override __rt_exit function. */
|
||||
;
|
||||
EXPORT __rt_exit
|
||||
__rt_exit
|
||||
|
||||
POP {r4-r12,lr} ; Restore dregs and LR
|
||||
BX lr ; Return to caller
|
||||
;
|
||||
;
|
||||
;
|
||||
POP {r4-r12,lr} // Restore dregs and LR
|
||||
BX lr // Return to caller
|
||||
|
||||
EXPORT __user_setup_stackheap
|
||||
; returns heap start address in R0
|
||||
; returns heap end address in R2
|
||||
; does not touch SP, it is already set up before the module runs
|
||||
// returns heap start address in R0
|
||||
// returns heap end address in R2
|
||||
// does not touch SP, it is already set up before the module runs
|
||||
|
||||
__user_setup_stackheap
|
||||
LDR r1, _tx_heap_offset ; load heap offset
|
||||
ADD r0, r9, r1 ; calculate heap base address
|
||||
MOV r2, #TXM_MODULE_HEAP_SIZE ; load heap size
|
||||
ADD r2, r2, r0 ; calculate heap end address
|
||||
LDR r1, _tx_heap_offset // load heap offset
|
||||
ADD r0, r9, r1 // calculate heap base address
|
||||
MOV r2, #TXM_MODULE_HEAP_SIZE // load heap size
|
||||
ADD r2, r2, r0 // calculate heap end address
|
||||
BX lr
|
||||
|
||||
ALIGN 4
|
||||
@@ -101,9 +100,9 @@ _tx_heap_offset
|
||||
|
||||
IMPORT txm_heap [DATA]
|
||||
|
||||
;
|
||||
; Dummy main function
|
||||
;
|
||||
|
||||
// Dummy main function
|
||||
|
||||
AREA section_main, CODE, READONLY, ALIGN=2
|
||||
EXPORT main
|
||||
main
|
||||
|
||||
@@ -1,91 +1,86 @@
|
||||
;/**************************************************************************/
|
||||
;/* */
|
||||
;/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
;/* */
|
||||
;/* This software is licensed under the Microsoft Software License */
|
||||
;/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
;/* and in the root directory of this software. */
|
||||
;/* */
|
||||
;/**************************************************************************/
|
||||
;
|
||||
;
|
||||
;/**************************************************************************/
|
||||
;/**************************************************************************/
|
||||
;/** */
|
||||
;/** ThreadX Component */
|
||||
;/** */
|
||||
;/** Thread */
|
||||
;/** */
|
||||
;/**************************************************************************/
|
||||
;/**************************************************************************/
|
||||
;
|
||||
;
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
/* */
|
||||
/* This software is licensed under the Microsoft Software License */
|
||||
/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
/* and in the root directory of this software. */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
/** */
|
||||
/** ThreadX Component */
|
||||
/** */
|
||||
/** Thread */
|
||||
/** */
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
|
||||
IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
|
||||
IMPORT _tx_execution_isr_exit
|
||||
ENDIF
|
||||
;
|
||||
;
|
||||
|
||||
AREA ||.text||, CODE, READONLY
|
||||
PRESERVE8
|
||||
;/**************************************************************************/
|
||||
;/* */
|
||||
;/* FUNCTION RELEASE */
|
||||
;/* */
|
||||
;/* _tx_thread_context_restore Cortex-M4/AC5 */
|
||||
;/* 6.1 */
|
||||
;/* AUTHOR */
|
||||
;/* */
|
||||
;/* William E. Lamie, Microsoft Corporation */
|
||||
;/* */
|
||||
;/* DESCRIPTION */
|
||||
;/* */
|
||||
;/* This function is only needed for legacy applications and it should */
|
||||
;/* not be called in any new development on a Cortex-M. */
|
||||
;/* This function restores the interrupt context if it is processing a */
|
||||
;/* nested interrupt. If not, it returns to the interrupt thread if no */
|
||||
;/* preemption is necessary. Otherwise, if preemption is necessary or */
|
||||
;/* if no thread was running, the function returns to the scheduler. */
|
||||
;/* */
|
||||
;/* INPUT */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* OUTPUT */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* CALLS */
|
||||
;/* */
|
||||
;/* _tx_thread_schedule Thread scheduling routine */
|
||||
;/* */
|
||||
;/* CALLED BY */
|
||||
;/* */
|
||||
;/* ISRs Interrupt Service Routines */
|
||||
;/* */
|
||||
;/* RELEASE HISTORY */
|
||||
;/* */
|
||||
;/* DATE NAME DESCRIPTION */
|
||||
;/* */
|
||||
;/* 09-30-2020 William E. Lamie Initial Version 6.1 */
|
||||
;/* */
|
||||
;/**************************************************************************/
|
||||
;VOID _tx_thread_context_restore(VOID)
|
||||
;{
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* FUNCTION RELEASE */
|
||||
/* */
|
||||
/* _tx_thread_context_restore Cortex-M4/AC5 */
|
||||
/* 6.1.2 */
|
||||
/* AUTHOR */
|
||||
/* */
|
||||
/* William E. Lamie, Microsoft Corporation */
|
||||
/* */
|
||||
/* DESCRIPTION */
|
||||
/* */
|
||||
/* This function is only needed for legacy applications and it should */
|
||||
/* not be called in any new development on a Cortex-M. */
|
||||
/* */
|
||||
/* INPUT */
|
||||
/* */
|
||||
/* None */
|
||||
/* */
|
||||
/* OUTPUT */
|
||||
/* */
|
||||
/* None */
|
||||
/* */
|
||||
/* CALLS */
|
||||
/* */
|
||||
/* None */
|
||||
/* */
|
||||
/* CALLED BY */
|
||||
/* */
|
||||
/* ISRs Interrupt Service Routines */
|
||||
/* */
|
||||
/* RELEASE HISTORY */
|
||||
/* */
|
||||
/* DATE NAME DESCRIPTION */
|
||||
/* */
|
||||
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
|
||||
/* 11-09-2020 Scott Larson Modified comment(s), */
|
||||
/* resulting in version 6.1.2 */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
// VOID _tx_thread_context_restore(VOID)
|
||||
// {
|
||||
EXPORT _tx_thread_context_restore
|
||||
_tx_thread_context_restore
|
||||
|
||||
IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
|
||||
;
|
||||
; /* Call the ISR exit function to indicate an ISR is complete. */
|
||||
;
|
||||
PUSH {r0,lr} ; Save ISR lr
|
||||
BL _tx_execution_isr_exit ; Call the ISR exit function
|
||||
POP {r0,lr} ; Restore ISR lr
|
||||
/* Call the ISR exit function to indicate an ISR is complete. */
|
||||
PUSH {r0,lr} // Save ISR lr
|
||||
BL _tx_execution_isr_exit // Call the ISR exit function
|
||||
POP {r0,lr} // Restore ISR lr
|
||||
ENDIF
|
||||
;
|
||||
|
||||
POP {lr}
|
||||
BX lr
|
||||
;}
|
||||
// }
|
||||
ALIGN
|
||||
LTORG
|
||||
END
|
||||
|
||||
@@ -1,91 +1,87 @@
|
||||
;/**************************************************************************/
|
||||
;/* */
|
||||
;/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
;/* */
|
||||
;/* This software is licensed under the Microsoft Software License */
|
||||
;/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
;/* and in the root directory of this software. */
|
||||
;/* */
|
||||
;/**************************************************************************/
|
||||
;
|
||||
;
|
||||
;/**************************************************************************/
|
||||
;/**************************************************************************/
|
||||
;/** */
|
||||
;/** ThreadX Component */
|
||||
;/** */
|
||||
;/** Thread */
|
||||
;/** */
|
||||
;/**************************************************************************/
|
||||
;/**************************************************************************/
|
||||
;
|
||||
;
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
/* */
|
||||
/* This software is licensed under the Microsoft Software License */
|
||||
/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
/* and in the root directory of this software. */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
/** */
|
||||
/** ThreadX Component */
|
||||
/** */
|
||||
/** Thread */
|
||||
/** */
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
|
||||
IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
|
||||
IMPORT _tx_execution_isr_enter
|
||||
ENDIF
|
||||
;
|
||||
;
|
||||
|
||||
AREA ||.text||, CODE, READONLY
|
||||
PRESERVE8
|
||||
;/**************************************************************************/
|
||||
;/* */
|
||||
;/* FUNCTION RELEASE */
|
||||
;/* */
|
||||
;/* _tx_thread_context_save Cortex-M4/AC5 */
|
||||
;/* 6.1 */
|
||||
;/* AUTHOR */
|
||||
;/* */
|
||||
;/* William E. Lamie, Microsoft Corporation */
|
||||
;/* */
|
||||
;/* DESCRIPTION */
|
||||
;/* */
|
||||
;/* This function is only needed for legacy applications and it should */
|
||||
;/* not be called in any new development on a Cortex-M. */
|
||||
;/* This function saves the context of an executing thread in the */
|
||||
;/* beginning of interrupt processing. The function also ensures that */
|
||||
;/* the system stack is used upon return to the calling ISR. */
|
||||
;/* */
|
||||
;/* INPUT */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* OUTPUT */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* CALLS */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* CALLED BY */
|
||||
;/* */
|
||||
;/* ISRs */
|
||||
;/* */
|
||||
;/* RELEASE HISTORY */
|
||||
;/* */
|
||||
;/* DATE NAME DESCRIPTION */
|
||||
;/* */
|
||||
;/* 09-30-2020 William E. Lamie Initial Version 6.1 */
|
||||
;/* */
|
||||
;/**************************************************************************/
|
||||
;VOID _tx_thread_context_save(VOID)
|
||||
;{
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* FUNCTION RELEASE */
|
||||
/* */
|
||||
/* _tx_thread_context_save Cortex-M4/AC5 */
|
||||
/* 6.1.2 */
|
||||
/* AUTHOR */
|
||||
/* */
|
||||
/* William E. Lamie, Microsoft Corporation */
|
||||
/* */
|
||||
/* DESCRIPTION */
|
||||
/* */
|
||||
/* This function is only needed for legacy applications and it should */
|
||||
/* not be called in any new development on a Cortex-M. */
|
||||
/* */
|
||||
/* INPUT */
|
||||
/* */
|
||||
/* None */
|
||||
/* */
|
||||
/* OUTPUT */
|
||||
/* */
|
||||
/* None */
|
||||
/* */
|
||||
/* CALLS */
|
||||
/* */
|
||||
/* None */
|
||||
/* */
|
||||
/* CALLED BY */
|
||||
/* */
|
||||
/* ISRs */
|
||||
/* */
|
||||
/* RELEASE HISTORY */
|
||||
/* */
|
||||
/* DATE NAME DESCRIPTION */
|
||||
/* */
|
||||
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
|
||||
/* 11-09-2020 Scott Larson Modified comment(s), */
|
||||
/* resulting in version 6.1.2 */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
// VOID _tx_thread_context_save(VOID)
|
||||
// {
|
||||
EXPORT _tx_thread_context_save
|
||||
_tx_thread_context_save
|
||||
|
||||
IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
|
||||
;
|
||||
; /* Call the ISR enter function to indicate an ISR is executing. */
|
||||
;
|
||||
PUSH {r0, lr} ; Save ISR lr
|
||||
BL _tx_execution_isr_enter ; Call the ISR enter function
|
||||
POP {r0, lr} ; Recover ISR lr
|
||||
/* Call the ISR enter function to indicate an ISR is executing. */
|
||||
PUSH {r0, lr} // Save ISR lr
|
||||
BL _tx_execution_isr_enter // Call the ISR enter function
|
||||
POP {r0, lr} // Recover ISR lr
|
||||
ENDIF
|
||||
;
|
||||
; /* Return to interrupt processing. */
|
||||
;
|
||||
BX lr ; Return to interrupt processing caller
|
||||
;}
|
||||
|
||||
/* Return to interrupt processing. */
|
||||
|
||||
BX lr // Return to interrupt processing caller
|
||||
// }
|
||||
ALIGN
|
||||
LTORG
|
||||
END
|
||||
|
||||
@@ -1,76 +1,74 @@
|
||||
;/**************************************************************************/
|
||||
;/* */
|
||||
;/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
;/* */
|
||||
;/* This software is licensed under the Microsoft Software License */
|
||||
;/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
;/* and in the root directory of this software. */
|
||||
;/* */
|
||||
;/**************************************************************************/
|
||||
;
|
||||
;
|
||||
;/**************************************************************************/
|
||||
;/**************************************************************************/
|
||||
;/** */
|
||||
;/** ThreadX Component */
|
||||
;/** */
|
||||
;/** Thread */
|
||||
;/** */
|
||||
;/**************************************************************************/
|
||||
;/**************************************************************************/
|
||||
;
|
||||
;
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
/* */
|
||||
/* This software is licensed under the Microsoft Software License */
|
||||
/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
/* and in the root directory of this software. */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
/** */
|
||||
/** ThreadX Component */
|
||||
/** */
|
||||
/** Thread */
|
||||
/** */
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
|
||||
AREA ||.text||, CODE, READONLY
|
||||
;/**************************************************************************/
|
||||
;/* */
|
||||
;/* FUNCTION RELEASE */
|
||||
;/* */
|
||||
;/* _tx_thread_interrupt_control Cortex-M4/AC5 */
|
||||
;/* 6.1 */
|
||||
;/* AUTHOR */
|
||||
;/* */
|
||||
;/* William E. Lamie, Microsoft Corporation */
|
||||
;/* */
|
||||
;/* DESCRIPTION */
|
||||
;/* */
|
||||
;/* This function is responsible for changing the interrupt lockout */
|
||||
;/* posture of the system. */
|
||||
;/* */
|
||||
;/* INPUT */
|
||||
;/* */
|
||||
;/* new_posture New interrupt lockout posture */
|
||||
;/* */
|
||||
;/* OUTPUT */
|
||||
;/* */
|
||||
;/* old_posture Old interrupt lockout posture */
|
||||
;/* */
|
||||
;/* CALLS */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* CALLED BY */
|
||||
;/* */
|
||||
;/* Application Code */
|
||||
;/* */
|
||||
;/* RELEASE HISTORY */
|
||||
;/* */
|
||||
;/* DATE NAME DESCRIPTION */
|
||||
;/* */
|
||||
;/* 09-30-2020 William E. Lamie Initial Version 6.1 */
|
||||
;/* */
|
||||
;/**************************************************************************/
|
||||
;UINT _tx_thread_interrupt_control(UINT new_posture)
|
||||
;{
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* FUNCTION RELEASE */
|
||||
/* */
|
||||
/* _tx_thread_interrupt_control Cortex-M4/AC5 */
|
||||
/* 6.1.2 */
|
||||
/* AUTHOR */
|
||||
/* */
|
||||
/* William E. Lamie, Microsoft Corporation */
|
||||
/* */
|
||||
/* DESCRIPTION */
|
||||
/* */
|
||||
/* This function is responsible for changing the interrupt lockout */
|
||||
/* posture of the system. */
|
||||
/* */
|
||||
/* INPUT */
|
||||
/* */
|
||||
/* new_posture New interrupt lockout posture */
|
||||
/* */
|
||||
/* OUTPUT */
|
||||
/* */
|
||||
/* old_posture Old interrupt lockout posture */
|
||||
/* */
|
||||
/* CALLS */
|
||||
/* */
|
||||
/* None */
|
||||
/* */
|
||||
/* CALLED BY */
|
||||
/* */
|
||||
/* Application Code */
|
||||
/* */
|
||||
/* RELEASE HISTORY */
|
||||
/* */
|
||||
/* DATE NAME DESCRIPTION */
|
||||
/* */
|
||||
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
|
||||
/* 11-09-2020 Scott Larson Modified comment(s), */
|
||||
/* resulting in version 6.1.2 */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
// UINT _tx_thread_interrupt_control(UINT new_posture)
|
||||
// {
|
||||
EXPORT _tx_thread_interrupt_control
|
||||
_tx_thread_interrupt_control
|
||||
;
|
||||
; /* Pickup current interrupt lockout posture. */
|
||||
;
|
||||
MRS r1, PRIMASK
|
||||
MSR PRIMASK, r0
|
||||
MOV r0, r1
|
||||
BX lr
|
||||
;
|
||||
;}
|
||||
MRS r1, PRIMASK // Pickup current interrupt lockout
|
||||
MSR PRIMASK, r0 // Apply the new interrupt lockout
|
||||
MOV r0, r1 // Transfer old to return register
|
||||
BX lr // Return to caller
|
||||
|
||||
// }
|
||||
END
|
||||
|
||||
@@ -1,75 +1,76 @@
|
||||
;/**************************************************************************/
|
||||
;/* */
|
||||
;/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
;/* */
|
||||
;/* This software is licensed under the Microsoft Software License */
|
||||
;/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
;/* and in the root directory of this software. */
|
||||
;/* */
|
||||
;/**************************************************************************/
|
||||
;
|
||||
;
|
||||
;/**************************************************************************/
|
||||
;/**************************************************************************/
|
||||
;/** */
|
||||
;/** ThreadX Component */
|
||||
;/** */
|
||||
;/** Thread */
|
||||
;/** */
|
||||
;/**************************************************************************/
|
||||
;/**************************************************************************/
|
||||
;
|
||||
;
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
/* */
|
||||
/* This software is licensed under the Microsoft Software License */
|
||||
/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
/* and in the root directory of this software. */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
/** */
|
||||
/** ThreadX Component */
|
||||
/** */
|
||||
/** Thread */
|
||||
/** */
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
|
||||
AREA ||.text||, CODE, READONLY
|
||||
;/**************************************************************************/
|
||||
;/* */
|
||||
;/* FUNCTION RELEASE */
|
||||
;/* */
|
||||
;/* _tx_thread_interrupt_disable Cortex-M4/AC5 */
|
||||
;/* 6.1 */
|
||||
;/* AUTHOR */
|
||||
;/* */
|
||||
;/* William E. Lamie, Microsoft Corporation */
|
||||
;/* */
|
||||
;/* DESCRIPTION */
|
||||
;/* */
|
||||
;/* This function is responsible for disabling interrupts and returning */
|
||||
;/* the previous interrupt lockout posture. */
|
||||
;/* */
|
||||
;/* INPUT */
|
||||
;/* */
|
||||
;/* old_posture Old interrupt lockout posture */
|
||||
;/* */
|
||||
;/* OUTPUT */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* CALLS */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* CALLED BY */
|
||||
;/* */
|
||||
;/* Application Code */
|
||||
;/* */
|
||||
;/* RELEASE HISTORY */
|
||||
;/* */
|
||||
;/* DATE NAME DESCRIPTION */
|
||||
;/* */
|
||||
;/* 09-30-2020 William E. Lamie Initial Version 6.1 */
|
||||
;/* */
|
||||
;/**************************************************************************/
|
||||
;UINT _tx_thread_interrupt_disable(UINT new_posture)
|
||||
;{
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* FUNCTION RELEASE */
|
||||
/* */
|
||||
/* _tx_thread_interrupt_disable Cortex-M4/AC5 */
|
||||
/* 6.1.2 */
|
||||
/* AUTHOR */
|
||||
/* */
|
||||
/* William E. Lamie, Microsoft Corporation */
|
||||
/* */
|
||||
/* DESCRIPTION */
|
||||
/* */
|
||||
/* This function is responsible for disabling interrupts and returning */
|
||||
/* the previous interrupt lockout posture. */
|
||||
/* */
|
||||
/* INPUT */
|
||||
/* */
|
||||
/* old_posture Old interrupt lockout posture */
|
||||
/* */
|
||||
/* OUTPUT */
|
||||
/* */
|
||||
/* None */
|
||||
/* */
|
||||
/* CALLS */
|
||||
/* */
|
||||
/* None */
|
||||
/* */
|
||||
/* CALLED BY */
|
||||
/* */
|
||||
/* Application Code */
|
||||
/* */
|
||||
/* RELEASE HISTORY */
|
||||
/* */
|
||||
/* DATE NAME DESCRIPTION */
|
||||
/* */
|
||||
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
|
||||
/* 11-09-2020 Scott Larson Modified comment(s), */
|
||||
/* resulting in version 6.1.2 */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
// UINT _tx_thread_interrupt_disable(UINT new_posture)
|
||||
// {
|
||||
EXPORT _tx_thread_interrupt_disable
|
||||
_tx_thread_interrupt_disable
|
||||
;
|
||||
; /* Return current interrupt lockout posture. */
|
||||
;
|
||||
|
||||
/* Return current interrupt lockout posture. */
|
||||
|
||||
MRS r0, PRIMASK
|
||||
CPSID i
|
||||
BX lr
|
||||
;
|
||||
;}
|
||||
|
||||
// }
|
||||
END
|
||||
|
||||
@@ -1,74 +1,75 @@
|
||||
;/**************************************************************************/
|
||||
;/* */
|
||||
;/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
;/* */
|
||||
;/* This software is licensed under the Microsoft Software License */
|
||||
;/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
;/* and in the root directory of this software. */
|
||||
;/* */
|
||||
;/**************************************************************************/
|
||||
;
|
||||
;
|
||||
;/**************************************************************************/
|
||||
;/**************************************************************************/
|
||||
;/** */
|
||||
;/** ThreadX Component */
|
||||
;/** */
|
||||
;/** Thread */
|
||||
;/** */
|
||||
;/**************************************************************************/
|
||||
;/**************************************************************************/
|
||||
;
|
||||
;
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
/* */
|
||||
/* This software is licensed under the Microsoft Software License */
|
||||
/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
/* and in the root directory of this software. */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
/** */
|
||||
/** ThreadX Component */
|
||||
/** */
|
||||
/** Thread */
|
||||
/** */
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
|
||||
AREA ||.text||, CODE, READONLY
|
||||
;/**************************************************************************/
|
||||
;/* */
|
||||
;/* FUNCTION RELEASE */
|
||||
;/* */
|
||||
;/* _tx_thread_interrupt_restore Cortex-M4/AC5 */
|
||||
;/* 6.1 */
|
||||
;/* AUTHOR */
|
||||
;/* */
|
||||
;/* William E. Lamie, Microsoft Corporation */
|
||||
;/* */
|
||||
;/* DESCRIPTION */
|
||||
;/* */
|
||||
;/* This function is responsible for restoring the previous */
|
||||
;/* interrupt lockout posture. */
|
||||
;/* */
|
||||
;/* INPUT */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* OUTPUT */
|
||||
;/* */
|
||||
;/* previous_posture Previous interrupt posture */
|
||||
;/* */
|
||||
;/* CALLS */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* CALLED BY */
|
||||
;/* */
|
||||
;/* Application Code */
|
||||
;/* */
|
||||
;/* RELEASE HISTORY */
|
||||
;/* */
|
||||
;/* DATE NAME DESCRIPTION */
|
||||
;/* */
|
||||
;/* 09-30-2020 William E. Lamie Initial Version 6.1 */
|
||||
;/* */
|
||||
;/**************************************************************************/
|
||||
;VOID _tx_thread_interrupt_restore(UINT new_posture)
|
||||
;{
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* FUNCTION RELEASE */
|
||||
/* */
|
||||
/* _tx_thread_interrupt_restore Cortex-M4/AC5 */
|
||||
/* 6.1.2 */
|
||||
/* AUTHOR */
|
||||
/* */
|
||||
/* William E. Lamie, Microsoft Corporation */
|
||||
/* */
|
||||
/* DESCRIPTION */
|
||||
/* */
|
||||
/* This function is responsible for restoring the previous */
|
||||
/* interrupt lockout posture. */
|
||||
/* */
|
||||
/* INPUT */
|
||||
/* */
|
||||
/* None */
|
||||
/* */
|
||||
/* OUTPUT */
|
||||
/* */
|
||||
/* previous_posture Previous interrupt posture */
|
||||
/* */
|
||||
/* CALLS */
|
||||
/* */
|
||||
/* None */
|
||||
/* */
|
||||
/* CALLED BY */
|
||||
/* */
|
||||
/* Application Code */
|
||||
/* */
|
||||
/* RELEASE HISTORY */
|
||||
/* */
|
||||
/* DATE NAME DESCRIPTION */
|
||||
/* */
|
||||
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
|
||||
/* 11-09-2020 Scott Larson Modified comment(s), */
|
||||
/* resulting in version 6.1.2 */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
// VOID _tx_thread_interrupt_restore(UINT new_posture)
|
||||
// {
|
||||
EXPORT _tx_thread_interrupt_restore
|
||||
_tx_thread_interrupt_restore
|
||||
;
|
||||
; /* Restore previous interrupt lockout posture. */
|
||||
;
|
||||
|
||||
/* Restore previous interrupt lockout posture. */
|
||||
|
||||
MSR PRIMASK, r0
|
||||
BX lr
|
||||
;
|
||||
;}
|
||||
|
||||
// }
|
||||
END
|
||||
|
||||
@@ -1,30 +1,28 @@
|
||||
;/**************************************************************************/
|
||||
;/* */
|
||||
;/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
;/* */
|
||||
;/* This software is licensed under the Microsoft Software License */
|
||||
;/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
;/* and in the root directory of this software. */
|
||||
;/* */
|
||||
;/**************************************************************************/
|
||||
;
|
||||
;
|
||||
;/**************************************************************************/
|
||||
;/**************************************************************************/
|
||||
;/** */
|
||||
;/** ThreadX Component */
|
||||
;/** */
|
||||
;/** Thread */
|
||||
;/** */
|
||||
;/**************************************************************************/
|
||||
;/**************************************************************************/
|
||||
;
|
||||
;
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
/* */
|
||||
/* This software is licensed under the Microsoft Software License */
|
||||
/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
/* and in the root directory of this software. */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
/** */
|
||||
/** ThreadX Component */
|
||||
/** */
|
||||
/** Thread */
|
||||
/** */
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
|
||||
IMPORT _tx_thread_current_ptr
|
||||
IMPORT _tx_thread_execute_ptr
|
||||
IMPORT _tx_timer_time_slice
|
||||
IMPORT _tx_thread_system_stack_ptr
|
||||
IF :DEF: TX_ENABLE_EXECUTION_CHANGE_NOTIFY
|
||||
IMPORT _tx_execution_thread_enter
|
||||
IMPORT _tx_execution_thread_exit
|
||||
@@ -34,418 +32,409 @@
|
||||
IMPORT _txm_module_manager_memory_fault_info
|
||||
IMPORT _txm_module_priv
|
||||
IMPORT _txm_module_user_mode_exit
|
||||
;
|
||||
;
|
||||
|
||||
AREA ||.text||, CODE, READONLY
|
||||
THUMB
|
||||
;/**************************************************************************/
|
||||
;/* */
|
||||
;/* FUNCTION RELEASE */
|
||||
;/* */
|
||||
;/* _tx_thread_schedule Cortex-M4/MPU/AC5 */
|
||||
;/* 6.1 */
|
||||
;/* AUTHOR */
|
||||
;/* */
|
||||
;/* Scott Larson, Microsoft Corporation */
|
||||
;/* */
|
||||
;/* DESCRIPTION */
|
||||
;/* */
|
||||
;/* This function waits for a thread control block pointer to appear in */
|
||||
;/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */
|
||||
;/* in the variable, the corresponding thread is resumed. */
|
||||
;/* */
|
||||
;/* INPUT */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* OUTPUT */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* CALLS */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* CALLED BY */
|
||||
;/* */
|
||||
;/* _tx_initialize_kernel_enter ThreadX entry function */
|
||||
;/* _tx_thread_system_return Return to system from thread */
|
||||
;/* _tx_thread_context_restore Restore thread's context */
|
||||
;/* */
|
||||
;/* RELEASE HISTORY */
|
||||
;/* */
|
||||
;/* DATE NAME DESCRIPTION */
|
||||
;/* */
|
||||
;/* 09-30-2020 Scott Larson Initial Version 6.1 */
|
||||
;/* */
|
||||
;/**************************************************************************/
|
||||
;VOID _tx_thread_schedule(VOID)
|
||||
;{
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* FUNCTION RELEASE */
|
||||
/* */
|
||||
/* _tx_thread_schedule Cortex-M4/MPU/AC5 */
|
||||
/* 6.1.2 */
|
||||
/* AUTHOR */
|
||||
/* */
|
||||
/* Scott Larson, Microsoft Corporation */
|
||||
/* */
|
||||
/* DESCRIPTION */
|
||||
/* */
|
||||
/* This function waits for a thread control block pointer to appear in */
|
||||
/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */
|
||||
/* in the variable, the corresponding thread is resumed. */
|
||||
/* */
|
||||
/* INPUT */
|
||||
/* */
|
||||
/* None */
|
||||
/* */
|
||||
/* OUTPUT */
|
||||
/* */
|
||||
/* None */
|
||||
/* */
|
||||
/* CALLS */
|
||||
/* */
|
||||
/* None */
|
||||
/* */
|
||||
/* CALLED BY */
|
||||
/* */
|
||||
/* _tx_initialize_kernel_enter ThreadX entry function */
|
||||
/* _tx_thread_system_return Return to system from thread */
|
||||
/* _tx_thread_context_restore Restore thread's context */
|
||||
/* */
|
||||
/* RELEASE HISTORY */
|
||||
/* */
|
||||
/* DATE NAME DESCRIPTION */
|
||||
/* */
|
||||
/* 09-30-2020 Scott Larson Initial Version 6.1 */
|
||||
/* 11-09-2020 Scott Larson Modified comment(s), arrange */
|
||||
/* code to fix link error when */
|
||||
/* VFP is enabled, resulting */
|
||||
/* in version 6.1.2 */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
// VOID _tx_thread_schedule(VOID)
|
||||
// {
|
||||
EXPORT _tx_thread_schedule
|
||||
_tx_thread_schedule
|
||||
;
|
||||
; /* This function should only ever be called on Cortex-M
|
||||
; from the first schedule request. Subsequent scheduling occurs
|
||||
; from the PendSV handling routines below. */
|
||||
;
|
||||
; /* Clear the preempt-disable flag to enable rescheduling after initialization on Cortex-M targets. */
|
||||
;
|
||||
MOV r0, #0 ; Build value for TX_FALSE
|
||||
LDR r2, =_tx_thread_preempt_disable ; Build address of preempt disable flag
|
||||
STR r0, [r2, #0] ; Clear preempt disable flag
|
||||
;
|
||||
; /* Clear CONTROL.FPCA bit so FPU registers aren't unnecessarily stacked. */
|
||||
;
|
||||
IF :DEF: __ARMVFP__
|
||||
MRS r0, CONTROL ; Pickup current CONTROL register
|
||||
BIC r0, r0, #4 ; Clear the FPCA bit
|
||||
MSR CONTROL, r0 ; Setup new CONTROL register
|
||||
ENDIF
|
||||
;
|
||||
; /* Enable memory fault registers. */
|
||||
;
|
||||
LDR r0, =0xE000ED24 ; Build SHCSR address
|
||||
LDR r1, =0x70000 ; Enable Usage, Bus, and MemManage faults
|
||||
STR r1, [r0] ;
|
||||
;
|
||||
; /* Enable interrupts */
|
||||
;
|
||||
CPSIE i
|
||||
;
|
||||
; /* Enter the scheduler for the first time. */
|
||||
;
|
||||
MOV r0, #0x10000000 ; Load PENDSVSET bit
|
||||
MOV r1, #0xE000E000 ; Load NVIC base
|
||||
STR r0, [r1, #0xD04] ; Set PENDSVBIT in ICSR
|
||||
DSB ; Complete all memory accesses
|
||||
ISB ; Flush pipeline
|
||||
|
||||
; /* Wait here for the PendSV to take place. */
|
||||
/* This function should only ever be called on Cortex-M
|
||||
from the first schedule request. Subsequent scheduling occurs
|
||||
from the PendSV handling routines below. */
|
||||
|
||||
/* Clear the preempt-disable flag to enable rescheduling after initialization on Cortex-M targets. */
|
||||
|
||||
MOV r0, #0 // Build value for TX_FALSE
|
||||
LDR r2, =_tx_thread_preempt_disable // Build address of preempt disable flag
|
||||
STR r0, [r2, #0] // Clear preempt disable flag
|
||||
|
||||
/* Clear CONTROL.FPCA bit so FPU registers aren't unnecessarily stacked. */
|
||||
|
||||
IF {TARGET_FPU_VFP} = {TRUE}
|
||||
MRS r0, CONTROL // Pickup current CONTROL register
|
||||
BIC r0, r0, #4 // Clear the FPCA bit
|
||||
MSR CONTROL, r0 // Setup new CONTROL register
|
||||
ENDIF
|
||||
|
||||
/* Enable memory fault registers. */
|
||||
|
||||
LDR r0, =0xE000ED24 // Build SHCSR address
|
||||
LDR r1, =0x70000 // Enable Usage, Bus, and MemManage faults
|
||||
STR r1, [r0] //
|
||||
|
||||
/* Enable interrupts */
|
||||
|
||||
CPSIE i
|
||||
|
||||
/* Enter the scheduler for the first time. */
|
||||
|
||||
MOV r0, #0x10000000 // Load PENDSVSET bit
|
||||
MOV r1, #0xE000E000 // Load NVIC base
|
||||
STR r0, [r1, #0xD04] // Set PENDSVBIT in ICSR
|
||||
DSB // Complete all memory accesses
|
||||
ISB // Flush pipeline
|
||||
|
||||
/* Wait here for the PendSV to take place. */
|
||||
|
||||
__tx_wait_here
|
||||
B __tx_wait_here ; Wait for the PendSV to happen
|
||||
;}
|
||||
;
|
||||
B __tx_wait_here // Wait for the PendSV to happen
|
||||
// }
|
||||
|
||||
|
||||
/* Memory Exception Handler. */
|
||||
|
||||
;
|
||||
; /* Memory Exception Handler. */
|
||||
;
|
||||
EXPORT MemManage_Handler
|
||||
MemManage_Handler
|
||||
;{
|
||||
CPSID i ; Disable interrupts
|
||||
;
|
||||
; /* Now pickup and store all the fault related information. */
|
||||
;
|
||||
LDR r12,=_txm_module_manager_memory_fault_info ; Pickup fault info struct
|
||||
LDR r0, =_tx_thread_current_ptr ; Build current thread pointer address
|
||||
LDR r1, [r0] ; Pickup the current thread pointer
|
||||
STR r1, [r12, #0] ; Save current thread pointer in fault info structure
|
||||
LDR r0, =0xE000ED24 ; Build SHCSR address
|
||||
LDR r1, [r0] ; Pickup SHCSR
|
||||
STR r1, [r12, #8] ; Save SHCSR
|
||||
LDR r0, =0xE000ED28 ; Build CFSR address
|
||||
LDR r1, [r0] ; Pickup CFSR
|
||||
STR r1, [r12, #12] ; Save CFSR
|
||||
LDR r0, =0xE000ED34 ; Build MMFAR address
|
||||
LDR r1, [r0] ; Pickup MMFAR
|
||||
STR r1, [r12, #16] ; Save MMFAR
|
||||
LDR r0, =0xE000ED38 ; Build BFAR address
|
||||
LDR r1, [r0] ; Pickup BFAR
|
||||
STR r1, [r12, #20] ; Save BFAR
|
||||
MRS r0, CONTROL ; Pickup current CONTROL register
|
||||
STR r0, [r12, #24] ; Save CONTROL
|
||||
MRS r1, PSP ; Pickup thread stack pointer
|
||||
STR r1, [r12, #28] ; Save thread stack pointer
|
||||
LDR r0, [r1] ; Pickup saved r0
|
||||
STR r0, [r12, #32] ; Save r0
|
||||
LDR r0, [r1, #4] ; Pickup saved r1
|
||||
STR r0, [r12, #36] ; Save r1
|
||||
STR r2, [r12, #40] ; Save r2
|
||||
STR r3, [r12, #44] ; Save r3
|
||||
STR r4, [r12, #48] ; Save r4
|
||||
STR r5, [r12, #52] ; Save r5
|
||||
STR r6, [r12, #56] ; Save r6
|
||||
STR r7, [r12, #60] ; Save r7
|
||||
STR r8, [r12, #64] ; Save r8
|
||||
STR r9, [r12, #68] ; Save r9
|
||||
STR r10,[r12, #72] ; Save r10
|
||||
STR r11,[r12, #76] ; Save r11
|
||||
LDR r0, [r1, #16] ; Pickup saved r12
|
||||
STR r0, [r12, #80] ; Save r12
|
||||
LDR r0, [r1, #20] ; Pickup saved lr
|
||||
STR r0, [r12, #84] ; Save lr
|
||||
LDR r0, [r1, #24] ; Pickup instruction address at point of fault
|
||||
STR r0, [r12, #4] ; Save point of fault
|
||||
LDR r0, [r1, #28] ; Pickup xPSR
|
||||
STR r0, [r12, #88] ; Save xPSR
|
||||
|
||||
MRS r0, CONTROL ; Pickup current CONTROL register
|
||||
BIC r0, r0, #1 ; Clear the UNPRIV bit
|
||||
MSR CONTROL, r0 ; Setup new CONTROL register
|
||||
CPSID i // Disable interrupts
|
||||
|
||||
LDR r0, =0xE000ED28 ; Build the Memory Management Fault Status Register (MMFSR)
|
||||
LDRB r1, [r0] ; Pickup the MMFSR, with the following bit definitions:
|
||||
; Bit 0 = 1 -> Instruction address violation
|
||||
; Bit 1 = 1 -> Load/store address violation
|
||||
; Bit 7 = 1 -> MMFAR is valid
|
||||
STRB r1, [r0] ; Clear the MMFSR
|
||||
/* Now pickup and store all the fault related information. */
|
||||
|
||||
IF :DEF: __ARMVFP__
|
||||
LDR r0, =0xE000EF34 ; Cleanup FPU context: Load FPCCR address
|
||||
LDR r1, [r0] ; Load FPCCR
|
||||
BIC r1, r1, #1 ; Clear the lazy preservation active bit
|
||||
STR r1, [r0] ; Store the value
|
||||
LDR r12,=_txm_module_manager_memory_fault_info // Pickup fault info struct
|
||||
LDR r0, =_tx_thread_current_ptr // Build current thread pointer address
|
||||
LDR r1, [r0] // Pickup the current thread pointer
|
||||
STR r1, [r12, #0] // Save current thread pointer in fault info structure
|
||||
LDR r0, =0xE000ED24 // Build SHCSR address
|
||||
LDR r1, [r0] // Pickup SHCSR
|
||||
STR r1, [r12, #8] // Save SHCSR
|
||||
LDR r0, =0xE000ED28 // Build CFSR address
|
||||
LDR r1, [r0] // Pickup CFSR
|
||||
STR r1, [r12, #12] // Save CFSR
|
||||
LDR r0, =0xE000ED34 // Build MMFAR address
|
||||
LDR r1, [r0] // Pickup MMFAR
|
||||
STR r1, [r12, #16] // Save MMFAR
|
||||
LDR r0, =0xE000ED38 // Build BFAR address
|
||||
LDR r1, [r0] // Pickup BFAR
|
||||
STR r1, [r12, #20] // Save BFAR
|
||||
MRS r0, CONTROL // Pickup current CONTROL register
|
||||
STR r0, [r12, #24] // Save CONTROL
|
||||
MRS r1, PSP // Pickup thread stack pointer
|
||||
STR r1, [r12, #28] // Save thread stack pointer
|
||||
LDR r0, [r1] // Pickup saved r0
|
||||
STR r0, [r12, #32] // Save r0
|
||||
LDR r0, [r1, #4] // Pickup saved r1
|
||||
STR r0, [r12, #36] // Save r1
|
||||
STR r2, [r12, #40] // Save r2
|
||||
STR r3, [r12, #44] // Save r3
|
||||
STR r4, [r12, #48] // Save r4
|
||||
STR r5, [r12, #52] // Save r5
|
||||
STR r6, [r12, #56] // Save r6
|
||||
STR r7, [r12, #60] // Save r7
|
||||
STR r8, [r12, #64] // Save r8
|
||||
STR r9, [r12, #68] // Save r9
|
||||
STR r10,[r12, #72] // Save r10
|
||||
STR r11,[r12, #76] // Save r11
|
||||
LDR r0, [r1, #16] // Pickup saved r12
|
||||
STR r0, [r12, #80] // Save r12
|
||||
LDR r0, [r1, #20] // Pickup saved lr
|
||||
STR r0, [r12, #84] // Save lr
|
||||
LDR r0, [r1, #24] // Pickup instruction address at point of fault
|
||||
STR r0, [r12, #4] // Save point of fault
|
||||
LDR r0, [r1, #28] // Pickup xPSR
|
||||
STR r0, [r12, #88] // Save xPSR
|
||||
|
||||
MRS r0, CONTROL // Pickup current CONTROL register
|
||||
BIC r0, r0, #1 // Clear the UNPRIV bit
|
||||
MSR CONTROL, r0 // Setup new CONTROL register
|
||||
|
||||
LDR r0, =0xE000ED28 // Build the Memory Management Fault Status Register (MMFSR)
|
||||
LDRB r1, [r0] // Pickup the MMFSR, with the following bit definitions:
|
||||
// Bit 0 = 1 -> Instruction address violation
|
||||
// Bit 1 = 1 -> Load/store address violation
|
||||
// Bit 7 = 1 -> MMFAR is valid
|
||||
STRB r1, [r0] // Clear the MMFSR
|
||||
|
||||
IF {TARGET_FPU_VFP} = {TRUE}
|
||||
LDR r0, =0xE000EF34 // Cleanup FPU context: Load FPCCR address
|
||||
LDR r1, [r0] // Load FPCCR
|
||||
BIC r1, r1, #1 // Clear the lazy preservation active bit
|
||||
STR r1, [r0] // Store the value
|
||||
ENDIF
|
||||
|
||||
BL _txm_module_manager_memory_fault_handler ; Call memory manager fault handler
|
||||
BL _txm_module_manager_memory_fault_handler // Call memory manager fault handler
|
||||
|
||||
IF :DEF: TX_ENABLE_EXECUTION_CHANGE_NOTIFY
|
||||
;
|
||||
; /* Call the thread exit function to indicate the thread is no longer executing. */
|
||||
;
|
||||
CPSID i ; Disable interrupts
|
||||
BL _tx_execution_thread_exit ; Call the thread exit function
|
||||
CPSIE i ; Enable interrupts
|
||||
/* Call the thread exit function to indicate the thread is no longer executing. */
|
||||
CPSID i // Disable interrupts
|
||||
BL _tx_execution_thread_exit // Call the thread exit function
|
||||
CPSIE i // Enable interrupts
|
||||
ENDIF
|
||||
|
||||
MOV r1, #0 ; Build NULL value
|
||||
LDR r0, =_tx_thread_current_ptr ; Pickup address of current thread pointer
|
||||
STR r1, [r0] ; Clear current thread pointer
|
||||
MOV r1, #0 // Build NULL value
|
||||
LDR r0, =_tx_thread_current_ptr // Pickup address of current thread pointer
|
||||
STR r1, [r0] // Clear current thread pointer
|
||||
|
||||
; Return from MemManage_Handler exception
|
||||
LDR r0, =0xE000ED04 ; Load ICSR
|
||||
LDR r1, =0x10000000 ; Set PENDSVSET bit
|
||||
STR r1, [r0] ; Store ICSR
|
||||
DSB ; Wait for memory access to complete
|
||||
CPSIE i ; Enable interrupts
|
||||
MOV lr, #0xFFFFFFFD ; Load exception return code
|
||||
BX lr ; Return from exception
|
||||
;}
|
||||
// Return from MemManage_Handler exception
|
||||
LDR r0, =0xE000ED04 // Load ICSR
|
||||
LDR r1, =0x10000000 // Set PENDSVSET bit
|
||||
STR r1, [r0] // Store ICSR
|
||||
DSB // Wait for memory access to complete
|
||||
CPSIE i // Enable interrupts
|
||||
MOV lr, #0xFFFFFFFD // Load exception return code
|
||||
BX lr // Return from exception
|
||||
|
||||
|
||||
/* Generic context PendSV handler. */
|
||||
|
||||
;
|
||||
; /* Generic context PendSV handler. */
|
||||
;
|
||||
EXPORT PendSV_Handler
|
||||
EXPORT __tx_PendSVHandler
|
||||
PendSV_Handler
|
||||
__tx_PendSVHandler
|
||||
;
|
||||
; /* Get current thread value and new thread pointer. */
|
||||
;
|
||||
|
||||
/* Get current thread value and new thread pointer. */
|
||||
|
||||
__tx_ts_handler
|
||||
|
||||
IF :DEF: TX_ENABLE_EXECUTION_CHANGE_NOTIFY
|
||||
;
|
||||
; /* Call the thread exit function to indicate the thread is no longer executing. */
|
||||
;
|
||||
CPSID i ; Disable interrupts
|
||||
PUSH {r0, lr} ; Save LR (and r0 just for alignment)
|
||||
BL _tx_execution_thread_exit ; Call the thread exit function
|
||||
POP {r0, lr} ; Recover LR
|
||||
CPSIE i ; Enable interrupts
|
||||
/* Call the thread exit function to indicate the thread is no longer executing. */
|
||||
CPSID i // Disable interrupts
|
||||
PUSH {r0, lr} // Save LR (and r0 just for alignment)
|
||||
BL _tx_execution_thread_exit // Call the thread exit function
|
||||
POP {r0, lr} // Recover LR
|
||||
CPSIE i // Enable interrupts
|
||||
ENDIF
|
||||
MOV32 r0, _tx_thread_current_ptr ; Build current thread pointer address
|
||||
MOV32 r2, _tx_thread_execute_ptr ; Build execute thread pointer address
|
||||
MOV r3, #0 ; Build NULL value
|
||||
LDR r1, [r0] ; Pickup current thread pointer
|
||||
;
|
||||
; /* Determine if there is a current thread to finish preserving. */
|
||||
;
|
||||
CBZ r1, __tx_ts_new ; If NULL, skip preservation
|
||||
;
|
||||
; /* Recover PSP and preserve current thread context. */
|
||||
;
|
||||
STR r3, [r0] ; Set _tx_thread_current_ptr to NULL
|
||||
MRS r12, PSP ; Pickup PSP pointer (thread's stack pointer)
|
||||
STMDB r12!, {r4-r11} ; Save its remaining registers
|
||||
IF :DEF: __ARMVFP__
|
||||
TST LR, #0x10 ; Determine if the VFP extended frame is present
|
||||
|
||||
LDR r0, =_tx_thread_current_ptr // Build current thread pointer address
|
||||
LDR r2, =_tx_thread_execute_ptr // Build execute thread pointer address
|
||||
MOV r3, #0 // Build NULL value
|
||||
LDR r1, [r0] // Pickup current thread pointer
|
||||
|
||||
/* Determine if there is a current thread to finish preserving. */
|
||||
|
||||
CBZ r1, __tx_ts_new // If NULL, skip preservation
|
||||
|
||||
/* Recover PSP and preserve current thread context. */
|
||||
|
||||
STR r3, [r0] // Set _tx_thread_current_ptr to NULL
|
||||
MRS r12, PSP // Pickup PSP pointer (thread's stack pointer)
|
||||
STMDB r12!, {r4-r11} // Save its remaining registers
|
||||
IF {TARGET_FPU_VFP} = {TRUE}
|
||||
TST LR, #0x10 // Determine if the VFP extended frame is present
|
||||
BNE _skip_vfp_save
|
||||
VSTMDB r12!,{s16-s31} ; Yes, save additional VFP registers
|
||||
VSTMDB r12!,{s16-s31} // Yes, save additional VFP registers
|
||||
_skip_vfp_save
|
||||
ENDIF
|
||||
MOV32 r4, _tx_timer_time_slice ; Build address of time-slice variable
|
||||
STMDB r12!, {LR} ; Save LR on the stack
|
||||
;
|
||||
; /* Determine if time-slice is active. If it isn't, skip time handling processing. */
|
||||
;
|
||||
LDR r5, [r4] ; Pickup current time-slice
|
||||
STR r12, [r1, #8] ; Save the thread stack pointer
|
||||
CBZ r5, __tx_ts_new ; If not active, skip processing
|
||||
;
|
||||
; /* Time-slice is active, save the current thread's time-slice and clear the global time-slice variable. */
|
||||
;
|
||||
STR r5, [r1, #24] ; Save current time-slice
|
||||
;
|
||||
; /* Clear the global time-slice. */
|
||||
;
|
||||
STR r3, [r4] ; Clear time-slice
|
||||
;
|
||||
; /* Executing thread is now completely preserved!!! */
|
||||
;
|
||||
LDR r4, =_tx_timer_time_slice // Build address of time-slice variable
|
||||
STMDB r12!, {LR} // Save LR on the stack
|
||||
|
||||
/* Determine if time-slice is active. If it isn't, skip time handling processing. */
|
||||
|
||||
LDR r5, [r4] // Pickup current time-slice
|
||||
STR r12, [r1, #8] // Save the thread stack pointer
|
||||
CBZ r5, __tx_ts_new // If not active, skip processing
|
||||
|
||||
/* Time-slice is active, save the current thread's time-slice and clear the global time-slice variable. */
|
||||
|
||||
STR r5, [r1, #24] // Save current time-slice
|
||||
|
||||
/* Clear the global time-slice. */
|
||||
|
||||
STR r3, [r4] // Clear time-slice
|
||||
|
||||
/* Executing thread is now completely preserved!!! */
|
||||
|
||||
__tx_ts_new
|
||||
;
|
||||
; /* Now we are looking for a new thread to execute! */
|
||||
;
|
||||
CPSID i ; Disable interrupts
|
||||
LDR r1, [r2] ; Is there another thread ready to execute?
|
||||
CBZ r1, __tx_ts_wait ; No, skip to the wait processing
|
||||
;
|
||||
; /* Yes, another thread is ready for else, make the current thread the new thread. */
|
||||
;
|
||||
STR r1, [r0] ; Setup the current thread pointer to the new thread
|
||||
CPSIE i ; Enable interrupts
|
||||
;
|
||||
; /* Increment the thread run count. */
|
||||
;
|
||||
|
||||
/* Now we are looking for a new thread to execute! */
|
||||
|
||||
CPSID i // Disable interrupts
|
||||
LDR r1, [r2] // Is there another thread ready to execute?
|
||||
CBNZ r1, __tx_ts_restore // Yes, schedule it
|
||||
|
||||
/* The following is the idle wait processing... in this case, no threads are ready for execution and the
|
||||
system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts
|
||||
are disabled to allow use of WFI for waiting for a thread to arrive. */
|
||||
|
||||
__tx_ts_wait
|
||||
CPSID i // Disable interrupts
|
||||
LDR r1, [r2] // Pickup the next thread to execute pointer
|
||||
CBNZ r1, __tx_ts_ready // If non-NULL, a new thread is ready!
|
||||
#ifdef TX_ENABLE_WFI
|
||||
DSB // Ensure no outstanding memory transactions
|
||||
WFI // Wait for interrupt
|
||||
ISB // Ensure pipeline is flushed
|
||||
#endif
|
||||
CPSIE i // Enable interrupts
|
||||
B __tx_ts_wait // Loop to continue waiting
|
||||
|
||||
/* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are
|
||||
already in the handler! */
|
||||
|
||||
__tx_ts_ready
|
||||
MOV r7, #0x08000000 // Build clear PendSV value
|
||||
MOV r8, #0xE000E000 // Build base NVIC address
|
||||
STR r7, [r8, #0xD04] // Clear any PendSV
|
||||
|
||||
__tx_ts_restore
|
||||
LDR r7, [r1, #4] ; Pickup the current thread run count
|
||||
MOV32 r4, _tx_timer_time_slice ; Build address of time-slice variable
|
||||
LDR r5, [r1, #24] ; Pickup thread's current time-slice
|
||||
ADD r7, r7, #1 ; Increment the thread run count
|
||||
STR r7, [r1, #4] ; Store the new run count
|
||||
;
|
||||
; /* Setup global time-slice with thread's current time-slice. */
|
||||
;
|
||||
STR r5, [r4] ; Setup global time-slice
|
||||
|
||||
/* A thread is ready, make the current thread the new thread
|
||||
and enable interrupts. */
|
||||
|
||||
STR r1, [r0] // Setup the current thread pointer to the new thread
|
||||
CPSIE i // Enable interrupts
|
||||
|
||||
/* Increment the thread run count. */
|
||||
|
||||
LDR r7, [r1, #4] // Pickup the current thread run count
|
||||
LDR r4, =_tx_timer_time_slice // Build address of time-slice variable
|
||||
LDR r5, [r1, #24] // Pickup thread's current time-slice
|
||||
ADD r7, r7, #1 // Increment the thread run count
|
||||
STR r7, [r1, #4] // Store the new run count
|
||||
|
||||
/* Setup global time-slice with thread's current time-slice. */
|
||||
|
||||
STR r5, [r4] // Setup global time-slice
|
||||
|
||||
IF :DEF: TX_ENABLE_EXECUTION_CHANGE_NOTIFY
|
||||
;
|
||||
; /* Call the thread entry function to indicate the thread is executing. */
|
||||
;
|
||||
PUSH {r0, r1} ; Save r0 and r1
|
||||
BL _tx_execution_thread_enter ; Call the thread execution enter function
|
||||
POP {r0, r1} ; Recover r0 and r1
|
||||
/* Call the thread entry function to indicate the thread is executing. */
|
||||
PUSH {r0, r1} // Save r0 and r1
|
||||
BL _tx_execution_thread_enter // Call the thread execution enter function
|
||||
POP {r0, r1} // Recover r0 and r1
|
||||
ENDIF
|
||||
;
|
||||
; /* Restore the thread context and PSP. */
|
||||
;
|
||||
LDR r12, [r1, #8] ; Pickup thread's stack pointer
|
||||
|
||||
MRS r5, CONTROL ; Pickup current CONTROL register
|
||||
LDR r4, [r1, #0x98] ; Pickup current user mode flag
|
||||
BIC r5, r5, #1 ; Clear the UNPRIV bit
|
||||
ORR r4, r4, r5 ; Build new CONTROL register
|
||||
MSR CONTROL, r4 ; Setup new CONTROL register
|
||||
/* Restore the thread context and PSP. */
|
||||
|
||||
LDR r0, =0xE000ED94 ; Build MPU control reg address
|
||||
MOV r3, #0 ; Build disable value
|
||||
STR r3, [r0] ; Disable MPU
|
||||
LDR r0, [r1, #0x90] ; Pickup the module instance pointer
|
||||
CBZ r0, skip_mpu_setup ; Is this thread owned by a module? No, skip MPU setup
|
||||
LDR r1, [r0, #0x64] ; Pickup MPU register[0]
|
||||
CBZ r1, skip_mpu_setup ; Is protection required for this module? No, skip MPU setup
|
||||
LDR r1, =0xE000ED9C ; Build address of MPU base register
|
||||
LDR r12, [r1, #8] // Pickup thread's stack pointer
|
||||
|
||||
; Use alias registers to quickly load MPU
|
||||
ADD r0, r0, #100 ; Build address of MPU register start in thread control block
|
||||
LDM r0!,{r2-r9} ; Load MPU regions 0-3
|
||||
STM r1,{r2-r9} ; Store MPU regions 0-3
|
||||
LDM r0!,{r2-r9} ; Load MPU regions 4-7
|
||||
STM r1,{r2-r9} ; Store MPU regions 4-7
|
||||
LDR r0, =0xE000ED94 ; Build MPU control reg address
|
||||
MOV r1, #5 ; Build enable value with background region enabled
|
||||
STR r1, [r0] ; Enable MPU
|
||||
MRS r5, CONTROL // Pickup current CONTROL register
|
||||
LDR r4, [r1, #0x98] // Pickup current user mode flag
|
||||
BIC r5, r5, #1 // Clear the UNPRIV bit
|
||||
ORR r4, r4, r5 // Build new CONTROL register
|
||||
MSR CONTROL, r4 // Setup new CONTROL register
|
||||
|
||||
LDR r0, =0xE000ED94 // Build MPU control reg address
|
||||
MOV r3, #0 // Build disable value
|
||||
STR r3, [r0] // Disable MPU
|
||||
LDR r0, [r1, #0x90] // Pickup the module instance pointer
|
||||
CBZ r0, skip_mpu_setup // Is this thread owned by a module? No, skip MPU setup
|
||||
LDR r1, [r0, #0x64] // Pickup MPU register[0]
|
||||
CBZ r1, skip_mpu_setup // Is protection required for this module? No, skip MPU setup
|
||||
LDR r1, =0xE000ED9C // Build address of MPU base register
|
||||
|
||||
// Use alias registers to quickly load MPU
|
||||
ADD r0, r0, #100 // Build address of MPU register start in thread control block
|
||||
LDM r0!,{r2-r9} // Load first four MPU regions
|
||||
STM r1,{r2-r9} // Store first four MPU regions
|
||||
LDM r0,{r2-r9} // Load second four MPU regions
|
||||
STM r1,{r2-r9} // Store second four MPU regions
|
||||
LDR r0, =0xE000ED94 // Build MPU control reg address
|
||||
MOV r1, #5 // Build enable value with background region enabled
|
||||
STR r1, [r0] // Enable MPU
|
||||
skip_mpu_setup
|
||||
LDMIA r12!, {LR} ; Pickup LR
|
||||
IF :DEF: __ARMVFP__
|
||||
TST LR, #0x10 ; Determine if the VFP extended frame is present
|
||||
BNE _skip_vfp_restore ; If not, skip VFP restore
|
||||
VLDMIA r12!, {s16-s31} ; Yes, restore additional VFP registers
|
||||
LDMIA r12!, {LR} // Pickup LR
|
||||
IF {TARGET_FPU_VFP} = {TRUE}
|
||||
TST LR, #0x10 // Determine if the VFP extended frame is present
|
||||
BNE _skip_vfp_restore // If not, skip VFP restore
|
||||
VLDMIA r12!, {s16-s31} // Yes, restore additional VFP registers
|
||||
_skip_vfp_restore
|
||||
ENDIF
|
||||
LDMIA r12!, {r4-r11} ; Recover thread's registers
|
||||
MSR PSP, r12 ; Setup the thread's stack pointer
|
||||
;
|
||||
; /* Return to thread. */
|
||||
;
|
||||
BX lr ; Return to thread!
|
||||
;
|
||||
; /* The following is the idle wait processing... in this case, no threads are ready for execution and the
|
||||
; system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts
|
||||
; are disabled to allow use of WFI for waiting for a thread to arrive. */
|
||||
;
|
||||
__tx_ts_wait
|
||||
CPSID i ; Disable interrupts
|
||||
LDR r1, [r2] ; Pickup the next thread to execute pointer
|
||||
STR r1, [r0] ; Store it in the current pointer
|
||||
CBNZ r1, __tx_ts_ready ; If non-NULL, a new thread is ready!
|
||||
IF :DEF:TX_ENABLE_WFI
|
||||
DSB ; Ensure no outstanding memory transactions
|
||||
WFI ; Wait for interrupt
|
||||
ISB ; Ensure pipeline is flushed
|
||||
ENDIF
|
||||
CPSIE i ; Enable interrupts
|
||||
B __tx_ts_wait ; Loop to continue waiting
|
||||
;
|
||||
; /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are
|
||||
; already in the handler! */
|
||||
;
|
||||
__tx_ts_ready
|
||||
MOV r7, #0x08000000 ; Build clear PendSV value
|
||||
MOV r8, #0xE000E000 ; Build base NVIC address
|
||||
STR r7, [r8, #0xD04] ; Clear any PendSV
|
||||
;
|
||||
; /* Re-enable interrupts and restore new thread. */
|
||||
;
|
||||
CPSIE i ; Enable interrupts
|
||||
B __tx_ts_restore ; Restore the thread
|
||||
;}
|
||||
LDMIA r12!, {r4-r11} // Recover thread's registers
|
||||
MSR PSP, r12 // Setup the thread's stack pointer
|
||||
|
||||
/* Return to thread. */
|
||||
|
||||
BX lr // Return to thread!
|
||||
|
||||
|
||||
/* SVC Handler. */
|
||||
|
||||
;
|
||||
; /* SVC Handler. */
|
||||
;
|
||||
EXPORT SVC_Handler
|
||||
EXPORT __tx_SVCallHandler
|
||||
SVC_Handler
|
||||
__tx_SVCallHandler
|
||||
;{
|
||||
MRS r0, PSP ; Pickup the PSP stack
|
||||
LDR r1, [r0, #24] ; Pickup the point of interrupt
|
||||
LDRB r2, [r1, #-2] ; Pickup the SVC parameter
|
||||
;
|
||||
; Determine which SVC trap we are processing
|
||||
;
|
||||
CMP r2, #1 ; Is it the entry into ThreadX?
|
||||
BNE _tx_thread_user_return ; No, return to user mode
|
||||
;
|
||||
; At this point we have an SVC 1, which means we are entering the kernel from a module thread with user mode selected
|
||||
;
|
||||
LDR r2, =_txm_module_priv ; Subtract 1 because of THUMB mode.
|
||||
SUB r2, r2, #1 ; Temporary fix until ARM describes how to load label above correctly.
|
||||
CMP r1, r2 ; Did we come from user_mode_entry?
|
||||
IT NE ; If no (not equal), then...
|
||||
BXNE lr ; return from where we came.
|
||||
MRS r0, PSP // Pickup the PSP stack
|
||||
LDR r1, [r0, #24] // Pickup the point of interrupt
|
||||
LDRB r2, [r1, #-2] // Pickup the SVC parameter
|
||||
|
||||
LDR r3, [r0, #20] ; This is the saved LR
|
||||
LDR r1, =_tx_thread_current_ptr ; Build current thread pointer address
|
||||
LDR r2, [r1] ; Pickup current thread pointer
|
||||
MOV r1, #0 ; Build clear value
|
||||
STR r1, [r2, #0x98] ; Clear the current user mode selection for thread
|
||||
STR r3, [r2, #0xA0] ; Save the original LR in thread control block
|
||||
/* Determine which SVC trap we are processing */
|
||||
|
||||
; If there is memory protection, use kernel stack
|
||||
LDR r0, [r2, #0x90] ; Load the module instance ptr
|
||||
LDR r0, [r0, #0x0C] ; Load the module property flags
|
||||
TST r0, #2 ; Check if memory protected
|
||||
CMP r2, #1 // Is it the entry into ThreadX?
|
||||
BNE _tx_thread_user_return // No, return to user mode
|
||||
|
||||
/* At this point we have an SVC 1, which means we are entering
|
||||
the kernel from a module thread with user mode selected. */
|
||||
|
||||
LDR r2, =_txm_module_priv // Load address of where we should have come from
|
||||
SUB r2, r2, #1 // Subtract 1 because of THUMB mode.
|
||||
CMP r1, r2 // Did we come from user_mode_entry?
|
||||
IT NE // If no (not equal), then...
|
||||
BXNE lr // return from where we came.
|
||||
|
||||
LDR r3, [r0, #20] // This is the saved LR
|
||||
LDR r1, =_tx_thread_current_ptr // Build current thread pointer address
|
||||
LDR r2, [r1] // Pickup current thread pointer
|
||||
MOV r1, #0 // Build clear value
|
||||
STR r1, [r2, #0x98] // Clear the current user mode selection for thread
|
||||
STR r3, [r2, #0xA0] // Save the original LR in thread control block
|
||||
|
||||
/* If there is memory protection, use kernel stack */
|
||||
LDR r0, [r2, #0x90] // Load the module instance ptr
|
||||
LDR r0, [r0, #0x0C] // Load the module property flags
|
||||
TST r0, #2 // Check if memory protected
|
||||
BEQ _tx_skip_kernel_stack_enter
|
||||
|
||||
; Switch to the module thread's kernel stack
|
||||
LDR r0, [r2, #0xA8] ; Load the module kernel stack end
|
||||
/* Switch to the module thread's kernel stack */
|
||||
LDR r0, [r2, #0xA8] // Load the module kernel stack end
|
||||
IF :LNOT: :DEF: TXM_MODULE_KERNEL_STACK_MAINTENANCE_DISABLE
|
||||
LDR r1, [r2, #0xA4] ; Load the module kernel stack start
|
||||
LDR r3, [r2, #0xAC] ; Load the module kernel stack size
|
||||
STR r1, [r2, #12] ; Set stack start
|
||||
STR r0, [r2, #16] ; Set stack end
|
||||
STR r3, [r2, #20] ; Set stack size
|
||||
LDR r1, [r2, #0xA4] // Load the module kernel stack start
|
||||
LDR r3, [r2, #0xAC] // Load the module kernel stack size
|
||||
STR r1, [r2, #12] // Set stack start
|
||||
STR r0, [r2, #16] // Set stack end
|
||||
STR r3, [r2, #20] // Set stack size
|
||||
ENDIF
|
||||
|
||||
MRS r3, PSP ; Pickup thread stack pointer
|
||||
STR r3, [r2, #0xB0] ; Save thread stack pointer
|
||||
MRS r3, PSP // Pickup thread stack pointer
|
||||
STR r3, [r2, #0xB0] // Save thread stack pointer
|
||||
|
||||
; Build kernel stack by copying thread stack two registers at a time
|
||||
ADD r3, r3, #32 ; start at bottom of hardware stack
|
||||
/* Build kernel stack by copying thread stack two registers at a time */
|
||||
ADD r3, r3, #32 // Start at bottom of hardware stack
|
||||
LDMDB r3!,{r1-r2}
|
||||
STMDB r0!,{r1-r2}
|
||||
LDMDB r3!,{r1-r2}
|
||||
@@ -455,44 +444,44 @@ __tx_SVCallHandler
|
||||
LDMDB r3!,{r1-r2}
|
||||
STMDB r0!,{r1-r2}
|
||||
|
||||
MSR PSP, r0 ; Set kernel stack pointer
|
||||
MSR PSP, r0 // Set kernel stack pointer
|
||||
|
||||
_tx_skip_kernel_stack_enter
|
||||
MRS r0, CONTROL ; Pickup current CONTROL register
|
||||
BIC r0, r0, #1 ; Clear the UNPRIV bit
|
||||
MSR CONTROL, r0 ; Setup new CONTROL register
|
||||
BX lr ; Return to thread
|
||||
MRS r0, CONTROL // Pickup current CONTROL register
|
||||
BIC r0, r0, #1 // Clear the UNPRIV bit
|
||||
MSR CONTROL, r0 // Setup new CONTROL register
|
||||
BX lr // Return to thread
|
||||
|
||||
_tx_thread_user_return
|
||||
LDR r2, =_txm_module_user_mode_exit ; Subtract 1 because of THUMB mode.
|
||||
SUB r2, r2, #1 ; Temporary fix until ARM describes how to load label above correctly.
|
||||
CMP r1, r2 ; Did we come from user_mode_exit?
|
||||
IT NE ; If no (not equal), then...
|
||||
BXNE lr ; return from where we came
|
||||
LDR r2, =_txm_module_user_mode_exit // Load address of where we should have come from
|
||||
SUB r2, r2, #1 // Subtract 1 because of THUMB mode.
|
||||
CMP r1, r2 // Did we come from user_mode_exit?
|
||||
IT NE // If no (not equal), then...
|
||||
BXNE lr // return from where we came
|
||||
|
||||
LDR r1, =_tx_thread_current_ptr ; Build current thread pointer address
|
||||
LDR r2, [r1] ; Pickup current thread pointer
|
||||
LDR r1, [r2, #0x9C] ; Pick up user mode
|
||||
STR r1, [r2, #0x98] ; Set the current user mode selection for thread
|
||||
LDR r1, =_tx_thread_current_ptr // Build current thread pointer address
|
||||
LDR r2, [r1] // Pickup current thread pointer
|
||||
LDR r1, [r2, #0x9C] // Pick up user mode
|
||||
STR r1, [r2, #0x98] // Set the current user mode selection for thread
|
||||
|
||||
; If there is memory protection, use kernel stack
|
||||
LDR r0, [r2, #0x90] ; Load the module instance ptr
|
||||
LDR r0, [r0, #0x0C] ; Load the module property flags
|
||||
TST r0, #2 ; Check if memory protected
|
||||
/* If there is memory protection, use kernel stack */
|
||||
LDR r0, [r2, #0x90] // Load the module instance ptr
|
||||
LDR r0, [r0, #0x0C] // Load the module property flags
|
||||
TST r0, #2 // Check if memory protected
|
||||
BEQ _tx_skip_kernel_stack_exit
|
||||
|
||||
IF :LNOT: :DEF: TXM_MODULE_KERNEL_STACK_MAINTENANCE_DISABLE
|
||||
LDR r0, [r2, #0xB4] ; Load the module thread stack start
|
||||
LDR r1, [r2, #0xB8] ; Load the module thread stack end
|
||||
LDR r3, [r2, #0xBC] ; Load the module thread stack size
|
||||
STR r0, [r2, #12] ; Set stack start
|
||||
STR r1, [r2, #16] ; Set stack end
|
||||
STR r3, [r2, #20] ; Set stack size
|
||||
LDR r0, [r2, #0xB4] // Load the module thread stack start
|
||||
LDR r1, [r2, #0xB8] // Load the module thread stack end
|
||||
LDR r3, [r2, #0xBC] // Load the module thread stack size
|
||||
STR r0, [r2, #12] // Set stack start
|
||||
STR r1, [r2, #16] // Set stack end
|
||||
STR r3, [r2, #20] // Set stack size
|
||||
ENDIF
|
||||
LDR r0, [r2, #0xB0] ; Load the module thread stack pointer
|
||||
MRS r3, PSP ; Pickup kernel stack pointer
|
||||
LDR r0, [r2, #0xB0] // Load the module thread stack pointer
|
||||
MRS r3, PSP // Pickup kernel stack pointer
|
||||
|
||||
; Copy kernel hardware stack to module thread stack.
|
||||
/* Copy kernel hardware stack to module thread stack. */
|
||||
LDM r3!,{r1-r2}
|
||||
STM r0!,{r1-r2}
|
||||
LDM r3!,{r1-r2}
|
||||
@@ -501,38 +490,35 @@ _tx_thread_user_return
|
||||
STM r0!,{r1-r2}
|
||||
LDM r3!,{r1-r2}
|
||||
STM r0!,{r1-r2}
|
||||
SUB r0, r0, #32 ; Subtract 32 to get back to top of stack
|
||||
MSR PSP, r0 ; Set thread stack pointer
|
||||
SUB r0, r0, #32 // Subtract 32 to get back to top of stack
|
||||
MSR PSP, r0 // Set thread stack pointer
|
||||
|
||||
LDR r1, =_tx_thread_current_ptr ; Build current thread pointer address
|
||||
LDR r2, [r1] ; Pickup current thread pointer
|
||||
LDR r1, [r2, #0x9C] ; Pick up user mode
|
||||
LDR r1, =_tx_thread_current_ptr // Build current thread pointer address
|
||||
LDR r2, [r1] // Pickup current thread pointer
|
||||
LDR r1, [r2, #0x9C] // Pick up user mode
|
||||
|
||||
_tx_skip_kernel_stack_exit
|
||||
MRS r0, CONTROL ; Pickup current CONTROL register
|
||||
ORR r0, r0, r1 ; OR in the user mode bit
|
||||
MSR CONTROL, r0 ; Setup new CONTROL register
|
||||
BX lr ; Return to thread
|
||||
;}
|
||||
MRS r0, CONTROL // Pickup current CONTROL register
|
||||
ORR r0, r0, r1 // OR in the user mode bit
|
||||
MSR CONTROL, r0 // Setup new CONTROL register
|
||||
BX lr // Return to thread
|
||||
|
||||
IF :DEF: __ARMVFP__
|
||||
IF {TARGET_FPU_VFP} = {TRUE}
|
||||
EXPORT tx_thread_fpu_enable
|
||||
tx_thread_fpu_enable
|
||||
;
|
||||
; /* Automatic VPF logic is supported, this function is present only for
|
||||
; backward compatibility purposes and therefore simply returns. */
|
||||
;
|
||||
BX LR ; Return to caller
|
||||
ENDIF
|
||||
|
||||
IF :DEF: __ARMVFP__
|
||||
EXPORT tx_thread_fpu_disable
|
||||
tx_thread_fpu_disable
|
||||
;
|
||||
; /* Automatic VPF logic is supported, this function is present only for
|
||||
; backward compatibility purposes and therefore simply returns. */
|
||||
;
|
||||
BX LR ; Return to caller
|
||||
|
||||
/* Automatic VPF logic is supported, this function is present only for
|
||||
backward compatibility purposes and therefore simply returns. */
|
||||
|
||||
BX LR // Return to caller
|
||||
|
||||
EXPORT _tx_vfp_access
|
||||
_tx_vfp_access
|
||||
VMOV.F32 s0, s0 // Simply access the VFP
|
||||
BX lr // Return to caller
|
||||
|
||||
ENDIF
|
||||
|
||||
ALIGN 4
|
||||
|
||||
@@ -1,133 +1,133 @@
|
||||
;/**************************************************************************/
|
||||
;/* */
|
||||
;/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
;/* */
|
||||
;/* This software is licensed under the Microsoft Software License */
|
||||
;/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
;/* and in the root directory of this software. */
|
||||
;/* */
|
||||
;/**************************************************************************/
|
||||
;
|
||||
;
|
||||
;/**************************************************************************/
|
||||
;/**************************************************************************/
|
||||
;/** */
|
||||
;/** ThreadX Component */
|
||||
;/** */
|
||||
;/** Thread */
|
||||
;/** */
|
||||
;/**************************************************************************/
|
||||
;/**************************************************************************/
|
||||
;
|
||||
;
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
/* */
|
||||
/* This software is licensed under the Microsoft Software License */
|
||||
/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
/* and in the root directory of this software. */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
/** */
|
||||
/** ThreadX Component */
|
||||
/** */
|
||||
/** Thread */
|
||||
/** */
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
|
||||
AREA ||.text||, CODE, READONLY
|
||||
;/**************************************************************************/
|
||||
;/* */
|
||||
;/* FUNCTION RELEASE */
|
||||
;/* */
|
||||
;/* _tx_thread_stack_build Cortex-M4/AC5 */
|
||||
;/* 6.1 */
|
||||
;/* AUTHOR */
|
||||
;/* */
|
||||
;/* William E. Lamie, Microsoft Corporation */
|
||||
;/* */
|
||||
;/* DESCRIPTION */
|
||||
;/* */
|
||||
;/* This function builds a stack frame on the supplied thread's stack. */
|
||||
;/* The stack frame results in a fake interrupt return to the supplied */
|
||||
;/* function pointer. */
|
||||
;/* */
|
||||
;/* INPUT */
|
||||
;/* */
|
||||
;/* thread_ptr Pointer to thread control blk */
|
||||
;/* function_ptr Pointer to return function */
|
||||
;/* */
|
||||
;/* OUTPUT */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* CALLS */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* CALLED BY */
|
||||
;/* */
|
||||
;/* _tx_thread_create Create thread service */
|
||||
;/* */
|
||||
;/* RELEASE HISTORY */
|
||||
;/* */
|
||||
;/* DATE NAME DESCRIPTION */
|
||||
;/* */
|
||||
;/* 09-30-2020 William E. Lamie Initial Version 6.1 */
|
||||
;/* */
|
||||
;/**************************************************************************/
|
||||
;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID))
|
||||
;{
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* FUNCTION RELEASE */
|
||||
/* */
|
||||
/* _tx_thread_stack_build Cortex-M4/AC5 */
|
||||
/* 6.1.2 */
|
||||
/* AUTHOR */
|
||||
/* */
|
||||
/* William E. Lamie, Microsoft Corporation */
|
||||
/* */
|
||||
/* DESCRIPTION */
|
||||
/* */
|
||||
/* This function builds a stack frame on the supplied thread's stack. */
|
||||
/* The stack frame results in a fake interrupt return to the supplied */
|
||||
/* function pointer. */
|
||||
/* */
|
||||
/* INPUT */
|
||||
/* */
|
||||
/* thread_ptr Pointer to thread control blk */
|
||||
/* function_ptr Pointer to return function */
|
||||
/* */
|
||||
/* OUTPUT */
|
||||
/* */
|
||||
/* None */
|
||||
/* */
|
||||
/* CALLS */
|
||||
/* */
|
||||
/* None */
|
||||
/* */
|
||||
/* CALLED BY */
|
||||
/* */
|
||||
/* _tx_thread_create Create thread service */
|
||||
/* */
|
||||
/* RELEASE HISTORY */
|
||||
/* */
|
||||
/* DATE NAME DESCRIPTION */
|
||||
/* */
|
||||
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
|
||||
/* 11-09-2020 Scott Larson Modified comment(s), */
|
||||
/* resulting in version 6.1.2 */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
// VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID))
|
||||
// {
|
||||
EXPORT _tx_thread_stack_build
|
||||
_tx_thread_stack_build
|
||||
;
|
||||
;
|
||||
; /* Build a fake interrupt frame. The form of the fake interrupt stack
|
||||
; on the Cortex-M4 should look like the following after it is built:
|
||||
;
|
||||
; Stack Top:
|
||||
; LR Interrupted LR (LR at time of PENDSV)
|
||||
; r4 Initial value for r4
|
||||
; r5 Initial value for r5
|
||||
; r6 Initial value for r6
|
||||
; r7 Initial value for r7
|
||||
; r8 Initial value for r8
|
||||
; r9 Initial value for r9
|
||||
; r10 Initial value for r10
|
||||
; r11 Initial value for r11
|
||||
; r0 Initial value for r0 (Hardware stack starts here!!)
|
||||
; r1 Initial value for r1
|
||||
; r2 Initial value for r2
|
||||
; r3 Initial value for r3
|
||||
; r12 Initial value for r12
|
||||
; lr Initial value for lr
|
||||
; pc Initial value for pc
|
||||
; xPSR Initial value for xPSR
|
||||
;
|
||||
; Stack Bottom: (higher memory address) */
|
||||
;
|
||||
LDR r2, [r0, #16] ; Pickup end of stack area
|
||||
BIC r2, r2, #0x7 ; Align frame for 8-byte alignment
|
||||
SUB r2, r2, #68 ; Subtract frame size
|
||||
LDR r3, =0xFFFFFFFD ; Build initial LR value
|
||||
STR r3, [r2, #0] ; Save on the stack
|
||||
;
|
||||
; /* Actually build the stack frame. */
|
||||
;
|
||||
MOV r3, #0 ; Build initial register value
|
||||
STR r3, [r2, #4] ; Store initial r4
|
||||
STR r3, [r2, #8] ; Store initial r5
|
||||
STR r3, [r2, #12] ; Store initial r6
|
||||
STR r3, [r2, #16] ; Store initial r7
|
||||
STR r3, [r2, #20] ; Store initial r8
|
||||
STR r3, [r2, #24] ; Store initial r9
|
||||
STR r3, [r2, #28] ; Store initial r10
|
||||
STR r3, [r2, #32] ; Store initial r11
|
||||
;
|
||||
; /* Hardware stack follows. */
|
||||
;
|
||||
STR r3, [r2, #36] ; Store initial r0
|
||||
STR r3, [r2, #40] ; Store initial r1
|
||||
STR r3, [r2, #44] ; Store initial r2
|
||||
STR r3, [r2, #48] ; Store initial r3
|
||||
STR r3, [r2, #52] ; Store initial r12
|
||||
MOV r3, #0xFFFFFFFF ; Poison EXC_RETURN value
|
||||
STR r3, [r2, #56] ; Store initial lr
|
||||
STR r1, [r2, #60] ; Store initial pc
|
||||
MOV r3, #0x01000000 ; Only T-bit need be set
|
||||
STR r3, [r2, #64] ; Store initial xPSR
|
||||
;
|
||||
; /* Setup stack pointer. */
|
||||
; thread_ptr -> tx_thread_stack_ptr = r2;
|
||||
;
|
||||
STR r2, [r0, #8] ; Save stack pointer in thread's
|
||||
; control block
|
||||
BX lr ; Return to caller
|
||||
;}
|
||||
|
||||
/* Build a fake interrupt frame. The form of the fake interrupt stack
|
||||
on the Cortex-M should look like the following after it is built:
|
||||
|
||||
Stack Top:
|
||||
LR Interrupted LR (LR at time of PENDSV)
|
||||
r4 Initial value for r4
|
||||
r5 Initial value for r5
|
||||
r6 Initial value for r6
|
||||
r7 Initial value for r7
|
||||
r8 Initial value for r8
|
||||
r9 Initial value for r9
|
||||
r10 Initial value for r10
|
||||
r11 Initial value for r11
|
||||
r0 Initial value for r0 (Hardware stack starts here!!)
|
||||
r1 Initial value for r1
|
||||
r2 Initial value for r2
|
||||
r3 Initial value for r3
|
||||
r12 Initial value for r12
|
||||
lr Initial value for lr
|
||||
pc Initial value for pc
|
||||
xPSR Initial value for xPSR
|
||||
|
||||
Stack Bottom: (higher memory address) */
|
||||
|
||||
LDR r2, [r0, #16] // Pickup end of stack area
|
||||
BIC r2, r2, #0x7 // Align frame for 8-byte alignment
|
||||
SUB r2, r2, #68 // Subtract frame size
|
||||
LDR r3, =0xFFFFFFFD // Build initial LR value
|
||||
STR r3, [r2, #0] // Save on the stack
|
||||
|
||||
/* Actually build the stack frame. */
|
||||
|
||||
MOV r3, #0 // Build initial register value
|
||||
STR r3, [r2, #4] // Store initial r4
|
||||
STR r3, [r2, #8] // Store initial r5
|
||||
STR r3, [r2, #12] // Store initial r6
|
||||
STR r3, [r2, #16] // Store initial r7
|
||||
STR r3, [r2, #20] // Store initial r8
|
||||
STR r3, [r2, #24] // Store initial r9
|
||||
STR r3, [r2, #28] // Store initial r10
|
||||
STR r3, [r2, #32] // Store initial r11
|
||||
|
||||
/* Hardware stack follows. */
|
||||
|
||||
STR r3, [r2, #36] // Store initial r0
|
||||
STR r3, [r2, #40] // Store initial r1
|
||||
STR r3, [r2, #44] // Store initial r2
|
||||
STR r3, [r2, #48] // Store initial r3
|
||||
STR r3, [r2, #52] // Store initial r12
|
||||
MOV r3, #0xFFFFFFFF // Poison EXC_RETURN value
|
||||
STR r3, [r2, #56] // Store initial lr
|
||||
STR r1, [r2, #60] // Store initial pc
|
||||
MOV r3, #0x01000000 // Only T-bit need be set
|
||||
STR r3, [r2, #64] // Store initial xPSR
|
||||
|
||||
/* Setup stack pointer. */
|
||||
// thread_ptr -> tx_thread_stack_ptr = r2;
|
||||
|
||||
STR r2, [r0, #8] // Save stack pointer in thread's
|
||||
// control block
|
||||
BX lr // Return to caller
|
||||
// }
|
||||
END
|
||||
|
||||
@@ -1,85 +1,87 @@
|
||||
;/**************************************************************************/
|
||||
;/* */
|
||||
;/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
;/* */
|
||||
;/* This software is licensed under the Microsoft Software License */
|
||||
;/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
;/* and in the root directory of this software. */
|
||||
;/* */
|
||||
;/**************************************************************************/
|
||||
;
|
||||
;
|
||||
;/**************************************************************************/
|
||||
;/**************************************************************************/
|
||||
;/** */
|
||||
;/** ThreadX Component */
|
||||
;/** */
|
||||
;/** Thread */
|
||||
;/** */
|
||||
;/**************************************************************************/
|
||||
;/**************************************************************************/
|
||||
;
|
||||
;
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
/* */
|
||||
/* This software is licensed under the Microsoft Software License */
|
||||
/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
/* and in the root directory of this software. */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
/** */
|
||||
/** ThreadX Component */
|
||||
/** */
|
||||
/** Thread */
|
||||
/** */
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
|
||||
AREA ||.text||, CODE, READONLY
|
||||
;/**************************************************************************/
|
||||
;/* */
|
||||
;/* FUNCTION RELEASE */
|
||||
;/* */
|
||||
;/* _tx_thread_system_return Cortex-M4/AC5 */
|
||||
;/* 6.1 */
|
||||
;/* AUTHOR */
|
||||
;/* */
|
||||
;/* William E. Lamie, Microsoft Corporation */
|
||||
;/* */
|
||||
;/* DESCRIPTION */
|
||||
;/* */
|
||||
;/* This function is target processor specific. It is used to transfer */
|
||||
;/* control from a thread back to the ThreadX system. Only a */
|
||||
;/* minimal context is saved since the compiler assumes temp registers */
|
||||
;/* are going to get slicked by a function call anyway. */
|
||||
;/* */
|
||||
;/* INPUT */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* OUTPUT */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* CALLS */
|
||||
;/* */
|
||||
;/* _tx_thread_schedule Thread scheduling loop */
|
||||
;/* */
|
||||
;/* CALLED BY */
|
||||
;/* */
|
||||
;/* ThreadX components */
|
||||
;/* */
|
||||
;/* RELEASE HISTORY */
|
||||
;/* */
|
||||
;/* DATE NAME DESCRIPTION */
|
||||
;/* */
|
||||
;/* 09-30-2020 William E. Lamie Initial Version 6.1 */
|
||||
;/* */
|
||||
;/**************************************************************************/
|
||||
;VOID _tx_thread_system_return(VOID)
|
||||
;{
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* FUNCTION RELEASE */
|
||||
/* */
|
||||
/* _tx_thread_system_return Cortex-M4/AC5 */
|
||||
/* 6.1.2 */
|
||||
/* AUTHOR */
|
||||
/* */
|
||||
/* William E. Lamie, Microsoft Corporation */
|
||||
/* */
|
||||
/* DESCRIPTION */
|
||||
/* */
|
||||
/* This function is target processor specific. It is used to transfer */
|
||||
/* control from a thread back to the ThreadX system. Only a */
|
||||
/* minimal context is saved since the compiler assumes temp registers */
|
||||
/* are going to get slicked by a function call anyway. */
|
||||
/* */
|
||||
/* INPUT */
|
||||
/* */
|
||||
/* None */
|
||||
/* */
|
||||
/* OUTPUT */
|
||||
/* */
|
||||
/* None */
|
||||
/* */
|
||||
/* CALLS */
|
||||
/* */
|
||||
/* _tx_thread_schedule Thread scheduling loop */
|
||||
/* */
|
||||
/* CALLED BY */
|
||||
/* */
|
||||
/* ThreadX components */
|
||||
/* */
|
||||
/* RELEASE HISTORY */
|
||||
/* */
|
||||
/* DATE NAME DESCRIPTION */
|
||||
/* */
|
||||
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
|
||||
/* 11-09-2020 Scott Larson Modified comment(s), */
|
||||
/* resulting in version 6.1.2 */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
// VOID _tx_thread_system_return(VOID)
|
||||
// {
|
||||
EXPORT _tx_thread_system_return
|
||||
_tx_thread_system_return
|
||||
;
|
||||
; /* Return to real scheduler via PendSV. Note that this routine is often
|
||||
; replaced with in-line assembly in tx_port.h to improved performance. */
|
||||
;
|
||||
MOV r0, #0x10000000 ; Load PENDSVSET bit
|
||||
MOV r1, #0xE000E000 ; Load NVIC base
|
||||
STR r0, [r1, #0xD04] ; Set PENDSVBIT in ICSR
|
||||
MRS r0, IPSR ; Pickup IPSR
|
||||
CMP r0, #0 ; Is it a thread returning?
|
||||
BNE _isr_context ; If ISR, skip interrupt enable
|
||||
MRS r1, PRIMASK ; Thread context returning, pickup PRIMASK
|
||||
CPSIE i ; Enable interrupts
|
||||
MSR PRIMASK, r1 ; Restore original interrupt posture
|
||||
|
||||
/* Return to real scheduler via PendSV. Note that this routine is often
|
||||
replaced with in-line assembly in tx_port.h to improved performance. */
|
||||
|
||||
MOV r0, #0x10000000 // Load PENDSVSET bit
|
||||
MOV r1, #0xE000E000 // Load NVIC base
|
||||
STR r0, [r1, #0xD04] // Set PENDSVBIT in ICSR
|
||||
MRS r0, IPSR // Pickup IPSR
|
||||
CMP r0, #0 // Is it a thread returning?
|
||||
BNE _isr_context // If ISR, skip interrupt enable
|
||||
MRS r1, PRIMASK // Thread context returning, pickup PRIMASK
|
||||
CPSIE i // Enable interrupts
|
||||
MSR PRIMASK, r1 // Restore original interrupt posture
|
||||
_isr_context
|
||||
BX lr ; Return to caller
|
||||
;}
|
||||
BX lr // Return to caller
|
||||
|
||||
// }
|
||||
END
|
||||
|
||||
@@ -1,26 +1,25 @@
|
||||
;/**************************************************************************/
|
||||
;/* */
|
||||
;/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
;/* */
|
||||
;/* This software is licensed under the Microsoft Software License */
|
||||
;/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
;/* and in the root directory of this software. */
|
||||
;/* */
|
||||
;/**************************************************************************/
|
||||
;
|
||||
;
|
||||
;/**************************************************************************/
|
||||
;/**************************************************************************/
|
||||
;/** */
|
||||
;/** ThreadX Component */
|
||||
;/** */
|
||||
;/** Timer */
|
||||
;/** */
|
||||
;/**************************************************************************/
|
||||
;/**************************************************************************/
|
||||
;
|
||||
;
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
/* */
|
||||
/* This software is licensed under the Microsoft Software License */
|
||||
/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
/* and in the root directory of this software. */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
/** */
|
||||
/** ThreadX Component */
|
||||
/** */
|
||||
/** Timer */
|
||||
/** */
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
|
||||
IMPORT _tx_timer_time_slice
|
||||
IMPORT _tx_timer_system_clock
|
||||
IMPORT _tx_timer_current_ptr
|
||||
@@ -33,227 +32,225 @@
|
||||
IMPORT _tx_thread_preempt_disable
|
||||
IMPORT _tx_thread_current_ptr
|
||||
IMPORT _tx_thread_execute_ptr
|
||||
;
|
||||
;
|
||||
|
||||
AREA ||.text||, CODE, READONLY
|
||||
PRESERVE8
|
||||
;/**************************************************************************/
|
||||
;/* */
|
||||
;/* FUNCTION RELEASE */
|
||||
;/* */
|
||||
;/* _tx_timer_interrupt Cortex-M4/AC5 */
|
||||
;/* 6.1 */
|
||||
;/* AUTHOR */
|
||||
;/* */
|
||||
;/* William E. Lamie, Microsoft Corporation */
|
||||
;/* */
|
||||
;/* DESCRIPTION */
|
||||
;/* */
|
||||
;/* This function processes the hardware timer interrupt. This */
|
||||
;/* processing includes incrementing the system clock and checking for */
|
||||
;/* time slice and/or timer expiration. If either is found, the */
|
||||
;/* interrupt context save/restore functions are called along with the */
|
||||
;/* expiration functions. */
|
||||
;/* */
|
||||
;/* INPUT */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* OUTPUT */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* CALLS */
|
||||
;/* */
|
||||
;/* _tx_timer_expiration_process Timer expiration processing */
|
||||
;/* _tx_thread_time_slice Time slice interrupted thread */
|
||||
;/* */
|
||||
;/* CALLED BY */
|
||||
;/* */
|
||||
;/* interrupt vector */
|
||||
;/* */
|
||||
;/* RELEASE HISTORY */
|
||||
;/* */
|
||||
;/* DATE NAME DESCRIPTION */
|
||||
;/* */
|
||||
;/* 09-30-2020 William E. Lamie Initial Version 6.1 */
|
||||
;/* */
|
||||
;/**************************************************************************/
|
||||
;VOID _tx_timer_interrupt(VOID)
|
||||
;{
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* FUNCTION RELEASE */
|
||||
/* */
|
||||
/* _tx_timer_interrupt Cortex-M4/AC5 */
|
||||
/* 6.1.2 */
|
||||
/* AUTHOR */
|
||||
/* */
|
||||
/* William E. Lamie, Microsoft Corporation */
|
||||
/* */
|
||||
/* DESCRIPTION */
|
||||
/* */
|
||||
/* This function processes the hardware timer interrupt. This */
|
||||
/* processing includes incrementing the system clock and checking for */
|
||||
/* time slice and/or timer expiration. If either is found, the */
|
||||
/* expiration functions are called. */
|
||||
/* */
|
||||
/* INPUT */
|
||||
/* */
|
||||
/* None */
|
||||
/* */
|
||||
/* OUTPUT */
|
||||
/* */
|
||||
/* None */
|
||||
/* */
|
||||
/* CALLS */
|
||||
/* */
|
||||
/* _tx_timer_expiration_process Timer expiration processing */
|
||||
/* _tx_thread_time_slice Time slice interrupted thread */
|
||||
/* */
|
||||
/* CALLED BY */
|
||||
/* */
|
||||
/* interrupt vector */
|
||||
/* */
|
||||
/* RELEASE HISTORY */
|
||||
/* */
|
||||
/* DATE NAME DESCRIPTION */
|
||||
/* */
|
||||
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
|
||||
/* 11-09-2020 Scott Larson Modified comment(s), */
|
||||
/* resulting in version 6.1.2 */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
// VOID _tx_timer_interrupt(VOID)
|
||||
// {
|
||||
EXPORT _tx_timer_interrupt
|
||||
_tx_timer_interrupt
|
||||
;
|
||||
; /* Upon entry to this routine, it is assumed that context save has already
|
||||
; been called, and therefore the compiler scratch registers are available
|
||||
; for use. */
|
||||
;
|
||||
; /* Increment the system clock. */
|
||||
; _tx_timer_system_clock++;
|
||||
;
|
||||
MOV32 r1, _tx_timer_system_clock ; Pickup address of system clock
|
||||
LDR r0, [r1, #0] ; Pickup system clock
|
||||
ADD r0, r0, #1 ; Increment system clock
|
||||
STR r0, [r1, #0] ; Store new system clock
|
||||
;
|
||||
; /* Test for time-slice expiration. */
|
||||
; if (_tx_timer_time_slice)
|
||||
; {
|
||||
;
|
||||
MOV32 r3, _tx_timer_time_slice ; Pickup address of time-slice
|
||||
LDR r2, [r3, #0] ; Pickup time-slice
|
||||
CBZ r2, __tx_timer_no_time_slice ; Is it non-active?
|
||||
; Yes, skip time-slice processing
|
||||
;
|
||||
; /* Decrement the time_slice. */
|
||||
; _tx_timer_time_slice--;
|
||||
;
|
||||
SUB r2, r2, #1 ; Decrement the time-slice
|
||||
STR r2, [r3, #0] ; Store new time-slice value
|
||||
;
|
||||
; /* Check for expiration. */
|
||||
; if (__tx_timer_time_slice == 0)
|
||||
;
|
||||
CBNZ r2, __tx_timer_no_time_slice ; Has it expired?
|
||||
;
|
||||
; /* Set the time-slice expired flag. */
|
||||
; _tx_timer_expired_time_slice = TX_TRUE;
|
||||
;
|
||||
MOV32 r3, _tx_timer_expired_time_slice ; Pickup address of expired flag
|
||||
MOV r0, #1 ; Build expired value
|
||||
STR r0, [r3, #0] ; Set time-slice expiration flag
|
||||
;
|
||||
; }
|
||||
;
|
||||
__tx_timer_no_time_slice
|
||||
;
|
||||
; /* Test for timer expiration. */
|
||||
; if (*_tx_timer_current_ptr)
|
||||
; {
|
||||
;
|
||||
MOV32 r1, _tx_timer_current_ptr ; Pickup current timer pointer address
|
||||
LDR r0, [r1, #0] ; Pickup current timer
|
||||
LDR r2, [r0, #0] ; Pickup timer list entry
|
||||
CBZ r2, __tx_timer_no_timer ; Is there anything in the list?
|
||||
; No, just increment the timer
|
||||
;
|
||||
; /* Set expiration flag. */
|
||||
; _tx_timer_expired = TX_TRUE;
|
||||
;
|
||||
MOV32 r3, _tx_timer_expired ; Pickup expiration flag address
|
||||
MOV r2, #1 ; Build expired value
|
||||
STR r2, [r3, #0] ; Set expired flag
|
||||
B __tx_timer_done ; Finished timer processing
|
||||
;
|
||||
; }
|
||||
; else
|
||||
; {
|
||||
__tx_timer_no_timer
|
||||
;
|
||||
; /* No timer expired, increment the timer pointer. */
|
||||
; _tx_timer_current_ptr++;
|
||||
;
|
||||
ADD r0, r0, #4 ; Move to next timer
|
||||
;
|
||||
; /* Check for wrap-around. */
|
||||
; if (_tx_timer_current_ptr == _tx_timer_list_end)
|
||||
;
|
||||
MOV32 r3, _tx_timer_list_end ; Pickup addr of timer list end
|
||||
LDR r2, [r3, #0] ; Pickup list end
|
||||
CMP r0, r2 ; Are we at list end?
|
||||
BNE __tx_timer_skip_wrap ; No, skip wrap-around logic
|
||||
;
|
||||
; /* Wrap to beginning of list. */
|
||||
; _tx_timer_current_ptr = _tx_timer_list_start;
|
||||
;
|
||||
MOV32 r3, _tx_timer_list_start ; Pickup addr of timer list start
|
||||
LDR r0, [r3, #0] ; Set current pointer to list start
|
||||
;
|
||||
__tx_timer_skip_wrap
|
||||
;
|
||||
STR r0, [r1, #0] ; Store new current timer pointer
|
||||
; }
|
||||
;
|
||||
__tx_timer_done
|
||||
;
|
||||
;
|
||||
; /* See if anything has expired. */
|
||||
; if ((_tx_timer_expired_time_slice) || (_tx_timer_expired))
|
||||
; {
|
||||
;
|
||||
MOV32 r3, _tx_timer_expired_time_slice ; Pickup addr of expired flag
|
||||
LDR r2, [r3, #0] ; Pickup time-slice expired flag
|
||||
CBNZ r2, __tx_something_expired ; Did a time-slice expire?
|
||||
; If non-zero, time-slice expired
|
||||
MOV32 r1, _tx_timer_expired ; Pickup addr of other expired flag
|
||||
LDR r0, [r1, #0] ; Pickup timer expired flag
|
||||
CBZ r0, __tx_timer_nothing_expired ; Did a timer expire?
|
||||
; No, nothing expired
|
||||
;
|
||||
__tx_something_expired
|
||||
;
|
||||
;
|
||||
STMDB sp!, {r0, lr} ; Save the lr register on the stack
|
||||
; and save r0 just to keep 8-byte alignment
|
||||
;
|
||||
; /* Did a timer expire? */
|
||||
; if (_tx_timer_expired)
|
||||
; {
|
||||
;
|
||||
MOV32 r1, _tx_timer_expired ; Pickup addr of expired flag
|
||||
LDR r0, [r1, #0] ; Pickup timer expired flag
|
||||
CBZ r0, __tx_timer_dont_activate ; Check for timer expiration
|
||||
; If not set, skip timer activation
|
||||
;
|
||||
; /* Process timer expiration. */
|
||||
; _tx_timer_expiration_process();
|
||||
;
|
||||
BL _tx_timer_expiration_process ; Call the timer expiration handling routine
|
||||
;
|
||||
; }
|
||||
__tx_timer_dont_activate
|
||||
;
|
||||
; /* Did time slice expire? */
|
||||
; if (_tx_timer_expired_time_slice)
|
||||
; {
|
||||
;
|
||||
MOV32 r3, _tx_timer_expired_time_slice ; Pickup addr of time-slice expired
|
||||
LDR r2, [r3, #0] ; Pickup the actual flag
|
||||
CBZ r2, __tx_timer_not_ts_expiration ; See if the flag is set
|
||||
; No, skip time-slice processing
|
||||
;
|
||||
; /* Time slice interrupted thread. */
|
||||
; _tx_thread_time_slice();
|
||||
|
||||
BL _tx_thread_time_slice ; Call time-slice processing
|
||||
MOV32 r0, _tx_thread_preempt_disable ; Build address of preempt disable flag
|
||||
LDR r1, [r0] ; Is the preempt disable flag set?
|
||||
CBNZ r1, __tx_timer_skip_time_slice ; Yes, skip the PendSV logic
|
||||
MOV32 r0, _tx_thread_current_ptr ; Build current thread pointer address
|
||||
LDR r1, [r0] ; Pickup the current thread pointer
|
||||
MOV32 r2, _tx_thread_execute_ptr ; Build execute thread pointer address
|
||||
LDR r3, [r2] ; Pickup the execute thread pointer
|
||||
MOV32 r0, 0xE000ED04 ; Build address of control register
|
||||
MOV32 r2, 0x10000000 ; Build value for PendSV bit
|
||||
CMP r1, r3 ; Are they the same?
|
||||
BEQ __tx_timer_skip_time_slice ; If the same, there was no time-slice performed
|
||||
STR r2, [r0] ; Not the same, issue the PendSV for preemption
|
||||
/* Upon entry to this routine, it is assumed that the compiler scratch registers are available
|
||||
for use. */
|
||||
|
||||
/* Increment the system clock. */
|
||||
// _tx_timer_system_clock++;
|
||||
|
||||
LDR r1, =_tx_timer_system_clock // Pickup address of system clock
|
||||
LDR r0, [r1, #0] // Pickup system clock
|
||||
ADD r0, r0, #1 // Increment system clock
|
||||
STR r0, [r1, #0] // Store new system clock
|
||||
|
||||
/* Test for time-slice expiration. */
|
||||
// if (_tx_timer_time_slice)
|
||||
// {
|
||||
|
||||
LDR r3, =_tx_timer_time_slice // Pickup address of time-slice
|
||||
LDR r2, [r3, #0] // Pickup time-slice
|
||||
CBZ r2, __tx_timer_no_time_slice // Is it non-active?
|
||||
// Yes, skip time-slice processing
|
||||
|
||||
/* Decrement the time_slice. */
|
||||
// _tx_timer_time_slice--;
|
||||
|
||||
SUB r2, r2, #1 // Decrement the time-slice
|
||||
STR r2, [r3, #0] // Store new time-slice value
|
||||
|
||||
/* Check for expiration. */
|
||||
// if (__tx_timer_time_slice == 0)
|
||||
|
||||
CBNZ r2, __tx_timer_no_time_slice // Has it expired?
|
||||
|
||||
/* Set the time-slice expired flag. */
|
||||
// _tx_timer_expired_time_slice = TX_TRUE;
|
||||
|
||||
LDR r3, =_tx_timer_expired_time_slice // Pickup address of expired flag
|
||||
MOV r0, #1 // Build expired value
|
||||
STR r0, [r3, #0] // Set time-slice expiration flag
|
||||
|
||||
// }
|
||||
|
||||
__tx_timer_no_time_slice
|
||||
|
||||
/* Test for timer expiration. */
|
||||
// if (*_tx_timer_current_ptr)
|
||||
// {
|
||||
|
||||
LDR r1, =_tx_timer_current_ptr // Pickup current timer pointer address
|
||||
LDR r0, [r1, #0] // Pickup current timer
|
||||
LDR r2, [r0, #0] // Pickup timer list entry
|
||||
CBZ r2, __tx_timer_no_timer // Is there anything in the list?
|
||||
// No, just increment the timer
|
||||
|
||||
/* Set expiration flag. */
|
||||
// _tx_timer_expired = TX_TRUE;
|
||||
|
||||
LDR r3, =_tx_timer_expired // Pickup expiration flag address
|
||||
MOV r2, #1 // Build expired value
|
||||
STR r2, [r3, #0] // Set expired flag
|
||||
B __tx_timer_done // Finished timer processing
|
||||
|
||||
// }
|
||||
// else
|
||||
// {
|
||||
__tx_timer_no_timer
|
||||
|
||||
/* No timer expired, increment the timer pointer. */
|
||||
// _tx_timer_current_ptr++;
|
||||
|
||||
ADD r0, r0, #4 // Move to next timer
|
||||
|
||||
/* Check for wrap-around. */
|
||||
// if (_tx_timer_current_ptr == _tx_timer_list_end)
|
||||
|
||||
LDR r3, =_tx_timer_list_end // Pickup addr of timer list end
|
||||
LDR r2, [r3, #0] // Pickup list end
|
||||
CMP r0, r2 // Are we at list end?
|
||||
BNE __tx_timer_skip_wrap // No, skip wrap-around logic
|
||||
|
||||
/* Wrap to beginning of list. */
|
||||
// _tx_timer_current_ptr = _tx_timer_list_start;
|
||||
|
||||
LDR r3, =_tx_timer_list_start // Pickup addr of timer list start
|
||||
LDR r0, [r3, #0] // Set current pointer to list start
|
||||
|
||||
__tx_timer_skip_wrap
|
||||
|
||||
STR r0, [r1, #0] // Store new current timer pointer
|
||||
// }
|
||||
|
||||
__tx_timer_done
|
||||
|
||||
/* See if anything has expired. */
|
||||
// if ((_tx_timer_expired_time_slice) || (_tx_timer_expired))
|
||||
// {
|
||||
|
||||
LDR r3, =_tx_timer_expired_time_slice // Pickup addr of expired flag
|
||||
LDR r2, [r3, #0] // Pickup time-slice expired flag
|
||||
CBNZ r2, __tx_something_expired // Did a time-slice expire?
|
||||
// If non-zero, time-slice expired
|
||||
LDR r1, =_tx_timer_expired // Pickup addr of other expired flag
|
||||
LDR r0, [r1, #0] // Pickup timer expired flag
|
||||
CBZ r0, __tx_timer_nothing_expired // Did a timer expire?
|
||||
// No, nothing expired
|
||||
|
||||
__tx_something_expired
|
||||
|
||||
STMDB sp!, {r0, lr} // Save the lr register on the stack
|
||||
// and save r0 just to keep 8-byte alignment
|
||||
|
||||
/* Did a timer expire? */
|
||||
// if (_tx_timer_expired)
|
||||
// {
|
||||
|
||||
LDR r1, =_tx_timer_expired // Pickup addr of expired flag
|
||||
LDR r0, [r1, #0] // Pickup timer expired flag
|
||||
CBZ r0, __tx_timer_dont_activate // Check for timer expiration
|
||||
// If not set, skip timer activation
|
||||
|
||||
/* Process timer expiration. */
|
||||
// _tx_timer_expiration_process();
|
||||
|
||||
BL _tx_timer_expiration_process // Call the timer expiration handling routine
|
||||
|
||||
// }
|
||||
__tx_timer_dont_activate
|
||||
|
||||
/* Did time slice expire? */
|
||||
// if (_tx_timer_expired_time_slice)
|
||||
// {
|
||||
|
||||
LDR r3, =_tx_timer_expired_time_slice // Pickup addr of time-slice expired
|
||||
LDR r2, [r3, #0] // Pickup the actual flag
|
||||
CBZ r2, __tx_timer_not_ts_expiration // See if the flag is set
|
||||
// No, skip time-slice processing
|
||||
|
||||
/* Time slice interrupted thread. */
|
||||
// _tx_thread_time_slice();
|
||||
|
||||
BL _tx_thread_time_slice // Call time-slice processing
|
||||
LDR r0, =_tx_thread_preempt_disable // Build address of preempt disable flag
|
||||
LDR r1, [r0] // Is the preempt disable flag set?
|
||||
CBNZ r1, __tx_timer_skip_time_slice // Yes, skip the PendSV logic
|
||||
LDR r0, =_tx_thread_current_ptr // Build current thread pointer address
|
||||
LDR r1, [r0] // Pickup the current thread pointer
|
||||
LDR r2, =_tx_thread_execute_ptr // Build execute thread pointer address
|
||||
LDR r3, [r2] // Pickup the execute thread pointer
|
||||
LDR r0, =0xE000ED04 // Build address of control register
|
||||
LDR r2, =0x10000000 // Build value for PendSV bit
|
||||
CMP r1, r3 // Are they the same?
|
||||
BEQ __tx_timer_skip_time_slice // If the same, there was no time-slice performed
|
||||
STR r2, [r0] // Not the same, issue the PendSV for preemption
|
||||
__tx_timer_skip_time_slice
|
||||
;
|
||||
; }
|
||||
;
|
||||
|
||||
// }
|
||||
|
||||
__tx_timer_not_ts_expiration
|
||||
;
|
||||
LDMIA sp!, {r0, lr} ; Recover lr register (r0 is just there for
|
||||
;
|
||||
; }
|
||||
;
|
||||
|
||||
LDMIA sp!, {r0, lr} // Recover lr register (r0 is just there for
|
||||
// the 8-byte stack alignment
|
||||
|
||||
// }
|
||||
|
||||
__tx_timer_nothing_expired
|
||||
|
||||
DSB ; Complete all memory access
|
||||
BX lr ; Return to caller
|
||||
;
|
||||
;}
|
||||
DSB // Complete all memory access
|
||||
BX lr // Return to caller
|
||||
|
||||
// }
|
||||
ALIGN
|
||||
LTORG
|
||||
END
|
||||
|
||||
@@ -1,141 +1,140 @@
|
||||
;/**************************************************************************/
|
||||
;/* */
|
||||
;/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
;/* */
|
||||
;/* This software is licensed under the Microsoft Software License */
|
||||
;/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
;/* and in the root directory of this software. */
|
||||
;/* */
|
||||
;/**************************************************************************/
|
||||
;
|
||||
;
|
||||
;/**************************************************************************/
|
||||
;/**************************************************************************/
|
||||
;/** */
|
||||
;/** ThreadX Component */
|
||||
;/** */
|
||||
;/** Module Manager */
|
||||
;/** */
|
||||
;/**************************************************************************/
|
||||
;/**************************************************************************/
|
||||
;
|
||||
;
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
/* */
|
||||
/* This software is licensed under the Microsoft Software License */
|
||||
/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
/* and in the root directory of this software. */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
/** */
|
||||
/** ThreadX Component */
|
||||
/** */
|
||||
/** Module Manager */
|
||||
/** */
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
|
||||
AREA ||.text||, CODE, READONLY
|
||||
THUMB
|
||||
;/**************************************************************************/
|
||||
;/* */
|
||||
;/* FUNCTION RELEASE */
|
||||
;/* */
|
||||
;/* _txm_module_manager_thread_stack_build Cortex-M4/MPU/AC5 */
|
||||
;/* 6.1 */
|
||||
;/* AUTHOR */
|
||||
;/* */
|
||||
;/* Scott Larson, Microsoft Corporation */
|
||||
;/* */
|
||||
;/* DESCRIPTION */
|
||||
;/* */
|
||||
;/* This function builds a stack frame on the supplied thread's stack. */
|
||||
;/* The stack frame results in a fake interrupt return to the supplied */
|
||||
;/* function pointer. */
|
||||
;/* */
|
||||
;/* INPUT */
|
||||
;/* */
|
||||
;/* thread_ptr Pointer to thread */
|
||||
;/* function_ptr Pointer to shell function */
|
||||
;/* */
|
||||
;/* OUTPUT */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* CALLS */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* CALLED BY */
|
||||
;/* */
|
||||
;/* _tx_thread_create Create thread service */
|
||||
;/* */
|
||||
;/* RELEASE HISTORY */
|
||||
;/* */
|
||||
;/* DATE NAME DESCRIPTION */
|
||||
;/* */
|
||||
;/* 09-30-2020 Scott Larson Initial Version 6.1 */
|
||||
;/* */
|
||||
;/**************************************************************************/
|
||||
;VOID _txm_module_manager_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(TX_THREAD *, TXM_MODULE_INSTANCE *))
|
||||
;{
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* FUNCTION RELEASE */
|
||||
/* */
|
||||
/* _txm_module_manager_thread_stack_build Cortex-M4/MPU/AC5 */
|
||||
/* 6.1.2 */
|
||||
/* AUTHOR */
|
||||
/* */
|
||||
/* Scott Larson, Microsoft Corporation */
|
||||
/* */
|
||||
/* DESCRIPTION */
|
||||
/* */
|
||||
/* This function builds a stack frame on the supplied thread's stack. */
|
||||
/* The stack frame results in a fake interrupt return to the supplied */
|
||||
/* function pointer. */
|
||||
/* */
|
||||
/* INPUT */
|
||||
/* */
|
||||
/* thread_ptr Pointer to thread */
|
||||
/* function_ptr Pointer to shell function */
|
||||
/* */
|
||||
/* OUTPUT */
|
||||
/* */
|
||||
/* None */
|
||||
/* */
|
||||
/* CALLS */
|
||||
/* */
|
||||
/* None */
|
||||
/* */
|
||||
/* CALLED BY */
|
||||
/* */
|
||||
/* _tx_thread_create Create thread service */
|
||||
/* */
|
||||
/* RELEASE HISTORY */
|
||||
/* */
|
||||
/* DATE NAME DESCRIPTION */
|
||||
/* */
|
||||
/* 09-30-2020 Scott Larson Initial Version 6.1 */
|
||||
/* 11-09-2020 Scott Larson Modified comment(s), */
|
||||
/* resulting in version 6.1.2 */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
// VOID _txm_module_manager_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(TX_THREAD *, TXM_MODULE_INSTANCE *))
|
||||
// {
|
||||
EXPORT _txm_module_manager_thread_stack_build
|
||||
_txm_module_manager_thread_stack_build
|
||||
;
|
||||
;
|
||||
; /* Build a fake interrupt frame. The form of the fake interrupt stack
|
||||
; on the Cortex-M should look like the following after it is built:
|
||||
;
|
||||
; Stack Top:
|
||||
; LR Interrupted LR (LR at time of PENDSV)
|
||||
; r4 Initial value for r4
|
||||
; r5 Initial value for r5
|
||||
; r6 Initial value for r6
|
||||
; r7 Initial value for r7
|
||||
; r8 Initial value for r8
|
||||
; r9 Initial value for r9
|
||||
; r10 Initial value for r10
|
||||
; r11 Initial value for r11
|
||||
; r0 Initial value for r0 (Hardware stack starts here!!)
|
||||
; r1 Initial value for r1
|
||||
; r2 Initial value for r2
|
||||
; r3 Initial value for r3
|
||||
; r12 Initial value for r12
|
||||
; lr Initial value for lr
|
||||
; pc Initial value for pc
|
||||
; xPSR Initial value for xPSR
|
||||
;
|
||||
; Stack Bottom: (higher memory address) */
|
||||
;
|
||||
LDR r2, [r0, #16] ; Pickup end of stack area
|
||||
BIC r2, r2, #0x7 ; Align frame
|
||||
SUB r2, r2, #68 ; Subtract frame size
|
||||
LDR r3, =0xFFFFFFFD ; Build initial LR value
|
||||
STR r3, [r2, #0] ; Save on the stack
|
||||
;
|
||||
; /* Actually build the stack frame. */
|
||||
;
|
||||
MOV r3, #0 ; Build initial register value
|
||||
STR r3, [r2, #4] ; Store initial r4
|
||||
STR r3, [r2, #8] ; Store initial r5
|
||||
STR r3, [r2, #12] ; Store initial r6
|
||||
STR r3, [r2, #16] ; Store initial r7
|
||||
STR r3, [r2, #20] ; Store initial r8
|
||||
STR r3, [r2, #28] ; Store initial r10
|
||||
STR r3, [r2, #32] ; Store initial r11
|
||||
;
|
||||
; /* Hardware stack follows. */
|
||||
;
|
||||
STR r0, [r2, #36] ; Store initial r0, which is the thread control block
|
||||
|
||||
LDR r3, [r0, #8] ; Pickup thread entry info pointer,which is in the stack pointer position of the thread control block.
|
||||
; It was setup in the txm_module_manager_thread_create function. It will be overwritten later in this
|
||||
; function with the actual, initial stack pointer.
|
||||
STR r3, [r2, #40] ; Store initial r1, which is the module entry information.
|
||||
LDR r3, [r3, #8] ; Pickup data base register from the module information
|
||||
STR r3, [r2, #24] ; Store initial r9 (data base register)
|
||||
MOV r3, #0 ; Clear r3 again
|
||||
/* Build a fake interrupt frame. The form of the fake interrupt stack
|
||||
on the Cortex-M should look like the following after it is built:
|
||||
|
||||
STR r3, [r2, #44] ; Store initial r2
|
||||
STR r3, [r2, #48] ; Store initial r3
|
||||
STR r3, [r2, #52] ; Store initial r12
|
||||
MOV r3, #0xFFFFFFFF ; Poison EXC_RETURN value
|
||||
STR r3, [r2, #56] ; Store initial lr
|
||||
STR r1, [r2, #60] ; Store initial pc
|
||||
MOV r3, #0x01000000 ; Only T-bit need be set
|
||||
STR r3, [r2, #64] ; Store initial xPSR
|
||||
;
|
||||
; /* Setup stack pointer. */
|
||||
; thread_ptr -> tx_thread_stack_ptr = r2;
|
||||
;
|
||||
STR r2, [r0, #8] ; Save stack pointer in thread's control block
|
||||
BX lr ; Return to caller
|
||||
;}
|
||||
Stack Top:
|
||||
LR Interrupted LR (LR at time of PENDSV)
|
||||
r4 Initial value for r4
|
||||
r5 Initial value for r5
|
||||
r6 Initial value for r6
|
||||
r7 Initial value for r7
|
||||
r8 Initial value for r8
|
||||
r9 Initial value for r9
|
||||
r10 Initial value for r10
|
||||
r11 Initial value for r11
|
||||
r0 Initial value for r0 (Hardware stack starts here!!)
|
||||
r1 Initial value for r1
|
||||
r2 Initial value for r2
|
||||
r3 Initial value for r3
|
||||
r12 Initial value for r12
|
||||
lr Initial value for lr
|
||||
pc Initial value for pc
|
||||
xPSR Initial value for xPSR
|
||||
|
||||
Stack Bottom: (higher memory address) */
|
||||
|
||||
LDR r2, [r0, #16] // Pickup end of stack area
|
||||
BIC r2, r2, #0x7 // Align frame
|
||||
SUB r2, r2, #68 // Subtract frame size
|
||||
LDR r3, =0xFFFFFFFD // Build initial LR value
|
||||
STR r3, [r2, #0] // Save on the stack
|
||||
|
||||
/* Actually build the stack frame. */
|
||||
|
||||
MOV r3, #0 // Build initial register value
|
||||
STR r3, [r2, #4] // Store initial r4
|
||||
STR r3, [r2, #8] // Store initial r5
|
||||
STR r3, [r2, #12] // Store initial r6
|
||||
STR r3, [r2, #16] // Store initial r7
|
||||
STR r3, [r2, #20] // Store initial r8
|
||||
STR r3, [r2, #28] // Store initial r10
|
||||
STR r3, [r2, #32] // Store initial r11
|
||||
|
||||
/* Hardware stack follows. */
|
||||
|
||||
STR r0, [r2, #36] // Store initial r0, which is the thread control block
|
||||
|
||||
LDR r3, [r0, #8] // Pickup thread entry info pointer,which is in the stack pointer position of the thread control block.
|
||||
// It was setup in the txm_module_manager_thread_create function. It will be overwritten later in this
|
||||
// function with the actual, initial stack pointer.
|
||||
STR r3, [r2, #40] // Store initial r1, which is the module entry information.
|
||||
LDR r3, [r3, #8] // Pickup data base register from the module information
|
||||
STR r3, [r2, #24] // Store initial r9 (data base register)
|
||||
MOV r3, #0 // Clear r3 again
|
||||
|
||||
STR r3, [r2, #44] // Store initial r2
|
||||
STR r3, [r2, #48] // Store initial r3
|
||||
STR r3, [r2, #52] // Store initial r12
|
||||
MOV r3, #0xFFFFFFFF // Poison EXC_RETURN value
|
||||
STR r3, [r2, #56] // Store initial lr
|
||||
STR r1, [r2, #60] // Store initial pc
|
||||
MOV r3, #0x01000000 // Only T-bit need be set
|
||||
STR r3, [r2, #64] // Store initial xPSR
|
||||
|
||||
/* Setup stack pointer. */
|
||||
// thread_ptr -> tx_thread_stack_ptr = r2;
|
||||
|
||||
STR r2, [r0, #8] // Save stack pointer in thread's control block
|
||||
BX lr // Return to caller
|
||||
// }
|
||||
END
|
||||
|
||||
|
||||
@@ -1,88 +1,90 @@
|
||||
;/**************************************************************************/
|
||||
;/* */
|
||||
;/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
;/* */
|
||||
;/* This software is licensed under the Microsoft Software License */
|
||||
;/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
;/* and in the root directory of this software. */
|
||||
;/* */
|
||||
;/**************************************************************************/
|
||||
;
|
||||
;
|
||||
;/**************************************************************************/
|
||||
;/**************************************************************************/
|
||||
;/** */
|
||||
;/** ThreadX Component */
|
||||
;/** */
|
||||
;/** Module Manager */
|
||||
;/** */
|
||||
;/**************************************************************************/
|
||||
;/**************************************************************************/
|
||||
;
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
/* */
|
||||
/* This software is licensed under the Microsoft Software License */
|
||||
/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
/* and in the root directory of this software. */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
/** */
|
||||
/** ThreadX Component */
|
||||
/** */
|
||||
/** Module Manager */
|
||||
/** */
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
|
||||
IMPORT _txm_module_manager_kernel_dispatch
|
||||
IMPORT _tx_thread_current_ptr
|
||||
;
|
||||
|
||||
AREA ||.text||, CODE, READONLY, ALIGN=5
|
||||
THUMB
|
||||
;/**************************************************************************/
|
||||
;/* */
|
||||
;/* FUNCTION RELEASE */
|
||||
;/* */
|
||||
;/* _txm_module_manager_user_mode_entry Cortex-M4/MPU/AC5 */
|
||||
;/* 6.1 */
|
||||
;/* AUTHOR */
|
||||
;/* */
|
||||
;/* Scott Larson, Microsoft Corporation */
|
||||
;/* */
|
||||
;/* DESCRIPTION */
|
||||
;/* */
|
||||
;/* This function allows modules to enter kernel mode. */
|
||||
;/* */
|
||||
;/* INPUT */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* OUTPUT */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* CALLS */
|
||||
;/* */
|
||||
;/* SVC 1 Enter kernel mode */
|
||||
;/* SVC 2 Exit kernel mode */
|
||||
;/* */
|
||||
;/* CALLED BY */
|
||||
;/* */
|
||||
;/* Modules in user mode */
|
||||
;/* */
|
||||
;/* RELEASE HISTORY */
|
||||
;/* */
|
||||
;/* DATE NAME DESCRIPTION */
|
||||
;/* */
|
||||
;/* 09-30-2020 Scott Larson Initial Version 6.1 */
|
||||
;/* */
|
||||
;/**************************************************************************/;
|
||||
;VOID _txm_module_manager_user_mode_entry(VOID)
|
||||
;{
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* FUNCTION RELEASE */
|
||||
/* */
|
||||
/* _txm_module_manager_user_mode_entry Cortex-M4/MPU/AC5 */
|
||||
/* 6.1.2 */
|
||||
/* AUTHOR */
|
||||
/* */
|
||||
/* Scott Larson, Microsoft Corporation */
|
||||
/* */
|
||||
/* DESCRIPTION */
|
||||
/* */
|
||||
/* This function allows modules to enter kernel mode. */
|
||||
/* */
|
||||
/* INPUT */
|
||||
/* */
|
||||
/* None */
|
||||
/* */
|
||||
/* OUTPUT */
|
||||
/* */
|
||||
/* None */
|
||||
/* */
|
||||
/* CALLS */
|
||||
/* */
|
||||
/* SVC 1 Enter kernel mode */
|
||||
/* SVC 2 Exit kernel mode */
|
||||
/* */
|
||||
/* CALLED BY */
|
||||
/* */
|
||||
/* Modules in user mode */
|
||||
/* */
|
||||
/* RELEASE HISTORY */
|
||||
/* */
|
||||
/* DATE NAME DESCRIPTION */
|
||||
/* */
|
||||
/* 09-30-2020 Scott Larson Initial Version 6.1 */
|
||||
/* 11-09-2020 Scott Larson Modified comment(s), */
|
||||
/* resulting in version 6.1.2 */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
// VOID _txm_module_manager_user_mode_entry(VOID)
|
||||
// {
|
||||
EXPORT _txm_module_manager_user_mode_entry
|
||||
_txm_module_manager_user_mode_entry
|
||||
SVC 1 ; Enter kernel
|
||||
SVC 1 // Enter kernel
|
||||
EXPORT _txm_module_priv
|
||||
_txm_module_priv
|
||||
; At this point, we are out of user mode. The original LR has been saved in the
|
||||
; thread control block. Simply call the kernel dispatch function.
|
||||
// At this point, we are out of user mode. The original LR has been saved in the
|
||||
// thread control block. Simply call the kernel dispatch function.
|
||||
BL _txm_module_manager_kernel_dispatch
|
||||
|
||||
; Pickup the original LR value while still in privileged mode
|
||||
LDR r2, =_tx_thread_current_ptr ; Build current thread pointer address
|
||||
LDR r3, [r2] ; Pickup current thread pointer
|
||||
LDR lr, [r3, #0xA0] ; Pickup saved LR from original call
|
||||
// Pickup the original LR value while still in privileged mode
|
||||
LDR r2, =_tx_thread_current_ptr // Build current thread pointer address
|
||||
LDR r3, [r2] // Pickup current thread pointer
|
||||
LDR lr, [r3, #0xA0] // Pickup saved LR from original call
|
||||
|
||||
SVC 2 ; Exit kernel and return to user mode
|
||||
SVC 2 // Exit kernel and return to user mode
|
||||
EXPORT _txm_module_user_mode_exit
|
||||
_txm_module_user_mode_exit
|
||||
BX lr ; Return to the caller
|
||||
;}
|
||||
BX lr // Return to the caller
|
||||
// }
|
||||
ALIGN 32
|
||||
END
|
||||
|
||||
Reference in New Issue
Block a user