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Release 6.1.11

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This commit is contained in:
Yuxin Zhou
2022-04-20 05:07:02 +00:00
parent f851772ce0
commit cef9cb22a5
784 changed files with 57616 additions and 101103 deletions
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9
ports/xtensa/xcc/src/tx_initialize_low_level.c
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@@ -52,7 +52,10 @@ int32_t xt_timer_intnum = -1;
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 12-31-2020 Cadence Design Systems Initial Version 6.1.3 */
/* 12-31-2020 Cadence Design Systems Initial Version 6.1.3 */
/* 04-25-2022 Scott Larson Modified comments and updated */
/* function names, */
/* resulting in version 6.1.11 */
/* */
/**************************************************************************/
VOID _tx_initialize_low_level(VOID)
@@ -154,14 +157,14 @@ VOID _tx_initialize_low_level(VOID)
/* Compute tick divisor if clock freq is not compile-time constant. */
#ifndef XT_CLOCK_FREQ
_xt_tick_divisor_init();
xt_tick_divisor_init();
#endif
/* Set up the periodic tick timer (assume enough time to complete init). */
#ifdef XT_CLOCK_FREQ
XT_WSR_CCOMPARE(XT_RSR_CCOUNT() + XT_TICK_DIVISOR);
#else
XT_WSR_CCOMPARE(XT_RSR_CCOUNT() + _xt_tick_divisor);
XT_WSR_CCOMPARE(XT_RSR_CCOUNT() + xt_tick_divisor);
#endif
#if XCHAL_HAVE_XEA3

7
ports/xtensa/xcc/src/tx_timer_interrupt.S
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@@ -64,7 +64,10 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 12-31-2020 Cadence Design Systems Initial Version 6.1.3 */
/* 12-31-2020 Cadence Design Systems Initial Version 6.1.3 */
/* 04-25-2022 Scott Larson Modified comments and updated */
/* function name, */
/* resulting in version 6.1.11 */
/* */
/**************************************************************************/
@@ -128,7 +131,7 @@ _tx_timer_interrupt:
#ifdef XT_CLOCK_FREQ
movi a2, XT_TICK_DIVISOR /* a2 = comparator increment */
#else
movi a3, _xt_tick_divisor
movi a3, xt_tick_divisor
l32i a2, a3, 0 /* a2 = comparator increment */
#endif
rsr a3, XT_CCOMPARE /* a3 = old comparator value */

12
ports/xtensa/xcc/src/xtensa_coproc_handler.S
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@@ -461,8 +461,10 @@ _xt_coproc_restorecs:
//-----------------------------------------------------------------------------
// For XEA3, coprocessor exceptions come here. This is a wrapper function that
// calls _xt_coproc_handler() to do the actual work. Since the handler can be
// interrupted make sure that no context switch occurs.
// calls _xt_coproc_handler() to do the actual work. We don't want the handler
// to be interrupted because that might cause a round-robin switch and leave
// coprocessor context in a confused state. So interrupts are disabled before
// calling the handler. They will be re-enabled on return from exception.
//-----------------------------------------------------------------------------
.text
@@ -474,9 +476,9 @@ _xt_coproc_exc:
#ifdef __XTENSA_CALL0_ABI__
addi a1, a1, -16 // reserve 16 bytes on stack
s32i a0, a1, 0 // save return address
s32i a2, a1, 4 // save a2
s32i a15, a1, 8 // must save a15 (see dispatch)
l32i a2, a1, 4
movi a3, PS_DI_MASK
xps a3, a3 // Set PS.DI, disable interrupts
l32i a3, a2, XT_STK_EXCCAUSE // a3 <- exccause
extui a2, a3, 8, 4 // a2 <- CP index
call0 _xt_coproc_handler
@@ -487,6 +489,8 @@ _xt_coproc_exc:
#else
entry a1, 48 // reserve 16 bytes on stack
s32i a0, a1, 0 // save return address
movi a3, PS_DI_MASK
xps a3, a3 // Set PS.DI, disable interrupts
l32i a3, a2, XT_STK_EXCCAUSE // a3 <- exccause
extui a2, a3, 8, 4 // a2 <- CP index
call0 _xt_coproc_handler

6
ports/xtensa/xcc/src/xtensa_init.c
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@@ -46,17 +46,17 @@
#ifdef XT_RTOS_TIMER_INT
#ifndef XT_CLOCK_FREQ
uint32_t _xt_tick_divisor = 0; /* cached number of cycles per tick */
uint32_t xt_tick_divisor = 0; /* cached number of cycles per tick */
/*
Compute and initialize at run-time the tick divisor (the number of
processor clock cycles in an RTOS tick, used to set the tick timer).
Called when the processor clock frequency is not known at compile-time.
*/
void _xt_tick_divisor_init(void)
void xt_tick_divisor_init(void)
{
#ifdef XT_BOARD
_xt_tick_divisor = xtbsp_clock_freq_hz() / XT_TICK_PER_SEC;
xt_tick_divisor = xtbsp_clock_freq_hz() / XT_TICK_PER_SEC;
#else
#error "No way to obtain processor clock frequency"
#endif /* XT_BOARD */

5
ports/xtensa/xcc/src/xtensa_vectors_xea3.S
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@@ -77,9 +77,6 @@
// The entry point vectors are common for call0 and windowed configurations.
//-----------------------------------------------------------------------------
.extern _DoubleExceptionHandler
.extern _xtos_exc_dispatch
.section .DispatchVector.text, "ax"
#if XCHAL_HAVE_VECBASE
.align 64 // 64-byte alignment needed when vecbase
@@ -105,7 +102,7 @@ _Reserved1:
.weak _DoubleExceptionVector
_DoubleExceptionVector:
j _DoubleExceptionHandler
j _DoubleExceptionHandler // Externally defined
.org 9 // Reserved
.local _Reserved2