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Release 6.1.11

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This commit is contained in:
Yuxin Zhou
2022-04-20 05:07:02 +00:00
parent f851772ce0
commit cef9cb22a5
784 changed files with 57616 additions and 101103 deletions
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12
ports_module/cortex_m0+/ac6/inc/tx_port.h
View File

@@ -26,7 +26,7 @@
/* PORT SPECIFIC C INFORMATION RELEASE */
/* */
/* tx_port.h Cortex-M0+/AC6 */
/* 6.1.10 */
/* 6.1.11 */
/* */
/* AUTHOR */
/* */
@@ -48,6 +48,9 @@
/* DATE NAME DESCRIPTION */
/* */
/* 01-31-2022 Scott Larson Initial Version 6.1.10 */
/* 04-25-2022 Scott Larson Modified comments and added */
/* volatile to registers, */
/* resulting in version 6.1.11 */
/* */
/**************************************************************************/
@@ -123,13 +126,13 @@ typedef unsigned short USHORT;
For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock
source constants would be:
#define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024)
#define TX_TRACE_TIME_SOURCE *((volatile ULONG *) 0x0a800024)
#define TX_TRACE_TIME_MASK 0x0000FFFFUL
*/
#ifndef TX_TRACE_TIME_SOURCE
#define TX_TRACE_TIME_SOURCE *((ULONG *) 0xE0001004)
#define TX_TRACE_TIME_SOURCE *((volatile ULONG *) 0xE0001004)
#endif
#ifndef TX_TRACE_TIME_MASK
#define TX_TRACE_TIME_MASK 0xFFFFFFFFUL
@@ -473,7 +476,8 @@ __attribute__( ( always_inline ) ) static inline void _tx_thread_system_return_i
{
unsigned int interrupt_save;
*((ULONG *) 0xE000ED04) = ((ULONG) 0x10000000);
/* Set PendSV to invoke ThreadX scheduler. */
*((volatile ULONG *) 0xE000ED04) = ((ULONG) 0x10000000);
if (__get_ipsr_value() == 0)
{
interrupt_save = __get_primask_value();

25
ports_module/cortex_m0+/ac6/module_manager/src/tx_thread_schedule.S
View File

@@ -30,7 +30,7 @@
/* FUNCTION RELEASE */
/* */
/* _tx_thread_schedule Cortex-M0+/AC6 */
/* 6.1.10 */
/* 6.1.11 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -63,6 +63,8 @@
/* DATE NAME DESCRIPTION */
/* */
/* 01-31-2022 Scott Larson Initial Version 6.1.10 */
/* 04-25-2022 Scott Larson Optimized MPU configuration, */
/* resulting in version 6.1.11 */
/* */
/**************************************************************************/
// VOID _tx_thread_schedule(VOID)
@@ -338,14 +340,23 @@ __tx_ts_restore:
CMP r0, #0
BEQ skip_mpu_setup // Is this thread owned by a module? No, skip MPU setup
MOV r8, r1 // Copy thread ptr
LDR r1, [r0, #0x64] // Pickup MPU register[0]
CMP r1, #0
MOVS r6, #0x8C
LDR r2, [r0, r6] // Pickup MPU region 5 address
CMP r2, #0
BEQ skip_mpu_setup // Is protection required for this module? No, skip MPU setup
LDR r1, =0xE000ED9C // Build address of MPU base register
// Is the MPU already set up for this module?
MOVS r1, #5 // Select region 5 from MPU
LDR r3, =0xE000ED98 // MPU_RNR register address
STR r1, [r3] // Set region to 5
LDR r1, =0xE000ED9C // MPU_RBAR register address
LDR r3, [r1] // Load address stored in MPU region 5
MOVS r6, #0x10
BICS r2, r2, r6 // Clear VALID bit
CMP r2, r3 // Is module already loaded?
BEQ _tx_enable_mpu // Yes - skip MPU reconfiguration
// Initialize loop to configure MPU registers
// Order doesn't matter, so txm_module_instance_mpu_registers[0]
// will be in region 7 and txm_module_instance_mpu_registers[7] will be in region 0.
MOVS r3, #0x64 // Index of MPU register settings in thread control block
ADD r0, r0, r3 // Build address of MPU register start in thread control block
MOVS r5, #0 // Select region 0
@@ -359,7 +370,7 @@ _tx_mpu_loop:
ADDS r5, r5, #1 // Increment to next region
CMP r5, #8 // Check if all regions have been set
BNE _tx_mpu_loop
_tx_enable_mpu:
LDR r0, =0xE000ED94 // Build MPU control reg address
MOVS r1, #5 // Build enable value with background region enabled
STR r1, [r0] // Enable MPU

14
ports_module/cortex_m0+/gnu/inc/tx_port.h
View File

@@ -26,7 +26,7 @@
/* PORT SPECIFIC C INFORMATION RELEASE */
/* */
/* tx_port.h Cortex-M0+/GNU */
/* 6.1.10 */
/* 6.1.11 */
/* */
/* AUTHOR */
/* */
@@ -48,6 +48,9 @@
/* DATE NAME DESCRIPTION */
/* */
/* 01-31-2022 Scott Larson Initial Version 6.1.10 */
/* 04-25-2022 Scott Larson Modified comments and added */
/* volatile to registers, */
/* resulting in version 6.1.11 */
/* */
/**************************************************************************/
@@ -138,13 +141,13 @@ typedef unsigned short USHORT;
For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock
source constants would be:
#define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024)
#define TX_TRACE_TIME_SOURCE *((volatile ULONG *) 0x0a800024)
#define TX_TRACE_TIME_MASK 0x0000FFFFUL
*/
#ifndef TX_TRACE_TIME_SOURCE
#define TX_TRACE_TIME_SOURCE *((ULONG *) 0xE0001004)
#define TX_TRACE_TIME_SOURCE *((volatile ULONG *) 0xE0001004)
#endif
#ifndef TX_TRACE_TIME_MASK
#define TX_TRACE_TIME_MASK 0xFFFFFFFFUL
@@ -305,7 +308,7 @@ __attribute__( ( always_inline ) ) static inline void __set_control(ULONG contro
else \
{ \
ULONG _tx_fpccr; \
_tx_fpccr = *((ULONG *) 0xE000EF34); \
_tx_fpccr = *((volatile ULONG *) 0xE000EF34); \
_tx_fpccr = _tx_fpccr & ((ULONG) 0x01); \
if (_tx_fpccr == ((ULONG) 0x01)) \
{ \
@@ -487,7 +490,8 @@ __attribute__( ( always_inline ) ) static inline void _tx_thread_system_return_i
{
unsigned int interrupt_save;
*((ULONG *) 0xE000ED04) = ((ULONG) 0x10000000);
/* Set PendSV to invoke ThreadX scheduler. */
*((volatile ULONG *) 0xE000ED04) = ((ULONG) 0x10000000);
if (__get_ipsr_value() == 0)
{
interrupt_save = __get_primask_value();

25
ports_module/cortex_m0+/gnu/module_manager/src/tx_thread_schedule.S
View File

@@ -30,7 +30,7 @@
/* FUNCTION RELEASE */
/* */
/* _tx_thread_schedule Cortex-M0+/GNU */
/* 6.1.10 */
/* 6.1.11 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -63,6 +63,8 @@
/* DATE NAME DESCRIPTION */
/* */
/* 01-31-2022 Scott Larson Initial Version 6.1.10 */
/* 04-25-2022 Scott Larson Optimized MPU configuration, */
/* resulting in version 6.1.11 */
/* */
/**************************************************************************/
// VOID _tx_thread_schedule(VOID)
@@ -338,14 +340,23 @@ __tx_ts_restore:
CMP r0, #0
BEQ skip_mpu_setup // Is this thread owned by a module? No, skip MPU setup
MOV r8, r1 // Copy thread ptr
LDR r1, [r0, #0x64] // Pickup MPU register[0]
CMP r1, #0
MOVS r6, #0x8C
LDR r2, [r0, r6] // Pickup MPU region 5 address
CMP r2, #0
BEQ skip_mpu_setup // Is protection required for this module? No, skip MPU setup
LDR r1, =0xE000ED9C // Build address of MPU base register
// Is the MPU already set up for this module?
MOVS r1, #5 // Select region 5 from MPU
LDR r3, =0xE000ED98 // MPU_RNR register address
STR r1, [r3] // Set region to 5
LDR r1, =0xE000ED9C // MPU_RBAR register address
LDR r3, [r1] // Load address stored in MPU region 5
MOVS r6, #0x10
BICS r2, r2, r6 // Clear VALID bit
CMP r2, r3 // Is module already loaded?
BEQ _tx_enable_mpu // Yes - skip MPU reconfiguration
// Initialize loop to configure MPU registers
// Order doesn't matter, so txm_module_instance_mpu_registers[0]
// will be in region 7 and txm_module_instance_mpu_registers[7] will be in region 0.
MOVS r3, #0x64 // Index of MPU register settings in thread control block
ADD r0, r0, r3 // Build address of MPU register start in thread control block
MOVS r5, #0 // Select region 0
@@ -359,7 +370,7 @@ _tx_mpu_loop:
ADDS r5, r5, #1 // Increment to next region
CMP r5, #8 // Check if all regions have been set
BNE _tx_mpu_loop
_tx_enable_mpu:
LDR r0, =0xE000ED94 // Build MPU control reg address
MOVS r1, #5 // Build enable value with background region enabled
STR r1, [r0] // Enable MPU

6
ports_module/cortex_m0+/iar/example_build/startup.s
View File

@@ -58,9 +58,9 @@ __vector_table
DC32 NMI_Handler ; NMI
DC32 HardFault_Handler ; HardFault
DC32 MemManage_Handler ; MemManage
DC32 0 ; BusFault
DC32 0 ; UsageFault
DC32 HardFault_Handler ; MemManage
DC32 HardFault_Handler ; BusFault
DC32 HardFault_Handler ; UsageFault
DC32 0 ; 7
DC32 0 ; 8
DC32 0 ; 9

13
ports_module/cortex_m0+/iar/inc/tx_port.h
View File

@@ -26,7 +26,7 @@
/* PORT SPECIFIC C INFORMATION RELEASE */
/* */
/* tx_port.h Cortex-M0+/IAR */
/* 6.1.10 */
/* 6.1.11 */
/* */
/* AUTHOR */
/* */
@@ -48,6 +48,9 @@
/* DATE NAME DESCRIPTION */
/* */
/* 01-31-2022 Scott Larson Initial Version 6.1.10 */
/* 04-25-2022 Scott Larson Modified comments and added */
/* volatile to registers, */
/* resulting in version 6.1.11 */
/* */
/**************************************************************************/
@@ -142,14 +145,14 @@ typedef unsigned short USHORT;
For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock
source constants would be:
#define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024)
#define TX_TRACE_TIME_SOURCE *((volatile ULONG *) 0x0a800024)
#define TX_TRACE_TIME_MASK 0x0000FFFFUL
*/
#ifndef TX_MISRA_ENABLE
#ifndef TX_TRACE_TIME_SOURCE
#define TX_TRACE_TIME_SOURCE *((ULONG *) 0xE0001004)
#define TX_TRACE_TIME_SOURCE *((volatile ULONG *) 0xE0001004)
#endif
#else
ULONG _tx_misra_time_stamp_get(VOID);
@@ -361,7 +364,7 @@ __attribute__( ( always_inline ) ) static inline void __set_control(ULONG contro
else \
{ \
ULONG _tx_fpccr; \
_tx_fpccr = *((ULONG *) 0xE000EF34); \
_tx_fpccr = *((volatile ULONG *) 0xE000EF34); \
_tx_fpccr = _tx_fpccr & ((ULONG) 0x01); \
if (_tx_fpccr == ((ULONG) 0x01)) \
{ \
@@ -532,7 +535,7 @@ static void _tx_thread_system_return_inline(void)
__istate_t interrupt_save;
/* Set PendSV to invoke ThreadX scheduler. */
*((ULONG *) 0xE000ED04) = ((ULONG) 0x10000000);
*((volatile ULONG *) 0xE000ED04) = ((ULONG) 0x10000000);
if (__get_IPSR() == 0)
{
interrupt_save = __get_interrupt_state();

34
ports_module/cortex_m0+/iar/module_manager/src/tx_thread_schedule.S
View File

@@ -36,7 +36,7 @@
/* FUNCTION RELEASE */
/* */
/* _tx_thread_schedule Cortex-M0+/IAR */
/* 6.1.10 */
/* 6.1.11 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -69,6 +69,9 @@
/* DATE NAME DESCRIPTION */
/* */
/* 01-31-2022 Scott Larson Initial Version 6.1.10 */
/* 04-25-2022 Scott Larson Optimized MPU configuration, */
/* change handler name, */
/* resulting in version 6.1.11 */
/* */
/**************************************************************************/
// VOID _tx_thread_schedule(VOID)
@@ -103,12 +106,8 @@ __tx_wait_here:
/* Memory Exception Handler. */
PUBLIC MemManage_Handler
PUBLIC BusFault_Handler
PUBLIC UsageFault_Handler
MemManage_Handler:
BusFault_Handler:
UsageFault_Handler:
PUBLIC HardFault_Handler
HardFault_Handler:
CPSID i // Disable interrupts
@@ -326,14 +325,23 @@ __tx_ts_restore:
CMP r0, #0
BEQ skip_mpu_setup // Is this thread owned by a module? No, skip MPU setup
MOV r8, r1 // Copy thread ptr
LDR r1, [r0, #0x64] // Pickup MPU register[0]
CMP r1, #0
MOVS r6, #0x8C
LDR r2, [r0, r6] // Pickup MPU region 5 address
CMP r2, #0
BEQ skip_mpu_setup // Is protection required for this module? No, skip MPU setup
LDR r1, =0xE000ED9C // Build address of MPU base register
// Is the MPU already set up for this module?
MOVS r1, #5 // Select region 5 from MPU
LDR r3, =0xE000ED98 // MPU_RNR register address
STR r1, [r3] // Set region to 5
LDR r1, =0xE000ED9C // MPU_RBAR register address
LDR r3, [r1] // Load address stored in MPU region 5
MOVS r6, #0x10
BICS r2, r2, r6 // Clear VALID bit
CMP r2, r3 // Is module already loaded?
BEQ _tx_enable_mpu // Yes - skip MPU reconfiguration
// Initialize loop to configure MPU registers
// Order doesn't matter, so txm_module_instance_mpu_registers[0]
// will be in region 7 and txm_module_instance_mpu_registers[7] will be in region 0.
MOVS r3, #0x64 // Index of MPU register settings in thread control block
ADD r0, r0, r3 // Build address of MPU register start in thread control block
MOVS r5, #0 // Select region 0
@@ -347,7 +355,7 @@ _tx_mpu_loop:
ADDS r5, r5, #1 // Increment to next region
CMP r5, #8 // Check if all regions have been set
BNE _tx_mpu_loop
_tx_enable_mpu:
LDR r0, =0xE000ED94 // Build MPU control reg address
MOVS r1, #5 // Build enable value with background region enabled
STR r1, [r0] // Enable MPU