7iwind/threadx
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Release 6.1.11

Browse Source
This commit is contained in:
Yuxin Zhou
2022-04-20 05:07:02 +00:00
parent f851772ce0
commit cef9cb22a5
784 changed files with 57616 additions and 101103 deletions
Download Patch File Download Diff File Expand all files Collapse all files

29
ports_module/cortex_m33/ac6/inc/tx_port.h
View File

@@ -26,7 +26,7 @@
/* PORT SPECIFIC C INFORMATION RELEASE */
/* */
/* tx_port.h Cortex-M33 */
/* 6.1.10 */
/* 6.1.11 */
/* */
/* AUTHOR */
/* */
@@ -61,13 +61,16 @@
/* added symbol to enable */
/* stack error handler, */
/* resulting in version 6.1.7 */
/* 10-15-2021 Scott Larson Modified comment(s), improved */
/* 10-15-2021 Scott Larson Modified comment(s), improved */
/* stack check error handling, */
/* resulting in version 6.1.9 */
/* 01-31-2022 Scott Larson Modified comment(s), unified */
/* this file across compilers, */
/* fixed predefined macro, */
/* resulting in version 6.1.10 */
/* 04-25-2022 Scott Larson Modified comments and added */
/* volatile to registers, */
/* resulting in version 6.1.11 */
/* */
/**************************************************************************/
@@ -196,14 +199,14 @@ UINT _tx_thread_secure_stack_free(struct TX_THREAD_STRUCT *tx_thread);
For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock
source constants would be:
#define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024)
#define TX_TRACE_TIME_SOURCE *((volatile ULONG *) 0x0a800024)
#define TX_TRACE_TIME_MASK 0x0000FFFFUL
*/
#ifndef TX_MISRA_ENABLE
#ifndef TX_TRACE_TIME_SOURCE
#define TX_TRACE_TIME_SOURCE *((ULONG *) 0xE0001004)
#define TX_TRACE_TIME_SOURCE *((volatile ULONG *) 0xE0001004)
#endif
#else
ULONG _tx_misra_time_stamp_get(VOID);
@@ -429,9 +432,9 @@ __attribute__( ( always_inline ) ) static inline void _tx_control_set(ULONG cont
#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) { \
ULONG _tx_vfp_state; \
_tx_vfp_state = _tx_control_get(); \
_tx_vfp_state = _tx_control_get(); \
_tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \
_tx_control_set(_tx_vfp_state); \
_tx_control_set(_tx_vfp_state); \
}
#else
@@ -456,26 +459,26 @@ __attribute__( ( always_inline ) ) static inline void _tx_control_set(ULONG cont
if ((_tx_system_state == ((ULONG) 0)) && ((thread_ptr) == _tx_thread_current_ptr)) \
{ \
ULONG _tx_vfp_state; \
_tx_vfp_state = _tx_control_get(); \
_tx_vfp_state = _tx_control_get(); \
_tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \
_tx_control_set(_tx_vfp_state); \
_tx_control_set(_tx_vfp_state); \
} \
else \
{ \
ULONG _tx_fpccr; \
_tx_fpccr = *((ULONG *) 0xE000EF34); \
_tx_fpccr = *((volatile ULONG *) 0xE000EF34); \
_tx_fpccr = _tx_fpccr & ((ULONG) 0x01); \
if (_tx_fpccr == ((ULONG) 0x01)) \
{ \
ULONG _tx_vfp_state; \
_tx_vfp_state = _tx_control_get(); \
_tx_vfp_state = _tx_control_get(); \
_tx_vfp_state = _tx_vfp_state & ((ULONG) 0x4); \
TX_VFP_TOUCH(); \
if (_tx_vfp_state == ((ULONG) 0)) \
{ \
_tx_vfp_state = _tx_control_get(); \
_tx_vfp_state = _tx_control_get(); \
_tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \
_tx_control_set(_tx_vfp_state); \
_tx_control_set(_tx_vfp_state); \
} \
} \
} \
@@ -657,7 +660,7 @@ __attribute__( ( always_inline ) ) static inline void _tx_thread_system_return_i
UINT interrupt_save;
/* Set PendSV to invoke ThreadX scheduler. */
*((ULONG *) 0xE000ED04) = ((ULONG) 0x10000000);
*((volatile ULONG *) 0xE000ED04) = ((ULONG) 0x10000000);
if (_tx_ipsr_get() == 0)
{
interrupt_save = __get_interrupt_posture();

66
ports_module/cortex_m33/ac6/module_manager/src/tx_thread_schedule.S
View File

@@ -29,8 +29,8 @@
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_schedule Cortex-M33/MPU/AC6 */
/* 6.1.7 */
/* _tx_thread_schedule Cortex-M33/AC6 */
/* 6.1.11 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -69,6 +69,9 @@
/* 06-02-2021 Scott Larson Fixed extended stack handling */
/* when calling kernel APIs, */
/* resulting in version 6.1.7 */
/* 04-25-2022 Scott Larson Optimized MPU configuration, */
/* added BASEPRI support, */
/* resulting in version 6.1.11 */
/* */
/**************************************************************************/
// VOID _tx_thread_schedule(VOID)
@@ -128,7 +131,12 @@ MemManage_Handler:
.thumb_func
BusFault_Handler:
#ifdef TX_PORT_USE_BASEPRI
LDR r1, =TX_PORT_BASEPRI // Mask interrupt priorities =< TX_PORT_BASEPRI
MSR BASEPRI, r1
#else
CPSID i // Disable interrupts
#endif /* TX_PORT_USE_BASEPRI */
/* Now pickup and store all the fault related information. */
@@ -195,7 +203,7 @@ BusFault_Handler:
BL _txm_module_manager_memory_fault_handler // Call memory manager fault handler
#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE))
/* Call the thread exit function to indicate the thread is no longer executing. */
CPSID i // Disable interrupts
BL _tx_execution_thread_exit // Call the thread exit function
@@ -211,7 +219,12 @@ BusFault_Handler:
LDR r1, =0x10000000 // Set PENDSVSET bit
STR r1, [r0] // Store ICSR
DSB // Wait for memory access to complete
#ifdef TX_PORT_USE_BASEPRI
MOV r0, 0 // Disable BASEPRI masking (enable interrupts)
MSR BASEPRI, r0
#else
CPSIE i // Enable interrupts
#endif
#ifdef TX_SINGLE_MODE_SECURE
LDR lr, =0xFFFFFFFD // Exception return to secure
#else
@@ -235,12 +248,22 @@ __tx_ts_handler:
#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE))
/* Call the thread exit function to indicate the thread is no longer executing. */
#ifdef TX_PORT_USE_BASEPRI
LDR r1, =TX_PORT_BASEPRI // Mask interrupt priorities =< TX_PORT_BASEPRI
MSR BASEPRI, r1
#else
CPSID i // Disable interrupts
#endif /* TX_PORT_USE_BASEPRI */
PUSH {r0, lr} // Save LR (and r0 just for alignment)
BL _tx_execution_thread_exit // Call the thread exit function
POP {r0, lr} // Recover LR
#ifdef TX_PORT_USE_BASEPRI
MOV r0, 0 // Disable BASEPRI masking (enable interrupts)
MSR BASEPRI, r0
#else
CPSIE i // Enable interrupts
#endif
#endif /* TX_PORT_USE_BASEPRI */
#endif /* EXECUTION PROFILE */
LDR r0, =_tx_thread_current_ptr // Build current thread pointer address
LDR r2, =_tx_thread_execute_ptr // Build execute thread pointer address
@@ -296,7 +319,12 @@ __tx_ts_new:
/* Now we are looking for a new thread to execute! */
#ifdef TX_PORT_USE_BASEPRI
LDR r1, =TX_PORT_BASEPRI // Mask interrupt priorities =< TX_PORT_BASEPRI
MSR BASEPRI, r1
#else
CPSID i // Disable interrupts
#endif
LDR r1, [r2] // Is there another thread ready to execute?
CBNZ r1, __tx_ts_restore // Yes, schedule it
@@ -305,7 +333,12 @@ __tx_ts_new:
are disabled to allow use of WFI for waiting for a thread to arrive. */
__tx_ts_wait:
#ifdef TX_PORT_USE_BASEPRI
LDR r1, =TX_PORT_BASEPRI // Mask interrupt priorities =< TX_PORT_BASEPRI
MSR BASEPRI, r1
#else
CPSID i // Disable interrupts
#endif
LDR r1, [r2] // Pickup the next thread to execute pointer
CBNZ r1, __tx_ts_ready // If non-NULL, a new thread is ready!
#ifdef TX_ENABLE_WFI
@@ -313,7 +346,12 @@ __tx_ts_wait:
WFI // Wait for interrupt
ISB // Ensure pipeline is flushed
#endif
#ifdef TX_PORT_USE_BASEPRI
MOV r4, #0 // Disable BASEPRI masking (enable interrupts)
MSR BASEPRI, r4
#else
CPSIE i // Enable interrupts
#endif
B __tx_ts_wait // Loop to continue waiting
/* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are
@@ -330,7 +368,12 @@ __tx_ts_restore:
and enable interrupts. */
STR r1, [r0] // Setup the current thread pointer to the new thread
#ifdef TX_PORT_USE_BASEPRI
MOV r4, #0 // Disable BASEPRI masking (enable interrupts)
MSR BASEPRI, r4
#else
CPSIE i // Enable interrupts
#endif
/* Increment the thread run count. */
@@ -378,9 +421,17 @@ _skip_secure_restore:
STR r3, [r0] // Disable MPU
LDR r0, [r1, #0x90] // Pickup the module instance pointer
CBZ r0, skip_mpu_setup // Is this thread owned by a module? No, skip MPU setup
LDR r1, [r0, #0x64] // Pickup MPU register[0]
CBZ r1, skip_mpu_setup // Is protection required for this module? No, skip MPU setup
LDR r1, =0xE000ED9C // Build address of MPU base register
LDR r2, [r0, #0x74] // Pickup MPU address of data region
CBZ r2, skip_mpu_setup // Is protection required for this module? No, skip MPU setup
// Is the MPU already set up for this module?
MOV r1, #2 // Select MPU region 2
LDR r3, =0xE000ED98 // MPU_RNR register address
STR r1, [r3] // Set region to 2
LDR r1, =0xE000ED9C // MPU_RBAR register address
LDR r3, [r1] // Load address stored in MPU region 2
CMP r2, r3 // Is module already loaded?
BEQ _tx_enable_mpu // Yes - skip MPU reconfiguration
// Use alias registers to quickly load MPU
LDR r2, =0xE000ED98 // Get region register
@@ -393,6 +444,7 @@ _skip_secure_restore:
STR r2, [r3] // Set region to 4
LDM r0, {r2-r9} // Load second four MPU regions
STM r1, {r2-r9} // Store second four MPU regions
_tx_enable_mpu:
LDR r0, =0xE000ED94 // Build MPU control reg address
MOV r1, #5 // Build enable value with background region enabled
STR r1, [r0] // Enable MPU

29
ports_module/cortex_m33/gnu/inc/tx_port.h
View File

@@ -26,7 +26,7 @@
/* PORT SPECIFIC C INFORMATION RELEASE */
/* */
/* tx_port.h Cortex-M33 */
/* 6.1.10 */
/* 6.1.11 */
/* */
/* AUTHOR */
/* */
@@ -61,13 +61,16 @@
/* added symbol to enable */
/* stack error handler, */
/* resulting in version 6.1.7 */
/* 10-15-2021 Scott Larson Modified comment(s), improved */
/* 10-15-2021 Scott Larson Modified comment(s), improved */
/* stack check error handling, */
/* resulting in version 6.1.9 */
/* 01-31-2022 Scott Larson Modified comment(s), unified */
/* this file across compilers, */
/* fixed predefined macro, */
/* resulting in version 6.1.10 */
/* 04-25-2022 Scott Larson Modified comments and added */
/* volatile to registers, */
/* resulting in version 6.1.11 */
/* */
/**************************************************************************/
@@ -196,14 +199,14 @@ UINT _tx_thread_secure_stack_free(struct TX_THREAD_STRUCT *tx_thread);
For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock
source constants would be:
#define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024)
#define TX_TRACE_TIME_SOURCE *((volatile ULONG *) 0x0a800024)
#define TX_TRACE_TIME_MASK 0x0000FFFFUL
*/
#ifndef TX_MISRA_ENABLE
#ifndef TX_TRACE_TIME_SOURCE
#define TX_TRACE_TIME_SOURCE *((ULONG *) 0xE0001004)
#define TX_TRACE_TIME_SOURCE *((volatile ULONG *) 0xE0001004)
#endif
#else
ULONG _tx_misra_time_stamp_get(VOID);
@@ -429,9 +432,9 @@ __attribute__( ( always_inline ) ) static inline void _tx_control_set(ULONG cont
#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) { \
ULONG _tx_vfp_state; \
_tx_vfp_state = _tx_control_get(); \
_tx_vfp_state = _tx_control_get(); \
_tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \
_tx_control_set(_tx_vfp_state); \
_tx_control_set(_tx_vfp_state); \
}
#else
@@ -456,26 +459,26 @@ __attribute__( ( always_inline ) ) static inline void _tx_control_set(ULONG cont
if ((_tx_system_state == ((ULONG) 0)) && ((thread_ptr) == _tx_thread_current_ptr)) \
{ \
ULONG _tx_vfp_state; \
_tx_vfp_state = _tx_control_get(); \
_tx_vfp_state = _tx_control_get(); \
_tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \
_tx_control_set(_tx_vfp_state); \
_tx_control_set(_tx_vfp_state); \
} \
else \
{ \
ULONG _tx_fpccr; \
_tx_fpccr = *((ULONG *) 0xE000EF34); \
_tx_fpccr = *((volatile ULONG *) 0xE000EF34); \
_tx_fpccr = _tx_fpccr & ((ULONG) 0x01); \
if (_tx_fpccr == ((ULONG) 0x01)) \
{ \
ULONG _tx_vfp_state; \
_tx_vfp_state = _tx_control_get(); \
_tx_vfp_state = _tx_control_get(); \
_tx_vfp_state = _tx_vfp_state & ((ULONG) 0x4); \
TX_VFP_TOUCH(); \
if (_tx_vfp_state == ((ULONG) 0)) \
{ \
_tx_vfp_state = _tx_control_get(); \
_tx_vfp_state = _tx_control_get(); \
_tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \
_tx_control_set(_tx_vfp_state); \
_tx_control_set(_tx_vfp_state); \
} \
} \
} \
@@ -657,7 +660,7 @@ __attribute__( ( always_inline ) ) static inline void _tx_thread_system_return_i
UINT interrupt_save;
/* Set PendSV to invoke ThreadX scheduler. */
*((ULONG *) 0xE000ED04) = ((ULONG) 0x10000000);
*((volatile ULONG *) 0xE000ED04) = ((ULONG) 0x10000000);
if (_tx_ipsr_get() == 0)
{
interrupt_save = __get_interrupt_posture();

66
ports_module/cortex_m33/gnu/module_manager/src/tx_thread_schedule.S
View File

@@ -28,8 +28,8 @@
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_schedule Cortex-M33/MPU/GNU */
/* 6.1.10 */
/* _tx_thread_schedule Cortex-M33/GNU */
/* 6.1.11 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -70,6 +70,9 @@
/* resulting in version 6.1.7 */
/* 01-31-2022 Scott Larson Fixed predefined macro name, */
/* resulting in version 6.1.10 */
/* 04-25-2022 Scott Larson Optimized MPU configuration, */
/* added BASEPRI support, */
/* resulting in version 6.1.11 */
/* */
/**************************************************************************/
// VOID _tx_thread_schedule(VOID)
@@ -129,7 +132,12 @@ MemManage_Handler:
.thumb_func
BusFault_Handler:
#ifdef TX_PORT_USE_BASEPRI
LDR r1, =TX_PORT_BASEPRI // Mask interrupt priorities =< TX_PORT_BASEPRI
MSR BASEPRI, r1
#else
CPSID i // Disable interrupts
#endif /* TX_PORT_USE_BASEPRI */
/* Now pickup and store all the fault related information. */
@@ -196,7 +204,7 @@ BusFault_Handler:
BL _txm_module_manager_memory_fault_handler // Call memory manager fault handler
#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE))
/* Call the thread exit function to indicate the thread is no longer executing. */
CPSID i // Disable interrupts
BL _tx_execution_thread_exit // Call the thread exit function
@@ -212,7 +220,12 @@ BusFault_Handler:
LDR r1, =0x10000000 // Set PENDSVSET bit
STR r1, [r0] // Store ICSR
DSB // Wait for memory access to complete
#ifdef TX_PORT_USE_BASEPRI
MOV r0, 0 // Disable BASEPRI masking (enable interrupts)
MSR BASEPRI, r0
#else
CPSIE i // Enable interrupts
#endif
#ifdef TX_SINGLE_MODE_SECURE
LDR lr, =0xFFFFFFFD // Exception return to secure
#else
@@ -236,12 +249,22 @@ __tx_ts_handler:
#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE))
/* Call the thread exit function to indicate the thread is no longer executing. */
#ifdef TX_PORT_USE_BASEPRI
LDR r1, =TX_PORT_BASEPRI // Mask interrupt priorities =< TX_PORT_BASEPRI
MSR BASEPRI, r1
#else
CPSID i // Disable interrupts
#endif /* TX_PORT_USE_BASEPRI */
PUSH {r0, lr} // Save LR (and r0 just for alignment)
BL _tx_execution_thread_exit // Call the thread exit function
POP {r0, lr} // Recover LR
#ifdef TX_PORT_USE_BASEPRI
MOV r0, 0 // Disable BASEPRI masking (enable interrupts)
MSR BASEPRI, r0
#else
CPSIE i // Enable interrupts
#endif
#endif /* TX_PORT_USE_BASEPRI */
#endif /* EXECUTION PROFILE */
LDR r0, =_tx_thread_current_ptr // Build current thread pointer address
LDR r2, =_tx_thread_execute_ptr // Build execute thread pointer address
@@ -297,7 +320,12 @@ __tx_ts_new:
/* Now we are looking for a new thread to execute! */
#ifdef TX_PORT_USE_BASEPRI
LDR r1, =TX_PORT_BASEPRI // Mask interrupt priorities =< TX_PORT_BASEPRI
MSR BASEPRI, r1
#else
CPSID i // Disable interrupts
#endif
LDR r1, [r2] // Is there another thread ready to execute?
CBNZ r1, __tx_ts_restore // Yes, schedule it
@@ -306,7 +334,12 @@ __tx_ts_new:
are disabled to allow use of WFI for waiting for a thread to arrive. */
__tx_ts_wait:
#ifdef TX_PORT_USE_BASEPRI
LDR r1, =TX_PORT_BASEPRI // Mask interrupt priorities =< TX_PORT_BASEPRI
MSR BASEPRI, r1
#else
CPSID i // Disable interrupts
#endif
LDR r1, [r2] // Pickup the next thread to execute pointer
CBNZ r1, __tx_ts_ready // If non-NULL, a new thread is ready!
#ifdef TX_ENABLE_WFI
@@ -314,7 +347,12 @@ __tx_ts_wait:
WFI // Wait for interrupt
ISB // Ensure pipeline is flushed
#endif
#ifdef TX_PORT_USE_BASEPRI
MOV r4, #0 // Disable BASEPRI masking (enable interrupts)
MSR BASEPRI, r4
#else
CPSIE i // Enable interrupts
#endif
B __tx_ts_wait // Loop to continue waiting
/* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are
@@ -331,7 +369,12 @@ __tx_ts_restore:
and enable interrupts. */
STR r1, [r0] // Setup the current thread pointer to the new thread
#ifdef TX_PORT_USE_BASEPRI
MOV r4, #0 // Disable BASEPRI masking (enable interrupts)
MSR BASEPRI, r4
#else
CPSIE i // Enable interrupts
#endif
/* Increment the thread run count. */
@@ -379,9 +422,17 @@ _skip_secure_restore:
STR r3, [r0] // Disable MPU
LDR r0, [r1, #0x90] // Pickup the module instance pointer
CBZ r0, skip_mpu_setup // Is this thread owned by a module? No, skip MPU setup
LDR r1, [r0, #0x64] // Pickup MPU register[0]
CBZ r1, skip_mpu_setup // Is protection required for this module? No, skip MPU setup
LDR r1, =0xE000ED9C // Build address of MPU base register
LDR r2, [r0, #0x74] // Pickup MPU address of data region
CBZ r2, skip_mpu_setup // Is protection required for this module? No, skip MPU setup
// Is the MPU already set up for this module?
MOV r1, #2 // Select MPU region 2
LDR r3, =0xE000ED98 // MPU_RNR register address
STR r1, [r3] // Set region to 2
LDR r1, =0xE000ED9C // MPU_RBAR register address
LDR r3, [r1] // Load address stored in MPU region 2
CMP r2, r3 // Is module already loaded?
BEQ _tx_enable_mpu // Yes - skip MPU reconfiguration
// Use alias registers to quickly load MPU
LDR r2, =0xE000ED98 // Get region register
@@ -394,6 +445,7 @@ _skip_secure_restore:
STR r2, [r3] // Set region to 4
LDM r0, {r2-r9} // Load second four MPU regions
STM r1, {r2-r9} // Store second four MPU regions
_tx_enable_mpu:
LDR r0, =0xE000ED94 // Build MPU control reg address
MOV r1, #5 // Build enable value with background region enabled
STR r1, [r0] // Enable MPU

29
ports_module/cortex_m33/iar/inc/tx_port.h
View File

@@ -26,7 +26,7 @@
/* PORT SPECIFIC C INFORMATION RELEASE */
/* */
/* tx_port.h Cortex-M33 */
/* 6.1.10 */
/* 6.1.11 */
/* */
/* AUTHOR */
/* */
@@ -61,13 +61,16 @@
/* added symbol to enable */
/* stack error handler, */
/* resulting in version 6.1.7 */
/* 10-15-2021 Scott Larson Modified comment(s), improved */
/* 10-15-2021 Scott Larson Modified comment(s), improved */
/* stack check error handling, */
/* resulting in version 6.1.9 */
/* 01-31-2022 Scott Larson Modified comment(s), unified */
/* this file across compilers, */
/* fixed predefined macro, */
/* resulting in version 6.1.10 */
/* 04-25-2022 Scott Larson Modified comments and added */
/* volatile to registers, */
/* resulting in version 6.1.11 */
/* */
/**************************************************************************/
@@ -196,14 +199,14 @@ UINT _tx_thread_secure_stack_free(struct TX_THREAD_STRUCT *tx_thread);
For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock
source constants would be:
#define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024)
#define TX_TRACE_TIME_SOURCE *((volatile ULONG *) 0x0a800024)
#define TX_TRACE_TIME_MASK 0x0000FFFFUL
*/
#ifndef TX_MISRA_ENABLE
#ifndef TX_TRACE_TIME_SOURCE
#define TX_TRACE_TIME_SOURCE *((ULONG *) 0xE0001004)
#define TX_TRACE_TIME_SOURCE *((volatile ULONG *) 0xE0001004)
#endif
#else
ULONG _tx_misra_time_stamp_get(VOID);
@@ -429,9 +432,9 @@ __attribute__( ( always_inline ) ) static inline void _tx_control_set(ULONG cont
#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) { \
ULONG _tx_vfp_state; \
_tx_vfp_state = _tx_control_get(); \
_tx_vfp_state = _tx_control_get(); \
_tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \
_tx_control_set(_tx_vfp_state); \
_tx_control_set(_tx_vfp_state); \
}
#else
@@ -456,26 +459,26 @@ __attribute__( ( always_inline ) ) static inline void _tx_control_set(ULONG cont
if ((_tx_system_state == ((ULONG) 0)) && ((thread_ptr) == _tx_thread_current_ptr)) \
{ \
ULONG _tx_vfp_state; \
_tx_vfp_state = _tx_control_get(); \
_tx_vfp_state = _tx_control_get(); \
_tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \
_tx_control_set(_tx_vfp_state); \
_tx_control_set(_tx_vfp_state); \
} \
else \
{ \
ULONG _tx_fpccr; \
_tx_fpccr = *((ULONG *) 0xE000EF34); \
_tx_fpccr = *((volatile ULONG *) 0xE000EF34); \
_tx_fpccr = _tx_fpccr & ((ULONG) 0x01); \
if (_tx_fpccr == ((ULONG) 0x01)) \
{ \
ULONG _tx_vfp_state; \
_tx_vfp_state = _tx_control_get(); \
_tx_vfp_state = _tx_control_get(); \
_tx_vfp_state = _tx_vfp_state & ((ULONG) 0x4); \
TX_VFP_TOUCH(); \
if (_tx_vfp_state == ((ULONG) 0)) \
{ \
_tx_vfp_state = _tx_control_get(); \
_tx_vfp_state = _tx_control_get(); \
_tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \
_tx_control_set(_tx_vfp_state); \
_tx_control_set(_tx_vfp_state); \
} \
} \
} \
@@ -657,7 +660,7 @@ __attribute__( ( always_inline ) ) static inline void _tx_thread_system_return_i
UINT interrupt_save;
/* Set PendSV to invoke ThreadX scheduler. */
*((ULONG *) 0xE000ED04) = ((ULONG) 0x10000000);
*((volatile ULONG *) 0xE000ED04) = ((ULONG) 0x10000000);
if (_tx_ipsr_get() == 0)
{
interrupt_save = __get_interrupt_posture();

68
ports_module/cortex_m33/iar/module_manager/src/tx_thread_schedule.s
View File

@@ -42,7 +42,7 @@
/* FUNCTION RELEASE */
/* */
/* _tx_thread_schedule Cortex-M33/IAR */
/* 6.1.8 */
/* 6.1.11 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -81,6 +81,9 @@
/* 06-02-2021 Scott Larson Fixed extended stack handling */
/* when calling kernel APIs, */
/* resulting in version 6.1.7 */
/* 04-25-2022 Scott Larson Optimized MPU configuration, */
/* added BASEPRI support, */
/* resulting in version 6.1.11 */
/* */
/**************************************************************************/
// VOID _tx_thread_schedule(VOID)
@@ -132,7 +135,12 @@ __tx_wait_here:
MemManage_Handler:
BusFault_Handler:
#ifdef TX_PORT_USE_BASEPRI
LDR r1, =TX_PORT_BASEPRI // Mask interrupt priorities =< TX_PORT_BASEPRI
MSR BASEPRI, r1
#else
CPSID i // Disable interrupts
#endif /* TX_PORT_USE_BASEPRI */
/* Now pickup and store all the fault related information. */
@@ -199,7 +207,7 @@ BusFault_Handler:
BL _txm_module_manager_memory_fault_handler // Call memory manager fault handler
#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE))
/* Call the thread exit function to indicate the thread is no longer executing. */
CPSID i // Disable interrupts
BL _tx_execution_thread_exit // Call the thread exit function
@@ -215,7 +223,12 @@ BusFault_Handler:
LDR r1, =0x10000000 // Set PENDSVSET bit
STR r1, [r0] // Store ICSR
DSB // Wait for memory access to complete
#ifdef TX_PORT_USE_BASEPRI
MOV r0, 0 // Disable BASEPRI masking (enable interrupts)
MSR BASEPRI, r0
#else
CPSIE i // Enable interrupts
#endif
#ifdef TX_SINGLE_MODE_SECURE
LDR lr, =0xFFFFFFFD // Exception return to secure
#else
@@ -232,12 +245,22 @@ __tx_ts_handler:
#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE))
/* Call the thread exit function to indicate the thread is no longer executing. */
#ifdef TX_PORT_USE_BASEPRI
LDR r1, =TX_PORT_BASEPRI // Mask interrupt priorities =< TX_PORT_BASEPRI
MSR BASEPRI, r1
#else
CPSID i // Disable interrupts
#endif /* TX_PORT_USE_BASEPRI */
PUSH {r0, lr} // Save LR (and r0 just for alignment)
BL _tx_execution_thread_exit // Call the thread exit function
POP {r0, lr} // Recover LR
#ifdef TX_PORT_USE_BASEPRI
MOV r0, 0 // Disable BASEPRI masking (enable interrupts)
MSR BASEPRI, r0
#else
CPSIE i // Enable interrupts
#endif
#endif /* TX_PORT_USE_BASEPRI */
#endif /* EXECUTION PROFILE */
LDR r0, =_tx_thread_current_ptr // Build current thread pointer address
LDR r2, =_tx_thread_execute_ptr // Build execute thread pointer address
@@ -293,7 +316,12 @@ __tx_ts_new:
/* Now we are looking for a new thread to execute! */
#ifdef TX_PORT_USE_BASEPRI
LDR r1, =TX_PORT_BASEPRI // Mask interrupt priorities =< TX_PORT_BASEPRI
MSR BASEPRI, r1
#else
CPSID i // Disable interrupts
#endif
LDR r1, [r2] // Is there another thread ready to execute?
CBNZ r1, __tx_ts_restore // Yes, schedule it
@@ -302,7 +330,12 @@ __tx_ts_new:
are disabled to allow use of WFI for waiting for a thread to arrive. */
__tx_ts_wait:
#ifdef TX_PORT_USE_BASEPRI
LDR r1, =TX_PORT_BASEPRI // Mask interrupt priorities =< TX_PORT_BASEPRI
MSR BASEPRI, r1
#else
CPSID i // Disable interrupts
#endif
LDR r1, [r2] // Pickup the next thread to execute pointer
CBNZ r1, __tx_ts_ready // If non-NULL, a new thread is ready!
#ifdef TX_ENABLE_WFI
@@ -310,7 +343,12 @@ __tx_ts_wait:
WFI // Wait for interrupt
ISB // Ensure pipeline is flushed
#endif
#ifdef TX_PORT_USE_BASEPRI
MOV r4, #0 // Disable BASEPRI masking (enable interrupts)
MSR BASEPRI, r4
#else
CPSIE i // Enable interrupts
#endif
B __tx_ts_wait // Loop to continue waiting
/* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are
@@ -327,7 +365,12 @@ __tx_ts_restore:
and enable interrupts. */
STR r1, [r0] // Setup the current thread pointer to the new thread
#ifdef TX_PORT_USE_BASEPRI
MOV r4, #0 // Disable BASEPRI masking (enable interrupts)
MSR BASEPRI, r4
#else
CPSIE i // Enable interrupts
#endif
/* Increment the thread run count. */
@@ -375,9 +418,17 @@ _skip_secure_restore:
STR r3, [r0] // Disable MPU
LDR r0, [r1, #0x90] // Pickup the module instance pointer
CBZ r0, skip_mpu_setup // Is this thread owned by a module? No, skip MPU setup
LDR r1, [r0, #0x64] // Pickup MPU register[0]
CBZ r1, skip_mpu_setup // Is protection required for this module? No, skip MPU setup
LDR r1, =0xE000ED9C // Build address of MPU base register
LDR r2, [r0, #0x74] // Pickup MPU address of data region
CBZ r2, skip_mpu_setup // Is protection required for this module? No, skip MPU setup
// Is the MPU already set up for this module?
MOV r1, #2 // Select MPU region 2
LDR r3, =0xE000ED98 // MPU_RNR register address
STR r1, [r3] // Set region to 2
LDR r1, =0xE000ED9C // MPU_RBAR register address
LDR r3, [r1] // Load address stored in MPU region 2
CMP r2, r3 // Is module already loaded?
BEQ _tx_enable_mpu // Yes - skip MPU reconfiguration
// Use alias registers to quickly load MPU
LDR r2, =0xE000ED98 // Get region register
@@ -390,6 +441,7 @@ _skip_secure_restore:
STR r2, [r3] // Set region to 4
LDM r0, {r2-r9} // Load second four MPU regions
STM r1, {r2-r9} // Store second four MPU regions
_tx_enable_mpu:
LDR r0, =0xE000ED94 // Build MPU control reg address
MOV r1, #5 // Build enable value with background region enabled
STR r1, [r0] // Enable MPU
@@ -412,8 +464,8 @@ _skip_vfp_restore:
SVC_Handler:
TST lr, #0x04 // Determine return stack from EXC_RETURN bit 2
ITE EQ
MRSEQ r0, MSP // Get MSP
MRSNE r0, PSP // Get PSP
MRSEQ r0, MSP // Get MSP if return stack is MSP
MRSNE r0, PSP // Get PSP if return stack is PSP
LDR r1, [r0,#24] // Load saved PC from stack
LDRB r2, [r1,#-2] // Load SVC number