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Release 6.1.8

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This commit is contained in:
Yuxin Zhou
2021-07-28 07:24:02 +00:00
parent 244365fc6a
commit d0dab58250
651 changed files with 11636 additions and 10696 deletions
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12
ports_module/cortex_m23/ac6/example_build/ThreadX_Library.uvoptx
View File

@@ -2947,6 +2947,18 @@
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>1</GroupNumber>
<FileNumber>232</FileNumber>
<FileType>2</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\module_manager\src\tx_thread_secure_stack_initialize.S</PathWithFileName>
<FilenameWithoutPath>tx_thread_secure_stack_initialize.S</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
</Group>
<Group>

5
ports_module/cortex_m23/ac6/example_build/ThreadX_Library.uvprojx
View File

@@ -1538,6 +1538,11 @@
<FileType>1</FileType>
<FilePath>..\module_manager\src\txm_module_manager_port_dispatch.c</FilePath>
</File>
<File>
<FileName>tx_thread_secure_stack_initialize.S</FileName>
<FileType>2</FileType>
<FilePath>..\module_manager\src\tx_thread_secure_stack_initialize.S</FilePath>
</File>
</Files>
</Group>
<Group>

4
ports_module/cortex_m23/ac6/example_build/sample_threadx_module/sample_threadx_module.c
View File

@@ -300,8 +300,8 @@ UINT status;
while(1)
{
/* Test external memory sharing. */
*(ULONG *)EXTERNAL_MEMORY = 0xABABABAB;
*(ULONG *)0x20040004 = 0x01010101;
// *(ULONG *)EXTERNAL_MEMORY = 0xABABABAB;
// *(ULONG *)0x20040004 = 0x01010101;
/* Increment the thread counter. */
thread_2_counter++;

4
ports_module/cortex_m23/ac6/example_build/tx_initialize_low_level.S
View File

@@ -29,7 +29,6 @@ SYSTICK_CYCLES = ((SYSTEM_CLOCK / 100) -1)
STACK_SIZE = 0x00000400
HEAP_SIZE = 0x00000000
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
@@ -96,8 +95,7 @@ _tx_initialize_low_level:
LDR r1, =__Vectors // Pickup address of vector table
STR r1, [r0] // Set vector table address
// /* Enable the cycle count register. */
//
/* Enable the cycle count register. */
// LDR r0, =0xE0001000 // Build address of DWT register
// LDR r1, [r0] // Pickup the current value
// ORR r1, r1, #1 // Set the CYCCNTENA bit

1
ports_module/cortex_m23/ac6/inc/tx_port.h
View File

@@ -68,7 +68,6 @@
#include <stdlib.h>
#include <string.h>
#include <arm_compat.h>
#include "ARMCM23_TZ.h" /* For intrinsic functions. */
/* Define ThreadX basic types for this port. */

2
ports_module/cortex_m23/ac6/inc/tx_secure_interface.h
View File

@@ -42,7 +42,7 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* */
/**************************************************************************/

17
ports_module/cortex_m23/ac6/module_manager/src/tx_thread_context_restore.S
View File

@@ -20,7 +20,9 @@
/**************************************************************************/
/**************************************************************************/
#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE))
.global _tx_execution_isr_exit
#endif
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
@@ -45,11 +47,11 @@
/* */
/* CALLS */
/* */
/* None */
/* [_tx_execution_isr_exit] Execution profiling ISR exit */
/* */
/* CALLED BY */
/* */
/* None */
/* ISRs Interrupt Service Routines */
/* */
/* RELEASE HISTORY */
/* */
@@ -68,7 +70,14 @@
.thumb_func
.type _tx_thread_context_restore, function
_tx_thread_context_restore:
/* Return to interrupt processing. */
#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE))
/* Call the ISR exit function to indicate an ISR is complete. */
PUSH {r0, lr} // Save return address
BL _tx_execution_isr_exit // Call the ISR exit function
POP {r0, lr} // Recover return address
#endif
BX lr
// }
.end

17
ports_module/cortex_m23/ac6/module_manager/src/tx_thread_context_save.S
View File

@@ -20,7 +20,9 @@
/**************************************************************************/
/**************************************************************************/
#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE))
.global _tx_execution_isr_enter
#endif
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
@@ -45,11 +47,11 @@
/* */
/* CALLS */
/* */
/* None */
/* [_tx_execution_isr_enter] Execution profiling ISR enter */
/* */
/* CALLED BY */
/* */
/* None */
/* ISRs */
/* */
/* RELEASE HISTORY */
/* */
@@ -68,7 +70,14 @@
.thumb_func
.type _tx_thread_context_save, function
_tx_thread_context_save:
/* Return to interrupt processing. */
#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE))
/* Call the ISR enter function to indicate an ISR is starting. */
PUSH {r0, lr} // Save return address
BL _tx_execution_isr_enter // Call the ISR enter function
POP {r0, lr} // Recover return address
#endif
BX lr
// }
.end

10
ports_module/cortex_m23/ac6/module_manager/src/tx_thread_interrupt_control.S
View File

@@ -68,11 +68,9 @@
.thumb_func
.type _tx_thread_interrupt_control, function
_tx_thread_interrupt_control:
/* Pickup current interrupt lockout posture. */
MRS r1, PRIMASK
MSR PRIMASK, r0
MOV r0, r1
BX lr
MRS r1, PRIMASK // Pickup current interrupt lockout
MSR PRIMASK, r0 // Apply the new interrupt lockout
MOV r0, r1 // Transfer old to return register
BX lr // Return to caller
// }
.end

6
ports_module/cortex_m23/ac6/module_manager/src/tx_thread_interrupt_disable.S
View File

@@ -38,11 +38,11 @@
/* */
/* INPUT */
/* */
/* old_posture Old interrupt lockout posture */
/* None */
/* */
/* OUTPUT */
/* */
/* None */
/* old_posture Old interrupt lockout posture */
/* */
/* CALLS */
/* */
@@ -59,7 +59,7 @@
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* */
/**************************************************************************/
// UINT _tx_thread_interrupt_disable(UINT new_posture)
// UINT _tx_thread_interrupt_disable(VOID)
// {
.section .text
.balign 4

6
ports_module/cortex_m23/ac6/module_manager/src/tx_thread_interrupt_restore.S
View File

@@ -38,11 +38,11 @@
/* */
/* INPUT */
/* */
/* None */
/* previous_posture Previous interrupt posture */
/* */
/* OUTPUT */
/* */
/* previous_posture Previous interrupt posture */
/* None */
/* */
/* CALLS */
/* */
@@ -59,7 +59,7 @@
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* */
/**************************************************************************/
// VOID _tx_thread_interrupt_restore(UINT new_posture)
// VOID _tx_thread_interrupt_restore(UINT previous_posture)
// {
.section .text
.balign 4

61
ports_module/cortex_m23/ac6/module_manager/src/tx_thread_schedule.S
View File

@@ -21,6 +21,10 @@
/**************************************************************************/
#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE))
.global _tx_execution_thread_enter
.global _tx_execution_thread_exit
#endif
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
@@ -71,29 +75,24 @@
.thumb_func
.type _tx_thread_schedule, function
_tx_thread_schedule:
/* This function should only ever be called on Cortex-M
from the first schedule request. Subsequent scheduling occurs
from the PendSV handling routine below. */
/* Clear the preempt-disable flag to enable rescheduling after initialization on Cortex-M targets. */
MOVW r0, #0 // Build value for TX_FALSE
LDR r2, =_tx_thread_preempt_disable // Build address of preempt disable flag
STR r0, [r2, #0] // Clear preempt disable flag
/* Enable memory fault registers. */
LDR r0, =0xE000ED24 // Build SHCSR address
LDR r1, =0x70000 // Enable Usage, Bus, and MemManage faults
STR r1, [r0] //
/* Enable interrupts */
CPSIE i
/* Enter the scheduler for the first time. */
LDR r0, =0x10000000 // Load PENDSVSET bit
LDR r1, =0xE000ED04 // Load ICSR address
STR r0, [r1] // Set PENDSVBIT in ICSR
@@ -221,19 +220,18 @@ BusFault_Handler:
PendSV_Handler:
__tx_ts_handler:
#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE))
/* Call the thread exit function to indicate the thread is no longer executing. */
CPSID i // Disable interrupts
PUSH {r0, lr} // Save LR (and r0 just for alignment)
BL _tx_execution_thread_exit // Call the thread exit function
POP {r0, r1} // Recover LR
MOV lr, r1
MOV lr, r1 //
CPSIE i // Enable interrupts
#endif
LDR r0, =_tx_thread_current_ptr // Build current thread pointer address
LDR r2, =_tx_thread_execute_ptr // Build execute thread pointer address
MOVW r3, #0 // Build NULL value
LDR r1, [r0] // Pickup current thread pointer
@@ -246,18 +244,18 @@ __tx_ts_handler:
STR r3, [r0] // Set _tx_thread_current_ptr to NULL
MRS r3, PSP // Pickup PSP pointer (thread's stack pointer)
SUBS r3, r3, #16 // Allocate stack space
STM r3!, {r4-r7} // Save its remaining registers (M3 Instruction: STMDB r12!, {r4-r11})
MOV r4, r8 //
MOV r5, r9 //
MOV r6, r10 //
MOV r7, r11 //
STM r3!, {r4-r7} // Save r4-r7 (M4 Instruction: STMDB r12!, {r4-r11})
MOV r4, r8 // Copy r8-r11 to multisave registers
MOV r5, r9
MOV r6, r10
MOV r7, r11
SUBS r3, r3, #32 // Allocate stack space
STM r3!, {r4-r7} //
STM r3!, {r4-r7} // Save r8-r11
SUBS r3, r3, #20 // Allocate stack space
MOV r5, lr //
STR r5, [r3] // Save LR on the stack
MOV r5, lr // Copy lr to saveable register
STR r5, [r3] // Save lr on the stack
STR r3, [r1, #8] // Save the thread stack pointer
#if (!defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE))
// Save secure context
LDR r5, =0xC4 // Secure stack index offset
@@ -339,7 +337,7 @@ __tx_ts_restore:
STR r5, [r4] // Setup global time-slice
#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE))
/* Call the thread entry function to indicate the thread is executing. */
PUSH {r0, r1} // Save r0 and r1
BL _tx_execution_thread_enter // Call the thread execution enter function
@@ -379,6 +377,8 @@ _skip_secure_restore:
CBZ r1, skip_mpu_setup // Is protection required for this module? No, skip MPU setup
// Initialize loop to configure MPU registers
// Order doesn't matter, so txm_module_instance_mpu_registers[0]
// will be in region 7 and txm_module_instance_mpu_registers[7] will be in region 0.
MOVS r3, #0x64 // Index of MPU register settings in thread control block
ADD r0, r0, r3 // Build address of MPU register start in thread control block
MOVS r5, #0 // Select region 0
@@ -416,7 +416,6 @@ skip_mpu_setup:
BX lr // Return to thread!
/* SVC Handler. */
.section .text
.balign 4
@@ -430,10 +429,10 @@ SVC_Handler:
MOVS r1, #0x04
TST r1, r0 // Determine return stack from EXC_RETURN bit 2
BEQ _tx_load_msp
MRS r0, PSP // Get PSP
MRS r0, PSP // Get PSP if return stack is PSP
B _tx_get_svc
_tx_load_msp:
MRS r0, MSP // Get MSP
MRS r0, MSP // Get MSP if return stack is MSP
_tx_get_svc:
LDR r1, [r0,#24] // Load saved PC from stack
LDR r3, =-2
@@ -554,14 +553,14 @@ _tx_exit_continue:
MRS r3, PSP // Pickup kernel stack pointer
/* Copy kernel hardware stack to module thread stack. */
LDM r3!,{r1-r2} // Get r0, r1 from kernel stack
STM r0!,{r1-r2} // Insert r0, r1 into thread stack
LDM r3!,{r1-r2} // Get r2, r3 from kernel stack
STM r0!,{r1-r2} // Insert r2, r3 into thread stack
LDM r3!,{r1-r2} // Get r12, lr from kernel stack
STM r0!,{r1-r2} // Insert r12, lr into thread stack
LDM r3!,{r1-r2} // Get pc, xpsr from kernel stack
STM r0!,{r1-r2} // Insert pc, xpsr into thread stack
LDM r3!, {r1-r2} // Get r0, r1 from kernel stack
STM r0!, {r1-r2} // Insert r0, r1 into thread stack
LDM r3!, {r1-r2} // Get r2, r3 from kernel stack
STM r0!, {r1-r2} // Insert r2, r3 into thread stack
LDM r3!, {r1-r2} // Get r12, lr from kernel stack
STM r0!, {r1-r2} // Insert r12, lr into thread stack
LDM r3!, {r1-r2} // Get pc, xpsr from kernel stack
STM r0!, {r1-r2} // Insert pc, xpsr into thread stack
SUBS r0, r0, #32 // Subtract 32 to get back to top of stack
MSR PSP, r0 // Set thread stack pointer
@@ -605,7 +604,7 @@ _tx_free_continue:
STR r0, [r1] // Store function return value
MOV lr, r2
BX lr
#endif // End of ifndef TX_SINGLE_MODE_SECURE, TX_SINGLE_MODE_NON_SECURE
#endif // End of ifndef TX_SINGLE_MODE_SECURE, TX_SINGLE_MODE_NON_SECURE

48
ports_module/cortex_m23/ac6/module_manager/src/tx_thread_secure_stack.c
View File

@@ -29,7 +29,7 @@
#define TX_SOURCE_CODE
#include "ARMCM23_TZ.h" /* For intrinsic functions. */
#include "cmsis_compiler.h" /* For intrinsic functions. */
#include "tx_secure_interface.h" /* Interface for NS code. */
/* Minimum size of secure stack. */
@@ -62,8 +62,8 @@ typedef struct TX_THREAD_SECURE_STACK_INFO_STRUCT
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_secure_stack_initialize Cortex-M23/AC6 */
/* 6.1.1 */
/* _tx_thread_secure_mode_stack_initialize Cortex-M23/AC6 */
/* 6.1.8 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -78,7 +78,7 @@ typedef struct TX_THREAD_SECURE_STACK_INFO_STRUCT
/* */
/* OUTPUT */
/* */
/* None */
/* status */
/* */
/* CALLS */
/* */
@@ -98,21 +98,35 @@ typedef struct TX_THREAD_SECURE_STACK_INFO_STRUCT
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* 10-16-2020 Scott Larson Modified comment(s), */
/* resulting in version 6.1.1 */
/* 08-02-2021 Scott Larson Modified comment(s), and */
/* changed name, execute in */
/* handler mode, */
/* resulting in version 6.1.8 */
/* */
/**************************************************************************/
__attribute__((cmse_nonsecure_entry))
void _tx_thread_secure_stack_initialize(void)
UINT _tx_thread_secure_mode_stack_initialize(void)
{
/* Set secure mode to use PSP. */
__set_CONTROL(__get_CONTROL() | 2);
/* Set process stack pointer and stack limit to 0 to throw exception when a thread
without a secure stack calls a secure function that tries to use secure stack. */
__set_PSPLIM(0);
__set_PSP(0);
return;
UINT status;
/* Make sure function is called from interrupt (threads should not call). */
if (__get_IPSR() == 0)
{
status = TX_CALLER_ERROR;
}
else
{
/* Set secure mode to use PSP. */
__set_CONTROL(__get_CONTROL() | 2);
/* Set process stack pointer and stack limit to 0 to throw exception when a thread
without a secure stack calls a secure function that tries to use secure stack. */
__set_PSPLIM(0);
__set_PSP(0);
status = TX_SUCCESS;
}
return status;
}
@@ -294,7 +308,7 @@ UINT _tx_thread_secure_mode_stack_free(TX_THREAD *thread_ptr)
{
UINT status;
TX_THREAD_SECURE_STACK_INFO *info_ptr;
status = TX_SUCCESS;
/* Pickup stack info from thread. */
@@ -379,7 +393,7 @@ void _tx_thread_secure_stack_context_save(TX_THREAD *thread_ptr)
{
TX_THREAD_SECURE_STACK_INFO *info_ptr;
ULONG sp;
/* This function should be called from scheduler only. */
if (__get_IPSR() == 0)
{

5
ports_module/cortex_m23/ac6/module_manager/src/tx_thread_secure_stack_allocate.S
View File

@@ -57,7 +57,7 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* */
/**************************************************************************/
// UINT _tx_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size)
@@ -66,7 +66,7 @@
.balign 4
.syntax unified
.eabi_attribute Tag_ABI_align_preserved, 1
.global _tx_thread_secure_stack_allocate
.global _tx_thread_secure_stack_allocate
.global _tx_alloc_return
.thumb_func
.type _tx_thread_secure_stack_allocate, function
@@ -80,7 +80,6 @@ _tx_alloc_return:
BEQ _alloc_return_interrupt_enabled
CPSID i // Otherwise, disable interrupts
#else
// Executing in single mode - this function is not needed.
MOVS r0, #0xFF // Feature not enabled
#endif
_alloc_return_interrupt_enabled:

5
ports_module/cortex_m23/ac6/module_manager/src/tx_thread_secure_stack_free.S
View File

@@ -55,7 +55,7 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* */
/**************************************************************************/
// UINT _tx_thread_secure_stack_free(TX_THREAD *thread_ptr)
@@ -64,7 +64,7 @@
.balign 4
.syntax unified
.eabi_attribute Tag_ABI_align_preserved, 1
.global _tx_thread_secure_stack_free
.global _tx_thread_secure_stack_free
.global _tx_free_return
.thumb_func
.type _tx_thread_secure_stack_free, function
@@ -78,7 +78,6 @@ _tx_free_return:
BEQ _free_return_interrupt_enabled
CPSID i // Otherwise, disable interrupts
#else
// Executing in single mode - this function is not needed.
MOVS r0, #0xFF // Feature not enabled
#endif
_free_return_interrupt_enabled:

79
ports_module/cortex_m23/ac6/module_manager/src/tx_thread_secure_stack_initialize.S Normal file
View File

@@ -0,0 +1,79 @@
/**************************************************************************/
/* */
/* Copyright (c) Microsoft Corporation. All rights reserved. */
/* */
/* This software is licensed under the Microsoft Software License */
/* Terms for Microsoft Azure RTOS. Full text of the license can be */
/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
/* and in the root directory of this software. */
/* */
/**************************************************************************/
/**************************************************************************/
/**************************************************************************/
/** */
/** ThreadX Component */
/** */
/** Thread */
/** */
/**************************************************************************/
/**************************************************************************/
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_secure_stack_initialize Cortex-M23/AC6 */
/* 6.1.8 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
/* */
/* DESCRIPTION */
/* */
/* This function enters the SVC handler to initialize a secure stack. */
/* */
/* INPUT */
/* */
/* none */
/* */
/* OUTPUT */
/* */
/* none */
/* */
/* CALLS */
/* */
/* SVC 3 */
/* */
/* CALLED BY */
/* */
/* TX_INITIALIZE_KERNEL_ENTER_EXTENSION */
/* */
/* RELEASE HISTORY */
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 08-02-2021 Scott Larson Initial Version 6.1.8 */
/* */
/**************************************************************************/
// VOID _tx_thread_secure_stack_initialize(VOID)
// {
.section .text
.balign 4
.syntax unified
.eabi_attribute Tag_ABI_align_preserved, 1
.global _tx_thread_secure_stack_initialize
.thumb_func
.type _tx_thread_secure_stack_initialize, function
_tx_thread_secure_stack_initialize:
#if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE)
CPSIE i // Enable interrupts for SVC call
SVC 3
CPSID i // Disable interrupts
#else
MOV r0, #0xFF // Feature not enabled
#endif
BX lr
.end

2
ports_module/cortex_m23/ac6/module_manager/src/tx_thread_stack_build.S
View File

@@ -58,7 +58,7 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* */
/**************************************************************************/
// VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID))

2
ports_module/cortex_m23/ac6/module_manager/src/tx_thread_stack_error_handler.c
View File

@@ -70,7 +70,7 @@ VOID (*_tx_thread_application_stack_error_handler)(TX_THREAD *thread_ptr);
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* */
/**************************************************************************/
VOID _tx_thread_stack_error_handler(TX_THREAD *thread_ptr)

2
ports_module/cortex_m23/ac6/module_manager/src/tx_thread_stack_error_notify.c
View File

@@ -68,7 +68,7 @@ extern VOID (*_tx_thread_application_stack_error_handler)(TX_THREAD *thread_ptr)
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* */
/**************************************************************************/
UINT _tx_thread_stack_error_notify(VOID (*stack_error_handler)(TX_THREAD *thread_ptr))

2
ports_module/cortex_m23/ac6/module_manager/src/tx_thread_system_return.S
View File

@@ -71,7 +71,7 @@
.thumb_func
.type _tx_thread_system_return, function
_tx_thread_system_return:
/* Return to real scheduler via PendSV. Note that this routine is often
/* Return to real scheduler via PendSV. Note that this routine is often
replaced with in-line assembly in tx_port.h to improved performance. */
LDR r0, =0x10000000 // Load PENDSVSET bit

97
ports_module/cortex_m23/ac6/module_manager/src/tx_timer_interrupt.S
View File

@@ -36,8 +36,7 @@
/* This function processes the hardware timer interrupt. This */
/* processing includes incrementing the system clock and checking for */
/* time slice and/or timer expiration. If either is found, the */
/* interrupt context save/restore functions are called along with the */
/* expiration functions. */
/* expiration functions are called. */
/* */
/* INPUT */
/* */
@@ -63,8 +62,8 @@
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* */
/**************************************************************************/
/* VOID _tx_timer_interrupt(VOID)
{ */
// VOID _tx_timer_interrupt(VOID)
// {
.section .text
.balign 4
.syntax unified
@@ -80,8 +79,7 @@ _tx_timer_interrupt:
/* Increment the system clock. */
// _tx_timer_system_clock++;
MOVW r1, #:lower16:_tx_timer_system_clock // Pickup address of system clock
MOVT r1, #:upper16:_tx_timer_system_clock
LDR r1, =_tx_timer_system_clock // Pickup address of system clock
LDR r0, [r1, #0] // Pickup system clock
ADDS r0, r0, #1 // Increment system clock
STR r0, [r1, #0] // Store new system clock
@@ -90,28 +88,27 @@ _tx_timer_interrupt:
// if (_tx_timer_time_slice)
// {
MOVW r3, #:lower16:_tx_timer_time_slice // Pickup address of time-slice
MOVT r3, #:upper16:_tx_timer_time_slice
LDR r3, =_tx_timer_time_slice // Pickup address of time-slice
LDR r2, [r3, #0] // Pickup time-slice
CBZ r2, __tx_timer_no_time_slice // Is it non-active?
CBZ r2, __tx_timer_no_time_slice // Is it non-active?
// Yes, skip time-slice processing
/* Decrement the time_slice. */
// _tx_timer_time_slice--;
/* Decrement the time_slice. */
// _tx_timer_time_slice--;
SUBS r2, r2, #1 // Decrement the time-slice
STR r2, [r3, #0] // Store new time-slice value
/* Check for expiration. */
// if (__tx_timer_time_slice == 0)
/* Check for expiration. */
// if (__tx_timer_time_slice == 0)
CBNZ r2, __tx_timer_no_time_slice // Has it expired?
// No, skip expiration processing
/* Set the time-slice expired flag. */
// _tx_timer_expired_time_slice = TX_TRUE;
/* Set the time-slice expired flag. */
// _tx_timer_expired_time_slice = TX_TRUE;
MOVW r3, #:lower16:_tx_timer_expired_time_slice // Pickup address of expired flag
MOVT r3, #:upper16:_tx_timer_expired_time_slice
LDR r3, =_tx_timer_expired_time_slice // Pickup address of expired flag
MOVW r0, #1 // Build expired value
STR r0, [r3, #0] // Set time-slice expiration flag
@@ -123,18 +120,16 @@ __tx_timer_no_time_slice:
// if (*_tx_timer_current_ptr)
// {
MOVW r1, #:lower16:_tx_timer_current_ptr // Pickup current timer pointer address
MOVT r1, #:upper16:_tx_timer_current_ptr
LDR r1, =_tx_timer_current_ptr // Pickup current timer pointer address
LDR r0, [r1, #0] // Pickup current timer
LDR r2, [r0, #0] // Pickup timer list entry
CBZ r2, __tx_timer_no_timer // Is there anything in the list?
// No, just increment the timer
/* Set expiration flag. */
// _tx_timer_expired = TX_TRUE;
/* Set expiration flag. */
// _tx_timer_expired = TX_TRUE;
MOVW r3, #:lower16:_tx_timer_expired // Pickup expiration flag address
MOVT r3, #:upper16:_tx_timer_expired
LDR r3, =_tx_timer_expired // Pickup expiration flag address
MOVW r2, #1 // Build expired value
STR r2, [r3, #0] // Set expired flag
B __tx_timer_done // Finished timer processing
@@ -144,25 +139,23 @@ __tx_timer_no_time_slice:
// {
__tx_timer_no_timer:
/* No timer expired, increment the timer pointer. */
// _tx_timer_current_ptr++;
/* No timer expired, increment the timer pointer. */
// _tx_timer_current_ptr++;
ADDS r0, r0, #4 // Move to next timer
/* Check for wrap-around. */
// if (_tx_timer_current_ptr == _tx_timer_list_end)
/* Check for wrap-around. */
// if (_tx_timer_current_ptr == _tx_timer_list_end)
MOVW r3, #:lower16:_tx_timer_list_end // Pickup addr of timer list end
MOVT r3, #:upper16:_tx_timer_list_end
LDR r3, =_tx_timer_list_end // Pickup addr of timer list end
LDR r2, [r3, #0] // Pickup list end
CMP r0, r2 // Are we at list end?
BNE __tx_timer_skip_wrap // No, skip wrap-around logic
/* Wrap to beginning of list. */
// _tx_timer_current_ptr = _tx_timer_list_start;
/* Wrap to beginning of list. */
// _tx_timer_current_ptr = _tx_timer_list_start;
MOVW r3, #:lower16:_tx_timer_list_start // Pickup addr of timer list start
MOVT r3, #:upper16:_tx_timer_list_start
LDR r3, =_tx_timer_list_start // Pickup addr of timer list start
LDR r0, [r3, #0] // Set current pointer to list start
__tx_timer_skip_wrap:
@@ -172,18 +165,15 @@ __tx_timer_skip_wrap:
__tx_timer_done:
/* See if anything has expired. */
// if ((_tx_timer_expired_time_slice) || (_tx_timer_expired))
// {
MOVW r3, #:lower16:_tx_timer_expired_time_slice // Pickup addr of expired flag
MOVT r3, #:upper16:_tx_timer_expired_time_slice
LDR r3, =_tx_timer_expired_time_slice // Pickup addr of expired flag
LDR r2, [r3, #0] // Pickup time-slice expired flag
CBNZ r2, __tx_something_expired // Did a time-slice expire?
// If non-zero, time-slice expired
MOVW r1, #:lower16:_tx_timer_expired // Pickup addr of other expired flag
MOVT r1, #:upper16:_tx_timer_expired
LDR r1, =_tx_timer_expired // Pickup addr of other expired flag
LDR r0, [r1, #0] // Pickup timer expired flag
CBZ r0, __tx_timer_nothing_expired // Did a timer expire?
// No, nothing expired
@@ -197,14 +187,13 @@ __tx_something_expired:
// if (_tx_timer_expired)
// {
MOVW r1, #:lower16:_tx_timer_expired // Pickup addr of expired flag
MOVT r1, #:upper16:_tx_timer_expired
LDR r1, =_tx_timer_expired // Pickup addr of expired flag
LDR r0, [r1, #0] // Pickup timer expired flag
CBZ r0, __tx_timer_dont_activate // Check for timer expiration
// If not set, skip timer activation
/* Process timer expiration. */
// _tx_timer_expiration_process();
/* Process timer expiration. */
// _tx_timer_expiration_process();
BL _tx_timer_expiration_process // Call the timer expiration handling routine
@@ -215,28 +204,21 @@ __tx_timer_dont_activate:
// if (_tx_timer_expired_time_slice)
// {
MOVW r3, #:lower16:_tx_timer_expired_time_slice // Pickup addr of time-slice expired
MOVT r3, #:upper16:_tx_timer_expired_time_slice
LDR r3, =_tx_timer_expired_time_slice // Pickup addr of time-slice expired
LDR r2, [r3, #0] // Pickup the actual flag
CBZ r2, __tx_timer_not_ts_expiration // See if the flag is set
// No, skip time-slice processing
/* Time slice interrupted thread. */
// _tx_thread_time_slice();
/* Time slice interrupted thread. */
// _tx_thread_time_slice();
BL _tx_thread_time_slice // Call time-slice processing
MOVW r0, #:lower16:_tx_thread_preempt_disable // Build address of preempt disable flag
MOVT r0, #:upper16:_tx_thread_preempt_disable
LDR r0, =_tx_thread_preempt_disable // Build address of preempt disable flag
LDR r1, [r0] // Is the preempt disable flag set?
CBNZ r1, __tx_timer_skip_time_slice // Yes, skip the PendSV logic
MOVW r0, #:lower16:_tx_thread_current_ptr // Build current thread pointer address
MOVT r0, #:upper16:_tx_thread_current_ptr
LDR r0, =_tx_thread_current_ptr // Build current thread pointer address
LDR r1, [r0] // Pickup the current thread pointer
MOVW r2, #:lower16:_tx_thread_execute_ptr // Build execute thread pointer address
MOVT r2, #:upper16:_tx_thread_execute_ptr
LDR r2, =_tx_thread_execute_ptr // Build execute thread pointer address
LDR r3, [r2] // Pickup the execute thread pointer
LDR r0, =0xE000ED04 // Build address of control register
LDR r2, =0x10000000 // Build value for PendSV bit
@@ -248,8 +230,8 @@ __tx_timer_skip_time_slice:
__tx_timer_not_ts_expiration:
POP {r0, r1} // Recover lr register (r0 is just there for
MOV lr, r1 // the 8-byte stack alignment
POP {r0, r1} // Recover lr register (r0 is just there for
MOV lr, r1 // the 8-byte stack alignment
// }
@@ -257,6 +239,5 @@ __tx_timer_nothing_expired:
DSB // Complete all memory access
BX lr // Return to caller
// }
.end

2
ports_module/cortex_m23/ac6/module_manager/src/txe_thread_secure_stack_allocate.c
View File

@@ -68,7 +68,7 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* */
/**************************************************************************/
UINT _txe_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size)

2
ports_module/cortex_m23/ac6/module_manager/src/txe_thread_secure_stack_free.c
View File

@@ -66,7 +66,7 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* */
/**************************************************************************/
UINT _txe_thread_secure_stack_free(TX_THREAD *thread_ptr)