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Release 6.1.8

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This commit is contained in:
Yuxin Zhou
2021-07-28 07:24:02 +00:00
parent 244365fc6a
commit d0dab58250
651 changed files with 11636 additions and 10696 deletions
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12
ports_module/cortex_m33/ac6/example_build/ThreadX_Library.uvoptx
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@@ -2947,6 +2947,18 @@
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>1</GroupNumber>
<FileNumber>232</FileNumber>
<FileType>2</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\module_manager\src\tx_thread_secure_stack_initialize.S</PathWithFileName>
<FilenameWithoutPath>tx_thread_secure_stack_initialize.S</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
</Group>
<Group>

5
ports_module/cortex_m33/ac6/example_build/ThreadX_Library.uvprojx
View File

@@ -1538,6 +1538,11 @@
<FileType>1</FileType>
<FilePath>..\module_manager\src\txm_module_manager_port_dispatch.c</FilePath>
</File>
<File>
<FileName>tx_thread_secure_stack_initialize.S</FileName>
<FileType>2</FileType>
<FilePath>..\module_manager\src\tx_thread_secure_stack_initialize.S</FilePath>
</File>
</Files>
</Group>
<Group>

7
ports_module/cortex_m33/ac6/inc/tx_port.h
View File

@@ -47,11 +47,11 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */
/* macro definition, */
/* resulting in version 6.1.6 */
/* 06-02-2021 Bhupendra Naphade Modified comment(s), */
/* 06-02-2021 Bhupendra Naphade Modified comment(s), */
/* added symbol to enable */
/* stack error handler, */
/* resulting in version 6.1.7 */
@@ -75,7 +75,6 @@
#include <stdlib.h>
#include <string.h>
#include <arm_compat.h>
#include "ARMCM33_DSP_FP_TZ.h" /* For intrinsic functions. */
/* Define ThreadX basic types for this port. */

2
ports_module/cortex_m33/ac6/inc/tx_secure_interface.h
View File

@@ -42,7 +42,7 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 12-31-2020 Scott Larson Initial Version 6.1.3 */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* */
/**************************************************************************/

15
ports_module/cortex_m33/ac6/module_manager/src/tx_thread_context_restore.S
View File

@@ -20,7 +20,9 @@
/**************************************************************************/
/**************************************************************************/
#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE))
.global _tx_execution_isr_exit
#endif
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
@@ -45,7 +47,7 @@
/* */
/* CALLS */
/* */
/* _tx_thread_schedule Thread scheduling routine */
/* [_tx_execution_isr_exit] Execution profiling ISR exit */
/* */
/* CALLED BY */
/* */
@@ -68,7 +70,14 @@
.thumb_func
.type _tx_thread_context_restore, function
_tx_thread_context_restore:
/* Just return! */
#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE))
/* Call the ISR exit function to indicate an ISR is complete. */
PUSH {r0, lr} // Save return address
BL _tx_execution_isr_exit // Call the ISR exit function
POP {r0, lr} // Recover return address
#endif
BX lr
// }
.end

15
ports_module/cortex_m33/ac6/module_manager/src/tx_thread_context_save.S
View File

@@ -20,7 +20,9 @@
/**************************************************************************/
/**************************************************************************/
#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE))
.global _tx_execution_isr_enter
#endif
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
@@ -45,7 +47,7 @@
/* */
/* CALLS */
/* */
/* None */
/* [_tx_execution_isr_enter] Execution profiling ISR enter */
/* */
/* CALLED BY */
/* */
@@ -68,7 +70,14 @@
.thumb_func
.type _tx_thread_context_save, function
_tx_thread_context_save:
/* Return to interrupt processing. */
#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE))
/* Call the ISR enter function to indicate an ISR is starting. */
PUSH {r0, lr} // Save return address
BL _tx_execution_isr_enter // Call the ISR enter function
POP {r0, lr} // Recover return address
#endif
BX lr
// }
.end

16
ports_module/cortex_m33/ac6/module_manager/src/tx_thread_interrupt_control.S
View File

@@ -68,11 +68,15 @@
.thumb_func
.type _tx_thread_interrupt_control, function
_tx_thread_interrupt_control:
/* Pickup current interrupt lockout posture. */
MRS r1, PRIMASK
MSR PRIMASK, r0
MOV r0, r1
BX lr
#ifdef TX_PORT_USE_BASEPRI
MRS r1, BASEPRI // Pickup current interrupt posture
MSR BASEPRI, r0 // Apply the new interrupt posture
MOV r0, r1 // Transfer old to return register
#else
MRS r1, PRIMASK // Pickup current interrupt lockout
MSR PRIMASK, r0 // Apply the new interrupt lockout
MOV r0, r1 // Transfer old to return register
#endif
BX lr // Return to caller
// }
.end

12
ports_module/cortex_m33/ac6/module_manager/src/tx_thread_interrupt_disable.S
View File

@@ -38,11 +38,11 @@
/* */
/* INPUT */
/* */
/* old_posture Old interrupt lockout posture */
/* None */
/* */
/* OUTPUT */
/* */
/* None */
/* old_posture Old interrupt lockout posture */
/* */
/* CALLS */
/* */
@@ -59,7 +59,7 @@
/* 12-31-2020 Scott Larson Initial Version 6.1.3 */
/* */
/**************************************************************************/
// UINT _tx_thread_interrupt_disable(UINT new_posture)
// UINT _tx_thread_interrupt_disable(VOID)
// {
.section .text
.balign 4
@@ -70,8 +70,14 @@
.type _tx_thread_interrupt_disable, function
_tx_thread_interrupt_disable:
/* Return current interrupt lockout posture. */
#ifdef TX_PORT_USE_BASEPRI
MRS r0, BASEPRI
LDR r1, =TX_PORT_BASEPRI
MSR BASEPRI, r1
#else
MRS r0, PRIMASK
CPSID i
#endif
BX lr
// }
.end

10
ports_module/cortex_m33/ac6/module_manager/src/tx_thread_interrupt_restore.S
View File

@@ -38,11 +38,11 @@
/* */
/* INPUT */
/* */
/* None */
/* previous_posture Previous interrupt posture */
/* */
/* OUTPUT */
/* */
/* previous_posture Previous interrupt posture */
/* None */
/* */
/* CALLS */
/* */
@@ -59,7 +59,7 @@
/* 12-31-2020 Scott Larson Initial Version 6.1.3 */
/* */
/**************************************************************************/
// VOID _tx_thread_interrupt_restore(UINT new_posture)
// VOID _tx_thread_interrupt_restore(UINT previous_posture)
// {
.section .text
.balign 4
@@ -70,7 +70,11 @@
.type _tx_thread_interrupt_restore, function
_tx_thread_interrupt_restore:
/* Restore previous interrupt lockout posture. */
#ifdef TX_PORT_USE_BASEPRI
MSR BASEPRI, r0
#else
MSR PRIMASK, r0
#endif
BX lr
// }
.end

65
ports_module/cortex_m33/ac6/module_manager/src/tx_thread_schedule.S
View File

@@ -21,6 +21,10 @@
/**************************************************************************/
#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE))
.global _tx_execution_thread_enter
.global _tx_execution_thread_exit
#endif
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
@@ -77,37 +81,31 @@
.thumb_func
.type _tx_thread_schedule, function
_tx_thread_schedule:
/* This function should only ever be called on Cortex-M
from the first schedule request. Subsequent scheduling occurs
from the PendSV handling routine below. */
/* Clear the preempt-disable flag to enable rescheduling after initialization on Cortex-M targets. */
MOV r0, #0 // Build value for TX_FALSE
LDR r2, =_tx_thread_preempt_disable // Build address of preempt disable flag
STR r0, [r2, #0] // Clear preempt disable flag
/* Clear CONTROL.FPCA bit so VFP registers aren't unnecessarily stacked. */
#ifdef __ARM_FP
/* Clear CONTROL.FPCA bit so VFP registers aren't unnecessarily stacked. */
MRS r0, CONTROL // Pickup current CONTROL register
BIC r0, r0, #4 // Clear the FPCA bit
MSR CONTROL, r0 // Setup new CONTROL register
#endif
/* Enable memory fault registers. */
LDR r0, =0xE000ED24 // Build SHCSR address
LDR r1, =0x70000 // Enable Usage, Bus, and MemManage faults
STR r1, [r0] //
/* Enable interrupts */
CPSIE i
/* Enter the scheduler for the first time. */
MOV r0, #0x10000000 // Load PENDSVSET bit
MOV r1, #0xE000E000 // Load NVIC base
STR r0, [r1, #0xD04] // Set PENDSVBIT in ICSR
@@ -235,7 +233,7 @@ BusFault_Handler:
PendSV_Handler:
__tx_ts_handler:
#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE))
/* Call the thread exit function to indicate the thread is no longer executing. */
CPSID i // Disable interrupts
PUSH {r0, lr} // Save LR (and r0 just for alignment)
@@ -346,7 +344,7 @@ __tx_ts_restore:
STR r5, [r4] // Setup global time-slice
#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE))
/* Call the thread entry function to indicate the thread is executing. */
PUSH {r0, r1} // Save r0 and r1
BL _tx_execution_thread_enter // Call the thread execution enter function
@@ -409,8 +407,6 @@ _skip_vfp_restore:
LDMIA r12!, {r4-r11} // Recover thread's registers
MSR PSP, r12 // Setup the thread's stack pointer
/* Return to thread. */
BX lr // Return to thread!
@@ -425,8 +421,8 @@ _skip_vfp_restore:
SVC_Handler:
TST lr, #0x04 // Determine return stack from EXC_RETURN bit 2
ITE EQ
MRSEQ r0, MSP // Get MSP
MRSNE r0, PSP // Get PSP
MRSEQ r0, MSP // Get MSP if return stack is MSP
MRSNE r0, PSP // Get PSP if return stack is PSP
LDR r1, [r0,#24] // Load saved PC from stack
LDRB r2, [r1,#-2] // Load SVC number
@@ -437,7 +433,7 @@ SVC_Handler:
CMP r2, #2 // Is it a secure stack free request?
BEQ _tx_svc_secure_free // Yes, go there
#endif // End of ifndef TX_SINGLE_MODE_SECURE, TX_SINGLE_MODE_NON_SECURE
#endif // End of ifndef TX_SINGLE_MODE_SECURE, TX_SINGLE_MODE_NON_SECURE
CMP r2, #3 // Is it the entry into ThreadX?
@@ -529,6 +525,27 @@ _tx_thread_user_return:
STR r1, [r2, #16] // Set stack end
STR r3, [r2, #20] // Set stack size
#endif
/* If lazy stacking is pending, check if it can be cleared.
if(LSPACT && tx_thread_module_stack_start < FPCAR && FPCAR < tx_thread_module_stack_end)
then clear LSPACT. */
LDR r3, =0xE000EF34 // Address of FPCCR
LDR r3, [r3] // Load FPCCR
TST r3, #1 // Check if LSPACT is set
BEQ _tx_no_lazy_clear // if clear, move on
LDR r1, =0xE000EF38 // Address of FPCAR
LDR r1, [r1] // Load FPCAR
LDR r0, [r2, #0xA4] // Load kernel stack start
CMP r1, r0 // If FPCAR < start, move on
BLO _tx_no_lazy_clear
LDR r0, [r2, #0xA8] // Load kernel stack end
CMP r0, r1 // If end < FPCAR, move on
BLO _tx_no_lazy_clear
BIC r3, #1 // Clear LSPACT
LDR r1, =0xE000EF34 // Address of FPCCR
STR r3, [r1] // Save updated FPCCR
_tx_no_lazy_clear:
LDR r0, [r2, #0xB0] // Load the module thread stack pointer
MRS r3, PSP // Pickup kernel stack pointer
TST r0, #1 // Is module stack extended?
@@ -538,14 +555,14 @@ _tx_thread_user_return:
ORREQ lr, lr, #0x10 // Else set bit, return with standard frame
/* Copy kernel hardware stack to module thread stack. */
LDM r3!, {r1-r2}
STM r0!, {r1-r2}
LDM r3!, {r1-r2}
STM r0!, {r1-r2}
LDM r3!, {r1-r2}
STM r0!, {r1-r2}
LDM r3!, {r1-r2}
STM r0!, {r1-r2}
LDM r3!, {r1-r2} // Get r0, r1 from kernel stack
STM r0!, {r1-r2} // Insert r0, r1 into thread stack
LDM r3!, {r1-r2} // Get r2, r3 from kernel stack
STM r0!, {r1-r2} // Insert r2, r3 into thread stack
LDM r3!, {r1-r2} // Get r12, lr from kernel stack
STM r0!, {r1-r2} // Insert r12, lr into thread stack
LDM r3!, {r1-r2} // Get pc, xpsr from kernel stack
STM r0!, {r1-r2} // Insert pc, xpsr into thread stack
SUB r0, r0, #32 // Subtract 32 to get back to top of stack
MSR PSP, r0 // Set thread stack pointer
@@ -586,11 +603,11 @@ _tx_svc_secure_free:
POP {r12, lr} // Restore SP and EXC_RETURN
STR r0, [r12] // Store function return value
BX lr
#endif // End of ifndef TX_SINGLE_MODE_SECURE, TX_SINGLE_MODE_NON_SECURE
#endif // End of ifndef TX_SINGLE_MODE_SECURE, TX_SINGLE_MODE_NON_SECURE
/* Kernel entry function from user mode. */
/* Kernel entry function from user mode. */
.global _txm_module_manager_kernel_dispatch
.align 5

48
ports_module/cortex_m33/ac6/module_manager/src/tx_thread_secure_stack.c
View File

@@ -29,7 +29,7 @@
#define TX_SOURCE_CODE
#include "ARMCM33_DSP_FP_TZ.h" /* For intrinsic functions. */
#include "cmsis_compiler.h" /* For intrinsic functions. */
#include "tx_secure_interface.h" /* Interface for NS code. */
/* Minimum size of secure stack. */
@@ -62,8 +62,8 @@ typedef struct TX_THREAD_SECURE_STACK_INFO_STRUCT
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_secure_stack_initialize Cortex-M33/AC6 */
/* 6.1.1 */
/* _tx_thread_secure_mode_stack_initialize Cortex-M33/AC6 */
/* 6.1.8 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -78,7 +78,7 @@ typedef struct TX_THREAD_SECURE_STACK_INFO_STRUCT
/* */
/* OUTPUT */
/* */
/* None */
/* status */
/* */
/* CALLS */
/* */
@@ -98,21 +98,35 @@ typedef struct TX_THREAD_SECURE_STACK_INFO_STRUCT
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* 10-16-2020 Scott Larson Modified comment(s), */
/* resulting in version 6.1.1 */
/* 08-02-2021 Scott Larson Modified comment(s), and */
/* changed name, execute in */
/* handler mode, */
/* resulting in version 6.1.8 */
/* */
/**************************************************************************/
__attribute__((cmse_nonsecure_entry))
void _tx_thread_secure_stack_initialize(void)
UINT _tx_thread_secure_mode_stack_initialize(void)
{
/* Set secure mode to use PSP. */
__set_CONTROL(__get_CONTROL() | 2);
/* Set process stack pointer and stack limit to 0 to throw exception when a thread
without a secure stack calls a secure function that tries to use secure stack. */
__set_PSPLIM(0);
__set_PSP(0);
return;
UINT status;
/* Make sure function is called from interrupt (threads should not call). */
if (__get_IPSR() == 0)
{
status = TX_CALLER_ERROR;
}
else
{
/* Set secure mode to use PSP. */
__set_CONTROL(__get_CONTROL() | 2);
/* Set process stack pointer and stack limit to 0 to throw exception when a thread
without a secure stack calls a secure function that tries to use secure stack. */
__set_PSPLIM(0);
__set_PSP(0);
status = TX_SUCCESS;
}
return status;
}
@@ -291,7 +305,7 @@ UINT _tx_thread_secure_mode_stack_free(TX_THREAD *thread_ptr)
{
UINT status;
TX_THREAD_SECURE_STACK_INFO *info_ptr;
status = TX_SUCCESS;
/* Pickup stack info from thread. */
@@ -376,7 +390,7 @@ void _tx_thread_secure_stack_context_save(TX_THREAD *thread_ptr)
{
TX_THREAD_SECURE_STACK_INFO *info_ptr;
ULONG sp;
/* This function should be called from scheduler only. */
if (__get_IPSR() == 0)
{

79
ports_module/cortex_m33/ac6/module_manager/src/tx_thread_secure_stack_initialize.S Normal file
View File

@@ -0,0 +1,79 @@
/**************************************************************************/
/* */
/* Copyright (c) Microsoft Corporation. All rights reserved. */
/* */
/* This software is licensed under the Microsoft Software License */
/* Terms for Microsoft Azure RTOS. Full text of the license can be */
/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
/* and in the root directory of this software. */
/* */
/**************************************************************************/
/**************************************************************************/
/**************************************************************************/
/** */
/** ThreadX Component */
/** */
/** Thread */
/** */
/**************************************************************************/
/**************************************************************************/
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_secure_stack_initialize Cortex-M33/AC6 */
/* 6.1.8 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
/* */
/* DESCRIPTION */
/* */
/* This function enters the SVC handler to initialize a secure stack. */
/* */
/* INPUT */
/* */
/* none */
/* */
/* OUTPUT */
/* */
/* none */
/* */
/* CALLS */
/* */
/* SVC 3 */
/* */
/* CALLED BY */
/* */
/* TX_INITIALIZE_KERNEL_ENTER_EXTENSION */
/* */
/* RELEASE HISTORY */
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 08-02-2021 Scott Larson Initial Version 6.1.8 */
/* */
/**************************************************************************/
// VOID _tx_thread_secure_stack_initialize(VOID)
// {
.section .text
.balign 4
.syntax unified
.eabi_attribute Tag_ABI_align_preserved, 1
.global _tx_thread_secure_stack_initialize
.thumb_func
.type _tx_thread_secure_stack_initialize, function
_tx_thread_secure_stack_initialize:
#if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE)
CPSIE i // Enable interrupts for SVC call
SVC 3
CPSID i // Disable interrupts
#else
MOV r0, #0xFF // Feature not enabled
#endif
BX lr
.end

2
ports_module/cortex_m33/ac6/module_manager/src/tx_thread_stack_build.S
View File

@@ -72,7 +72,7 @@
.type _tx_thread_stack_build, function
_tx_thread_stack_build:
/* Build a fake interrupt frame. The form of the fake interrupt stack
on the Cortex-M33 should look like the following after it is built:
on the Cortex-M should look like the following after it is built:
Stack Top:
LR Interrupted LR (LR at time of PENDSV)

14
ports_module/cortex_m33/ac6/module_manager/src/tx_thread_stack_error_handler.c
View File

@@ -28,8 +28,8 @@
#include "tx_api.h"
#include "tx_thread.h"
/* Define the global function pointer for stack error handling. If a stack error is
detected and the application has registered a stack error handler, it will be
/* Define the global function pointer for stack error handling. If a stack error is
detected and the application has registered a stack error handler, it will be
called via this function pointer. */
VOID (*_tx_thread_application_stack_error_handler)(TX_THREAD *thread_ptr);
@@ -38,8 +38,8 @@ VOID (*_tx_thread_application_stack_error_handler)(TX_THREAD *thread_ptr);
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_stack_error_handler Cortex-M33/AC6 */
/* 6.1.3 */
/* _tx_thread_stack_error_handler Cortex-M33 */
/* 6.1 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -70,12 +70,11 @@ VOID (*_tx_thread_application_stack_error_handler)(TX_THREAD *thread_ptr);
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 12-31-2020 Scott Larson Initial Version 6.1.3 */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* */
/**************************************************************************/
VOID _tx_thread_stack_error_handler(TX_THREAD *thread_ptr)
{
#ifndef TX_THREAD_NO_TERMINATE_STACK_ERROR
/* Is there a thread? */
if (thread_ptr)
@@ -88,10 +87,7 @@ VOID _tx_thread_stack_error_handler(TX_THREAD *thread_ptr)
/* Determine if the application has registered an error handler. */
if (_tx_thread_application_stack_error_handler != TX_NULL)
{
/* Yes, an error handler is present, simply call the application error handler. */
(_tx_thread_application_stack_error_handler)(thread_ptr);
}
}

8
ports_module/cortex_m33/ac6/module_manager/src/tx_thread_stack_error_notify.c
View File

@@ -35,8 +35,8 @@ extern VOID (*_tx_thread_application_stack_error_handler)(TX_THREAD *thread_ptr)
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_stack_error_notify Cortex-M33/AC6 */
/* 6.1.3 */
/* _tx_thread_stack_error_notify Cortex-M33 */
/* 6.1 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -68,7 +68,7 @@ extern VOID (*_tx_thread_application_stack_error_handler)(TX_THREAD *thread_ptr)
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 12-31-2020 Scott Larson Initial Version 6.1.3 */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* */
/**************************************************************************/
UINT _tx_thread_stack_error_notify(VOID (*stack_error_handler)(TX_THREAD *thread_ptr))
@@ -76,7 +76,6 @@ UINT _tx_thread_stack_error_notify(VOID (*stack_error_handler)(TX_THREAD *threa
TX_INTERRUPT_SAVE_AREA
/* Disable interrupts. */
TX_DISABLE
@@ -95,4 +94,3 @@ TX_INTERRUPT_SAVE_AREA
/* Return success to caller. */
return(TX_SUCCESS);
}

9
ports_module/cortex_m33/ac6/module_manager/src/tx_thread_system_return.S
View File

@@ -75,14 +75,21 @@ _tx_thread_system_return:
replaced with in-line assembly in tx_port.h to improved performance. */
MOV r0, #0x10000000 // Load PENDSVSET bit
LDR r1, =0xE000E000 // Load NVIC base
MOV r1, #0xE000E000 // Load NVIC base
STR r0, [r1, #0xD04] // Set PENDSVBIT in ICSR
MRS r0, IPSR // Pickup IPSR
CMP r0, #0 // Is it a thread returning?
BNE _isr_context // If ISR, skip interrupt enable
#ifdef TX_PORT_USE_BASEPRI
MRS r1, BASEPRI // Thread context returning, pickup BASEPRI
MOV r0, #0
MSR BASEPRI, r0 // Enable interrupts
MSR BASEPRI, r1 // Restore original interrupt posture
#else
MRS r1, PRIMASK // Thread context returning, pickup PRIMASK
CPSIE i // Enable interrupts
MSR PRIMASK, r1 // Restore original interrupt posture
#endif
_isr_context:
BX lr // Return to caller
// }

59
ports_module/cortex_m33/ac6/module_manager/src/tx_timer_interrupt.S
View File

@@ -36,8 +36,7 @@
/* This function processes the hardware timer interrupt. This */
/* processing includes incrementing the system clock and checking for */
/* time slice and/or timer expiration. If either is found, the */
/* interrupt context save/restore functions are called along with the */
/* expiration functions. */
/* expiration functions are called. */
/* */
/* INPUT */
/* */
@@ -63,8 +62,8 @@
/* 12-31-2020 Scott Larson Initial Version 6.1.3 */
/* */
/**************************************************************************/
/* VOID _tx_timer_interrupt(VOID)
{ */
// VOID _tx_timer_interrupt(VOID)
// {
.section .text
.balign 4
.syntax unified
@@ -74,8 +73,7 @@
.type _tx_timer_interrupt, function
_tx_timer_interrupt:
/* Upon entry to this routine, it is assumed that context save has already
been called, and therefore the compiler scratch registers are available
/* Upon entry to this routine, it is assumed that the compiler scratch registers are available
for use. */
/* Increment the system clock. */
@@ -92,22 +90,23 @@ _tx_timer_interrupt:
LDR r3, =_tx_timer_time_slice // Pickup address of time-slice
LDR r2, [r3, #0] // Pickup time-slice
CBZ r2, __tx_timer_no_time_slice // Is it non-active?
CBZ r2, __tx_timer_no_time_slice // Is it non-active?
// Yes, skip time-slice processing
/* Decrement the time_slice. */
// _tx_timer_time_slice--;
/* Decrement the time_slice. */
// _tx_timer_time_slice--;
SUB r2, r2, #1 // Decrement the time-slice
STR r2, [r3, #0] // Store new time-slice value
/* Check for expiration. */
// if (__tx_timer_time_slice == 0)
/* Check for expiration. */
// if (__tx_timer_time_slice == 0)
CBNZ r2, __tx_timer_no_time_slice // Has it expired?
// No, skip expiration processing
/* Set the time-slice expired flag. */
// _tx_timer_expired_time_slice = TX_TRUE;
/* Set the time-slice expired flag. */
// _tx_timer_expired_time_slice = TX_TRUE;
LDR r3, =_tx_timer_expired_time_slice // Pickup address of expired flag
MOV r0, #1 // Build expired value
@@ -127,8 +126,8 @@ __tx_timer_no_time_slice:
CBZ r2, __tx_timer_no_timer // Is there anything in the list?
// No, just increment the timer
/* Set expiration flag. */
// _tx_timer_expired = TX_TRUE;
/* Set expiration flag. */
// _tx_timer_expired = TX_TRUE;
LDR r3, =_tx_timer_expired // Pickup expiration flag address
MOV r2, #1 // Build expired value
@@ -140,21 +139,21 @@ __tx_timer_no_time_slice:
// {
__tx_timer_no_timer:
/* No timer expired, increment the timer pointer. */
// _tx_timer_current_ptr++;
/* No timer expired, increment the timer pointer. */
// _tx_timer_current_ptr++;
ADD r0, r0, #4 // Move to next timer
/* Check for wrap-around. */
// if (_tx_timer_current_ptr == _tx_timer_list_end)
/* Check for wrap-around. */
// if (_tx_timer_current_ptr == _tx_timer_list_end)
LDR r3, =_tx_timer_list_end // Pickup addr of timer list end
LDR r2, [r3, #0] // Pickup list end
CMP r0, r2 // Are we at list end?
BNE __tx_timer_skip_wrap // No, skip wrap-around logic
/* Wrap to beginning of list. */
// _tx_timer_current_ptr = _tx_timer_list_start;
/* Wrap to beginning of list. */
// _tx_timer_current_ptr = _tx_timer_list_start;
LDR r3, =_tx_timer_list_start // Pickup addr of timer list start
LDR r0, [r3, #0] // Set current pointer to list start
@@ -166,7 +165,6 @@ __tx_timer_skip_wrap:
__tx_timer_done:
/* See if anything has expired. */
// if ((_tx_timer_expired_time_slice) || (_tx_timer_expired))
// {
@@ -182,7 +180,7 @@ __tx_timer_done:
__tx_something_expired:
STMDB sp!, {r0, lr} // Save the lr register on the stack
PUSH {r0, lr} // Save the lr register on the stack
// and save r0 just to keep 8-byte alignment
/* Did a timer expire? */
@@ -194,8 +192,8 @@ __tx_something_expired:
CBZ r0, __tx_timer_dont_activate // Check for timer expiration
// If not set, skip timer activation
/* Process timer expiration. */
// _tx_timer_expiration_process();
/* Process timer expiration. */
// _tx_timer_expiration_process();
BL _tx_timer_expiration_process // Call the timer expiration handling routine
@@ -211,8 +209,8 @@ __tx_timer_dont_activate:
CBZ r2, __tx_timer_not_ts_expiration // See if the flag is set
// No, skip time-slice processing
/* Time slice interrupted thread. */
// _tx_thread_time_slice();
/* Time slice interrupted thread. */
// _tx_thread_time_slice();
BL _tx_thread_time_slice // Call time-slice processing
LDR r0, =_tx_thread_preempt_disable // Build address of preempt disable flag
@@ -223,17 +221,17 @@ __tx_timer_dont_activate:
LDR r2, =_tx_thread_execute_ptr // Build execute thread pointer address
LDR r3, [r2] // Pickup the execute thread pointer
LDR r0, =0xE000ED04 // Build address of control register
MOV r2, 0x10000000 // Build value for PendSV bit
LDR r2, =0x10000000 // Build value for PendSV bit
CMP r1, r3 // Are they the same?
BEQ __tx_timer_skip_time_slice // If the same, there was no time-slice performed
STR r2, [r0] // Not the same, issue the PendSV for preemption
__tx_timer_skip_time_slice:
// }
__tx_timer_not_ts_expiration:
LDMIA sp!, {r0, lr} // Recover lr register (r0 is just there for
POP {r0, lr} // Recover lr register (r0 is just there for
// the 8-byte stack alignment
// }
@@ -241,6 +239,5 @@ __tx_timer_nothing_expired:
DSB // Complete all memory access
BX lr // Return to caller
// }
.end

10
ports_module/cortex_m33/ac6/module_manager/src/txe_thread_secure_stack_allocate.c
View File

@@ -33,8 +33,8 @@
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_secure_stack_allocate PORTABLE C */
/* 6.1.3 */
/* _tx_thread_secure_stack_allocate Cortex-M33 */
/* 6.1 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -68,7 +68,7 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 12-31-2020 Scott Larson Initial Version 6.1.3 */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* */
/**************************************************************************/
UINT _txe_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size)
@@ -84,7 +84,6 @@ UINT status;
/* Check for an invalid thread pointer. */
if (thread_ptr == TX_NULL)
{
/* Thread pointer is invalid, return appropriate error code. */
status = TX_THREAD_ERROR;
}
@@ -92,7 +91,6 @@ UINT status;
/* Now check for invalid thread ID. */
else if (thread_ptr -> tx_thread_id != TX_THREAD_ID)
{
/* Thread pointer is invalid, return appropriate error code. */
status = TX_THREAD_ERROR;
}
@@ -111,7 +109,6 @@ UINT status;
/* Determine if everything is okay. */
if (status == TX_SUCCESS)
{
/* Call actual secure stack allocate function. */
status = _tx_thread_secure_stack_allocate(thread_ptr, stack_size);
}
@@ -120,4 +117,3 @@ UINT status;
return(status);
#endif
}

7
ports_module/cortex_m33/ac6/module_manager/src/txe_thread_secure_stack_free.c
View File

@@ -33,8 +33,8 @@
/* */
/* FUNCTION RELEASE */
/* */
/* _txe_thread_secure_stack_free PORTABLE C */
/* 6.1.3 */
/* _txe_thread_secure_stack_free Cortex-M33 */
/* 6.1 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -66,7 +66,7 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 12-31-2020 Scott Larson Initial Version 6.1.3 */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* */
/**************************************************************************/
UINT _txe_thread_secure_stack_free(TX_THREAD *thread_ptr)
@@ -118,4 +118,3 @@ UINT status;
return(status);
#endif
}

6
ports_module/cortex_m33/ac6/module_manager/src/txm_module_manager_alignment_adjust.c
View File

@@ -30,8 +30,8 @@
/* */
/* FUNCTION RELEASE */
/* */
/* _txm_module_manager_alignment_adjust Cortex-M33/MPU/AC6 */
/* 6.1.3 */
/* _txm_module_manager_alignment_adjust Cortex-M33 */
/* 6.1.8 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -65,7 +65,7 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 12-31-2020 Scott Larson Initial Version 6.1.3 */
/* 08-02-2021 Scott Larson Initial Version 6.1.8 */
/* */
/**************************************************************************/
VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble,

6
ports_module/cortex_m33/ac6/module_manager/src/txm_module_manager_external_memory_enable.c
View File

@@ -33,8 +33,8 @@
/* */
/* FUNCTION RELEASE */
/* */
/* _txm_module_manager_external_memory_enable Cortex-M33/MPU/AC6 */
/* 6.1.3 */
/* _txm_module_manager_external_memory_enable Cortex-M33 */
/* 6.1.8 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -68,7 +68,7 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 12-31-2020 Scott Larson Initial Version 6.1.3 */
/* 08-02-2021 Scott Larson Initial Version 6.1.8 */
/* */
/**************************************************************************/
UINT _txm_module_manager_external_memory_enable(TXM_MODULE_INSTANCE *module_instance,

6
ports_module/cortex_m33/ac6/module_manager/src/txm_module_manager_memory_fault_handler.c
View File

@@ -45,8 +45,8 @@ TXM_MODULE_MANAGER_FAULT_INFO
/* */
/* FUNCTION RELEASE */
/* */
/* _txm_module_manager_memory_fault_handler Cortex-M33/MPU/AC6 */
/* 6.1.3 */
/* _txm_module_manager_memory_fault_handler Cortex-M33 */
/* 6.1.8 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -76,7 +76,7 @@ TXM_MODULE_MANAGER_FAULT_INFO
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 12-31-2020 Scott Larson Initial Version 6.1.3 */
/* 08-02-2021 Scott Larson Initial Version 6.1.8 */
/* */
/**************************************************************************/
VOID _txm_module_manager_memory_fault_handler(VOID)

6
ports_module/cortex_m33/ac6/module_manager/src/txm_module_manager_memory_fault_notify.c
View File

@@ -38,8 +38,8 @@ extern VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTA
/* */
/* FUNCTION RELEASE */
/* */
/* _txm_module_manager_memory_fault_notify Cortex-M33/MPU/AC6 */
/* 6.1.3 */
/* _txm_module_manager_memory_fault_notify Cortex-M33 */
/* 6.1.8 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -71,7 +71,7 @@ extern VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTA
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 12-31-2020 Scott Larson Initial Version 6.1.3 */
/* 08-02-2021 Scott Larson Initial Version 6.1.8 */
/* */
/**************************************************************************/
UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *))

4
ports_module/cortex_m33/ac6/module_manager/src/txm_module_manager_mm_register_setup.c
View File

@@ -29,7 +29,7 @@
/* */
/* FUNCTION RELEASE */
/* */
/* _txm_module_manager_mm_register_setup Cortex-M33/Generic */
/* _txm_module_manager_mm_register_setup Cortex-M33 */
/* 6.1.6 */
/* AUTHOR */
/* */
@@ -123,7 +123,7 @@ ULONG callback_stack_size;
/* */
/* FUNCTION RELEASE */
/* */
/* _txm_module_manager_inside_data_check Cortex-M33/Generic */
/* _txm_module_manager_inside_data_check Cortex-M33 */
/* 6.1.6 */
/* AUTHOR */
/* */

6
ports_module/cortex_m33/ac6/module_manager/src/txm_module_manager_port_dispatch.c
View File

@@ -30,8 +30,8 @@
/* */
/* FUNCTION RELEASE */
/* */
/* _txm_module_manager_port_dispatch Cortex-M33/AC6 */
/* 6.1.3 */
/* _txm_module_manager_port_dispatch Cortex-M33 */
/* 6.1.8 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -65,7 +65,7 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 12-31-2020 Scott Larson Initial Version 6.1.3 */
/* 08-02-2021 Scott Larson Initial Version 6.1.8 */
/* */
/**************************************************************************/
ALIGN_TYPE _txm_module_manager_port_dispatch(TXM_MODULE_INSTANCE *module_instance, ULONG kernel_request, ALIGN_TYPE param_0, ALIGN_TYPE param_1, ALIGN_TYPE param_2)

2
ports_module/cortex_m33/ac6/module_manager/src/txm_module_manager_thread_stack_build.S
View File

@@ -60,7 +60,7 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 12-31-2020 Scott Larson Initial Version 6.1.3 */
/* 08-02-2021 Scott Larson Initial Version 6.1.8 */
/* */
/**************************************************************************/
// VOID _txm_module_manager_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(TX_THREAD *, TXM_MODULE_INSTANCE *))