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riscv : add riscv qemu virt support and fix fs bit error in mstatus

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This commit is contained in:
Jer6y
2024-10-25 20:03:11 +08:00
parent 485a02faec
commit d24da0e2ea
20 changed files with 1463 additions and 0 deletions
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1
ports/risc-v64/gnu/src/tx_initialize_low_level.S
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@@ -69,6 +69,7 @@ __tx_free_memory_start:
/* VOID _tx_initialize_low_level(VOID)
{ */
.global _tx_initialize_low_level
.weak _tx_initialize_low_level
_tx_initialize_low_level:
sd sp, _tx_thread_system_stack_ptr, t0 // Save system stack pointer

8
ports/risc-v64/gnu/src/tx_thread_context_restore.S
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@@ -149,6 +149,10 @@ _tx_thread_context_restore:
LOAD t0, 30*REGBYTES(sp) // Recover mepc
csrw mepc, t0 // Setup mepc
li t0, 0x1880 // Prepare MPIP
#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double)
li t1, 1<<13
or t0, t1, t0
#endif
csrw mstatus, t0 // Enable MPIP
LOAD x1, 28*REGBYTES(sp) // Recover RA
@@ -259,6 +263,10 @@ _tx_thread_no_preempt_restore:
LOAD t0, 240(sp) // Recover mepc
csrw mepc, t0 // Setup mepc
li t0, 0x1880 // Prepare MPIP
#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double)
li t1, 1<<13
or t0, t1, t0
#endif
csrw mstatus, t0 // Enable MPIP
LOAD x1, 28*REGBYTES(sp) // Recover RA

4
ports/risc-v64/gnu/src/tx_thread_schedule.S
View File

@@ -201,6 +201,10 @@ _tx_thread_schedule_loop:
LOAD t0, 30*REGBYTES(sp) // Recover mepc
csrw mepc, t0 // Store mepc
li t0, 0x1880 // Prepare MPIP
#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double)
li t1, 1<<13
or t0, t1, t0
#endif
csrw mstatus, t0 // Enable MPIP
LOAD x1, 28*REGBYTES(sp) // Recover RA