riscv : add riscv qemu virt support and fix fs bit error in mstatus

2024-10-25 20:03:11 +08:00
parent 485a02faec
commit d24da0e2ea
20 changed files with 1463 additions and 0 deletions
--- a/ports/risc-v64/gnu/src/tx_thread_schedule.S
+++ b/ports/risc-v64/gnu/src/tx_thread_schedule.S
@@ -201,6 +201,10 @@ _tx_thread_schedule_loop:
    LOAD    t0, 30*REGBYTES(sp)                         // Recover mepc
    csrw    mepc, t0                                    // Store mepc
    li      t0, 0x1880                                  // Prepare MPIP
+#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double)
+    li      t1, 1<<13
+    or      t0, t1, t0
+#endif
    csrw    mstatus, t0                                 // Enable MPIP

    LOAD    x1,  28*REGBYTES(sp)                        // Recover RA