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update to v6.1.3

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This commit is contained in:
Scott Larson
2021-01-08 13:31:36 -08:00
parent b0e9b132b5
commit f108ebdbaf
477 changed files with 98409 additions and 5320 deletions
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67
ports/xtensa/xcc/inc/tx_api_asm.h Normal file
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/**************************************************************************/
/* */
/* Copyright (c) Microsoft Corporation. All rights reserved. */
/* */
/* This software is licensed under the Microsoft Software License */
/* Terms for Microsoft Azure RTOS. Full text of the license can be */
/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
/* and in the root directory of this software. */
/* */
/**************************************************************************/
/**************************************************************************/
/* */
/* DESCRIPTION */
/* */
/* This file contains macro constants for ThreadX API structures */
/* and enums that need to be used in assembly coded port sources. */
/* Most of these constants are derived from definitions in tx_api.h. */
/* Only the constants that are needed are included here to reduce */
/* the maintenance required when the structures or enums change. */
/* Structure offsets depend on the compiler, so are tools-specific, */
/* which usually means port-specific since a compiler's struct */
/* packing rules depend on properties of the target architecture. */
/* */
/* RELEASE HISTORY */
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 12-31-2020 Cadence Design Systems Initial Version 6.1.3 */
/* */
/**************************************************************************/
#ifndef TX_API_ASM_H
#define TX_API_ASM_H
#include "tx_port.h"
/* API input parameters and general constants. */
#define TX_TRUE 1
#define TX_FALSE 0
#define TX_NULL 0
/* ThreadX thread control block structure. */
// typedef struct TX_THREAD_STRUCT
// {
#define tx_thread_run_count 0x04
#define tx_thread_stack_ptr 0x08
#define tx_thread_stack_end 0x10
#define tx_thread_time_slice 0x18
#define tx_thread_new_time_slice 0x1C
#define tx_thread_solicited 0x28
#ifdef TX_THREAD_SAFE_CLIB
#define tx_real_thread_entry 0x2C
#define tx_thread_clib_ptr 0x30
#define tx_thread_cp_state 0x34
#else
#define tx_thread_cp_state 0x2C
#endif
// }
#endif /* TX_API_ASM_H */

479
ports/xtensa/xcc/inc/tx_port.h Normal file
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/**************************************************************************/
/* */
/* Copyright (c) Microsoft Corporation. All rights reserved. */
/* */
/* This software is licensed under the Microsoft Software License */
/* Terms for Microsoft Azure RTOS. Full text of the license can be */
/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
/* and in the root directory of this software. */
/* */
/**************************************************************************/
/**************************************************************************/
/** */
/** ThreadX Component */
/** */
/** Port Specific */
/** */
/**************************************************************************/
/**************************************************************************/
/* */
/* DESCRIPTION */
/* */
/* This file contains data type definitions that make the ThreadX */
/* real-time kernel function identically on a variety of different */
/* processor architectures. For example, the size or number of bits */
/* in an "int" data type vary between microprocessor architectures and */
/* even C compilers for the same microprocessor. ThreadX does not */
/* directly use native C data types. Instead, ThreadX creates its */
/* own special types that can be mapped to actual data types by this */
/* file to guarantee consistency in the interface and functionality. */
/* */
/* RELEASE HISTORY */
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 12-31-2020 Cadence Design Systems Initial Version 6.1.3 */
/* */
/**************************************************************************/
#ifndef TX_PORT_H
#define TX_PORT_H
/* Determine if the optional ThreadX user define file should be used. */
#ifdef TX_INCLUDE_USER_DEFINE_FILE
#include "tx_user.h"
#endif
/* Comment this out to disable thread-safe C library support. */
#define TX_THREAD_SAFE_CLIB 1
/* Include the glue to Xtensa-generic parts of this ThreadX port. */
#include "xtensa_rtos.h"
/* Parts of this file should not been seen by assembler sources. */
#ifndef __ASSEMBLER__
/* Some generic C sources call memset() and need this (else compiler warns).
Until the generic sources take care of this, do it here. */
#include <string.h>
/* Define compiler library include files and library-specific macros. */
/*
Thread-safety support for the supported C libraries. At this time
only the newlib and Xtensa C libraries are supported.
The C library reent structure can be quite large so it is placed
at the end of TX_THREAD, and a pointer to it is defined near the
beginning of TX_THREAD where assembly code can easily get to it
at a fixed offset.
*/
#ifdef TX_THREAD_SAFE_CLIB
struct TX_THREAD_STRUCT;
extern char *_tx_clib_heap_start, *_tx_clib_heap_end;
extern void _tx_clib_reent_init (struct TX_THREAD_STRUCT *thread_ptr);
extern void _tx_clib_reent_cleanup (struct TX_THREAD_STRUCT *thread_ptr, int partial);
extern void _tx_clib_thread_setup(struct TX_THREAD_STRUCT *thread_ptr);
#include <sys/reent.h>
#define TX_CLIB_THREAD_EXTENSION \
VOID (*tx_real_thread_entry)(ULONG id); /* Actual entry point */ \
struct _reent * tx_thread_clib_ptr; /* C lib reentrancy ptr */
#define TX_CLIB_THREAD_EXTENSION_END \
struct _reent tx_thread_clib_reent; /* C lib reentrancy struct */
#define TX_CLIB_THREAD_CREATE_EXTENSION(thread_ptr)
#define TX_CLIB_THREAD_DELETE_EXTENSION(thread_ptr)
#define TX_CLIB_THREAD_EXIT_EXTENSION(thread_ptr)
#define TX_THREAD_CLIB_EXTENSION(thread_ptr) \
_tx_clib_thread_setup(thread_ptr);
#else
#define TX_CLIB_THREAD_EXTENSION
#define TX_CLIB_THREAD_EXTENSION_END
#define TX_CLIB_THREAD_CREATE_EXTENSION(thread_ptr)
#define TX_CLIB_THREAD_DELETE_EXTENSION(thread_ptr)
#define TX_CLIB_THREAD_EXIT_EXTENSION(thread_ptr)
#define TX_THREAD_CLIB_EXTENSION(thread_ptr)
#endif
/* Define ThreadX basic types for this port. */
#define VOID void
typedef char CHAR;
typedef unsigned char UCHAR;
typedef int INT;
typedef unsigned int UINT;
typedef long LONG;
typedef unsigned long ULONG;
typedef short SHORT;
typedef unsigned short USHORT;
#endif /* #ifndef __ASSEMBLER__ */
/* Define the priority levels for ThreadX. Legal values range
from 32 to 1024 and MUST be evenly divisible by 32. */
#ifndef TX_MAX_PRIORITIES
#define TX_MAX_PRIORITIES 32
#endif
/*
Define the minimum stack size for a thread on this processor.
If the size supplied during thread creation is less than TX_MINIMUM_STACK,
the thread create call will return an error. The minimum allows for a
thread whose entry function makes no calls and needs no local frame.
TX_MINIMUM_STACK_BASIC allows the entry function to at least call
tx_thread_relinquish(). An extra 0x10 bytes is allowed in all cases to
allow for stack pointer alignment to 16 bytes. There is an additional premium
for the stack checking functionality of TX_ENABLE_STACK_CHECKING.
In Xtensa, all these amounts depend on the function call ABI used by the
configuration (in general, Call0 ABI needs about 0x20 bytes less stack space
per function call frame). These amounts assume no compiler optimization (-O0).
Optimization usually requires less stack.
TX_MINIMUM_STACK_BASIC is a MINIMUM for threads that call tx_thread_relinquish()
only. Threads that do more, and in particular call C library functions such as
printf(), need much more stack space and it is up to the application developer
to determine how much.
*/
#ifdef __XTENSA_CALL0_ABI__
/* Call0 ABI */
#ifndef TX_MINIMUM_STACK
#define TX_MINIMUM_STACK (XT_STK_FRMSZ + 0x10)
#endif
#ifdef TX_ENABLE_STACK_CHECKING
#define TX_STACK_CHECK_PREMIUM 0x30
#else
#define TX_STACK_CHECK_PREMIUM 0
#endif
#ifndef TX_MINIMUM_STACK_BASIC
#define TX_MINIMUM_STACK_BASIC (XT_STK_FRMSZ + 0x70 + TX_STACK_CHECK_PREMIUM)
#endif
#else /* Windowed ABI */
#ifndef TX_MINIMUM_STACK
#define TX_MINIMUM_STACK (XT_STK_FRMSZ + 0x20)
#endif
#ifdef TX_ENABLE_STACK_CHECKING
#define TX_STACK_CHECK_PREMIUM 0x50
#else
#define TX_STACK_CHECK_PREMIUM 0
#endif
#ifndef TX_MINIMUM_STACK_BASIC
#define TX_MINIMUM_STACK_BASIC (XT_STK_FRMSZ + 0x100 + TX_STACK_CHECK_PREMIUM)
#endif
#endif
/*
Minimum stack size for the ThreadX system stack on this processor.
This is just a useful starting point for an application, it is not
checked by ThreadX. The minimum system stack size allows for the
possible depth of interrupt nesting (XCHAL_EXCM_LEVEL-1 interrupt
stack frames and XCHAL_EXCM_LEVEL interrupt handlers including timer),
assuming very basic interrupt handlers (allows 1 call12). It needs to
be increased to support the application's real interrupt handlers (and
timer interrupt if TX_TIMER_PROCESS_IN_ISR). The system stack is located
where the stack pointer is inside tx_kernel_enter() which is usually from
main(), and so is determined by the development tools. It grows downward
toward the first available memory pointer passed to tx_application_define().
An application should allow sufficient space for the system stack.
For XEA3, allow a minimum of XCHAL_NUM_INTLEVELS nested interrupts. The stack
frames are minimal-sized and may need to be increased to support real applications.
*/
#if XCHAL_HAVE_XEA3
#define TX_SYSTEM_STACK_MINIMUM (XCHAL_NUM_INTLEVELS * 0x40)
#ifndef TX_SYSTEM_STACK_SIZE
#if TX_SYSTEM_STACK_MINIMUM > 2048
#define TX_SYSTEM_STACK_SIZE TX_SYSTEM_STACK_MINIMUM
#else
#define TX_SYSTEM_STACK_SIZE 2048
#endif
#endif
#else
#define TX_SYSTEM_STACK_MINIMUM (((XCHAL_EXCM_LEVEL-1) * (0x40 + XT_STK_FRMSZ)) + 0x40)
#ifndef TX_SYSTEM_STACK_SIZE
#define TX_SYSTEM_STACK_SIZE 4096
#endif
#endif
/*
Define the system timer thread's default stack size and priority.
These are only applicable if TX_TIMER_PROCESS_IN_ISR is not defined.
*/
#ifndef TX_TIMER_THREAD_STACK_SIZE
#ifdef __XTENSA_CALL0_ABI__
#define TX_TIMER_THREAD_STACK_SIZE (TX_MINIMUM_STACK_BASIC + 0x100)
#else
#define TX_TIMER_THREAD_STACK_SIZE (TX_MINIMUM_STACK_BASIC + 0x200)
#endif
#endif
/* Parts of this file should not been seen by assembler sources. */
#ifndef __ASSEMBLER__
#ifndef TX_TIMER_THREAD_PRIORITY
#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */
#endif
/* Define various constants for the ThreadX Xtensa port. */
#if XCHAL_HAVE_XEA3
#define TX_INT_DISABLE 0x8 /* Disable interrupts value */
#define TX_INT_ENABLE 0x0 /* Enable interrupt value */
#else
#define TX_INT_DISABLE XCHAL_EXCM_LEVEL /* Disable interrupts value */
#define TX_INT_ENABLE 0x0 /* Enable interrupt value */
#endif
/*
Define the clock source for trace event entry time stamp. The following
two item are port specific. For example, if the time source is at the
address 0x0a800024 and is 16-bits in size, the clock source constants
would be:
#define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024)
#define TX_TRACE_TIME_MASK 0x0000FFFFUL
*/
#ifndef TX_TRACE_TIME_SOURCE
#define TX_TRACE_TIME_SOURCE ++_tx_trace_simulated_time
#endif
#ifndef TX_TRACE_TIME_MASK
#define TX_TRACE_TIME_MASK 0xFFFFFFFFUL
#endif
/*
Define the port specific options for the _tx_build_options variable.
This variable indicates how the ThreadX library was built.
*/
#if defined(XT_SIMULATOR) || !defined(XT_BOARD)
#define TX_XT_OPT_SIMULATOR (1UL << 0)
#else
#define TX_XT_OPT_SIMULATOR 0
#endif
#if defined(XT_BOARD)
#define TX_XT_OPT_BOARD (1UL << 1)
#else
#define TX_XT_OPT_BOARD 0
#endif
#if defined(XT_INTEXC_HOOKS)
#define TX_XT_OPT_INTEXC_HOOKS (1UL << 2)
#else
#define TX_XT_OPT_INTEXC_HOOKS 0
#endif
#if defined(TX_THREAD_SAFE_CLIB)
#define TX_XT_OPT_CLIB (1UL << 3)
#else
#define TX_XT_OPT_CLIB 0
#endif
#define TX_PORT_SPECIFIC_BUILD_OPTIONS (TX_XT_OPT_SIMULATOR | TX_XT_OPT_BOARD \
| TX_XT_OPT_INTEXC_HOOKS | TX_XT_OPT_CLIB)
/*
Define the in-line initialization constant so that modules with in-line
initialization capabilities can prevent their initialization from being
a function call.
*/
#define TX_INLINE_INITIALIZATION
/*
Determine whether or not stack checking is enabled. By default, ThreadX
stack checking is disabled. When the following is defined, ThreadX thread
stack checking is enabled. If enabled (TX_ENABLE_STACK_CHECKING is defined),
the TX_DISABLE_STACK_FILLING define is canceled, thereby forcing the stack
fill which is necessary for the stack checking logic.
*/
#ifdef TX_ENABLE_STACK_CHECKING
#undef TX_DISABLE_STACK_FILLING
#endif
/*
Define the TX_THREAD control block extensions for this port. The main
reason for the multiple macros is so that backward compatibility can
be maintained with existing ThreadX kernel awareness modules.
*/
#if XCHAL_CP_NUM > 0
#define TX_CP_THREAD_EXTENSION \
/* Co-proc state save areas, with padding for alignment: */ \
UINT tx_thread_cp_state[(XT_CP_SIZE+3)/4];
#else
#define TX_CP_THREAD_EXTENSION
#endif
#define TX_THREAD_EXTENSION_0 \
/* These extensions needs to be accessed from assembly code at context switches */ \
UINT tx_thread_solicited; /* Non-zero indicates solicited entry */ \
TX_CLIB_THREAD_EXTENSION /* Ptr to C library re-ent struct */ \
TX_CP_THREAD_EXTENSION /* Coprocessor state save areas */
#define TX_THREAD_EXTENSION_1 \
TX_CLIB_THREAD_EXTENSION_END
#define TX_THREAD_EXTENSION_2
/* Execution profile related */
#define TX_THREAD_EXTENSION_3 \
unsigned long long tx_thread_execution_time_total; \
unsigned long tx_thread_execution_time_last_start;
/* Define the port extensions of the remaining ThreadX objects. */
#define TX_BLOCK_POOL_EXTENSION
#define TX_BYTE_POOL_EXTENSION
#define TX_EVENT_FLAGS_GROUP_EXTENSION
#define TX_MUTEX_EXTENSION
#define TX_QUEUE_EXTENSION
#define TX_SEMAPHORE_EXTENSION
#define TX_TIMER_EXTENSION
/* Define the user extension field of the thread control block. Nothing
additional is needed for this port so it is defined as white space. */
#ifndef TX_THREAD_USER_EXTENSION
#define TX_THREAD_USER_EXTENSION
#endif
/* Define the macros for processing extensions in tx_thread_create, tx_thread_delete,
tx_thread_shell_entry, and tx_thread_terminate. */
#if XCHAL_CP_NUM > 0
extern void _xt_coproc_release(void * coproc_sa_base);
#define TX_THREAD_DELETE_EXTENSION(thread_ptr) \
_xt_coproc_release(&thread_ptr->tx_thread_cp_state);
#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) \
_xt_coproc_release(&thread_ptr->tx_thread_cp_state);
#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) \
_xt_coproc_release(&thread_ptr->tx_thread_cp_state);
#define TX_THREAD_CP_EXTENSION(thread_ptr) \
/* Initialize XT_CP_ASA ptr to aligned save area: */ \
/* NOTE: keep this matched with xtensa_context.h. */ \
thread_ptr->tx_thread_cp_state[0] = 0; \
thread_ptr->tx_thread_cp_state[1] = 0; \
thread_ptr->tx_thread_cp_state[2] = \
((((UINT)thread_ptr->tx_thread_cp_state)+12+XCHAL_TOTAL_SA_ALIGN-1) \
& -XCHAL_TOTAL_SA_ALIGN);
#else
#define TX_THREAD_DELETE_EXTENSION(thread_ptr)
#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr)
#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr)
#define TX_THREAD_CP_EXTENSION(thread_ptr)
#endif
#define TX_THREAD_CREATE_EXTENSION(thread_ptr) \
TX_THREAD_CLIB_EXTENSION(thread_ptr) \
TX_THREAD_CP_EXTENSION(thread_ptr)
/* Define the ThreadX object creation extensions for the remaining objects. */
#define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr)
#define TX_BYTE_POOL_CREATE_EXTENSION(pool_ptr)
#define TX_EVENT_FLAGS_GROUP_CREATE_EXTENSION(group_ptr)
#define TX_MUTEX_CREATE_EXTENSION(mutex_ptr)
#define TX_QUEUE_CREATE_EXTENSION(queue_ptr)
#define TX_SEMAPHORE_CREATE_EXTENSION(semaphore_ptr)
#define TX_TIMER_CREATE_EXTENSION(timer_ptr)
/* Define the ThreadX object deletion extensions for the remaining objects. */
#define TX_BLOCK_POOL_DELETE_EXTENSION(pool_ptr)
#define TX_BYTE_POOL_DELETE_EXTENSION(pool_ptr)
#define TX_EVENT_FLAGS_GROUP_DELETE_EXTENSION(group_ptr)
#define TX_MUTEX_DELETE_EXTENSION(mutex_ptr)
#define TX_QUEUE_DELETE_EXTENSION(queue_ptr)
#define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr)
#define TX_TIMER_DELETE_EXTENSION(timer_ptr)
/*
Define ThreadX interrupt lockout and restore macros for protection
on access of critical kernel information. The restore interrupt macro
must restore the interrupt posture of the running thread prior to the
value present prior to the disable macro. In most cases, the save area
macro is used to define a local function save area for the disable and
restore macros.
*/
extern unsigned int _tx_thread_interrupt_control(unsigned int new_posture);
#define TX_INTERRUPT_SAVE_AREA register unsigned int interrupt_save;
#ifdef TX_DISABLE_INLINE_MACROS
#define TX_DISABLE interrupt_save = _tx_thread_interrupt_control(TX_INT_DISABLE);
#define TX_RESTORE _tx_thread_interrupt_control(interrupt_save);
#else
#define TX_DISABLE interrupt_save = xthal_disable_interrupts();
#define TX_RESTORE xthal_restore_interrupts(interrupt_save);
#endif
/* Define the interrupt lockout macros for each ThreadX object. */
#define TX_BLOCK_POOL_DISABLE TX_DISABLE
#define TX_BYTE_POOL_DISABLE TX_DISABLE
#define TX_EVENT_FLAGS_GROUP_DISABLE TX_DISABLE
#define TX_MUTEX_DISABLE TX_DISABLE
#define TX_QUEUE_DISABLE TX_DISABLE
#define TX_SEMAPHORE_DISABLE TX_DISABLE
#if XCHAL_HAVE_XEA3
/* Variables that keep track of the timer and software interrupt numbers in use. */
extern int xt_sw_intnum;
extern int xt_timer_intnum;
#endif
/* Define the version ID of ThreadX. This may be utilized by the application. */
#ifdef TX_THREAD_INIT
CHAR _tx_version_id[] =
"Copyright (c) Microsoft Corporation. * Azure RTOS Xtensa Version 6.1.3 *";
#else
extern CHAR _tx_version_id[];
#endif
#endif /* #ifndef __ASSEMBLER__ */
#endif

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/**************************************************************************/
/* */
/* Copyright (c) Microsoft Corporation. All rights reserved. */
/* */
/* This software is licensed under the Microsoft Software License */
/* Terms for Microsoft Azure RTOS. Full text of the license can be */
/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
/* and in the root directory of this software. */
/* */
/**************************************************************************/
/**************************************************************************/
/**************************************************************************/
/** */
/** ThreadX Component */
/** */
/** User Specific */
/** */
/**************************************************************************/
/**************************************************************************/
/**************************************************************************/
/* */
/* PORT SPECIFIC C INFORMATION RELEASE */
/* */
/* tx_user.h PORTABLE C */
/* 6.0.1 */
/* */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
/* */
/* DESCRIPTION */
/* */
/* This file contains user defines for configuring ThreadX in specific */
/* ways. This file will have an effect only if the application and */
/* ThreadX library are built with TX_INCLUDE_USER_DEFINE_FILE defined. */
/* Note that all the defines in this file may also be made on the */
/* command line when building ThreadX library and application objects. */
/* */
/* RELEASE HISTORY */
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
/* */
/**************************************************************************/
#ifndef TX_USER_H
#define TX_USER_H
/* Define various build options for the ThreadX port. The application should either make changes
here by commenting or un-commenting the conditional compilation defined OR supply the defines
though the compiler's equivalent of the -D option.
For maximum speed, the following should be defined:
TX_MAX_PRIORITIES 32
TX_DISABLE_PREEMPTION_THRESHOLD
TX_DISABLE_REDUNDANT_CLEARING
TX_DISABLE_NOTIFY_CALLBACKS
TX_NOT_INTERRUPTABLE
TX_TIMER_PROCESS_IN_ISR
TX_REACTIVATE_INLINE
TX_DISABLE_STACK_FILLING
TX_INLINE_THREAD_RESUME_SUSPEND
For minimum size, the following should be defined:
TX_MAX_PRIORITIES 32
TX_DISABLE_PREEMPTION_THRESHOLD
TX_DISABLE_REDUNDANT_CLEARING
TX_DISABLE_NOTIFY_CALLBACKS
TX_NOT_INTERRUPTABLE
TX_TIMER_PROCESS_IN_ISR
Of course, many of these defines reduce functionality and/or change the behavior of the
system in ways that may not be worth the trade-off. For example, the TX_TIMER_PROCESS_IN_ISR
results in faster and smaller code, however, it increases the amount of processing in the ISR.
In addition, some services that are available in timers are not available from ISRs and will
therefore return an error if this option is used. This may or may not be desirable for a
given application. */
/* Override various options with default values already assigned in tx_port.h. Please also refer
to tx_port.h for descriptions on each of these options. */
/*
#define TX_MAX_PRIORITIES 32
#define TX_MINIMUM_STACK ????
#define TX_THREAD_USER_EXTENSION ????
#define TX_TIMER_THREAD_STACK_SIZE ????
#define TX_TIMER_THREAD_PRIORITY ????
*/
/* Determine if timer expirations (application timers, timeouts, and tx_thread_sleep calls
should be processed within the a system timer thread or directly in the timer ISR.
By default, the timer thread is used. When the following is defined, the timer expiration
processing is done directly from the timer ISR, thereby eliminating the timer thread control
block, stack, and context switching to activate it. */
/*
#define TX_TIMER_PROCESS_IN_ISR
*/
/* Determine if in-line timer reactivation should be used within the timer expiration processing.
By default, this is disabled and a function call is used. When the following is defined,
reactivating is performed in-line resulting in faster timer processing but slightly larger
code size. */
/*
#define TX_REACTIVATE_INLINE
*/
/* Determine is stack filling is enabled. By default, ThreadX stack filling is enabled,
which places an 0xEF pattern in each byte of each thread's stack. This is used by
debuggers with ThreadX-awareness and by the ThreadX run-time stack checking feature. */
/*
#define TX_DISABLE_STACK_FILLING
*/
/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is
disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack
checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING
define is negated, thereby forcing the stack fill which is necessary for the stack checking
logic. */
/*
#define TX_ENABLE_STACK_CHECKING
*/
/* Determine if preemption-threshold should be disabled. By default, preemption-threshold is
enabled. If the application does not use preemption-threshold, it may be disabled to reduce
code size and improve performance. */
/*
#define TX_DISABLE_PREEMPTION_THRESHOLD
*/
/* Determine if global ThreadX variables should be cleared. If the compiler startup code clears
the .bss section prior to ThreadX running, the define can be used to eliminate unnecessary
clearing of ThreadX global variables. */
/*
#define TX_DISABLE_REDUNDANT_CLEARING
*/
/* Determine if no timer processing is required. This option will help eliminate the timer
processing when not needed. The user will also have to comment out the call to
tx_timer_interrupt, which is typically made from assembly language in
tx_initialize_low_level. Note: if TX_NO_TIMER is used, the define TX_TIMER_PROCESS_IN_ISR
must also be used. */
/*
#define TX_NO_TIMER
#ifndef TX_TIMER_PROCESS_IN_ISR
#define TX_TIMER_PROCESS_IN_ISR
#endif
*/
/* Determine if the notify callback option should be disabled. By default, notify callbacks are
enabled. If the application does not use notify callbacks, they may be disabled to reduce
code size and improve performance. */
/*
#define TX_DISABLE_NOTIFY_CALLBACKS
*/
/* Determine if the tx_thread_resume and tx_thread_suspend services should have their internal
code in-line. This results in a larger image, but improves the performance of the thread
resume and suspend services. */
/*
#define TX_INLINE_THREAD_RESUME_SUSPEND
*/
/* Determine if the internal ThreadX code is non-interruptable. This results in smaller code
size and less processing overhead, but increases the interrupt lockout time. */
/*
#define TX_NOT_INTERRUPTABLE
*/
/* Determine if the trace event logging code should be enabled. This causes slight increases in
code size and overhead, but provides the ability to generate system trace information which
is available for viewing in TraceX. */
/*
#define TX_ENABLE_EVENT_TRACE
*/
/* Determine if block pool performance gathering is required by the application. When the following is
defined, ThreadX gathers various block pool performance information. */
/*
#define TX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO
*/
/* Determine if byte pool performance gathering is required by the application. When the following is
defined, ThreadX gathers various byte pool performance information. */
/*
#define TX_BYTE_POOL_ENABLE_PERFORMANCE_INFO
*/
/* Determine if event flags performance gathering is required by the application. When the following is
defined, ThreadX gathers various event flags performance information. */
/*
#define TX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO
*/
/* Determine if mutex performance gathering is required by the application. When the following is
defined, ThreadX gathers various mutex performance information. */
/*
#define TX_MUTEX_ENABLE_PERFORMANCE_INFO
*/
/* Determine if queue performance gathering is required by the application. When the following is
defined, ThreadX gathers various queue performance information. */
/*
#define TX_QUEUE_ENABLE_PERFORMANCE_INFO
*/
/* Determine if semaphore performance gathering is required by the application. When the following is
defined, ThreadX gathers various semaphore performance information. */
/*
#define TX_SEMAPHORE_ENABLE_PERFORMANCE_INFO
*/
/* Determine if thread performance gathering is required by the application. When the following is
defined, ThreadX gathers various thread performance information. */
/*
#define TX_THREAD_ENABLE_PERFORMANCE_INFO
*/
/* Determine if timer performance gathering is required by the application. When the following is
defined, ThreadX gathers various timer performance information. */
/*
#define TX_TIMER_ENABLE_PERFORMANCE_INFO
*/
#endif

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/**************************************************************************/
/* Copyright (c) Cadence Design Systems, Inc. */
/* */
/* Permission is hereby granted, free of charge, to any person obtaining */
/* a copy of this software and associated documentation files (the */
/* "Software"), to deal in the Software without restriction, including */
/* without limitation the rights to use, copy, modify, merge, publish, */
/* distribute, sublicense, and/or sell copies of the Software, and to */
/* permit persons to whom the Software is furnished to do so, subject to */
/* the following conditions: */
/* */
/* The above copyright notice and this permission notice shall be */
/* included in all copies or substantial portions of the Software. */
/* */
/* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, */
/* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF */
/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. */
/* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY */
/* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, */
/* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE */
/* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
/**************************************************************************/
/**************************************************************************/
/* Xtensa-specific API for RTOS ports. */
/**************************************************************************/
#ifndef XTENSA_API_H
#define XTENSA_API_H
#include <xtensa/hal.h>
#include "xtensa_context.h"
/* Typedef for C-callable interrupt handler function */
typedef void (*xt_handler)(void *);
/* Typedef for C-callable exception handler function */
typedef void (*xt_exc_handler)(XtExcFrame *);
/*
-------------------------------------------------------------------------------
Call this function to set a handler for the specified exception.
n - Exception number (type)
f - Handler function address, NULL to uninstall handler.
The handler will be passed a pointer to the exception frame, which is created
on the stack of the thread that caused the exception.
If the handler returns, the thread context will be restored and the faulting
instruction will be retried. Any values in the exception frame that are
modified by the handler will be restored as part of the context. For details
of the exception frame structure see xtensa_context.h.
-------------------------------------------------------------------------------
*/
extern xt_exc_handler xt_set_exception_handler(uint32_t n, xt_exc_handler f);
/*
-------------------------------------------------------------------------------
Call this function to set a handler for the specified interrupt.
n - Interrupt number.
f - Handler function address, NULL to uninstall handler.
arg - Argument to be passed to handler.
-------------------------------------------------------------------------------
*/
extern xt_handler xt_set_interrupt_handler(uint32_t n, xt_handler f, void * arg);
/*
-------------------------------------------------------------------------------
Call this function to enable the specified interrupt.
intnum - Interrupt number to be enabled.
Returns: Nothing.
-------------------------------------------------------------------------------
*/
extern void xt_interrupt_enable(uint32_t intnum);
/*
-------------------------------------------------------------------------------
Call this function to disable the specified interrupt.
intnum - Interrupt number to be disabled.
Returns: Nothing.
-------------------------------------------------------------------------------
*/
extern void xt_interrupt_disable(uint32_t intnum);
/*
-------------------------------------------------------------------------------
Call this function to trigger the specified (s/w) interrupt.
intnum - Interrupt number to be triggered.
Returns: Nothing.
-------------------------------------------------------------------------------
*/
extern void xt_interrupt_trigger(uint32_t intnum);
/*
-------------------------------------------------------------------------------
Call this function to clear the specified (s/w or edge-triggered)
interrupt.
intnum - Interrupt number to be cleared.
Returns: Nothing.
-------------------------------------------------------------------------------
*/
extern void xt_interrupt_clear(uint32_t intnum);
#endif /* XTENSA_API_H */

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/**************************************************************************/
/* Copyright (c) Cadence Design Systems, Inc. */
/* */
/* Permission is hereby granted, free of charge, to any person obtaining */
/* a copy of this software and associated documentation files (the */
/* "Software"), to deal in the Software without restriction, including */
/* without limitation the rights to use, copy, modify, merge, publish, */
/* distribute, sublicense, and/or sell copies of the Software, and to */
/* permit persons to whom the Software is furnished to do so, subject to */
/* the following conditions: */
/* */
/* The above copyright notice and this permission notice shall be */
/* included in all copies or substantial portions of the Software. */
/* */
/* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, */
/* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF */
/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. */
/* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY */
/* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, */
/* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE */
/* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
/**************************************************************************/
/**************************************************************************
XTENSA CONTEXT FRAMES AND MACROS FOR RTOS ASSEMBLER SOURCES
This header contains definitions and macros for use primarily by Xtensa
RTOS assembly source files. It includes and uses the Xtensa hardware
abstraction layer (HAL) to deal with config specifics. It may also be
included in C source files.
NOTE: The Xtensa architecture requires stack pointer alignment to 16 bytes.
***************************************************************************/
#ifndef XTENSA_CONTEXT_H
#define XTENSA_CONTEXT_H
#ifdef __ASSEMBLER__
#include <xtensa/coreasm.h>
#endif
#include <xtensa/config/tie.h>
#include <xtensa/corebits.h>
#include <xtensa/config/system.h>
#if defined (__ASSEMBLER__)
#include "tx_api_asm.h"
#endif
/* Align a value up to nearest n-byte boundary, where n is a power of 2. */
#define ALIGNUP(n, val) (((val) + (n)-1) & -(n))
/*
-------------------------------------------------------------------------------
Macros that help define structures for both C and assembler.
-------------------------------------------------------------------------------
*/
#if defined(_ASMLANGUAGE) || defined(__ASSEMBLER__)
#define XSTRUCT_BEGIN .pushsection .text; .struct 0
#define XSTRUCT_FIELD(ctype,size,asname,name) asname: .space size
#define XSTRUCT_AFIELD(ctype,size,asname,name,n) asname: .space (size)*(n)
#define XSTRUCT_END(sname) sname##Size:; .popsection
#else
#define XSTRUCT_BEGIN typedef struct {
#define XSTRUCT_FIELD(ctype,size,asname,name) ctype name;
#define XSTRUCT_AFIELD(ctype,size,asname,name,n) ctype name[n];
#define XSTRUCT_END(sname) } sname;
#endif //_ASMLANGUAGE || __ASSEMBLER__
/*
-------------------------------------------------------------------------------
INTERRUPT/EXCEPTION STACK FRAME FOR A THREAD OR NESTED INTERRUPT
A stack frame of this structure is allocated for any interrupt or exception.
It goes on the current stack. If the RTOS has a system stack for handling
interrupts, every thread stack must allow space for just one interrupt stack
frame, then nested interrupt stack frames go on the system stack.
The frame includes basic registers (explicit) and "extra" registers introduced
by user TIE or the use of the MAC16 option in the user's Xtensa config.
The frame size is minimized by omitting regs not applicable to user's config.
For Windowed ABI, this stack frame includes the interruptee's base save area,
another base save area to manage gcc nested functions, and a little temporary
space to help manage the spilling of the register windows.
-------------------------------------------------------------------------------
*/
#if XCHAL_HAVE_XEA2
XSTRUCT_BEGIN
XSTRUCT_FIELD (long, 4, XT_STK_EXIT, exit) /* exit point for dispatch */
XSTRUCT_FIELD (long, 4, XT_STK_PC, pc) /* return PC */
XSTRUCT_FIELD (long, 4, XT_STK_PS, ps) /* return PS */
XSTRUCT_FIELD (long, 4, XT_STK_A0, a0)
XSTRUCT_FIELD (long, 4, XT_STK_A1, a1) /* stack pointer before interrupt */
XSTRUCT_FIELD (long, 4, XT_STK_A2, a2)
XSTRUCT_FIELD (long, 4, XT_STK_A3, a3)
XSTRUCT_FIELD (long, 4, XT_STK_A4, a4)
XSTRUCT_FIELD (long, 4, XT_STK_A5, a5)
XSTRUCT_FIELD (long, 4, XT_STK_A6, a6)
XSTRUCT_FIELD (long, 4, XT_STK_A7, a7)
XSTRUCT_FIELD (long, 4, XT_STK_A8, a8)
XSTRUCT_FIELD (long, 4, XT_STK_A9, a9)
XSTRUCT_FIELD (long, 4, XT_STK_A10, a10)
XSTRUCT_FIELD (long, 4, XT_STK_A11, a11)
XSTRUCT_FIELD (long, 4, XT_STK_A12, a12)
XSTRUCT_FIELD (long, 4, XT_STK_A13, a13)
XSTRUCT_FIELD (long, 4, XT_STK_A14, a14)
XSTRUCT_FIELD (long, 4, XT_STK_A15, a15)
XSTRUCT_FIELD (long, 4, XT_STK_SAR, sar)
XSTRUCT_FIELD (long, 4, XT_STK_EXCCAUSE, exccause)
XSTRUCT_FIELD (long, 4, XT_STK_EXCVADDR, excvaddr)
#if XCHAL_HAVE_LOOPS
XSTRUCT_FIELD (long, 4, XT_STK_LBEG, lbeg)
XSTRUCT_FIELD (long, 4, XT_STK_LEND, lend)
XSTRUCT_FIELD (long, 4, XT_STK_LCOUNT, lcount)
#endif
#if XCHAL_HAVE_EXCLUSIVE
XSTRUCT_FIELD (long, 4, XT_STK_ATOMCTL, atomctl)
#endif
#ifndef __XTENSA_CALL0_ABI__
/* Temporary space for saving stuff during window spill */
XSTRUCT_FIELD (long, 4, XT_STK_TMP0, tmp0)
XSTRUCT_FIELD (long, 4, XT_STK_TMP1, tmp1)
XSTRUCT_FIELD (long, 4, XT_STK_TMP2, tmp2)
#endif
#ifdef XT_USE_SWPRI
/* Storage for virtual priority mask */
XSTRUCT_FIELD (long, 4, XT_STK_VPRI, vpri)
#endif
#ifdef XT_USE_OVLY
/* Storage for overlay state */
XSTRUCT_FIELD (long, 4, XT_STK_OVLY, ovly)
#endif
XSTRUCT_END(XtExcFrame)
#endif /* XCHAL_HAVE_XEA2 */
#if XCHAL_HAVE_XEA3
XSTRUCT_BEGIN
XSTRUCT_FIELD (long, 4, XT_STK_ATOMCTL, atomctl)
XSTRUCT_FIELD (long, 4, XT_STK_LCOUNT, lcount)
XSTRUCT_FIELD (long, 4, XT_STK_LEND, lend)
XSTRUCT_FIELD (long, 4, XT_STK_LBEG, lbeg)
XSTRUCT_FIELD (long, 4, XT_STK_PC, pc)
XSTRUCT_FIELD (long, 4, XT_STK_PS, ps)
XSTRUCT_FIELD (long, 4, XT_STK_EXCCAUSE, exccause)
XSTRUCT_FIELD (long, 4, XT_STK_EXCVADDR, excvaddr)
#ifdef __XTENSA_CALL0_ABI__
XSTRUCT_FIELD (long, 4, XT_STK_A0, a0)
XSTRUCT_FIELD (long, 4, XT_STK_A1, a1)
XSTRUCT_FIELD (long, 4, XT_STK_A2, a2)
XSTRUCT_FIELD (long, 4, XT_STK_A3, a3)
XSTRUCT_FIELD (long, 4, XT_STK_A4, a4)
XSTRUCT_FIELD (long, 4, XT_STK_A5, a5)
XSTRUCT_FIELD (long, 4, XT_STK_A6, a6)
XSTRUCT_FIELD (long, 4, XT_STK_A7, a7)
#endif
XSTRUCT_FIELD (long, 4, XT_STK_A8, a8)
XSTRUCT_FIELD (long, 4, XT_STK_A9, a9)
XSTRUCT_FIELD (long, 4, XT_STK_A10, a10)
XSTRUCT_FIELD (long, 4, XT_STK_A11, a11)
XSTRUCT_FIELD (long, 4, XT_STK_A12, a12)
XSTRUCT_FIELD (long, 4, XT_STK_A13, a13)
XSTRUCT_FIELD (long, 4, XT_STK_A14, a14)
XSTRUCT_FIELD (long, 4, XT_STK_A15, a15)
#ifdef __XTENSA_WINDOWED_ABI__
XSTRUCT_AFIELD(long, 4, XT_STK_SPILL, spill, 8)
#endif
XSTRUCT_END(XtExcFrame)
#endif /* XCHAL_HAVE_XEA3 */
#if defined(_ASMLANGUAGE) || defined(__ASSEMBLER__)
#define XT_STK_NEXT1 XtExcFrameSize
#else
#define XT_STK_NEXT1 sizeof(XtExcFrame)
#endif
/* Allocate extra storage if needed for non-CP TIE state. Allow for alignment
padding as needed.
*/
#if XCHAL_EXTRA_SA_SIZE != 0
#if XCHAL_EXTRA_SA_ALIGN <= 16
#define XT_STK_EXTRA ALIGNUP(XCHAL_EXTRA_SA_ALIGN, XT_STK_NEXT1)
#else
/* If need more alignment than stack, add space for dynamic alignment */
#define XT_STK_EXTRA (ALIGNUP(XCHAL_EXTRA_SA_ALIGN, XT_STK_NEXT1) + XCHAL_EXTRA_SA_ALIGN)
#endif
#define XT_STK_NEXT2 (XT_STK_EXTRA + XCHAL_EXTRA_SA_SIZE)
#else
/* No extra storage required */
#define XT_STK_NEXT2 XT_STK_NEXT1
#endif
#if XCHAL_HAVE_XEA3
/* Total frame size */
#define XT_STK_FRMSZ (ALIGNUP(0x10, XT_STK_NEXT2))
/* Exception/interrupt frame size */
#define XT_STK_XFRM_SZ XT_STK_NEXT1
/* Extra save area size (including alignment padding) */
#define XT_STK_XTRA_SZ (XT_STK_FRMSZ - XT_STK_XFRM_SZ)
/* Alignment padding area size */
#if XCHAL_EXTRA_SA_SIZE != 0
#define XT_STK_ALIGN_SZ (XT_STK_EXTRA - XT_STK_NEXT1)
#endif
#else
/*
-------------------------------------------------------------------------------
This is the frame size. Add space for 4 registers (interruptee's base save
area) and some space for gcc nested functions if any.
-------------------------------------------------------------------------------
*/
#define XT_STK_FRMSZ (ALIGNUP(0x10, XT_STK_NEXT2) + 0x20)
#endif
/*
-------------------------------------------------------------------------------
CO-PROCESSOR STATE SAVE AREA FOR A THREAD
The RTOS must provide an area per thread to save the state of co-processors
when that thread does not have control. Co-processors are context-switched
lazily (on demand) only when a new thread uses a co-processor instruction,
otherwise a thread retains ownership of the co-processor even when it loses
control of the processor. An Xtensa co-processor exception is triggered when
any co-processor instruction is executed by a thread that is not the owner,
and the context switch of that co-processor is then peformed by the handler.
Ownership represents which thread's state is currently in the co-processor.
Co-processors may not be used by interrupt or exception handlers. If an
co-processor instruction is executed by an interrupt or exception handler,
the co-processor exception handler will trigger a kernel panic and freeze.
This restriction is introduced to reduce the overhead of saving and restoring
co-processor state (which can be quite large) and in particular remove that
overhead from interrupt handlers.
The co-processor state save area may be in any convenient per-thread location
such as in the thread control block or above the thread stack area. It need
not be in the interrupt stack frame since interrupts don't use co-processors.
Along with the save area for each co-processor, two bitmasks with flags per
co-processor (laid out as in the CPENABLE reg) help manage context-switching
co-processors as efficiently as possible:
XT_CPENABLE
The contents of a non-running thread's CPENABLE register.
It represents the co-processors owned (and whose state is still needed)
by the thread. When a thread is preempted, its CPENABLE is saved here.
When a thread solicits a context-swtich, its CPENABLE is cleared - the
compiler has saved the (caller-saved) co-proc state if it needs to.
When a non-running thread loses ownership of a CP, its bit is cleared.
When a thread runs, it's XT_CPENABLE is loaded into the CPENABLE reg.
Avoids co-processor exceptions when no change of ownership is needed.
XT_CPSTORED
A bitmask with the same layout as CPENABLE, a bit per co-processor.
Indicates whether the state of each co-processor is saved in the state
save area. When a thread enters the kernel, only the state of co-procs
still enabled in CPENABLE is saved. When the co-processor exception
handler assigns ownership of a co-processor to a thread, it restores
the saved state only if this bit is set, and clears this bit.
XT_CP_CS_ST
A bitmask with the same layout as CPENABLE, a bit per co-processor.
Indicates whether callee-saved state is saved in the state save area.
Callee-saved state is saved by itself on a solicited context switch,
and restored when needed by the coprocessor exception handler.
Unsolicited switches will cause the entire coprocessor to be saved
when necessary.
XT_CP_ASA
Pointer to the aligned save area. Allows it to be aligned more than
the overall save area (which might only be stack-aligned or TCB-aligned).
Especially relevant for Xtensa cores configured with a very large data
path that requires alignment greater than 16 bytes (ABI stack alignment).
-------------------------------------------------------------------------------
*/
#if XCHAL_CP_NUM > 0
/* Offsets of each coprocessor save area within the 'aligned save area': */
#define XT_CP0_SA 0
#define XT_CP1_SA ALIGNUP(XCHAL_CP1_SA_ALIGN, XT_CP0_SA + XCHAL_CP0_SA_SIZE)
#define XT_CP2_SA ALIGNUP(XCHAL_CP2_SA_ALIGN, XT_CP1_SA + XCHAL_CP1_SA_SIZE)
#define XT_CP3_SA ALIGNUP(XCHAL_CP3_SA_ALIGN, XT_CP2_SA + XCHAL_CP2_SA_SIZE)
#define XT_CP4_SA ALIGNUP(XCHAL_CP4_SA_ALIGN, XT_CP3_SA + XCHAL_CP3_SA_SIZE)
#define XT_CP5_SA ALIGNUP(XCHAL_CP5_SA_ALIGN, XT_CP4_SA + XCHAL_CP4_SA_SIZE)
#define XT_CP6_SA ALIGNUP(XCHAL_CP6_SA_ALIGN, XT_CP5_SA + XCHAL_CP5_SA_SIZE)
#define XT_CP7_SA ALIGNUP(XCHAL_CP7_SA_ALIGN, XT_CP6_SA + XCHAL_CP6_SA_SIZE)
#define XT_CP_SA_SIZE ALIGNUP(16, XT_CP7_SA + XCHAL_CP7_SA_SIZE)
/* Offsets within the overall save area: */
#define XT_CPENABLE 0 /* (2 bytes) coprocessors active for this thread */
#define XT_CPSTORED 2 /* (2 bytes) coprocessors saved for this thread */
#define XT_CP_CS_ST 4 /* (2 bytes) coprocessor callee-saved regs stored for this thread */
#define XT_CP_ASA 8 /* (4 bytes) ptr to aligned save area */
/* Overall size allows for dynamic alignment: */
#define XT_CP_SIZE (12 + XT_CP_SA_SIZE + XCHAL_TOTAL_SA_ALIGN)
#else
#define XT_CP_SIZE 0
#endif
/*
-------------------------------------------------------------------------------
MACROS TO HANDLE ABI SPECIFICS OF FUNCTION ENTRY AND RETURN
Convenient where the frame size requirements are the same for both ABIs.
ENTRY(sz), RET(sz) are for framed functions (have locals or make calls).
ENTRY0, RET0 are for frameless functions (no locals, no calls).
where size = size of stack frame in bytes (must be >0 and aligned to 16).
For framed functions the frame is created and the return address saved at
base of frame (Call0 ABI) or as determined by hardware (Windowed ABI).
For frameless functions, there is no frame and return address remains in a0.
Note: Because CPP macros expand to a single line, macros requiring multi-line
expansions are implemented as assembler macros.
-------------------------------------------------------------------------------
*/
#ifdef __ASSEMBLER__
#ifdef __XTENSA_CALL0_ABI__
/* Call0 */
#define ENTRY(sz) entry1 sz
.macro entry1 size=0x10
addi sp, sp, -\size
s32i a0, sp, 0
.endm
#define ENTRY0
#define RET(sz) ret1 sz
.macro ret1 size=0x10
l32i a0, sp, 0
addi sp, sp, \size
ret
.endm
#define RET0 ret
#else
/* Windowed */
#if XCHAL_HAVE_XEA3
#define ENTRY(sz) entry sp, (sz + 0x20)
#define ENTRY0 entry sp, 0x20
#else
#define ENTRY(sz) entry sp, (sz + 0x10)
#define ENTRY0 entry sp, 0x10
#endif
#define RET(sz) retw
#define RET0 retw
#endif
#endif
/*
-------------------------------------------------------------------------------
This flag is meant for internal use. Have all interrupts be dispatched via a
common wrapper, which takes care of doing some OS-specific stuff common to
all interrupt handlers. Said stuff cannot safely be handled in the RTOS_ENTER
and RTOS_EXIT macros.
-------------------------------------------------------------------------------
*/
#if (defined TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || (defined XT_INTEXC_HOOKS)
#define XT_USE_INT_WRAPPER 1
#else
#define XT_USE_INT_WRAPPER 0
#endif
#if XCHAL_HAVE_XEA3
#ifdef XT_USE_SWPRI
//#warning "Software prioritization of interrupts (XT_USE_SWPRI) not supported for XEA3."
#endif
#ifdef __ASSEMBLER__
// RTOS-specific entry macro. Use only a8, a12-a14.
.macro XT_RTOS_INT_ENTER
.endm
// RTOS-specific exit macro. Use only a8-a14.
// (In call0, a15 holds user SP, must be preserved)
.macro XT_RTOS_INT_EXIT
// Check nesting count and branch on nest state.
movi a8, _tx_thread_system_state
movi a9, _tx_thread_execute_ptr // a9 <- &_tx_thread_execute_ptr (new)
movi a10, _tx_thread_preempt_disable // a10 <- &_tx_thread_preempt_disable
l32i a8, a8, 0
bnez a8, .Lnested // state != 0 means nested
movi a8, _tx_thread_current_ptr // a8 <- &_tx_thread_current_ptr (old)
l32i a9, a9, 0 // a9 <- _tx_thread_execute_ptr
l32i a11, a8, 0 // a11 <- _tx_thread_current_ptr
beqz a11, .Lsched // no old thread, go to scheduler
l32i a10, a10, 0 // a10 <- _tx_thread_preempt_disable
beq a11, a9, .Lnested // no change, restore current thread
bgei a10, 1, .Lnested // no preemption, restore current thread
// Preemption, save remaining state of current (outgoing) thread
movi a12, _tx_timer_time_slice // a12 <- &_tx_timer_time_slice
addi a10, a1, -XT_STK_FRMSZ
s32i a10, a11, tx_thread_stack_ptr // save outgoing thread stack pointer
l32i a10, a12, 0 // a10 <- _tx_timer_time_slice
s32i a10, a11, tx_thread_time_slice // save outgoing time slice value
movi a10, 0
s32i a10, a12, 0 // disable time slice
s32i a10, a11, tx_thread_solicited // mark as preempted
s32i a10, a8, 0 // Clear _tx_thread_current_ptr
#if XCHAL_CP_NUM > 0
rsr a12, CPENABLE // Save and clear CPENABLE
s16i a12, a11, tx_thread_cp_state + XT_CPENABLE
wsr a10, CPENABLE
#endif
// Save non-CP TIE state if any
#if XCHAL_EXTRA_SA_SIZE > 0
addi a10, a1, -XT_STK_FRMSZ + XT_STK_ALIGN_SZ // where to save
#if XCHAL_EXTRA_SA_ALIGN > 16
movi a12, -XCHAL_EXTRA_SA_ALIGN
and a10, a10, a12 // align dynamically >16 bytes
#endif
xchal_ncp_store a10, a11, a12, a13, a14
#endif
// If windowed ABI, a0-a7 was not saved by dispatch code.
// These don't go into the exception frame, but below the
// exception frame pointer.
#ifdef __XTENSA_WINDOWED_ABI__
addi a10, a1, -XT_STK_FRMSZ -32
s32i a0, a10, 0
s32i a2, a10, 8
s32i a3, a10, 12
s32i a4, a10, 16
s32i a5, a10, 20
s32i a6, a10, 24
s32i a7, a10, 28
#endif
.Lsched:
// When we get here, interrupts are disabled, a8 = &_tx_thread_current_ptr,
// a9 = _tx_thread_execute_ptr
movi a9, _tx_thread_execute_ptr // a9 <- &_tx_thread_execute_ptr (new)
l32i a9, a9, 0 // a9 <- _tx_thread_execute_ptr
s32i a9, a8, 0 // _tx_thread_current_ptr = _tx_thread_execute_ptr
beqz a9, _xt_idle // go idle if _tx_thread_execute_ptr == 0
l32i a10, a9, tx_thread_run_count
l32i a11, a9, tx_thread_time_slice
movi a12, _tx_timer_time_slice
addi a10, a10, 1
s32i a10, a9, tx_thread_run_count
s32i a11, a12, 0 // _tx_timer_time_slice = _tx_thread_current_ptr->tx_thread_time_slice
#ifdef TX_THREAD_SAFE_CLIB
#if XSHAL_CLIB == XTHAL_CLIB_NEWLIB
movi a10, _impure_ptr
#elif XSHAL_CLIB == XTHAL_CLIB_XCLIB
movi a10, _reent_ptr
#else
#error TX_THREAD_SAFE_CLIB defined with unsupported C library.
#endif
l32i a11, a9, tx_thread_clib_ptr
s32i a11, a10, 0
#endif
#if XCHAL_CP_NUM > 0
l16ui a10, a9, tx_thread_cp_state + XT_CPENABLE
wsr a10, CPENABLE // restore CPENABLE
#endif
l32i a1, a9, tx_thread_stack_ptr // SP = _tx_thread_execute_ptr->tx_thread_stack_ptr
#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
// Call the thread entry function to indicate the thread is executing.
// SP should be pointing to a safe region at this point.
#ifdef __XTENSA_CALL0_ABI__
call0 _tx_execution_thread_enter
#else
call8 _tx_execution_thread_enter
#endif
#endif
l32i a2, a9, tx_thread_solicited // a2 = solicited flag
beqz a2, 1f
// Solicited restore
addi a1, a1, XT_STK_FRMSZ // restore original SP
addi a2, a1, -XT_STK_XFRM_SZ
l32i a3, a2, XT_STK_PC // a3 = return PC
movi a2, PS_DI
xps a2, a2 // disable interrupts
movi a2, 0
wsr.ms a2 // restore normal DISPST
rsync
jx a3 // return to yield point
1:
// Preempt restore
#if XCHAL_EXTRA_SA_SIZE > 0
addi a10, a1, XT_STK_ALIGN_SZ // where to restore from
#if XCHAL_EXTRA_SA_ALIGN > 16
movi a12, -XCHAL_EXTRA_SA_ALIGN
and a10, a10, a12 // align dynamically >16 bytes
#endif
xchal_ncp_load a10, a11, a12, a13, a14
#endif
#ifdef __XTENSA_WINDOWED_ABI__
// Restore a0-a7 for windowed ABI
addi a8, a1, -32
l32i a0, a8, 0
l32i a2, a8, 8
l32i a3, a8, 12
l32i a4, a8, 16
l32i a5, a8, 20
l32i a6, a8, 24
l32i a7, a8, 28
#else
// For call0, dispatch exit code expects a15 = original SP
addi a15, a1, XT_STK_FRMSZ
#endif
addi a1, a1, XT_STK_FRMSZ // set up SP for dispatch exit
.Lnested:
// Return to the current saved context.
.endm
#endif /* __ASSEMBLER__ */
#endif /* XCHAL_HAVE_XEA3 */
#endif /* XTENSA_CONTEXT_H */

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/**************************************************************************/
/* Copyright (c) Cadence Design Systems, Inc. */
/* */
/* Permission is hereby granted, free of charge, to any person obtaining */
/* a copy of this software and associated documentation files (the */
/* "Software"), to deal in the Software without restriction, including */
/* without limitation the rights to use, copy, modify, merge, publish, */
/* distribute, sublicense, and/or sell copies of the Software, and to */
/* permit persons to whom the Software is furnished to do so, subject to */
/* the following conditions: */
/* */
/* The above copyright notice and this permission notice shall be */
/* included in all copies or substantial portions of the Software. */
/* */
/* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, */
/* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF */
/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. */
/* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY */
/* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, */
/* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE */
/* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
/**************************************************************************/
/**************************************************************************
RTOS-SPECIFIC INFORMATION FOR XTENSA RTOS ASSEMBLER SOURCES
This header is the primary glue between generic Xtensa RTOS support
sources and a specific RTOS port for Xtensa. It contains definitions
and macros for use primarily by Xtensa assembly coded source files.
Macros in this header map callouts from generic Xtensa files to specific
RTOS functions. It may also be included in C source files.
Xtensa RTOS ports support all RTOS-compatible configurations of the Xtensa
architecture, using the Xtensa hardware abstraction layer (HAL) to deal
with configuration specifics.
Should be included by all Xtensa generic and RTOS port-specific sources.
***************************************************************************/
#ifndef XTENSA_RTOS_H
#define XTENSA_RTOS_H
#ifdef __ASSEMBLER__
#include <xtensa/coreasm.h>
#else
#include <stdint.h>
#include <xtensa/config/core.h>
#endif
#include <xtensa/corebits.h>
#include <xtensa/config/system.h>
#include <xtensa/simcall.h>
/*
Include any RTOS specific definitions that are needed by this header.
*/
#include "tx_user.h"
/*
Name of RTOS (for messages).
*/
#define XT_RTOS_NAME ThreadX
/*
Check some Xtensa configuration requirements and report error if not met.
Error messages can be customize to the RTOS port.
*/
#if !XCHAL_HAVE_XEA2 && !XCHAL_HAVE_XEA3
#error "ThreadX/Xtensa requires Xtensa Exception Architecture v2 (XEA2) or higher."
#endif
/***************************************************************************
RTOS CALLOUT MACROS MAPPED TO RTOS PORT-SPECIFIC FUNCTIONS.
Define callout macros used in generic Xtensa code to interact with the RTOS.
The macros are simply the function names for use in calls from assembler code.
Some of these functions may call back to generic functions in xtensa_context.h .
***************************************************************************/
/*
Inform RTOS of entry into an interrupt handler that will affect it.
Allows RTOS to manage switch to any system stack and count nesting level.
Called after minimal context has been saved, with interrupts disabled.
RTOS port can call0 _xt_context_save to save the rest of the context.
May only be called from assembly code by the 'call0' instruction.
*/
// void XT_RTOS_INT_ENTER(void)
#define XT_RTOS_INT_ENTER _tx_thread_context_save
/*
Inform RTOS of completion of an interrupt handler, and give control to
RTOS to perform thread/task scheduling, switch back from any system stack
and restore the context, and return to the exit dispatcher saved in the
stack frame at XT_STK_EXIT. RTOS port can call0 _xt_context_restore
to save the context saved in XT_RTOS_INT_ENTER via _xt_context_save,
leaving only a minimal part of the context to be restored by the exit
dispatcher. This function does not return to the place it was called from.
May only be called from assembly code by the 'call0' instruction.
*/
// void XT_RTOS_INT_EXIT(void)
#define XT_RTOS_INT_EXIT _tx_thread_context_restore
/*
Convenience macros to disable and enable interrupts.
*/
#if XCHAL_HAVE_XEA3
#define XT_INTS_DISABLE(reg) movi reg, PS_DI; xps reg, reg
#define XT_INTS_ENABLE(reg) wsr reg, PS; rsync
#else
#define XT_INTS_DISABLE(reg) rsil reg, XCHAL_EXCM_LEVEL
#define XT_INTS_ENABLE(reg) wsr reg, PS; rsync
#endif
/*
Inform RTOS of the occurrence of a tick timer interrupt.
If RTOS has no tick timer, leave XT_RTOS_TIMER_INT undefined.
May be coded in or called from C or assembly, per ABI conventions.
*/
#ifndef TX_NO_TIMER
// void XT_RTOS_TIMER_INT(void)
#define XT_RTOS_TIMER_INT _tx_timer_interrupt
#endif
/*
Return in a15 the base address of the co-processor state save area for the
thread that triggered a co-processor exception, or 0 if no thread was running.
The state save area is structured as defined in xtensa_context.h and has size
XT_CP_SIZE. Co-processor instructions should only be used in thread code, never
in interrupt handlers or the RTOS kernel. May only be called from assembly code
and by the 'call0' instruction. A result of 0 indicates an unrecoverable error.
The implementation may use only a2-4, a15 (all other regs must be preserved).
*/
// void* XT_RTOS_CP_STATE(void)
#define XT_RTOS_CP_STATE _tx_thread_coproc_state
/***************************************************************************
HOOKS TO DYNAMICALLY INSTALL INTERRUPT AND EXCEPTION HANDLERS PER LEVEL.
This Xtensa RTOS port provides hooks for dynamically installing exception
and interrupt handlers to facilitate automated testing where each test
case can install its own handler for user exceptions and each interrupt
priority (level). This consists of an array of function pointers indexed
by interrupt priority, with index 0 being the user exception handler hook.
Each entry in the array is initially 0, and may be replaced by a function
pointer of type XT_INTEXC_HOOK. A handler may be uninstalled by installing 0.
The handler for low and medium priority obeys ABI conventions so may be coded
in C. For the exception handler, the cause is the contents of the EXCCAUSE
reg, and the result is -1 if handled, else the cause (still needs handling).
For interrupt handlers, the cause is a mask of pending enabled interrupts at
that level, and the result is the same mask with the bits for the handled
interrupts cleared (those not cleared still need handling). This allows a test
case to either pre-handle or override the default handling for the exception
or interrupt level (see xtensa_vectors.S).
High priority handlers (including NMI) must be coded in assembly, are always
called by 'call0' regardless of ABI, must preserve all registers except a0,
and must not use or modify the interrupted stack. The hook argument 'cause'
is not passed and the result is ignored, so as not to burden the caller with
saving and restoring a2 (it assumes only one interrupt per level - see the
discussion in high priority interrupts in xtensa_vectors.S). The handler
therefore should be coded to prototype 'void h(void)' even though it plugs
into an array of handlers of prototype 'uint32_t h(uint32_t)'.
To enable interrupt/exception hooks, compile the RTOS with '-DXT_INTEXC_HOOKS'.
***************************************************************************/
#define XT_INTEXC_HOOK_NUM (1 + XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI)
#ifndef __ASSEMBLER__
typedef uint32_t (*XT_INTEXC_HOOK)(uint32_t cause);
extern volatile XT_INTEXC_HOOK _xt_intexc_hooks[XT_INTEXC_HOOK_NUM];
#endif
/***************************************************************************
CONVENIENCE INCLUSIONS.
Ensures RTOS specific files need only include this one Xtensa-generic header.
These headers are included last so they can use the RTOS definitions above.
***************************************************************************/
#include "xtensa_context.h"
#ifdef XT_RTOS_TIMER_INT
#include "xtensa_timer.h"
#endif
#endif /* XTENSA_RTOS_H */

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/**************************************************************************/
/* Copyright (c) Cadence Design Systems, Inc. */
/* */
/* Permission is hereby granted, free of charge, to any person obtaining */
/* a copy of this software and associated documentation files (the */
/* "Software"), to deal in the Software without restriction, including */
/* without limitation the rights to use, copy, modify, merge, publish, */
/* distribute, sublicense, and/or sell copies of the Software, and to */
/* permit persons to whom the Software is furnished to do so, subject to */
/* the following conditions: */
/* */
/* The above copyright notice and this permission notice shall be */
/* included in all copies or substantial portions of the Software. */
/* */
/* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, */
/* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF */
/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. */
/* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY */
/* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, */
/* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE */
/* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
/**************************************************************************/
/**************************************************************************
XTENSA INFORMATION FOR RTOS TICK TIMER AND CLOCK FREQUENCY
This header contains timer related definitions and macros for use by
Xtensa RTOS source files. It includes and uses the Xtensa hardware
abstraction layer (HAL) to deal with config specifics.
If the RTOS has no timer interrupt, then there is no tick timer and the
clock frequency is irrelevant, so all of these macros are left undefined
and the Xtensa core configuration need not have a timer.
***************************************************************************/
#ifndef XTENSA_TIMER_H
#define XTENSA_TIMER_H
#include "xtensa_rtos.h" /* in case this wasn't included directly */
#ifdef XT_RTOS_TIMER_INT /* skip all this stuff if no timer int */
#ifdef __ASSEMBLER__
#include <xtensa/coreasm.h>
#else
#include <xtensa/tie/xt_timer.h>
#endif
#include <xtensa/corebits.h>
#include <xtensa/config/system.h>
#if XCHAL_HAVE_XEA3
/*
If the user has not specified a timer by defining XT_TIMER_INDEX, then
select timer 0.
*/
#ifndef XT_TIMER_INDEX
#define XT_TIMER_INDEX 0
#endif
#else /* XEA2 */
/*
Select timer to use for periodic tick, and determine its interrupt number
and priority. User may specify a timer by defining XT_TIMER_INDEX with -D,
in which case its validity is checked (it must exist in this core and must
not be on a high priority interrupt - an error will be reported in invalid).
Otherwise select the first low or medium priority interrupt timer available.
*/
#ifndef XT_TIMER_INDEX
#if XCHAL_TIMER3_INTERRUPT != XTHAL_TIMER_UNCONFIGURED
#if XCHAL_INT_LEVEL(XCHAL_TIMER3_INTERRUPT) <= XCHAL_EXCM_LEVEL
#undef XT_TIMER_INDEX
#define XT_TIMER_INDEX 3
#endif
#endif
#if XCHAL_TIMER2_INTERRUPT != XTHAL_TIMER_UNCONFIGURED
#if XCHAL_INT_LEVEL(XCHAL_TIMER2_INTERRUPT) <= XCHAL_EXCM_LEVEL
#undef XT_TIMER_INDEX
#define XT_TIMER_INDEX 2
#endif
#endif
#if XCHAL_TIMER1_INTERRUPT != XTHAL_TIMER_UNCONFIGURED
#if XCHAL_INT_LEVEL(XCHAL_TIMER1_INTERRUPT) <= XCHAL_EXCM_LEVEL
#undef XT_TIMER_INDEX
#define XT_TIMER_INDEX 1
#endif
#endif
#if XCHAL_TIMER0_INTERRUPT != XTHAL_TIMER_UNCONFIGURED
#if XCHAL_INT_LEVEL(XCHAL_TIMER0_INTERRUPT) <= XCHAL_EXCM_LEVEL
#undef XT_TIMER_INDEX
#define XT_TIMER_INDEX 0
#endif
#endif
#endif
#endif /* XCHAL_HAVE_XEA3 */
#ifndef XT_TIMER_INDEX
#error "There is no suitable timer in this Xtensa configuration."
#endif
#define XT_CCOMPARE (CCOMPARE + XT_TIMER_INDEX)
#define XT_TIMER_INTNUM XCHAL_TIMER_INTERRUPT(XT_TIMER_INDEX)
#define XT_TIMER_INTPRI XCHAL_INT_LEVEL(XT_TIMER_INTNUM)
#if XCHAL_HAVE_XEA2
#define XT_TIMER_INTEN (1 << XT_TIMER_INTNUM)
#endif
#if XT_TIMER_INDEX == 0
#define XT_WSR_CCOMPARE XT_WSR_CCOMPARE0
#elif XT_TIMER_INDEX == 1
#define XT_WSR_CCOMPARE XT_WSR_CCOMPARE1
#elif XT_TIMER_INDEX == 2
#define XT_WSR_CCOMPARE XT_WSR_CCOMPARE2
#endif
#if XT_TIMER_INTNUM == XTHAL_TIMER_UNCONFIGURED
#error "The timer selected by XT_TIMER_INDEX does not exist in this core."
#elif !XCHAL_HAVE_XEA3 && (XT_TIMER_INTPRI > XCHAL_EXCM_LEVEL)
#error "The timer interrupt cannot be high priority (use medium or low)."
#endif
/*
Default number of timer ticks per second. This can be redefined as required
either by editing here or by overriding from the command line during build.
*/
#ifndef XT_TICK_PER_SEC
#define XT_TICK_PER_SEC 100
#endif
/*
Set processor clock frequency and determine clock divisor for timer tick.
If using a supported board via the board-independent API defined in xtbsp.h,
this may be left undefined but XT_BOARD must be defined. The frequency and
tick divisor will be computed during run-time initialization.
*/
#ifndef XT_BOARD
#ifndef XT_CLOCK_FREQ
#define XT_CLOCK_FREQ 1000000
#endif
#define XT_TICK_DIVISOR (XT_CLOCK_FREQ / XT_TICK_PER_SEC)
#else
#ifndef __ASSEMBLER__
extern uint32_t xt_tick_divisor;
extern void xt_tick_divisor_init(void);
#endif
#define XT_TICK_DIVISOR xt_tick_divisor
#endif /* XT_BOARD */
#endif /* XT_RTOS_TIMER_INT */
#endif /* XTENSA_TIMER_H */