update to v6.1.3
This commit is contained in:
Scott Larson
157
ports/xtensa/xcc/inc/xtensa_timer.h
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157
ports/xtensa/xcc/inc/xtensa_timer.h
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/**************************************************************************/
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/* Copyright (c) Cadence Design Systems, Inc. */
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/* */
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/* Permission is hereby granted, free of charge, to any person obtaining */
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/* a copy of this software and associated documentation files (the */
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/* "Software"), to deal in the Software without restriction, including */
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/* without limitation the rights to use, copy, modify, merge, publish, */
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/* distribute, sublicense, and/or sell copies of the Software, and to */
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/* permit persons to whom the Software is furnished to do so, subject to */
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/* the following conditions: */
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/* */
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/* The above copyright notice and this permission notice shall be */
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/* included in all copies or substantial portions of the Software. */
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/* */
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/* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, */
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/* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF */
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/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. */
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/* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY */
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/* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, */
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/* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE */
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/* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
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/**************************************************************************/
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/**************************************************************************
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XTENSA INFORMATION FOR RTOS TICK TIMER AND CLOCK FREQUENCY
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This header contains timer related definitions and macros for use by
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Xtensa RTOS source files. It includes and uses the Xtensa hardware
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abstraction layer (HAL) to deal with config specifics.
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If the RTOS has no timer interrupt, then there is no tick timer and the
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clock frequency is irrelevant, so all of these macros are left undefined
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and the Xtensa core configuration need not have a timer.
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***************************************************************************/
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#ifndef XTENSA_TIMER_H
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#define XTENSA_TIMER_H
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#include "xtensa_rtos.h" /* in case this wasn't included directly */
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#ifdef XT_RTOS_TIMER_INT /* skip all this stuff if no timer int */
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#ifdef __ASSEMBLER__
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#include <xtensa/coreasm.h>
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#else
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#include <xtensa/tie/xt_timer.h>
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#endif
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#include <xtensa/corebits.h>
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#include <xtensa/config/system.h>
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#if XCHAL_HAVE_XEA3
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/*
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If the user has not specified a timer by defining XT_TIMER_INDEX, then
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select timer 0.
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*/
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#ifndef XT_TIMER_INDEX
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#define XT_TIMER_INDEX 0
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#endif
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#else /* XEA2 */
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/*
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Select timer to use for periodic tick, and determine its interrupt number
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and priority. User may specify a timer by defining XT_TIMER_INDEX with -D,
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in which case its validity is checked (it must exist in this core and must
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not be on a high priority interrupt - an error will be reported in invalid).
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Otherwise select the first low or medium priority interrupt timer available.
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*/
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#ifndef XT_TIMER_INDEX
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#if XCHAL_TIMER3_INTERRUPT != XTHAL_TIMER_UNCONFIGURED
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#if XCHAL_INT_LEVEL(XCHAL_TIMER3_INTERRUPT) <= XCHAL_EXCM_LEVEL
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#undef XT_TIMER_INDEX
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#define XT_TIMER_INDEX 3
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#endif
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#endif
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#if XCHAL_TIMER2_INTERRUPT != XTHAL_TIMER_UNCONFIGURED
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#if XCHAL_INT_LEVEL(XCHAL_TIMER2_INTERRUPT) <= XCHAL_EXCM_LEVEL
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#undef XT_TIMER_INDEX
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#define XT_TIMER_INDEX 2
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#endif
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#endif
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#if XCHAL_TIMER1_INTERRUPT != XTHAL_TIMER_UNCONFIGURED
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#if XCHAL_INT_LEVEL(XCHAL_TIMER1_INTERRUPT) <= XCHAL_EXCM_LEVEL
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#undef XT_TIMER_INDEX
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#define XT_TIMER_INDEX 1
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#endif
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#endif
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#if XCHAL_TIMER0_INTERRUPT != XTHAL_TIMER_UNCONFIGURED
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#if XCHAL_INT_LEVEL(XCHAL_TIMER0_INTERRUPT) <= XCHAL_EXCM_LEVEL
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#undef XT_TIMER_INDEX
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#define XT_TIMER_INDEX 0
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#endif
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#endif
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#endif
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#endif /* XCHAL_HAVE_XEA3 */
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#ifndef XT_TIMER_INDEX
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#error "There is no suitable timer in this Xtensa configuration."
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#endif
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#define XT_CCOMPARE (CCOMPARE + XT_TIMER_INDEX)
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#define XT_TIMER_INTNUM XCHAL_TIMER_INTERRUPT(XT_TIMER_INDEX)
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#define XT_TIMER_INTPRI XCHAL_INT_LEVEL(XT_TIMER_INTNUM)
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#if XCHAL_HAVE_XEA2
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#define XT_TIMER_INTEN (1 << XT_TIMER_INTNUM)
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#endif
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#if XT_TIMER_INDEX == 0
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#define XT_WSR_CCOMPARE XT_WSR_CCOMPARE0
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#elif XT_TIMER_INDEX == 1
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#define XT_WSR_CCOMPARE XT_WSR_CCOMPARE1
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#elif XT_TIMER_INDEX == 2
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#define XT_WSR_CCOMPARE XT_WSR_CCOMPARE2
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#endif
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#if XT_TIMER_INTNUM == XTHAL_TIMER_UNCONFIGURED
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#error "The timer selected by XT_TIMER_INDEX does not exist in this core."
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#elif !XCHAL_HAVE_XEA3 && (XT_TIMER_INTPRI > XCHAL_EXCM_LEVEL)
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#error "The timer interrupt cannot be high priority (use medium or low)."
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#endif
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/*
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Default number of timer ticks per second. This can be redefined as required
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either by editing here or by overriding from the command line during build.
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*/
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#ifndef XT_TICK_PER_SEC
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#define XT_TICK_PER_SEC 100
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#endif
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/*
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Set processor clock frequency and determine clock divisor for timer tick.
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If using a supported board via the board-independent API defined in xtbsp.h,
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this may be left undefined but XT_BOARD must be defined. The frequency and
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tick divisor will be computed during run-time initialization.
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*/
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#ifndef XT_BOARD
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#ifndef XT_CLOCK_FREQ
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#define XT_CLOCK_FREQ 1000000
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#endif
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#define XT_TICK_DIVISOR (XT_CLOCK_FREQ / XT_TICK_PER_SEC)
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#else
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#ifndef __ASSEMBLER__
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extern uint32_t xt_tick_divisor;
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extern void xt_tick_divisor_init(void);
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#endif
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#define XT_TICK_DIVISOR xt_tick_divisor
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#endif /* XT_BOARD */
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#endif /* XT_RTOS_TIMER_INT */
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#endif /* XTENSA_TIMER_H */
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