update to v6.1.3
This commit is contained in:
Scott Larson
277
ports/xtensa/xcc/src/tx_timer_interrupt.S
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277
ports/xtensa/xcc/src/tx_timer_interrupt.S
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/**************************************************************************/
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/* */
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/* Copyright (c) Microsoft Corporation. All rights reserved. */
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/* */
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/* This software is licensed under the Microsoft Software License */
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/* Terms for Microsoft Azure RTOS. Full text of the license can be */
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/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
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/* and in the root directory of this software. */
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/* */
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/**************************************************************************/
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/**************************************************************************/
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/* Copyright (c) Cadence Design Systems, Inc. */
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/* */
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/* Permission is hereby granted, free of charge, to any person obtaining */
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/* a copy of this software and associated documentation files (the */
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/* "Software"), to deal in the Software without restriction, including */
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/* without limitation the rights to use, copy, modify, merge, publish, */
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/* distribute, sublicense, and/or sell copies of the Software, and to */
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/* permit persons to whom the Software is furnished to do so, subject to */
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/* the following conditions: */
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/* */
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/* The above copyright notice and this permission notice shall be */
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/* included in all copies or substantial portions of the Software. */
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/* */
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/* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, */
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/* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF */
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/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. */
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/* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY */
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/* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, */
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/* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE */
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/* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
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/**************************************************************************/
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/**************************************************************************/
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/**************************************************************************/
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/** */
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/** ThreadX Component */
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/** */
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/** Timer */
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/** */
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/**************************************************************************/
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/**************************************************************************/
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#include "xtensa_rtos.h"
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#include "tx_api_asm.h"
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#ifndef TX_NO_TIMER
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.text
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/**************************************************************************/
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/* */
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/* DESCRIPTION */
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/* */
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/* This function processes the hardware timer interrupt. This */
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/* processing includes incrementing the system clock and checking for */
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/* time slice and/or timer expiration. If either is found, the */
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/* interrupt context save/restore functions are called along with the */
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/* expiration functions. */
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/* */
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/* RELEASE HISTORY */
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/* */
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/* DATE NAME DESCRIPTION */
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/* */
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/* 12-31-2020 Cadence Design Systems Initial Version 6.1.3 */
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/* */
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/**************************************************************************/
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// VOID _tx_timer_interrupt(VOID)
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// {
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.globl _tx_timer_interrupt
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.type _tx_timer_interrupt,@function
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.align 4
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_tx_timer_interrupt:
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#ifdef __XTENSA_CALL0_ABI__
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/* Define local variable spill offsets in stack frame for Call0 ABI. */
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#define __tx_timer_interrupt_a0 0 /* ENTRY()/RET() saves/restores */
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#define __tx_timer_interrupt_a2 4 /* preserve a2 */
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#define __tx_timer_interrupt_a3 8 /* preserve a3 */
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#endif
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ENTRY(16)
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.globl tx_timer_user_isr
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.weak tx_timer_user_isr
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movi a2, tx_timer_user_isr
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beqz a2, 1f
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#ifdef __XTENSA_CALL0_ABI__
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callx0 a2
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#else
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callx8 a2
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#endif
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1:
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/*
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Xtensa timers work by comparing a cycle counter with a preset value.
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Once the match occurs an interrupt is generated, and the handler has
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to set a new cycle count into the comparator. To avoid clock drift
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due to interrupt latency, the new cycle count is computed from the old,
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not the time the interrupt was serviced. However if a timer interrupt
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is ever serviced more than one tick late, it is necessary to process
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multiple ticks until the new cycle count is in the future, otherwise
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the next timer interrupt would not occur until after the cycle counter
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had wrapped (2^32 cycles later).
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do {
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ticks++;
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old_ccompare = read_ccompare_i();
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write_ccompare_i( old_ccompare + divisor );
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service one tick;
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diff = read_ccount() - old_ccompare;
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} while ( diff > divisor );
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*/
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.L_tx_timer_catchup:
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/* Increment the system clock. */
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// _tx_timer_system_clock++;
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movi a2, _tx_timer_system_clock /* a2 = &_tx_timer_system_clock */
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l32i a3, a2, 0 /* a3 = _tx_timer_system_clock++ */
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addi a3, a3, 1
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s32i a3, a2, 0
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/* Update the timer comparator for the next tick. */
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#ifdef XT_CLOCK_FREQ
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movi a2, XT_TICK_DIVISOR /* a2 = comparator increment */
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#else
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movi a3, _xt_tick_divisor
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l32i a2, a3, 0 /* a2 = comparator increment */
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#endif
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rsr a3, XT_CCOMPARE /* a3 = old comparator value */
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add a4, a3, a2 /* a4 = new comparator value */
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wsr a4, XT_CCOMPARE /* update comp. and clear interrupt */
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esync
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/* Test for time-slice expiration. */
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// if (_tx_timer_time_slice)
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// {
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movi a4, _tx_timer_time_slice /* a4 = &_tx_timer_time_slice */
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l32i a5, a4, 0 /* a5 = _tx_timer_time_slice */
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beqz a5, .L_tx_timer_no_time_slice
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/* Decrement the time_slice. */
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// _tx_timer_time_slice--;
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addi a5, a5, -1
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s32i a5, a4, 0
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/* Check for expiration. */
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// if (_tx_timer_time_slice == 0)
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bnez a5, .L_tx_timer_no_time_slice
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/* Set the time-slice expired flag. */
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// _tx_timer_expired_time_slice = TX_TRUE;
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movi a4, _tx_timer_expired_time_slice
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movi a5, TX_TRUE
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s32i a5, a4, 0
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// }
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.L_tx_timer_no_time_slice:
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/* Test for timer expiration. */
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// if (*_tx_timer_current_ptr)
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// {
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movi a4, _tx_timer_current_ptr /* a4 = &_tx_timer_current_ptr */
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l32i a5, a4, 0 /* a5 = _tx_timer_current_ptr */
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l32i a6, a5, 0 /* a6 = *_tx_timer_current_ptr */
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beqz a6, .L_tx_timer_no_timer
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/* Set expiration flag. */
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// _tx_timer_expired = TX_TRUE;
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movi a6, _tx_timer_expired
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movi a7, TX_TRUE
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s32i a7, a6, 0
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j .L_tx_timer_done
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// }
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// else
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// {
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.L_tx_timer_no_timer:
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/* No timer expired, increment the timer pointer. */
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// _tx_timer_current_ptr++;
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/* Check for wrap-around. */
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// if (_tx_timer_current_ptr == _tx_timer_list_end)
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movi a6, _tx_timer_list_end
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l32i a6, a6, 0 /* a6 = _tx_timer_list_end */
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addi a5, a5, 4 /* a5 = ++_tx_timer_current_ptr */
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bne a5, a6, .L_tx_timer_skip_wrap
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/* Wrap to beginning of list. */
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// _tx_timer_current_ptr = _tx_timer_list_start;
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movi a6, _tx_timer_list_start
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l32i a5, a6, 0 /* a5 = _tx_timer_list_start */
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.L_tx_timer_skip_wrap:
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s32i a5, a4, 0 /* _tx_timer_current_ptr = a5 */
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// }
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.L_tx_timer_done:
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/* See if anything has expired. */
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// if ((_tx_timer_expired_time_slice) || (_tx_timer_expired))
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// {
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#ifdef __XTENSA_CALL0_ABI__
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/* Preserve a2 and a3 across calls. */
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s32i a2, sp, __tx_timer_interrupt_a2
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s32i a3, sp, __tx_timer_interrupt_a3
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#endif
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/* Did a timer expire? */
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// if (_tx_timer_expired)
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// {
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movi a4, _tx_timer_expired
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l32i a5, a4, 0
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beqz a5, .L_tx_timer_dont_activate
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/* Call the timer expiration processing. */
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// _tx_timer_expiration_process();
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#ifdef __XTENSA_CALL0_ABI__
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call0 _tx_timer_expiration_process
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#else
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call8 _tx_timer_expiration_process
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#endif
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// }
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.L_tx_timer_dont_activate:
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/* Did time slice expire? */
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// if (_tx_timer_expired_time_slice)
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// {
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movi a4, _tx_timer_expired_time_slice
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l32i a5, a4, 0
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beqz a5, .L_tx_timer_not_ts_expiration
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/* Time slice interrupted thread. */
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// _tx_thread_time_slice();
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#ifdef __XTENSA_CALL0_ABI__
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call0 _tx_thread_time_slice
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#else
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call8 _tx_thread_time_slice
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#endif
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// }
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.L_tx_timer_not_ts_expiration:
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#ifdef __XTENSA_CALL0_ABI__
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/* Restore a2 and a3. */
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l32i a2, sp, __tx_timer_interrupt_a2
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l32i a3, sp, __tx_timer_interrupt_a3
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#endif
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// }
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.Ln_tx_timer_nothing_expired:
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/* Check if we need to process more ticks to catch up. */
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esync /* ensure comparator update complete */
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rsr a4, CCOUNT /* a4 = cycle count */
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sub a4, a4, a3 /* diff = ccount - old comparator */
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blt a2, a4, .L_tx_timer_catchup /* repeat while diff > divisor */
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RET(16)
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// }
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#endif /* TX_NO_TIMER */
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