update to v6.1.3
This commit is contained in:
Scott Larson
156
ports/xtensa/xcc/src/xtensa_intr_asm.S
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156
ports/xtensa/xcc/src/xtensa_intr_asm.S
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/**************************************************************************/
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/* Copyright (c) Cadence Design Systems, Inc. */
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/* */
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/* Permission is hereby granted, free of charge, to any person obtaining */
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/* a copy of this software and associated documentation files (the */
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/* "Software"), to deal in the Software without restriction, including */
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/* without limitation the rights to use, copy, modify, merge, publish, */
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/* distribute, sublicense, and/or sell copies of the Software, and to */
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/* permit persons to whom the Software is furnished to do so, subject to */
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/* the following conditions: */
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/* */
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/* The above copyright notice and this permission notice shall be */
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/* included in all copies or substantial portions of the Software. */
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/* */
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/* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, */
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/* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF */
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/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. */
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/* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY */
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/* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, */
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/* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE */
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/* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
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/**************************************************************************/
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/**************************************************************************/
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/* */
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/* DESCRIPTION */
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/* */
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/* Xtensa interrupt handling data and assembly routines. */
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/* Also see xtensa_intr.c. */
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/* */
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/* RELEASE HISTORY */
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/* */
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/* DATE NAME DESCRIPTION */
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/* */
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/* 12-31-2020 Cadence Design Systems Initial Version 6.1.3 */
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/* */
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/**************************************************************************/
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#include <xtensa/hal.h>
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#include <xtensa/config/core.h>
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#include "tx_port.h"
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#include "xtensa_context.h"
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#if XCHAL_HAVE_INTERRUPTS
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/*
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-------------------------------------------------------------------------------
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INTENABLE virtualization information.
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-------------------------------------------------------------------------------
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*/
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#if XCHAL_HAVE_XEA2
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.data
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.global _xt_intdata
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.align 8
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_xt_intdata:
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.global _xt_intenable
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.type _xt_intenable,@object
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.size _xt_intenable,4
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.global _xt_vpri_mask
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.type _xt_vpri_mask,@object
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.size _xt_vpri_mask,4
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_xt_intenable: .word 0 /* Virtual INTENABLE */
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_xt_vpri_mask: .word 0xFFFFFFFF /* Virtual priority mask */
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#endif
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/*
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-------------------------------------------------------------------------------
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System interrupt stack.
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-------------------------------------------------------------------------------
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*/
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#if (XCHAL_HAVE_XEA2 || XCHAL_HAVE_ISB)
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.data
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#else
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.section .intr.top, "aw"
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#endif
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.global _xt_interrupt_stack
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.global _xt_interrupt_stack_top
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.align 16
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_xt_interrupt_stack:
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.space TX_SYSTEM_STACK_SIZE
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_xt_interrupt_stack_top:
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/*
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-------------------------------------------------------------------------------
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Table of C-callable interrupt handlers for each interrupt. For XEA2 configs,
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not all slots can be filled, because interrupts at level > EXCM_LEVEL will
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not be dispatched to a C handler by default.
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-------------------------------------------------------------------------------
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*/
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#if (XCHAL_HAVE_XEA2 || XCHAL_HAVE_ISB)
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.data
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#else
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.section .intr.data, "aw"
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#endif
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.global _xt_interrupt_table
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.align 16
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_xt_interrupt_table:
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/*
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-------------------------------------------------------------------------------
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If using the interrupt wrapper, make the first entry in the interrupt table
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point to the wrapper (XEA3) or leave it empty (XEA2).
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-------------------------------------------------------------------------------
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*/
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#if XCHAL_HAVE_XEA3
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.word xt_interrupt_wrapper
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.word 0
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#elif XT_USE_INT_WRAPPER
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.word 0
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.word 0
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#endif
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.set i, 0
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.rept XCHAL_NUM_INTERRUPTS
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.word xt_unhandled_interrupt /* handler address */
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.word i /* handler arg (default: intnum) */
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.set i, i+1
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.endr
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#endif /* XCHAL_HAVE_INTERRUPTS */
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#if XCHAL_HAVE_EXCEPTIONS
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/*
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-------------------------------------------------------------------------------
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Table of C-callable exception handlers for each exception. Note that not all
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slots will be active, because some exceptions (e.g. coprocessor exceptions)
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are always handled by the OS and cannot be hooked by user handlers.
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-------------------------------------------------------------------------------
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*/
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.data
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.global _xt_exception_table
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.align 4
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_xt_exception_table:
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.rept XCHAL_EXCCAUSE_NUM
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.word xt_unhandled_exception /* handler address */
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.endr
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#endif
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