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Release 6.1.7

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This commit is contained in:
Bo Chen
2021-06-02 06:45:05 +00:00
parent d759e6bb9e
commit f5056f4923
1269 changed files with 57325 additions and 55178 deletions
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32
ports/cortex_m23/iar/inc/tx_port.h
View File

@@ -26,7 +26,7 @@
/* PORT SPECIFIC C INFORMATION RELEASE */
/* */
/* tx_port.h Cortex-M23/IAR */
/* 6.1.5 */
/* 6.1.7 */
/* */
/* AUTHOR */
/* */
@@ -51,6 +51,10 @@
/* 03-02-2021 Scott Larson Modified comment(s), added */
/* ULONG64_DEFINED, */
/* resulting in version 6.1.5 */
/* 06-02-2021 Yuxin Zhou Modified comment(s), added */
/* conditional compilation */
/* for ARMv8-M (Cortex M23/33) */
/* resulting in version 6.1.7 */
/* */
/**************************************************************************/
@@ -97,6 +101,12 @@ UINT _txe_thread_secure_stack_free(struct TX_THREAD_STRUCT *thread_ptr);
UINT _tx_thread_secure_stack_allocate(struct TX_THREAD_STRUCT *tx_thread, ULONG stack_size);
UINT _tx_thread_secure_stack_free(struct TX_THREAD_STRUCT *tx_thread);
/* This port overrides tx_thread_stack_error_notify with an architecture specific version */
#define TX_PORT_THREAD_STACK_ERROR_NOTIFY
/* This port overrides tx_thread_stack_error_handler with an architecture specific version */
#define TX_PORT_THREAD_STACK_ERROR_HANDLER
/* This hardware has stack checking that we take advantage of - do NOT define. */
#ifdef TX_ENABLE_STACK_CHECKING
#error "Do not define TX_ENABLE_STACK_CHECKING"
@@ -258,13 +268,7 @@ ULONG _tx_misra_time_stamp_get(VOID);
#endif
#ifndef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
#define TX_THREAD_EXTENSION_3
#else
#define TX_THREAD_EXTENSION_3 unsigned long long tx_thread_execution_time_total; \
unsigned long long tx_thread_execution_time_last_start;
#endif
/* Define the port extensions of the remaining ThreadX objects. */
@@ -385,7 +389,7 @@ extern void _tx_thread_secure_stack_initialize(void);
#ifndef TX_DISABLE_INLINE
#define TX_LOWEST_SET_BIT_CALCULATE(m, b) (b) = (UINT)__CLZ(__RBIT((m)));
#define TX_LOWEST_SET_BIT_CALCULATE(m, b) (b) = (UINT) __CLZ(__RBIT((m)));
#endif
@@ -433,21 +437,11 @@ __istate_t interrupt_save;
#endif
/* Define the interrupt lockout macros for each ThreadX object. */
#define TX_BLOCK_POOL_DISABLE TX_DISABLE
#define TX_BYTE_POOL_DISABLE TX_DISABLE
#define TX_EVENT_FLAGS_GROUP_DISABLE TX_DISABLE
#define TX_MUTEX_DISABLE TX_DISABLE
#define TX_QUEUE_DISABLE TX_DISABLE
#define TX_SEMAPHORE_DISABLE TX_DISABLE
/* Define the version ID of ThreadX. This may be utilized by the application. */
#ifdef TX_THREAD_INIT
CHAR _tx_version_id[] =
"Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M23/IAR Version 6.1 *";
"Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M23/IAR Version 6.1.7 *";
#else
#ifdef TX_MISRA_ENABLE
extern CHAR _tx_version_id[100];

5
ports/cortex_m23/iar/readme_threadx.txt
View File

@@ -136,6 +136,11 @@ For generic code revision information, please refer to the readme_threadx_generi
file, which is included in your distribution. The following details the revision
information associated with this specific port of ThreadX:
06-02-2021 Release 6.1.7 changes:
tx_thread_secure_stack_initialize.s New file
tx_thread_schedule.s Added secure stack initialize to SVC hander
tx_thread_secure_stack.c Fixed stack pointer save, initialize in handler mode
04-02-2021 Release 6.1.6 changes:
tx_port.h Updated macro definition
tx_thread_schedule.s Added low power support

11
ports/cortex_m23/iar/src/tx_thread_context_restore.s
View File

@@ -64,9 +64,14 @@
;{
PUBLIC _tx_thread_context_restore
_tx_thread_context_restore:
;
; /* Return to interrupt processing. */
;
#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE))
/* Call the ISR exit function to indicate an ISR is complete. */
PUSH {r0, lr} // Save return address
BL _tx_execution_isr_exit // Call the ISR exit function
POP {r0, lr} // Recover return address
#endif
BX lr
;}
END

13
ports/cortex_m23/iar/src/tx_thread_context_save.s
View File

@@ -64,9 +64,16 @@
;{
PUBLIC _tx_thread_context_save
_tx_thread_context_save:
;
; /* Return to interrupt processing. */
;
#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE))
/* Call the ISR enter function to indicate an ISR is starting. */
PUSH {r0, lr} // Save return address
BL _tx_execution_isr_enter // Call the ISR enter function
POP {r0, lr} // Recover return address
#endif
/* Context is already saved - just return. */
BX lr
;}
END

545
ports/cortex_m23/iar/src/tx_thread_schedule.s
View File

@@ -1,26 +1,25 @@
;/**************************************************************************/
;/* */
;/* Copyright (c) Microsoft Corporation. All rights reserved. */
;/* */
;/* This software is licensed under the Microsoft Software License */
;/* Terms for Microsoft Azure RTOS. Full text of the license can be */
;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
;/* and in the root directory of this software. */
;/* */
;/**************************************************************************/
;
;
;/**************************************************************************/
;/**************************************************************************/
;/** */
;/** ThreadX Component */
;/** */
;/** Thread */
;/** */
;/**************************************************************************/
;/**************************************************************************/
;
;
/**************************************************************************/
/* */
/* Copyright (c) Microsoft Corporation. All rights reserved. */
/* */
/* This software is licensed under the Microsoft Software License */
/* Terms for Microsoft Azure RTOS. Full text of the license can be */
/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
/* and in the root directory of this software. */
/* */
/**************************************************************************/
/**************************************************************************/
/**************************************************************************/
/** */
/** ThreadX Component */
/** */
/** Thread */
/** */
/**************************************************************************/
/**************************************************************************/
EXTERN _tx_thread_current_ptr
EXTERN _tx_thread_execute_ptr
EXTERN _tx_timer_time_slice
@@ -32,326 +31,320 @@
EXTERN _tx_thread_secure_stack_context_save
EXTERN _tx_thread_secure_mode_stack_allocate
EXTERN _tx_thread_secure_mode_stack_free
EXTERN _tx_thread_secure_mode_stack_initialize
#ifdef TX_LOW_POWER
EXTERN tx_low_power_enter
EXTERN tx_low_power_exit
#endif
;
;
SECTION `.text`:CODE:NOROOT(2)
THUMB
;/**************************************************************************/
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_schedule Cortex-M23/IAR */
;/* 6.1.6 */
;/* AUTHOR */
;/* */
;/* Scott Larson, Microsoft Corporation */
;/* */
;/* DESCRIPTION */
;/* */
;/* This function waits for a thread control block pointer to appear in */
;/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */
;/* in the variable, the corresponding thread is resumed. */
;/* */
;/* INPUT */
;/* */
;/* None */
;/* */
;/* OUTPUT */
;/* */
;/* None */
;/* */
;/* CALLS */
;/* */
;/* None */
;/* */
;/* CALLED BY */
;/* */
;/* _tx_initialize_kernel_enter ThreadX entry function */
;/* _tx_thread_system_return Return to system from thread */
;/* */
;/* RELEASE HISTORY */
;/* */
;/* DATE NAME DESCRIPTION */
;/* */
;/* 09-30-2020 Scott Larson Initial Version 6.1 */
;/* 04-02-2021 Scott Larson Modified comment(s), added */
;/* low power code, */
;/* resulting in version 6.1.6 */
;/* */
;/**************************************************************************/
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_schedule Cortex-M23/IAR */
/* 6.1.7 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
/* */
/* DESCRIPTION */
/* */
/* This function waits for a thread control block pointer to appear in */
/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */
/* in the variable, the corresponding thread is resumed. */
/* */
/* INPUT */
/* */
/* None */
/* */
/* OUTPUT */
/* */
/* None */
/* */
/* CALLS */
/* */
/* None */
/* */
/* CALLED BY */
/* */
/* _tx_initialize_kernel_enter ThreadX entry function */
/* _tx_thread_system_return Return to system from thread */
/* */
/* RELEASE HISTORY */
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* 04-02-2021 Scott Larson Modified comment(s), added */
/* low power code, */
/* resulting in version 6.1.6 */
/* 06-02-2021 Scott Larson Added secure stack initialize */
/* in SVC handler, */
/* resulting in version 6.1.7 */
/* */
/**************************************************************************/
;VOID _tx_thread_schedule(VOID)
;{
PUBLIC _tx_thread_schedule
_tx_thread_schedule:
;
; /* This function should only ever be called on Cortex-M
; from the first schedule request. Subsequent scheduling occurs
; from the PendSV handling routines below. */
;
; /* Clear the preempt-disable flag to enable rescheduling after initialization on Cortex-M targets. */
;
MOV r0, #0 ; Build value for TX_FALSE
LDR r2, =_tx_thread_preempt_disable ; Build address of preempt disable flag
STR r0, [r2, #0] ; Clear preempt disable flag
;
; /* Enable interrupts */
;
/* This function should only ever be called on Cortex-M
from the first schedule request. Subsequent scheduling occurs
from the PendSV handling routine below. */
/* Clear the preempt-disable flag to enable rescheduling after initialization on Cortex-M targets. */
MOV r0, #0 // Build value for TX_FALSE
LDR r2, =_tx_thread_preempt_disable // Build address of preempt disable flag
STR r0, [r2, #0] // Clear preempt disable flag
/* Enable interrupts */
CPSIE i
;
; /* Enter the scheduler for the first time. */
;
LDR r0, =0x10000000 ; Load PENDSVSET bit
LDR r1, =0xE000ED04 ; Load ICSR address
STR r0, [r1] ; Set PENDSVBIT in ICSR
DSB ; Complete all memory accesses
ISB ; Flush pipeline
;
; /* Wait here for the PendSV to take place. */
;
/* Enter the scheduler for the first time. */
LDR r0, =0x10000000 // Load PENDSVSET bit
LDR r1, =0xE000ED04 // Load ICSR address
STR r0, [r1] // Set PENDSVBIT in ICSR
DSB // Complete all memory accesses
ISB // Flush pipeline
/* Wait here for the PendSV to take place. */
__tx_wait_here:
B __tx_wait_here ; Wait for the PendSV to happen
;}
;
; /* Generic context switching PendSV handler. */
;
B __tx_wait_here // Wait for the PendSV to happen
// }
/* Generic context switching PendSV handler. */
PUBLIC PendSV_Handler
PendSV_Handler:
;
; /* Get current thread value and new thread pointer. */
;
__tx_ts_handler:
#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
;
; /* Call the thread exit function to indicate the thread is no longer executing. */
;
CPSID i ; Disable interrupts
PUSH {r0, lr} ; Save LR (and r0 just for alignment)
BL _tx_execution_thread_exit ; Call the thread exit function
POP {r0, r1} ; Recover LR
MOV lr, r1 ;
CPSIE i ; Enable interrupts
#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE))
/* Call the thread exit function to indicate the thread is no longer executing. */
CPSID i // Disable interrupts
PUSH {r0, lr} // Save LR (and r0 just for alignment)
BL _tx_execution_thread_exit // Call the thread exit function
POP {r0, r1} // Recover LR
MOV lr, r1 //
CPSIE i // Enable interrupts
#endif
MOV32 r0, _tx_thread_current_ptr ; Build current thread pointer address
MOV32 r2, _tx_thread_execute_ptr ; Build execute thread pointer address
MOV r3, #0 ; Build NULL value
LDR r1, [r0] ; Pickup current thread pointer
;
; /* Determine if there is a current thread to finish preserving. */
;
CBZ r1, __tx_ts_new ; If NULL, skip preservation
;
; /* Recover PSP and preserve current thread context. */
;
STR r3, [r0] ; Set _tx_thread_current_ptr to NULL
MRS r3, PSP ; Pickup PSP pointer (thread's stack pointer)
SUBS r3, r3, #16 ; Allocate stack space
STM r3!, {r4-r7} ; Save its remaining registers (M3 Instruction: STMDB r12!, {r4-r11})
MOV r4, r8 ;
MOV r5, r9 ;
MOV r6, r10 ;
MOV r7, r11 ;
SUBS r3, r3, #32 ; Allocate stack space
STM r3!, {r4-r7} ;
SUBS r3, r3, #20 ; Allocate stack space
MOV r5, lr ;
STR r5, [r3] ; Save LR on the stack
STR r3, [r1, #8] ; Save its stack pointer
MOV32 r0, _tx_thread_current_ptr // Build current thread pointer address
MOV32 r2, _tx_thread_execute_ptr // Build execute thread pointer address
MOV r3, #0 // Build NULL value
LDR r1, [r0] // Pickup current thread pointer
/* Determine if there is a current thread to finish preserving. */
CBZ r1, __tx_ts_new // If NULL, skip preservation
/* Recover PSP and preserve current thread context. */
STR r3, [r0] // Set _tx_thread_current_ptr to NULL
MRS r3, PSP // Pickup PSP pointer (thread's stack pointer)
SUBS r3, r3, #16 // Allocate stack space
STM r3!, {r4-r7} // Save its remaining registers (M3 Instruction: STMDB r12!, {r4-r11})
MOV r4, r8 //
MOV r5, r9 //
MOV r6, r10 //
MOV r7, r11 //
SUBS r3, r3, #32 // Allocate stack space
STM r3!, {r4-r7} //
SUBS r3, r3, #20 // Allocate stack space
MOV r5, lr //
STR r5, [r3] // Save LR on the stack
STR r3, [r1, #8] // Save the thread stack pointer
#if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE)
; Save secure context
LDR r5, =0x90 ; Secure stack index offset
LDR r5, [r1, r5] ; Load secure stack index
CBZ r5, _skip_secure_save ; Skip save if there is no secure context
PUSH {r0, r1, r2, r3} ; Save scratch registers
MOV r0, r1 ; Move thread ptr to r0
BL _tx_thread_secure_stack_context_save ; Save secure stack
POP {r0, r1, r2, r3} ; Restore secure registers
#if (!defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE))
// Save secure context
LDR r5, =0x90 // Secure stack index offset
LDR r5, [r1, r5] // Load secure stack index
CBZ r5, _skip_secure_save // Skip save if there is no secure context
PUSH {r0, r1, r2, r3} // Save scratch registers
MOV r0, r1 // Move thread ptr to r0
BL _tx_thread_secure_stack_context_save // Save secure stack
POP {r0, r1, r2, r3} // Restore secure registers
_skip_secure_save:
#endif
;
; /* Determine if time-slice is active. If it isn't, skip time handling processing. */
;
LDR r4, =_tx_timer_time_slice ; Build address of time-slice variable
LDR r5, [r4] ; Pickup current time-slice
CBZ r5, __tx_ts_new ; If not active, skip processing
;
; /* Time-slice is active, save the current thread's time-slice and clear the global time-slice variable. */
;
STR r5, [r1, #24] ; Save current time-slice
;
; /* Clear the global time-slice. */
;
MOVS r5, #0 ; Build clear value
STR r5, [r4] ; Clear time-slice
;
; /* Executing thread is now completely preserved!!! */
;
__tx_ts_new:
;
; /* Now we are looking for a new thread to execute! */
;
CPSID i ; Disable interrupts
LDR r1, [r2] ; Is there another thread ready to execute?
CBZ r1, __tx_ts_wait ; No, skip to the wait processing
;
; /* Yes, another thread is ready for else, make the current thread the new thread. */
;
STR r1, [r0] ; Setup the current thread pointer to the new thread
CPSIE i ; Enable interrupts
;
; /* Increment the thread run count. */
;
__tx_ts_restore:
LDR r7, [r1, #4] ; Pickup the current thread run count
MOV32 r4, _tx_timer_time_slice ; Build address of time-slice variable
LDR r5, [r1, #24] ; Pickup thread's current time-slice
ADDS r7, r7, #1 ; Increment the thread run count
STR r7, [r1, #4] ; Store the new run count
;
; /* Setup global time-slice with thread's current time-slice. */
;
STR r5, [r4] ; Setup global time-slice
#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
;
; /* Call the thread entry function to indicate the thread is executing. */
;
PUSH {r0, r1} ; Save r0/r1
BL _tx_execution_thread_enter ; Call the thread execution enter function
POP {r0, r1} ; Recover r0/r1
/* Determine if time-slice is active. If it isn't, skip time handling processing. */
LDR r4, =_tx_timer_time_slice // Build address of time-slice variable
LDR r5, [r4] // Pickup current time-slice
CBZ r5, __tx_ts_new // If not active, skip processing
/* Time-slice is active, save the current thread's time-slice and clear the global time-slice variable. */
STR r5, [r1, #24] // Save current time-slice
/* Clear the global time-slice. */
MOVS r5, #0 // Build clear value
STR r5, [r4] // Clear time-slice
/* Executing thread is now completely preserved!!! */
__tx_ts_new:
/* Now we are looking for a new thread to execute! */
CPSID i // Disable interrupts
LDR r1, [r2] // Is there another thread ready to execute?
CBZ r1, __tx_ts_wait // No, skip to the wait processing
/* Yes, another thread is ready for else, make the current thread the new thread. */
STR r1, [r0] // Setup the current thread pointer to the new thread
CPSIE i // Enable interrupts
/* Increment the thread run count. */
__tx_ts_restore:
LDR r7, [r1, #4] // Pickup the current thread run count
MOV32 r4, _tx_timer_time_slice // Build address of time-slice variable
LDR r5, [r1, #24] // Pickup thread's current time-slice
ADDS r7, r7, #1 // Increment the thread run count
STR r7, [r1, #4] // Store the new run count
/* Setup global time-slice with thread's current time-slice. */
STR r5, [r4] // Setup global time-slice
#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE))
/* Call the thread entry function to indicate the thread is executing. */
PUSH {r0, r1} // Save r0 and r1
BL _tx_execution_thread_enter // Call the thread execution enter function
POP {r0, r1} // Recover r0 and r1
#endif
#if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE)
; Restore secure context
LDR r5, =0x90 ; Secure stack index offset
LDR r0, [r1, r5] ; Load secure stack index
CBZ r0, _skip_secure_restore ; Skip restore if there is no secure context
PUSH {r0, r1} ; Save r1 (and dummy r0)
MOV r0, r1 ; Move thread ptr to r0
BL _tx_thread_secure_stack_context_restore ; Restore secure stack
POP {r0, r1} ; Restore r1 (and dummy r0)
#if (!defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE))
// Restore secure context
LDR r5, =0x90 // Secure stack index offset
LDR r0, [r1, r5] // Load secure stack index
CBZ r0, _skip_secure_restore // Skip restore if there is no secure context
PUSH {r0, r1} // Save r1 (and dummy r0)
MOV r0, r1 // Move thread ptr to r0
BL _tx_thread_secure_stack_context_restore // Restore secure stack
POP {r0, r1} // Restore r1 (and dummy r0)
_skip_secure_restore:
#endif
;
; /* Restore the thread context and PSP. */
;
/* Restore the thread context and PSP. */
#ifdef TX_SINGLE_MODE_SECURE
; There are only stack limit registers in secure mode on the M23
LDR r3, [r1, #12] ; Get stack start
MSR PSPLIM, r3 ; Set stack limit
// There are only stack limit registers in secure mode on the M23
LDR r3, [r1, #12] // Get stack start
MSR PSPLIM, r3 // Set stack limit
#endif
LDR r3, [r1, #8] ; Pickup thread's stack pointer
LDR r5, [r3] ; Recover saved LR
ADDS r3, r3, #4 ; Position past LR
MOV lr, r5 ; Restore LR
LDM r3!, {r4-r7} ; Recover thread's registers (r4-r11)
MOV r11, r7 ;
MOV r10, r6 ;
MOV r9, r5 ;
MOV r8, r4 ;
LDM r3!, {r4-r7} ;
MSR PSP, r3 ; Setup the thread's stack pointer
;
; /* Return to thread. */
;
BX lr ; Return to thread!
;
; /* The following is the idle wait processing... in this case, no threads are ready for execution and the
; system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts
; are disabled to allow use of WFI for waiting for a thread to arrive. */
;
LDR r3, [r1, #8] // Pickup thread's stack pointer
LDR r5, [r3] // Recover saved LR
ADDS r3, r3, #4 // Position past LR
MOV lr, r5 // Restore LR
LDM r3!, {r4-r7} // Recover thread's registers (r4-r11)
MOV r11, r7 //
MOV r10, r6 //
MOV r9, r5 //
MOV r8, r4 //
LDM r3!, {r4-r7} //
MSR PSP, r3 // Setup the thread's stack pointer
/* Return to thread. */
BX lr // Return to thread!
/* The following is the idle wait processing... in this case, no threads are ready for execution and the
system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts
are disabled to allow use of WFI for waiting for a thread to arrive. */
__tx_ts_wait:
CPSID i ; Disable interrupts
LDR r1, [r2] ; Pickup the next thread to execute pointer
STR r1, [r0] ; Store it in the current pointer
CBNZ r1, __tx_ts_ready ; If non-NULL, a new thread is ready!
CPSID i // Disable interrupts
LDR r1, [r2] // Pickup the next thread to execute pointer
STR r1, [r0] // Store it in the current pointer
CBNZ r1, __tx_ts_ready // If non-NULL, a new thread is ready!
#ifdef TX_LOW_POWER
PUSH {r0-r3}
BL tx_low_power_enter ; Possibly enter low power mode
BL tx_low_power_enter // Possibly enter low power mode
POP {r0-r3}
#endif
#ifdef TX_ENABLE_WFI
DSB ; Ensure no outstanding memory transactions
WFI ; Wait for interrupt
ISB ; Ensure pipeline is flushed
DSB // Ensure no outstanding memory transactions
WFI // Wait for interrupt
ISB // Ensure pipeline is flushed
#endif
#ifdef TX_LOW_POWER
PUSH {r0-r3}
BL tx_low_power_exit ; Exit low power mode
BL tx_low_power_exit // Exit low power mode
POP {r0-r3}
#endif
CPSIE i ; Enable interrupts
B __tx_ts_wait ; Loop to continue waiting
;
; /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are
; already in the handler! */
;
CPSIE i // Enable interrupts
B __tx_ts_wait // Loop to continue waiting
/* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are
already in the handler! */
__tx_ts_ready:
LDR r7, =0x08000000 ; Build clear PendSV value
LDR r5, =0xE000ED04 ; Build ICSR address
STR r7, [r5] ; Clear any PendSV
;
; /* Re-enable interrupts and restore new thread. */
;
CPSIE i ; Enable interrupts
B __tx_ts_restore ; Restore the thread
LDR r7, =0x08000000 // Build clear PendSV value
LDR r5, =0xE000ED04 // Build ICSR address
STR r7, [r5] // Clear any PendSV
/* Re-enable interrupts and restore new thread. */
CPSIE i // Enable interrupts
B __tx_ts_restore // Restore the thread
#if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE)
; SVC_Handler is not needed when ThreadX is running in single mode.
#if (!defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE))
// SVC_Handler is not needed when ThreadX is running in single mode.
PUBLIC SVC_Handler
SVC_Handler:
MOVS r0, #4
MOV r1, lr
TST r1, r0 ; Determine return stack from EXC_RETURN bit 2
TST r1, r0 // Determine return stack from EXC_RETURN bit 2
BEQ _tx_get_msp
MRS r0, PSP ; Get PSP if return stack is PSP
MRS r0, PSP // Get PSP if return stack is PSP
B _tx_got_sp
_tx_get_msp:
MRS r0, MSP ; Get MSP if return stack is MSP
MRS r0, MSP // Get MSP if return stack is MSP
_tx_got_sp:
LDR r1, [r0, #24] ; Load saved PC from stack
SUBS r1, r1, #2 ; Calculate SVC number address
LDRB r1, [r1] ; Load SVC number
LDR r1, [r0, #24] // Load saved PC from stack
SUBS r1, r1, #2 // Calculate SVC number address
LDRB r1, [r1] // Load SVC number
CMP r1, #1 ; Is it a secure stack allocate request?
BEQ _tx_svc_secure_alloc ; Yes, go there
CMP r1, #1 // Is it a secure stack allocate request?
BEQ _tx_svc_secure_alloc // Yes, go there
CMP r1, #2 ; Is it a secure stack free request?
BEQ _tx_svc_secure_free ; Yes, go there
CMP r1, #2 // Is it a secure stack free request?
BEQ _tx_svc_secure_free // Yes, go there
CMP r1, #3 // Is it a secure stack init request?
BEQ _tx_svc_secure_init // Yes, go there
; Unknown SVC argument - just return
// Unknown SVC argument - just return
BX lr
_tx_svc_secure_alloc:
PUSH {r0, lr} ; Save SP and EXC_RETURN
LDM r0, {r0-r3} ; Load function parameters from stack
PUSH {r0, lr} // Save SP and EXC_RETURN
LDM r0, {r0-r3} // Load function parameters from stack
BL _tx_thread_secure_mode_stack_allocate
POP {r1, r2} ; Restore SP and EXC_RETURN
STR r0, [r1] ; Store function return value
POP {r1, r2} // Restore SP and EXC_RETURN
STR r0, [r1] // Store function return value
MOV lr, r2
BX lr
_tx_svc_secure_free:
PUSH {r0, lr} ; Save SP and EXC_RETURN
LDM r0, {r0-r3} ; Load function parameters from stack
PUSH {r0, lr} // Save SP and EXC_RETURN
LDM r0, {r0-r3} // Load function parameters from stack
BL _tx_thread_secure_mode_stack_free
POP {r1, r2} ; Restore SP and EXC_RETURN
STR r0, [r1] ; Store function return value
POP {r1, r2} // Restore SP and EXC_RETURN
STR r0, [r1] // Store function return value
MOV lr, r2
BX lr
#endif ; End of ifndef TX_SINGLE_MODE_SECURE, TX_SINGLE_MODE_NON_SECURE
_tx_svc_secure_init:
PUSH {r0,lr} // Save SP and EXC_RETURN
BL _tx_thread_secure_mode_stack_initialize
POP {r1, r2} // Restore SP and EXC_RETURN
MOV lr, r2
BX lr
#endif // End of ifndef TX_SINGLE_MODE_SECURE, TX_SINGLE_MODE_NON_SECURE
END

48
ports/cortex_m23/iar/src/tx_thread_secure_stack.c
View File

@@ -62,8 +62,8 @@ typedef struct TX_THREAD_SECURE_STACK_INFO_STRUCT
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_secure_stack_initialize Cortex-M23/IAR */
/* 6.1.1 */
/* _tx_thread_secure_mode_stack_initialize Cortex-M23/IAR */
/* 6.1.7 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -78,7 +78,7 @@ typedef struct TX_THREAD_SECURE_STACK_INFO_STRUCT
/* */
/* OUTPUT */
/* */
/* None */
/* status */
/* */
/* CALLS */
/* */
@@ -98,21 +98,35 @@ typedef struct TX_THREAD_SECURE_STACK_INFO_STRUCT
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* 10-16-2020 Scott Larson Modified comment(s), */
/* resulting in version 6.1.1 */
/* 06-02-2021 Scott Larson Modified comment(s), changed */
/* name, execute in handler */
/* mode, disable optimization, */
/* resulting in version 6.1.7 */
/* */
/**************************************************************************/
__attribute__((cmse_nonsecure_entry))
void _tx_thread_secure_stack_initialize(void)
UINT _tx_thread_secure_mode_stack_initialize(void)
{
/* Set secure mode to use PSP. */
__set_CONTROL(__get_CONTROL() | 2);
/* Set process stack pointer and stack limit to 0 to throw exception when a thread
without a secure stack calls a secure function that tries to use secure stack. */
__set_PSPLIM(0);
__set_PSP(0);
return;
UINT status;
/* Make sure function is called from interrupt (threads should not call). */
if (__get_IPSR() == 0)
{
status = TX_CALLER_ERROR;
}
else
{
/* Set secure mode to use PSP. */
__set_CONTROL(__get_CONTROL() | 2);
/* Set process stack pointer and stack limit to 0 to throw exception when a thread
without a secure stack calls a secure function that tries to use secure stack. */
__set_PSPLIM(0);
__set_PSP(0);
status = TX_SUCCESS;
}
return status;
}
@@ -335,7 +349,7 @@ TX_THREAD_SECURE_STACK_INFO *info_ptr;
/* FUNCTION RELEASE */
/* */
/* _tx_thread_secure_stack_context_save Cortex-M23/IAR */
/* 6.1.1 */
/* 6.1.7 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -370,6 +384,8 @@ TX_THREAD_SECURE_STACK_INFO *info_ptr;
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* 10-16-2020 Scott Larson Modified comment(s), */
/* resulting in version 6.1.1 */
/* 06-02-2021 Scott Larson Fix stack pointer save, */
/* resulting in version 6.1.7 */
/* */
/**************************************************************************/
__attribute__((cmse_nonsecure_entry))
@@ -402,7 +418,7 @@ ULONG sp;
}
/* Save stack pointer. */
*(ULONG *) info_ptr -> tx_thread_secure_stack_ptr = sp;
info_ptr -> tx_thread_secure_stack_ptr = (VOID *) sp;
/* Set process stack pointer and stack limit to 0 to throw exception when a thread
without a secure stack calls a secure function that tries to use secure stack. */

74
ports/cortex_m23/iar/src/tx_thread_secure_stack_initialize.s Normal file
View File

@@ -0,0 +1,74 @@
/**************************************************************************/
/* */
/* Copyright (c) Microsoft Corporation. All rights reserved. */
/* */
/* This software is licensed under the Microsoft Software License */
/* Terms for Microsoft Azure RTOS. Full text of the license can be */
/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
/* and in the root directory of this software. */
/* */
/**************************************************************************/
/**************************************************************************/
/**************************************************************************/
/** */
/** ThreadX Component */
/** */
/** Thread */
/** */
/**************************************************************************/
/**************************************************************************/
SECTION `.text`:CODE:NOROOT(2)
THUMB
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_secure_stack_initialize Cortex-M23/IAR */
/* 6.1.7 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
/* */
/* DESCRIPTION */
/* */
/* This function enters the SVC handler to initialize a secure stack. */
/* */
/* INPUT */
/* */
/* none */
/* */
/* OUTPUT */
/* */
/* none */
/* */
/* CALLS */
/* */
/* SVC 3 */
/* */
/* CALLED BY */
/* */
/* TX_INITIALIZE_KERNEL_ENTER_EXTENSION */
/* */
/* RELEASE HISTORY */
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 06-02-2021 Scott Larson Initial Version 6.1.7 */
/* */
/**************************************************************************/
// VOID _tx_thread_secure_stack_initialize(VOID)
// {
EXPORT _tx_thread_secure_stack_initialize
_tx_thread_secure_stack_initialize:
#if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE)
CPSIE i // Enable interrupts for SVC call
SVC 3
CPSID i // Disable interrupts
#else
MOV r0, #0xFF // Feature not enabled
#endif
BX lr
END