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Release 6.1.7

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This commit is contained in:
Bo Chen
2021-06-02 06:45:05 +00:00
parent d759e6bb9e
commit f5056f4923
1269 changed files with 57325 additions and 55178 deletions
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31
ports/cortex_m33/iar/inc/tx_port.h
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@@ -26,7 +26,7 @@
/* PORT SPECIFIC C INFORMATION RELEASE */
/* */
/* tx_port.h Cortex-M33/IAR */
/* 6.1.5 */
/* 6.1.7 */
/* */
/* AUTHOR */
/* */
@@ -51,6 +51,10 @@
/* 03-02-2021 Scott Larson Modified comment(s), added */
/* ULONG64_DEFINED, */
/* resulting in version 6.1.5 */
/* 06-02-2021 Yuxin Zhou Modified comment(s), and */
/* added symbol to enable */
/* stack error handler, */
/* resulting in version 6.1.7 */
/* */
/**************************************************************************/
@@ -97,6 +101,12 @@ UINT _txe_thread_secure_stack_free(struct TX_THREAD_STRUCT *thread_ptr);
UINT _tx_thread_secure_stack_allocate(struct TX_THREAD_STRUCT *tx_thread, ULONG stack_size);
UINT _tx_thread_secure_stack_free(struct TX_THREAD_STRUCT *tx_thread);
/* This port overrides tx_thread_stack_error_notify with an architecture specific version */
#define TX_PORT_THREAD_STACK_ERROR_NOTIFY
/* This port overrides tx_thread_stack_error_handler with an architecture specific version */
#define TX_PORT_THREAD_STACK_ERROR_HANDLER
/* This hardware has stack checking that we take advantage of - do NOT define. */
#ifdef TX_ENABLE_STACK_CHECKING
#error "Do not define TX_ENABLE_STACK_CHECKING"
@@ -258,14 +268,7 @@ ULONG _tx_misra_time_stamp_get(VOID);
#endif
#ifndef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
#define TX_THREAD_EXTENSION_3
#else
#define TX_THREAD_EXTENSION_3 unsigned long long tx_thread_execution_time_total; \
unsigned long long tx_thread_execution_time_last_start;
#endif
/* Define the port extensions of the remaining ThreadX objects. */
@@ -504,12 +507,6 @@ extern void _tx_thread_secure_stack_initialize(void);
is used to define a local function save area for the disable and restore
macros. */
/* The embedded assembler blocks are design so as to be inlinable by the
armlink linker inlining. This requires them to consist of either a
single 32-bit instruction, or either one or two 16-bit instructions
followed by a "BX lr". Note that to reduce the critical region size, the
16-bit "CPSID i" instruction is preceeded by a 16-bit NOP */
#ifdef TX_DISABLE_INLINE
UINT _tx_thread_interrupt_disable(VOID);
@@ -560,7 +557,7 @@ __istate_t interrupt_save;
#ifdef TX_THREAD_INIT
CHAR _tx_version_id[] =
"Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M33/IAR Version 6.1 *";
"Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M33/IAR Version 6.1.7 *";
#else
#ifdef TX_MISRA_ENABLE
extern CHAR _tx_version_id[100];
@@ -569,8 +566,4 @@ extern CHAR _tx_version_id[];
#endif
#endif
#endif